MAX11058ECB+T [MAXIM]
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| 型号： | MAX11058ECB+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 暂无描述 转换器 模数转换器 信息通信管理 |
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| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-5106; Rev 2; 1/11
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
4/7–MAX1059
General Description
Features
o 16-Bit ADC (MAX11047/MAX11048/MAX11049)
The MAX11047/MAX11048/MAX11049 and MAX11057/
MAX11058/MAX11059 16-bit/14-bit ADCs offer 4, 6, or 8
independent input channels. Featuring independent track
and hold (T/H) and SAR circuitry, these parts provide
simultaneous sampling at 250ksps for each channel.
o 14-Bit ADC (MAX11057/MAX11058/MAX11059)
o 8-Channel ADC (MAX11047/MAX11057)
o 6-Channel ADC (MAX11048/MAX11058)
o 4-Channel ADC (MAX11049/MAX11059)
o Single Analog and Digital Supply
o High-Impedance Inputs Up to 1GΩ
o On-Chip T/H Circuit for Each Channel
o Fast 3µs Conversion Time
The devices accept a 0 to +5V input. All inputs are
overrange protected with internal 20mA input clamps
providing overrange protection with a simple external
resistor. Other features include a 4MHz T/H input band-
width, internal clock, and internal or external reference.
A 20MHz, bidirectional, parallel interface provides the
conversion results and accepts digital configuration
inputs.
o High Throughput: 250ksps for Each Channel
o 16-/14-Bit, High-Speed, Parallel Interface
o Internal Clocked Conversions
The devices operate with a 4.75V to 5.25V analog supply
and a separate flexible 2.7V to 5.25V digital supply for
interfacing with the host without a level shifter. The
MAX11047/MAX11048/MAX11049 are available in a 56-pin
TQFN and 64-pin TQFP packages while the MAX11057/
MAX11058/MAX11059 are available in TQFP only. All
devices operate over the extended -40°C to +85°C tem-
perature range.
o 10ns Aperture Delay
o 100ps Channel-to-Channel T/H Matching
o Low Drift, Accurate 4.096V Internal Reference
Providing an Input Range of 0 to 5V
o External Reference Range of 3.0V to 4.25V,
Allowing Full-Scale Input Ranges of +3.7V to
+5.2V
o 56-Pin TQFN (8mm x 8mm) and 64-Pin TQFP
Applications
Automatic Test Equipment
(10mm x 10mm) Packages
o Evaluation Kit Available (MAX11046EVKIT+)
Power-Factor Monitoring and Correction
Power-Grid Protection
Functional Diagram
Multiphase Motor Control
AVDD
CH0
DVDD
Vibration and Waveform Analysis
DB15**
16-/14-BIT ADCs
16-/14-BIT ADCs
CLAMP
CLAMP
S/H
S/H
Ordering Information
DB4
PART
PIN-PACKAGE
56 TQFN-EP*
64 TQFP-EP*
56 TQFN-EP*
64 TQFP-EP*
56 TQFN-EP*
64 TQFP-EP*
64 TQFP-EP*
64 TQFP-EP*
64 TQFP-EP*
CHANNELS
DB3/CR3
MAX11047ETN+
MAX11047ECB+
MAX11048ETN+
MAX11048ECB+
MAX11049ETN+
MAX11049ECB+
MAX11057ECB+
MAX11058ECB+
MAX11059ECB+
4
4
6
6
8
8
4
6
8
†
DB0/CR0
CH7
CONFIGURATION
REGISTERS
WRb
AGNDS
AGND
RDb
CSb
INTERFACE
AND
CONTROL
CONVST
SHDN
EOCb
MAX11047/MAX11048/MAX11049/
MAX11057/MAX11058/MAX11059
DGND
RDC
INT REF
10kΩ
BANDGAP
REFERENCE
REF
BUF
Note: All devices are specified over the -40°C to +85°C operating
temperature range.
EXT REF
REFIO
RDC_SENSE*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
*CONNECTED INTERNALLY ON THE TQFN PARTS
**MAX11047/MAX11048/MAX11049
MAX11049/MAX11059
†
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND ........................................................-0.3V to +6V
DVDD to AGND and DGND .....................................-0.3V to +6V
DGND to AGND.....................................................-0.3V to +0.3V
AGNDS to AGND...................................................-0.3V to +0.3V
CH0–CH7 to AGND...............................................-2.5V to +7.5V
REFIO, RDC to AGND ..................................-0.3V to the lower of
(AVDD + 0.3V) and +6V
Maximum Current into Any Pin Except AVDD, DVDD, AGND,
DGND ........................................................................... 50mA
Continuous Power Dissipation (T = +70°C)
A
56-Pin TQFN (derated 47.6mW/°C above +70°C)..3809.5mW
64-Pin TQFP (derate 43.5mW/°C above +70°C.........3478mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
EOC, WR, RD, CS, CONVST to AGND.........-0.3V to the lower of
(DVDD + 0.3V) and +6V
DB0–DB15 to AGND ....................................-0.3V to the lower of
(DVDD + 0.3V) and +6V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= 4.75V to 5.25V, V
= +2.7V to 5.25V, V
= V
= V = 0V, V
DGND
= internal reference, C
= 4 x 33µF,
AVDD
DVDD
AGNDS
AGND
REFIO
RDC
C
= 0.1µF, C
= 4 x 0.1µF || 10µF, C
= 3 x 0.1µF || 10µF; all digital inputs at DVDD or DGND, unless otherwise noted.
REFIO
AVDD
DVDD
T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE (Note 1)
MAX11047/MAX11048/MAX11049
MAX11057/MAX11058/MAX11059
MAX11047/MAX11048/MAX11049
MAX11057/MAX11058/MAX11059
16
14
Resolution
N
Bits
LSB
-2
0ꢀ65
0ꢀ2
+2
+0ꢀ9
Integral Nonlinearity
Differential Nonlinearity
No Missing Codes
INL
-0ꢀ9
MAX11047/MAX11048/MAX11049
> -1
0ꢀ7
< +1ꢀ2
+0ꢀ7
DNL
LSB
Bits
MAX11057/MAX11058/MAX11059
MAX11047/MAX11048/MAX11049
MAX11057/MAX11058/MAX11059
-0ꢀ6
16
0ꢀ2
14
Offset Error
±0ꢀ001
±0ꢀ012
%FSR
µV/°C
%FSR
%FSR
%FSR
%FSR
%FSR
ppm/°C
Offset Temperature Coefficient
Channel Offset Matching
Gain Error
0ꢀ8
0ꢀ01
0ꢀ012
0ꢀ017
0ꢀ01
Positive Full-Scale Error
Positive Full-Scale Error Matching
Channel Gain-Error Matching
Gain Temperature Coefficient
DYNAMIC PERFORMANCE
Between all channels
0ꢀ01
0ꢀ6
4/7–MAX1059
MAX11047/MAX11048/MAX11049,
90ꢀ7
84ꢀ5
92ꢀ3
85ꢀ3
f
= 10kHz, full-scale input
IN
Signal-to-Noise Ratio
SNR
dB
MAX11057/MAX11058/MAX11059,
= 10kHz, full-scale input
f
IN
2
_______________________________________________________________________________________
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
4/7–MAX1059
ELECTRICAL CHARACTERISTICS (continued)
V
= 4.75V to 5.25V, V
= +2.7V to 5.25V, V
= V
= V = 0V, V
DGND
= internal reference, C
= 4 x 33µF,
AVDD
DVDD
AGNDS
AGND
REFIO
RDC
C
= 0.1µF, C
= 4 x 0.1µF || 10µF, C
= 3 x 0.1µF || 10µF; all digital inputs at DVDD or DGND, unless otherwise noted.
REFIO
AVDD
DVDD
T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX11047/MAX11048/MAX11049,
90.5
92
f
= 10kHz, full-scale input
IN
Signal-to-Noise and Distortion
Ratio
SINAD
dB
MAX11057/MAX11058/MAX11059,
84.5
85.2
f
= 10kHz, full-scale input
IN
MAX11047/MAX11048/
MAX11049
MAX11057/MAX11058/
MAX11059
98
95
108
108
f
= 10kHz,
IN
Spurious-Free Dynamic Range
Total Harmonic Distortion
SFDR
THD
dB
full-scale input
MAX11047/MAX11048/
MAX11049
MAX11057/MAX11058/
MAX11059
-108
-108
-98
-95
f
= 10kHz,
IN
dB
dB
full-scale input
f
= 60Hz, full scale and ground on
IN
Channel-to-Channel Crosstalk
ANALOG INPUTS (CH0–CH7)
Input Voltage Range
-126
-100
adjacent channel (Note 2)
1.22 x
REFIO
(Note 3)
0
V
V
Input Leakage Current
Input Capacitance
-1
+1
µA
pF
15
Input-Clamp Protection Current
TRACK AND HOLD
Throughput Rate
Each input simultaneously
Per channel
-20
1
+20
250
mA
ksps
µs
Acquisition Time
t
ACQ
-3dB point
4
> 0.2
10
Full-Power Bandwidth
MHz
-0.1dB point
Aperture Delay
ns
ps
Aperture-Delay Matching
Aperture Jitter
100
50
ps
RMS
INTERNAL REFERENCE
REFIO Voltage
V
V
4.080
4.096
4
4.112
V
REF
REFIO Temperature Coefficient
EXTERNAL REFERENCE
Input Current
ppm/°C
-10
+10
4.25
µA
V
REF Voltage Input Range
REF Input Capacitance
3.00
REF
15
10
pF
DIGITAL INPUTS (CR0–CR3, RD, WR, CS, CONVST)
Input-Voltage High
Input-Voltage Low
Input Capacitance
Input Current
V
V
V
= 2.7V to 5.25V
= 2.7V to 5.25V
2
V
V
IH
DVDD
DVDD
V
0.8
10
IL
IN
IN
C
pF
µA
I
V
= 0 or V
DVDD
IN
_______________________________________________________________________________________
3
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
ELECTRICAL CHARACTERISTICS (continued)
V
= 4.75V to 5.25V, V
= +2.7V to 5.25V, V
= V
= V = 0V, V
DGND
= internal reference, C
= 4 x 33µF,
AVDD
DVDD
AGNDS
AGND
REFIO
RDC
C
= 0.1µF, C
= 4 x 0.1µF || 10µF, C
= 3 x 0.1µF || 10µF; all digital inputs at DVDD or DGND, unless otherwise noted.
REFIO
AVDD
DVDD
T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL OUTPUTS (DB0–DB15, EOC)
V
DVDD
0.4
-
Output-Voltage High
V
I
I
= 1.2mA
SOURCE
V
OH
Output-Voltage Low
V
= 1mA
SINK
0.4
10
V
OL
Three-State Leakage Current
Three-State Output Capacitance
DB0–DB15, V ꢀ V or V ꢀ V
µA
pF
RD
IH
CS
IH
IH
DB0–DB15, V ꢀ V or V ꢀ V
15
RD
IH
CS
POWER SUPPLIES (MAX11047/MAX11057)
Analog Supply Voltage
Digital Supply Voltage
Analog Supply Current
Digital Supply Current
Shutdown Current
AVDD
DVDD
4.75
2.70
5.25
5.25
25
V
V
I
I
mA
mA
µA
µA
AVDD
DVDD
V
= 3.3V (Note 4)
5.5
10
DVDD
For DVDD
For AVDD
Shutdown Current
10
MAX11047
MAX11057
±1.2
±0.3
V
= 4.9V to 5.1V
AVDD
Power-Supply Rejection
PSR
LSB
(Note 5)
POWER SUPPLIES (MAX11048/MAX11058)
Analog Supply Voltage
Digital Supply Voltage
Analog Supply Current
Digital Supply Current
Shutdown Current
AVDD
DVDD
4.75
2.70
5.25
5.25
32
V
V
I
I
mA
mA
µA
µA
AVDD
DVDD
V
= 3.3V (Note 4)
6.5
10
DVDD
For DVDD
For AVDD
Shutdown Current
10
MAX11048
MAX11058
±1.2
±0.3
V
= 4.9V to 5.1V
AVDD
Power-Supply Rejection
PSR
LSB
(Note 5)
POWER SUPPLIES (MAX11049/MAX11059)
Analog Supply Voltage
Digital Supply Voltage
Analog Supply Current
Digital Supply Current
Shutdown Current
AVDD
DVDD
4.75
2.70
5.25
5.25
39
V
V
I
mA
mA
µA
µA
AVDD
DVDD
I
V
= 3.3V (Note 4)
7
DVDD
For DVDD
For AVDD
10
4/7–MAX1059
Shutdown Current
10
MAX11049
MAX11059
±1.2
±0.3
V
= 4.9V to 5.1V
AVDD
Power-Supply Rejection
PSR
LSB
(Note 5)
TIMING CHARACTERISTICS (Note 4)
CONVST Rise to EOC Fall
Acquisition Time
t
Conversion time (Note 6)
3
µs
µs
ns
CON
t
1
ACQ
CS Rise to CONVST Rise
t
Sample quiet time (Note 6)
500
Q
4
_______________________________________________________________________________________
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
4/7–MAX1059
ELECTRICAL CHARACTERISTICS (continued)
V
= 4.75V to 5.25V, V
= +2.7V to 5.25V, V
= V
= V = 0V, V
DGND
= internal reference, C
= 4 x 33µF,
AVDD
DVDD
AGNDS
AGND
REFIO
RDC
C
= 0.1µF, C
= 4 x 0.1µF || 10µF, C
= 3 x 0.1µF || 10µF; all digital inputs at DVDD or DGND, unless otherwise noted.
REFIO
AVDD
DVDD
T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ns
CONVST Rise to EOC Rise
EOC Fall to CONVST Fall
t
65
140
0
1
t
CONVST mode B0 = 0 only (Note 7)
CONVST mode B0 = 1 only
0
ns
CONVST Low Time
CS Fall to WR Fall
WR Low Time
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
0
CS Rise to WR Rise
Input Data Setup Time
Input Data Hold Time
CS Fall to RD Fall
RD Low Time
10
0
0
30
0
RD Rise to CS Rise
RD High Time
t
10
t
11
t
12
t
13
10
RD Fall to Data Valid
RD Rise to Data Hold Time
35
(Note 7)
5
Note 1: See the Definitions section at the end of the data sheet.
Note 2: Tested with alternating channels modulated at full scale and ground.
Note 3: See the Input Range and Protection section.
Note 4: C
= 30pF on DB0–DB15 and EOC. Inputs (CH0–CH7) alternate between full scale and zero scale. f
= 250ksps. All
LOAD
CONV
data is read out.
Note 5: Defined as the change in positive full scale caused by a 2ꢀ variation in the nominal supply voltage.
Note 6: It is recommended that RD, WR, and CS are kept high for the quiet time (t ) and conversion time (t
).
CON
Q
Note 7: Guaranteed by design.
Typical Operating Characteristics
(V
= 5V, V
= 3.3V, T = +25°C, f
= 250ksps, internal reference, unless otherwise noted.)
AVDD
DVDD
A
SAMPLE
DIFFERENTIAL NONLINEARITY (DNL)
vs. CODE FOR MAX1104_
INTEGRAL NONLINEARITY (INL)
vs. CODE FOR MAX1104_
1.0
0.8
1.0
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
V
V
f
= 5.0V
= 3.3V
V
V
f
= 5.0V
= 3.3V
AVDD
DVDD
AVDD
DVDD
= 250ksps
= 250ksps
SAMPLE
SAMPLE
T
A
= +25°C
= 4.096V
T
A
= +25°C
= 4.096V
V
V
RDC
RDC
0
16384
32768
49152
65536
57344
0
16384
32768
49152
65536
57344
8192
24576
40960
8192
24576
40960
OUTPUT CODE (DECIMAL)
OUTPUT CODE (DECIMAL)
_______________________________________________________________________________________
5
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
Typical Operating Characteristics (continued)
(V
= 5V, V
= 3.3V, T = +25°C, f
= 250ksps, internal reference, unless otherwise noted.)
SAMPLE
AVDD
DVDD
A
ANALOG SUPPLY CURRENT
vs. SUPPLY VOLTAGE
INL AND DNL vs. ANALOG SUPPLY
VOLTAGE FOR MAX1104_
INL AND DNL vs. TEMPERATURE
FOR MAX1104_
1.5
1.0
0.5
0
36
34
32
30
28
26
24
22
20
18
1.5
MAX INL
MAX DNL
MAX11049 CONVERTING
1.0
0.5
0
MAX11049 STATIC
MAX11048 CONVERTING
MAX DNL
MIN INL
MIN INL
MAX INL
MIN DNL
MAX11048 STATIC
T
= +25°C
A
-0.5
-1.0
-1.5
-0.5
-1.0
-1.5
f
= 250ksps
SAMPLE
MAX11047 CONVERTING
V
= 3.3V
DVDD
V
V
f
= 5.0V
= 3.3V
AVDD
DVDD
f
= 250ksps
SAMPLE
MIN DNL
T
= +25°C
A
= 250ksps
SAMPLE
V
= 4.096V
MAX11047 STATIC
RDC
V
RDC
= 4.096V
4.75
4.85
4.95
5.05
(V)
5.15
5.25
4.75
4.85
4.95
5.05
(V)
5.15
5.25
-40
-15
10
35
60
85
V
AVDD
V
AVDD
TEMPERATURE (°C)
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
DIGITAL SUPPLY CURRENT
vs. TEMPERATURE
DIGITAL SUPPLY CURRENT
vs. SUPPLY VOLTAGE
7.2
6.0
4.8
3.6
2.4
1.2
0
12
10
8
T
= +25°C
MAX11049 CONVERTING
A
34
30
26
22
18
f
= 250ksps
SAMPLE
MAX11049 CONVERTING
C
= 15pF
DBxx
MAX11049 STATIC
MAX11049 CONVERTING
MAX11048 CONVERTING
MAX11048 CONVERTING
MAX11047 CONVERTING
6
MAX11048 STATIC
V
f
= 5.0V
AVDD
4
= 250ksps
MAX11048 CONVERTING
SAMPLE
MAX11047 CONVERTING
MAX11049/MAX11048/
MAX11047 STATIC
V
f
= 3.3V
MAX11049/MAX11048/
MAX11047 STATIC
DVDD
2
= 250ksps
SAMPLE
C
DBxx
= 15pF
MAX11047 CONVERTING
MAX11047 STATIC
0
-40
-15
10
35
60
85
-40
-15
10
35
60
85
2.75
3.25 3.75
4.25
(V)
4.75
5.25
TEMPERATURE (°C)
TEMPERATURE (°C)
V
DVDD
ANALOG AND DIGITAL SHUTDOWN
CURRENT vs. TEMPERATURE
ANALOG AND DIGITAL SHUTDOWN
CURRENT vs. SUPPY VOLTAGE
INTERNAL REFERENCE VOLTAGES
vs. SUPPLY VOLTAGE
5
4
3
2
1
0
5
4
3
2
1
0
4.09630
4.09625
4.09620
4.09615
4.09610
4.09605
4.09600
4.09595
4.09590
V
V
= 5.0V
AVDD
T
= +25°C
T
= +25°C
A
V
A
RDC
= 3.3V
DVDD
I
I
AVDD
AVDD
4/7–MAX1059
I
DVDD
I
DVDD
V
REFIO
-40
-15
10
35
60
85
2.75
3.25
3.75
4.25
4.75
5.25
4.75
4.85
4.95
5.05
(V)
5.15
5.25
TEMPERATURE (°C)
AVDD OR DVDD (V)
V
AVDD
6
_______________________________________________________________________________________
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
4/7–MAX1059
Typical Operating Characteristics (continued)
(V
= 5V, V
= 3.3V, T = +25°C, f
= 250ksps, internal reference, unless otherwise noted.)
AVDD
DVDD
A
SAMPLE
INTERNAL REFERENCE VOLTAGES
vs. TEMPERATURE
OFFSET ERROR AND OFFSET ERROR
MATCHING vs. TEMPERATURE
OFFSET ERROR AND OFFSET ERROR
MATCHING vs. SUPPLY VOLTAGE
4.112
4.108
4.104
4.100
4.096
4.092
4.088
4.084
4.080
0.010
0.006
0.010
f = 250ksps
SAMPLE
f
= 250ksps
SAMPLE
V
= 5.0V
AVDD
V
AVDD
V
REFIO
= 5.0V
= 4.096V
T
A
= +25°C
V
= 4.096V
RDC
0.006
0.002
UPPER TYPICAL LIMIT
LOWER TYPICAL LIMIT
OFFSET ERROR MATCHING
OFFSET ERROR MATCHING
0.002
-0.002
-0.006
-0.010
-0.002
-0.006
-0.010
OFFSET ERROR
OFFSET ERROR
-40
-15
10
35
60
85
-40
-15
10
35
60
85
4.75
4.85
4.95
5.05
(V)
5.15
5.25
TEMPERATURE (°C)
TEMPERATURE (°C)
V
AVDD
GAIN ERROR AND GAIN ERROR
MATCHING vs. SUPPLY VOLTAGE
GAIN ERROR AND GAIN ERROR
MATCHING vs. TEMPERATURE
FFT PLOT FOR MAX1104_
0.010
0.006
0.010
0.006
0
f
= 250ksps
f
= 250ksps
f
f
T
= 10kHz
= 250ksps
SAMPLE
= +25°C
SAMPLE
SAMPLE
IN
T
A
= +25°C
V
AVDD
V
REFIO
= 5.0V
= 4.096V
-20
-40
V
= 4.096V
RDC
A
V
AVDD
= 5.0V
GAIN ERROR MATCHING
GAIN ERROR MATCHING
0.002
0.002
-60
-80
-0.002
-0.006
-0.010
-0.002
-0.006
-0.010
-100
-120
-140
GAIN ERROR
GAIN ERROR
4.75
4.85
4.95
V
5.05
(V)
5.15
5.25
-40
-15
10
35
60
85
0
25
50
75
100
125
TEMPERATURE (°C)
FREQUENCY (kHz)
AVDD
SIGNAL-TO-NOISE RATIO (SNR) AND
SIGNAL-TO-NOISE AND DISTORTION RATIO
(SINAD) vs. TEMPERATURE FOR MAX1104_
TOTAL HARMONIC DISTORTION (THD)
vs. TEMPERATURE FOR MAX1104_
TWO-TONE IMD PLOT FOR MAX1104_
0
-20
93.0
-108.0
-108.5
-109.0
-109.5
-110.0
f
f
f
= 9834Hz
= 10384Hz
V
= 5.0V
AVDD
IN1
IN2
f
f
T
= 10kHz
= 250ksps
SAMPLE
= +25°C
A
IN
= 250ksps
SAMPLE
SNR
92.5
92.0
91.5
91.0
T
A
= +25°C
-40
V
V
V
= 5.0V
= 4.096V
= -0.01dBFS
V
RDC
= 4.096V
AVDD
V = -0.025dB FROM FS
IN
RDC
-60
IN
-80
V
= 5.0V
= 10kHz
= 250ksps
= +25°C
= 4.096V
AVDD
f
f
IN
SAMPLE
SINAD
-100
-120
-140
T
A
V
V
RDC
= -0.025dB FROM FS
IN
7.6
8.4
9.2
10.0 10.8 11.6 12.4
-40
-15
10
35
60
85
-40
-15
10
35
60
85
FREQUENCY (kHz)
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
7
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
Typical Operating Characteristics (continued)
(V
= 5V, V
= 3.3V, T = +25°C, f
= 250ksps, internal reference, unless otherwise noted.)
SAMPLE
AVDD
DVDD
A
THD vs. ANALOG SUPPLY VOLTAGE
FOR MAX1104_
SIGNAL-TO-NOISE AND DISTORTION RATIO
(SINAD) vs. FREQUENCY FOR MAX1104_
SNR AND SINAD vs. ANALOG SUPPLY
VOLTAGE FOR MAX1104_
-108.0
94
93
92
91
90
89
88
93.0
92.5
92.0
91.5
91.0
f
f
= 10kHz
IN
f
f
T
= 10kHz
= 250ksps
SAMPLE
= +25°C
IN
= 250ksps
SAMPLE
T
A
= +25°C
A
-108.5
-109.0
-109.5
-110.0
V
V
= 4.096V
= -0.025dB FROM FS
V
V
= 4.096V
= -0.025dB FROM FS
SNR
RDC
RDC
IN
IN
SINAD
V
f
= 5.0V
AVDD
= 250ksps
SAMPLE
T
A
= +25°C
V
= 4.096V
RDC
V
IN
= -0.025dB FROM FS
4.75
4.85
4.95
V
5.05
(V)
5.15
5.25
0.1
1.0
10.0
100.0
4.75
4.85
4.95
V
5.05
(V)
5.15
5.25
FREQUENCY (kHz)
AVDD
AVDD
THD vs. INPUT FREQUENCY
FOR MAX1104_
OUTPUT NOISE HISTOGRAM WITH INPUT
CONNECTED TO 2.5V FOR MAX1104_
CROSSTALK vs. FREQUENCY
-85
-90
24000
20000
16000
12000
8000
4000
0
-90
-100
-110
-120
-130
-140
V
f
= 5.0V
V
V
f
= 2.500270V
= 5.0V
AVDD
f
f
T
V
V
V
= 60Hz
CHX
AVDD
IN
= 250ksps
SAMPLE
= 250ksps
= +25°C
SAMPLE
T
A
= +25°C
= 4.096V
= -0.025dB FROM FS
= 250ksps
SAMPLE
A
V
V
T
A
= +25°C
RDC
= 5.0V
AVDD
-95
IN
= 4.096V
RDC
= -0.025dB FROM FS
INACTIVE CHANNEL AT GND
IN
-100
-105
-110
-115
-120
0.1
1.0
10.0
100.0
32768 32769 32770 32771 32772 32773 32774
OUTPUT CODE (DECIMAL)
0.1
1
10
100
FREQUENCY (kHz)
FREQUENCY (kHz)
CONVERSION TIME vs. ANALOG
SUPPLY VOLTAGE
CONVERSION TIME vs. TEMPERATURE
3.00
2.99
2.98
2.97
2.96
2.95
2.94
2.93
2.92
3.00
T
= +25°C
V
= 5.0V
AVDD
A
2.99
2.98
2.97
2.96
2.95
2.94
2.93
2.92
4/7–MAX1059
4.75
4.85
4.95
5.05
(V)
5.15
5.25
-40
-15
10
35
60
85
V
TEMPERATURE (°C)
AVDD
8
_______________________________________________________________________________________
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
4/7–MAX1059
Pin Configurations
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
TOP VIEW
RDC
AGNDS
CH0*/I.C.
AGND
32
31
30
AGNDS
49
50
42 41 40 39 38 37 36 35 34 33 32 31 30 29
†‡
†‡
I.C. /CH7*
28
27
26
25
24
23
22
21
RDC
43
44
AGND 51
AVDD 52
AGNDS
†‡
AGNDS
CH0*/I.C.
AGND
AVDD
AGNDS
RDC
29 AVDD
†‡
I.C. /CH7* 45
AGND 46
AVDD 47
AGNDS 48
RDC 49
AGNDS
RDC
28
27
26
25
24
23
22
21
20
19
18
AGNDS 53
RDC 54
RDC_SENSE
AGND
RDC_SENSE 55
AGND 56
MAX11047
MAX11048
MAX11049
MAX11047
MAX11048
MAX11049
AVDD
AVDD 57
DGND 50
DVDD 51
WR 52
DGND
AGNDS
58
AGNDS
DGND
20 DVDD
DGND
DVDD
WR
59
60
61
62
63
19 SHDN
DVDD
CS 53
18 CONVST
17 EOC
SHDN
RD 54
CONVST
EOC
CS
*EP
DB15 55
DB14 56
16 DB0/CR0
15 DB1/CR1
+
*EP
RD
+
DB15 64
17 DB0/CR0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
‡
†
MAX11047
MAX11048
TQFN
8mm x 8mm
*MAX11049
TQFP
10mm x 10mm
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
AGNDS
CH0*/I.C.
AGND
32
31
30
AGNDS
49
50
†‡
†‡
I.C. /CH7*
AGND 51
AVDD 52
29 AVDD
AGNDS
RDC
28
27
26
25
24
23
22
21
20
19
18
AGNDS 53
RDC 54
RDC_SENSE
AGND
RDC_SENSE 55
AGND 56
MAX11057
MAX11058
MAX11059
AVDD
AVDD 57
AGNDS
58
AGNDS
DGND
DGND
DVDD
WR
59
60
61
62
63
DVDD
SHDN
CONVST
EOC
CS
*EP
RD
+
DB13 64
17 CR0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
‡
†
MAX11057
MAX11058
TQFP
10mm x 10mm
*MAX11059
_______________________________________________________________________________________
9
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
Pin Description
PIN
NAME
FUNCTION
MAX11047 MAX11048 MAX11049
(TQFN-EP) (TQFN-EP) (TQFN-EP)
1
1
1
DB13
DB12
DB11
DB10
DB9
16-Bit Parallel Data Bus Digital Output Bit 13
16-Bit Parallel Data Bus Digital Output Bit 12
16-Bit Parallel Data Bus Digital Output Bit 11
16-Bit Parallel Data Bus Digital Output Bit 10
16-Bit Parallel Data Bus Digital Output Bit 9
16-Bit Parallel Data Bus Digital Output Bit 8
Digital Ground
2
2
2
3
3
3
4
4
4
5
5
5
6
6
6
DB8
7, 21, 50
7, 21, 50
7, 21, 50
DGND
DVDD
DB7
8, 20, 51
8, 20, 51
8, 20, 51
Digital Supply. Bypass to DGND with a 0.1µF capacitor at each DV input.
DD
9
9
9
16-Bit Parallel Data Bus Digital Output Bit 7
16-Bit Parallel Data Bus Digital Output Bit 6
16-Bit Parallel Data Bus Digital Output Bit 5
16-Bit Parallel Data Bus Digital Output Bit 4
10
11
12
13
14
15
16
10
11
12
13
14
15
16
10
11
12
13
14
15
16
DB6
DB5
DB4
DB3/CR3 16-Bit Parallel Data Bus Digital Output Bit 3/Configuration Register Input Bit 3
DB2/CR2 16-Bit Parallel Data Bus Digital Output Bit 2/Configuration Register Input Bit 2
DB1/CR1 16-Bit Parallel Data Bus Digital Output Bit 1/Configuration Register Input Bit 1
DB0/CR0 16-Bit Parallel Data Bus Digital Output Bit 0/Configuration Register Input Bit 0
Active-Low End of Conversion Output. EOC goes low when conversion is
completed. EOC goes high when a conversion is initiated.
17
17
17
EOC
Convert Start Input. Rising edge of CONVST ends sample and starts a
CONVST conversion on the captured sample. The ADC is in acquisition mode when
CONVST is low and CONVST mode = 0.
18
18
18
Shutdown Input. If SHDN is held high, the entire device enters and stays in a
19
19
19
SHDN
RDC
low-current state. Contents of the Configuration register are not lost when in
the shutdown state.
Reference Buffer Decoupling. Connect all RDC outputs together. Bypass to
AGND with at least an 80µF total capacitance. See the Layout, Grounding,
and Bypassing section.
22, 28, 35, 22, 28, 35, 22, 28, 35,
43, 49 43, 49 43, 49
23, 27, 33, 23, 27, 33, 23, 27, 33,
AGNDS
AVDD
AGND
I.C.
Signal Ground. Connect all AGND and AGNDS inputs together on PWB.
38, 44, 48
38, 44, 48
38, 44, 48
24, 30,
41, 47
24, 30,
41, 47
24, 30,
41, 47
Analog Supply Input. Bypass AV
to AGND with a 0.1µF capacitor at each
DD
AV
input.
DD
25, 31,
40, 46
25, 31,
40, 46
25, 31,
40, 46
4/7–MAX1059
Analog Ground. Connect all AGND inputs together.
Internally Connected. Connect to AGND
26, 29,
42, 45
26, 45
—
32
34
29
32
26
29
CH0
CH1
Channel 0 Analog Input
Channel 1 Analog Input
External Reference Input/Internal Reference Output. Place a 0.1µF capacitor
from REFIO to AGND.
36
36
36
REFIO
10 ______________________________________________________________________________________
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
4/7–MAX1059
Pin Description (continued)
PIN
NAME
FUNCTION
MAX11047 MAX11048 MAX11049
(TQFN-EP) (TQFN-EP) (TQFN-EP)
37
39
—
—
—
—
34
37
39
42
—
—
32
34
37
39
42
45
CH2
CH3
CH4
CH5
CH6
CH7
Channel 2 Analog Input
Channel 3 Analog Input
Channel 4 Analog Input
Channel 5 Analog Input
Channel 6 Analog Input
Channel 7 Analog Input
Active-Low Write Input. Drive WR low to write to the ADC. Configuration
registers are loaded on the rising edge of WR.
52
53
54
52
53
54
52
53
54
WR
CS
RD
Active Low-Chip Select Input. Drive CS low when reading from or writing to
the ADC.
Active-Low Read Input. Drive RD low to read from the ADC. Each rising edge
of RD advances the channel output on the data bus.
55
56
55
56
55
56
DB15
DB14
16-Bit Parallel Data Bus Digital Output Bit 15
16-Bit Parallel Data Bus Digital Output Bit 14
Exposed Pad. Internally connected to AGND. Connect to a large ground
plane to maximize thermal performance. Not intended as an electrical
connection point.
—
—
—
EP
PIN
NAME
FUNCTION
MAX11047 MAX11048 MAX11049
(TQFP-EP) (TQFP-EP) (TQFP-EP)
1
1
1
DB14
DB13
DB12
DB11
DB10
DB9
16-Bit Parallel Data Bus Digital Output Bit 14
16-Bit Parallel Data Bus Digital Output Bit 13
16-Bit Parallel Data Bus Digital Output Bit 12
16-Bit Parallel Data Bus Digital Output Bit 11
16-Bit Parallel Data Bus Digital Output Bit 10
16-Bit Parallel Data Bus Digital Output Bit 9
16-Bit Parallel Data Bus Digital Output Bit 8
Digital Ground
2
2
2
3
3
3
4
4
4
5
5
5
6
6
6
7
8, 22, 59
9, 21, 60
10
7
8, 22, 59
9, 21, 60
10
7
8, 22, 59
9, 21, 60
10
DB8
DGND
DV
Digital Supply. Bypass to DGND with a 0.µF capacitor at each DVDD input.
16-Bit Parallel Data Bus Digital Output Bit 7
16-Bit Parallel Data Bus Digital Output Bit 6
16-Bit Parallel Data Bus Digital Output Bit 5
16-Bit Parallel Data Bus Digital Output Bit 4
DD
DB7
DB6
DB5
DB4
11
11
11
12
12
12
13
13
13
14
14
14
DB3/CR3 16-Bit Parallel Data Bus Digital Output Bit 3/Configuration Register Input Bit 3
DB2/CR2 16-Bit Parallel Data Bus Digital Output Bit 2/Configuration Register Input Bit 2
DB1/CR1 16-Bit Parallel Data Bus Digital Output Bit 1/Configuration Register Input Bit 1
DB0/CR0 16-Bit Parallel Data Bus Digital Output Bit 0/Configuration Register Input Bit 0
15
15
15
16
16
16
17
17
17
______________________________________________________________________________________ 11
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
Pin Description (continued)
PIN
NAME
FUNCTION
MAX11047 MAX11048 MAX11049
(TQFP-EP) (TQFP-EP) (TQFP-EP)
Active-Low, End-of-Conversion Output. EOC goes low when a conversion is
completed. EOC goes high when a conversion is initiated.
18
19
18
19
18
19
EOC
Convert Start Input. The rising edge of CONVST ends sample and starts a
conversion on the captured sample. The ADC is in acquisition mode when
CONVST is low and CONVST mode = 0.
CONVST
Shutdown Input. If SHDN is held high, the entire device enters and stays in a
low-current state. Contents of the Configuration register are not lost when in
the shutdown state.
20
20
20
SHDN
23, 28, 32, 23, 28, 32, 23, 28, 32,
38, 43, 49, 38, 43, 49, 38, 43, 49,
AGNDS
Signal Ground. Connect all AGND and AGNDS inputs together.
53, 58
24, 29, 35, 24, 29, 35, 24, 29, 35,
46, 52, 57 46, 52, 57 46, 52, 57
25, 30, 36, 25, 30, 36, 25, 30, 36,
53, 58
53, 58
Analog Supply Input. Bypass AVDD to AGND with a 0.1µF capacitor at each
AVDD input.
AV
DD
AGND
Analog Ground. Connect all AGND inputs together.
45, 51, 56
45, 51, 56
45, 51, 56
26, 55
26, 55
26, 55
RDC_SENSE Reference Buffer Sense Feedback. Connect to RDC plane.
Reference Buffer Decoupling. Connect all RDC outputs together. Bypass to
27, 33, 40, 27, 33, 40, 27, 33, 40,
48, 54
RDC
AGND with at least an 80µF total capacitance. See the Layout, Grounding,
and Bypassing section.
48, 54
48, 54
31, 34,
47, 50
31, 50
—
I.C.
Internally Connected. Connect to AGND.
37
39
34
37
31
34
CH0
CH1
Channel 0 Analog Input
Channel 1 Analog Input
External Reference Input/Internal Reference Output. Place a 0.1µF capacitor
from REFIO to AGND.
41
41
41
REFIO
42
44
—
—
—
—
39
42
44
47
—
—
37
39
42
44
47
50
CH2
CH3
CH4
CH5
CH6
CH7
Channel 2 Analog Input
Channel 3 Analog Input
Channel 4 Analog Input
Channel 5 Analog Input
Channel 6 Analog Input
Channel 7 Analog Input
Active-Low Write Input. Drive WR low to write to the ADC. Configuration
registers are loaded on the rising edge of WR.
61
62
61
62
61
62
WR
CS
4/7–MAX1059
Active-Low Chip-Select Input. Drive CS low when reading from or writing to
the ADC.
Active-Low Read Input. Drive RD low to read from the ADC. Each rising edge
of RD advances the channel output on the data bus.
63
64
63
64
63
64
RD
DB15
16-Bit Parallel Data Bus Digital Out Bit 15
Exposed Pad. Internally connected to AGND. Connect to a large ground
plane to maximize thermal performance. Not intended as an electrical
connection point.
—
—
—
EP
12 ______________________________________________________________________________________
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
4/7–MAX1059
Pin Description (continued)
PIN
NAME
FUNCTION
MAX11057 MAX11058 MAX11059
(TQFP-EP) (TQFP-EP) (TQFP-EP)
1
1
1
DB12
DB11
DB10
DB9
14-Bit Parallel Data Bus Digital Output Bit 12
14-Bit Parallel Data Bus Digital Output Bit 11
14-Bit Parallel Data Bus Digital Output Bit 10
14-Bit Parallel Data Bus Digital Output Bit 9
14-Bit Parallel Data Bus Digital Output Bit 8
14-Bit Parallel Data Bus Digital Output Bit 7
14-Bit Parallel Data Bus Digital Output Bit 6
Digital Ground
2
2
2
3
3
3
4
4
4
5
5
5
DB8
6
6
6
DB7
7
8, 22, 59
9, 21, 60
10
7
8, 22, 59
9, 21, 60
10
7
8, 22, 59
9, 21, 60
10
DB6
DGND
DV
Digital Supply. Bypass to DGND with a 0.1µF capacitor at each DVDD input.
14-Bit Parallel Data Bus Digital Output Bit 5
14-Bit Parallel Data Bus Digital Output Bit 4
14-Bit Parallel Data Bus Digital Output Bit 3
14-Bit Parallel Data Bus Digital Output Bit 2
DD
DB5
DB4
DB3
DB2
11
11
11
12
12
12
13
13
13
14
14
14
DB1/CR3 14-Bit Parallel Data Bus Digital Output Bit 1/Configuration Register Input Bit 3
DB0/CR2 14-Bit Parallel Data Bus Digital Output Bit 0/Configuration Register Input Bit 2
15
15
15
16
16
16
CR1
CR0
Configuration Register Input Bit 1
Configuration Register Input Bit 0
17
17
17
Active-Low, End-of-Conversion Output. EOC goes low when a conversion is
completed. EOC goes high when a conversion is initiated.
18
18
18
EOC
Convert Start Input. The rising edge of CONVST ends sample and starts a
conversion on the captured sample. The ADC is in acquisition mode when
CONVST is low and CONVST mode = 0.
19
19
19
CONVST
Shutdown Input. If SHDN is held high, the entire device enters and stays in a
low-current state. Contents of the Configuration register are not lost when in
the shutdown state.
20
20
20
SHDN
23, 28, 32, 23, 28, 32, 23, 28, 32,
38, 43, 49, 38, 43, 49, 38, 43, 49,
AGNDS
Signal Ground. Connect all AGND and AGNDS inputs together.
53, 58
24, 29, 35, 24, 29, 35, 24, 29, 35,
46, 52, 57 46, 52, 57 46, 52, 57
25, 30, 36, 25, 30, 36, 25, 30, 36,
53, 58
53, 58
Analog Supply Input. Bypass AVDD to AGND with a 0.1µF capacitor at each
AVDD input.
AV
DD
AGND
Analog Ground. Connect all AGND inputs together.
45, 51, 56
45, 51, 56
45, 51, 56
26, 55
26, 55
26, 55
RDC_SENSE Reference Buffer Sense Feedback. Connect to RDC plane.
Reference Buffer Decoupling. Connect all RDC outputs together. Bypass to
27, 33,
40,48, 54
27, 33,
40,48, 54
27, 33,
40,48, 54
RDC
AGND with at least an 80µF total capacitance. See the Layout, Grounding,
and Bypassing section.
31, 34,
47, 50
31, 50
—
I.C.
Internally Connected. Connect to AGND.
37
39
34
37
31
34
CH0
CH1
Channel 0 Analog Input
Channel 1 Analog Input
______________________________________________________________________________________ 13
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
Pin Description (continued)
PIN
NAME
FUNCTION
MAX11057 MAX11058 MAX11059
(TQFP-EP) (TQFP-EP) (TQFP-EP)
External Reference Input/Internal Reference Output. Place a 0.1µF capacitor
from REFIO to AGND.
41
41
41
REFIO
42
44
—
—
—
—
39
42
44
47
—
—
37
39
42
44
47
50
CH2
CH3
CH4
CH5
CH6
CH7
Channel 2 Analog Input
Channel 3 Analog Input
Channel 4 Analog Input
Channel 5 Analog Input
Channel 6 Analog Input
Channel 7 Analog Input
Active-Low Write Input. Drive WR low to write to the ADC. Configuration
registers are loaded on the rising edge of WR.
61
62
61
62
61
62
WR
CS
Active-Low Chip-Select Input. Drive CS low when reading from or writing to
the ADC.
Active-Low Read Input. Drive RD low to read from the ADC. Each rising edge
of RD advances the channel output on the data bus.
63
64
63
64
63
64
RD
DB13
14-Bit Parallel Data Bus Digital Out Bit 13
Exposed Pad. Internally connected to AGND. Connect to a large ground
plane to maximize thermal performance. Not intended as an electrical
connection point.
—
—
—
EP
data bus is bidirectional and allows for easy program-
Detailed Description
ming of the configuration register. The devices feature a
reference buffer, which is driven by an internal bandgap
The MAX11047/MAX11048/MAX11049 and MAX11057/
MAX11058/MAX11059 are fast, low-power ADCs that
combine 4, 6, or 8 independent ADC channels in a sin-
gle IC. Each channel includes simultaneously sampling
independent T/H circuitry that preserves relative phase
information between inputs making the devices ideal for
motor control and power monitoring. The devices are
available with a 0 to 5V input range that features
20mA overrange, fault-tolerant inputs. The devices
operate with a single 4.75V to 5.25V supply. A separate
2.7V to 5.25V supply for digital circuitry makes the
devices compatible with low-voltage processors.
reference circuit (V
= 4.096V). Drive REFIO with an
REFIO
external reference or bypass with a 0.1µF capacitor to
ground when using the internal reference.
Analog Inputs
Track and Hold (T/H)
To preserve phase information across all channels,
each input includes a dedicated T/H circuitry. The input
tracking circuitry provides a 4MHz small-signal band-
width, enabling the device to digitize high-speed tran-
sient events and measure periodic signals with
bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. Use anti-alias filtering
to avoid high-frequency signals being aliased into the
frequency band of interest.
4/7–MAX1059
The devices perform conversions for all channels in paral-
lel by activating independent ADCs. Results are available
through a high-speed, 20MHz, parallel data bus after a
conversion time of 3µs following the end of a sample. The
14 ______________________________________________________________________________________
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
4/7–MAX1059
of 0V to +V
, the clamps begin to turn on.
Input Range and Protection
The full-scale analog input voltage is a product of the
reference voltage. For the devices, the input is unipolar
in the range of:
AVDD
Consequently, to obtain the highest accuracy, ensure
that the input voltage does not exceed the range of 0V
to +V
.
AVDD
To make use of the input clamps, connect a resistor
5.0
4.096
(R ) between the analog input and the voltage source
S
0 to +V
x
REFIO
to limit the voltage at the analog input so that the fault
current into the devices does not exceed 20mA. Note
that the voltage at the analog input pin limits to approxi-
mately 7V during a fault condition so the following
In external reference mode, drive V
with a 3.0V to
REFIO
4.25V source, resulting in a full-scale input range of
3.662V to 5.188V, respectively.
equation can be used to calculate the value of R :
S
All analog inputs are fault-protected up to 20mA. The
devices include an input clamping circuit that activates
when the input voltage at the analog input is above
V
− 7V
FAULT_MAX
R
=
S
20mA
(V
+ 300mV) or below -300mV. The clamp circuit
AVDD
where V
is the maximum voltage that the
source produces during a fault condition.
FAULT_MAX
remains high impedance while the input signal is within
the range of 0V to +V
and draws little to no cur-
AVDD
rent. However, when the input signal exceeds the range
PIN
VOLTAGE
INPUT
SIGNAL
DVDD
AVDD
DB15**
R
S
CH0
16-/14-BIT ADC
S/H
S/H
CLAMP
CLAMP
SOURCE
DB4
DB3/CR3
†
DB0/CR0
CH7
16-/14-BIT ADC
CONFIGURATION
REGISTERS
WRb
AGNDS
AGND
RDb
CSb
INTERFACE
AND
CONTROL
CONVST
SHDN
EOCb
MAX11047/MAX11048/MAX11049/
MAX11057/MAX11058/MAX11059
INT REF
DGND
RDC
10kΩ
BANDGAP
REFERENCE
REF
BUF
EXT REF
REFIO
RDC_SENSE*
†
*CONNECTED INTERNALLY ON THE TQFN PARTS
**MAX11047/MAX11048/MAX11049
MAX11049/MAX11059
Figure 1. Required Setup for Clamp Circuit
______________________________________________________________________________________ 15
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
25
20
15
10
5
25
R
V
= 1170I
R
V
= 1170I
S
S
20
15
10
5
= 5.0V
= 5.0V
AVDD
AVDD
AT CH_ INPUT
AT SOURCE
AT CH_ INPUT
AT SOURCE
0
0
-5
-5
-10
-15
-20
-25
-10
-15
-20
-25
-30 -20 -10
0
10
20
30
40
-4
-2
0
2
4
6
8
SIGNAL VOLTAGE AT SOURCE AND CH_ INPUT (V)
SIGNAL VOLTAGE AT SOURCE AND CH_ INPUT (V)
Figure 2. Input Clamp Characteristics
Figure 3. Input Clamp Characteristics (Zoom In)
Figures 2 and 3 illustrate the clamp circuit voltage-cur-
CR1 (Reserved)
rent characteristics for a source impedance R
=
CR1 must be set to 0.
S
1280Ω. While the input voltage is within the -300mV to
CR0 (CONVST Mode)
CR0 selects the acquisition mode. The POR default = 0.
+(V + 300mV) range, no current flows in the input
AVDD
clamps. Once the input voltage goes beyond this volt-
age range, the clamps turn on and limit the voltage at
the input pin.
0 = CONVST controls the acquisition and conversion.
Drive CONVST low to start acquisition. The rising edge
of CONVST begins the conversion.
Applications Information
1 = acquisition mode starts as soon as previous con-
version is complete. The rising edge of CONVST begins
the conversion.
Digital Interface
The bidirectional, parallel, digital interface, CR0–CR3,
sets the 4-bit configuration register. This interface
configures the following control signals: chip select
(CS), read (RD), write (WR), end of conversion (EOC),
and convert start (CONVST). Figures 6 and 7 and the
Timing Characteristics in the Electrical Characteristics
table show the operation of the interface.
Programming the Configuration Register
To program the configuration register, bring the CS and
WR low and apply the required configuration data on
CR3–CR0 of the bus and then raise WR once to save
changes.
CAUTION: The host driving CR3–CR0 must relin-
quish the bus when the conversion results of the
ADC are being read.
DB0–DB15/13, output the 16-/14-bit conversion result.
All bits are high impedance when RD = 1 or CS = 1.
CR3 (Int/Ext Reference)
CR3 selects the internal or external reference. The POR
default = 0.
Starting a Conversion
CONVST initiates conversions. The devices provide two
acquisition modes set through the configuration regis-
ter. Allow a quiet time (t ) of 500ns prior to the start of
Q
conversion to avoid any noise interference during read-
out or write operations from corrupting a sample.
0 = internal reference, REFIO internally driven through a
10kΩ resistor, bypass with 0.1µF capacitor to AGND.
1 = external reference, drive REFIO with a high quality
reference.
4/7–MAX1059
Table 1. Configuration Register
CR2 (Output Data Format)
CR2 selects the output data format. The POR default = 0.
CR3
CR2
CR1
CR0
0 = offset binary.
Int/Ext
Reference
Output
Data Format
Must be set
to 0
CONVST
Mode
1 = two’s complement.
16 ______________________________________________________________________________________
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
4/7–MAX1059
In default mode (CR0 = 0), drive CONVST low to place
together. The reference buffer is externally compensat-
ed and requires at least 10µF on the RDC node for sta-
bility. For best performance, provide a total of at least
80µF on the RDC outputs.
the devices into acquisition mode. All the input switch-
es are closed and the internal T/H circuits track the
respective input voltage. Keep the CONVST signal low
for at least 1µs (t
) to enable proper settling of the
ACQ
Transfer Functions
Figures 8 and 9 show the transfer functions for all the
formats and devices. Code transitions occur halfway
between successive-integer LSB values.
sampled voltages. On the rising edge of CONVST, the
switches are opened and the devices begin the conver-
sion on all the samples in parallel. EOC remains high
until the conversion is completed.
In the second mode (CR0 = 1), the devices enter acqui-
sition mode as soon as the previous conversion is com-
pleted. CONVST rising edge initiates the next sample
and conversion sequence. Drive CONVST low for at least
20ns to be valid.
Layout, Grounding, and Bypassing
For best performance, use PCBs with ground planes.
Ensure that digital and analog signal lines are separated
from each other. Do not run analog and digital lines par-
allel to one another (especially clock lines), and avoid
running digital lines underneath the ADC package. A
single solid GND plane configuration with digital signals
routed from one direction and analog signals from the
other provides the best performance. Connect DGND,
AGND, and AGNDS pins on the devices to this ground
plane. Keep the ground return to the power supply for
this ground low impedance and as short as possible for
noise-free operation.
Provide adequate time for acquisition and the requisite
quiet time in both modes to achieve accurate sampling
and maximum performance of the devices.
Reading Conversion Results
The CS and RD are active-low, digital inputs that control
the readout through the 16-/14-bit, parallel, 20MHz data
bus (D0–D15/13). After EOC transitions low, read the
conversion data by driving CS and RD low. Each low
period of RD presents the next channel’s result. When
CS or RD are high, the data bus is high impedance. CS
may be driven high between individual channel read-
outs or left low during the entire 8-channel readout.
To achieve the highest performance, connect all the
RDC pins 22, 28, 35, 43, and 49 for the TQFN package
or pins 27, 33, 40, 48, and 54 for the TQFP package to
a local RDC plane on the PCB. In addition, on the TQFP
package, the RDC_SENSE pins 26 and 55 should be
directly connected to this RDC plane as well. Bypass
the RDC outputs with a total of at least 80µF of capaci-
tance. For example, if two capacitors are used, place
two 47µF, 10V X5R capacitors in 1210 case size as
close as possible to pins 22 and 49 (TQFN), or pins 27
and 54 (TQFP). Alternatively, if four capacitors are
used, place four 22µF, 10V X5R capacitors in 1210
case size as close as possible to pins 22, 28, 43, and
49 (TQFN), or pins 27, 33, 48, and 54 (TQFP). Ensure
that each capacitor is connected directly into the GND
plane with an independent via.
Reference
Internal Reference
The devices feature a precision, low-drift, internal
bandgap reference. Bypass REFIO with a 0.1µF capaci-
tor to AGND to reduce noise. The REFIO output voltage
may be used as a reference for other circuits. The output
impedance of REFIO is 10kΩ. Drive only high-impedance
circuits or buffer externally when using REFIO to drive
external circuitry.
External Reference
Set the configuration register to disable the internal ref-
erence and drive REFIO with a high-quality external ref-
erence. To avoid signal degradation, ensure that the
integrated reference noise applied to REFIO is less
than 10µV in the bandwidth of up to 50kHz.
In cases where Y5U or Z5U ceramics are used, select
higher voltage rating capacitors to compensate for the
high-voltage coefficient of these ceramic capacitors,
thus ensuring that at least 80µF of capacitance is on
the RDC plane when the plane is driven to 4.096V by
the internal reference buffer. For example, at 4.096V, a
22µF X5R ceramic capacitor with a 10V rating diminish-
es to only 20µF, whereas the same capacitor in Y5U
ceramic at 4.096V decreases to about 13µF. However,
a 22µF Y5U ceramic capacitor with a 25V rating capac-
itor is approximately 20µF at 4.096V.
Reference Buffer
The devices have a built- in reference buffer to provide
a low-impedance reference source to the SAR convert-
ers. This buffer is used in both internal and external ref-
erence modes. The internal reference buffer output
feeds five RDC outputs. Connect all RDC outputs
______________________________________________________________________________________ 17
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
Bypass AVDD and DVDD to the ground plane with
0.1µF ceramic chip capacitors on each pin as close as
possible to the device to minimize parasitic inductance.
Add at least one bulk 10µF decoupling capacitor to
AVDD and DVDD per PCB. Interconnect all of the
AVDD inputs and DVDD inputs using two solid power
planes. For best performance, bring the AVDD power
plane in on the analog interface side of the devices and
the DVDD power plane from the digital interface side of
the devices.
For sampling periods near minimum (1µs) use a 1nF
C0G ceramic chip capacitor between each of the chan-
nel inputs to the ground plane as close as possible to the
devices. This capacitor reduces the inductance seen by
the sampling circuitry and reduces the voltage transient
seen by the input source circuit.
CS
(USER SUPPLIED)
t
5
t
t
4
3
WR
(USER SUPPLIED)
t
7
t
6
CONFIGURATION
REGISTER
CR0–CR3
(USER SUPPLIED)
Figure 4. Programming Configuration-Register Timing Requirements
CS
(USER SUPPLIED)
t
10
t
t
t
8
9
11
RD
(USER SUPPLIED)
t
13
t
12
4/7–MAX1059
S
n
S
n + 1
DB0–DB15
Figure 5. Readout Timing Requirements
18 ______________________________________________________________________________________
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
4/7–MAX1059
SAMPLE
t
t
CON
ACQ
CONVST
EOC
t
1
t
O
t
Q
CS
RD
DB0–DB15
S
S
S
S
7
0
1
6
Figure 6. Conversion Timing Diagram (CR0 = 0)
SAMPLE
t
t
CON
ACQ
CONVST
EOC
t
2
t
O
t
Q
CS
RD
DB0–DB15
S
S
S
S
7
0
1
6
Figure 7. Conversion Timing Diagram (CR0 = 1)
______________________________________________________________________________________ 19
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
FS
65536
FULL-SCALE
TRANSITION
FS
16384
FULL-SCALE
TRANSITION
7FFF
7FFE
1FFF
1FFE
V
LSB
=
V
LSB
=
0001
0000
FFFF
FFFE
0001
0000
3FFF
3FFE
8001
8000
2001
2000
0
FS/2
INPUT VOLTAGE (LSB)
0
FS/2
INPUT VOLTAGE (LSB)
+FS
+FS
V
x 65536
5
4.096
5 x V
V
x 16384
5
4.096
5 x V
REF
IN
REF
IN
OUTPUT CODE =
- 32768, FS =
OUTPUT CODE =
- 8192, FS =
4.096
4.096
V
REFIO
x
V
REFIO
x
Figure 8a. Two’s Complement Transfer Function for 16-Bit
Devices
Figure 8b. Two’s Complement Transfer Function for 14-Bit
Devices
FS
65536
FULL-SCALE
TRANSITION
FS
16384
FULL-SCALE
TRANSITION
FFFF
FFFE
3FFF
3FFE
V
LSB
=
V
LSB
=
8001
8000
7FFF
7FFE
2001
2000
1FFF
1FFE
0001
0000
0001
0000
4/7–MAX1059
0
FS/2
+FS
0
FS/2
+FS
INPUT VOLTAGE (LSB)
INPUT VOLTAGE (LSB)
V
x 65536
5
4.096
5 x V
4.096
V
x 16384
5
4.096
5 x V
REF
4.096
IN
REF
IN
OUTPUT CODE =
,
FS =
OUTPUT CODE =
,
FS =
V
x
V
x
REFIO
REFIO
Figure 9a. Offset-Binary Transfer Function for 16-Bit Devices
Figure 9b. Offset-Binary Transfer Function for 14-Bit Devices
20 ______________________________________________________________________________________
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
4/7–MAX1059
DSP Motor Control
Figure 11 shows a typical DSP motor control application.
Typical Application Circuits
Power-Grid Protection
Figure 10 shows a typical power-grid protection application.
VOLTAGE
TRANSFORMER
PHASE 1
OPT
2.5V
ADC
OPT
ADC
CURRENT
TRANSFORMER
2.5V
VN
IN
ADC
ADC
NEUTRAL
LOAD 1
MAX11049
MAX11059
LOAD 2
LOAD 3
I3
ADC
V3
ADC
I2
PHASE 2
V2
ADC
ADC
PHASE 3
Figure 10. Power-Grid Protection
______________________________________________________________________________________ 21
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
DSP-BASED DIGITAL
PROCESSING ENGINE
MAX1104x
MAX1105x
16-/14-BIT
ADCs
IGBT CURRENT DRIVERS
16-/14-BIT
ADCs
16-/14-BIT
ADCs
16-/14-BIT
ADCs
16-/14-BIT
ADCs
I
PHASE1
I
PHASE3
I
PHASE2
3-PHASE ELECTRIC MOTOR
POSITION
ENCODER
Figure 11. DSP Motor Control
4/7–MAX1059
22 ______________________________________________________________________________________
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
4/7–MAX1059
complement mode and 0x0000 to 0x0001 in offset
binary mode. For the devices, the analog input voltage
to produce these code transitions is measured and the
Definitions
Integral Nonlinearity (INL)
INL is the deviation of the values on an actual transfer
function from a straight line. For these devices, this
straight line is a line drawn between the end points of
the transfer function, once offset and gain errors have
been nullified.
gain error is computed by subtracting (5/4.096) x V
REF
x (65,534/65,536) or (5/4.096) x V
x (16382/16384),
REF
respectively, from this measurement.
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, SNR is the ratio of the full-scale analog input
(RMS value) to the RMS quantization error (residual
error). The ideal, theoretical minimum analog-to-digital
noise is caused by quantization noise error only and
results directly from the ADC’s resolution (N bits):
Differential Nonlinearity (DNL)
DNL is the difference between an actual step width and
the ideal value of 1 LSB. For these devices, the DNL of
each digital output code is measured and the worst-case
value is reported in the Electrical Characteristics table. A
DNL error specification of greater than -1 LSB guaran-
tees no missing codes and a monotonic transfer function
for an SAR ADC. For example, -0.9 LSB guarantees no
missing code while -1.1 LSB results in missing code.
SNR = (6.02 x N + 1.76)dB
where N = 16/14 bits. In reality, there are other noise
sources besides quantization noise: thermal noise, ref-
erence noise, clock jitter, etc. SNR is computed by tak-
ing the ratio of the RMS signal to the RMS noise, which
includes all spectral components not including the fun-
damental, the first five harmonics, and the DC offset.
Offset Error
For the MAX11047/MAX11048/MAX11049, the offset
error is defined at code transition 0x0000 to 0x0001 in
offset binary encoding and 0x8000 to 0x8001 for two’s
complement encoding. For the MAX11057/MAX11058/
MAX11059, the offset error is defined at code transition
0x0000 to 0x0001 in offset binary encoding and 0x2000
to 0x2001 for two’s complement encoding. The offset
code transitions should occur with an analog input volt-
Signal-to-Noise Plus Distortion (SINAD)
SINAD is the ratio of the fundamental input frequency’s
RMS amplitude to the RMS equivalent of all the other
ADC output signals:
⎡
⎢
⎣
⎤
⎥
⎦
Signal
(Noise + Distortion)
RMS
age of exactly 0.5 x (5/4.096) x V
/65,536 above
REF
SINAD(dB) = 10 × log
GND for 16-bit devices or 0.5 x (5/4.096) x V
/16384
REF
RMS
above GND for 14-bit devices. The offset error is
defined as the deviation between the actual analog
input voltage required to produce the offset code transi-
tion and the ideal analog input of 0.5 x (5/4.096) x
Effective Number of Bits (ENOB)
The ENOB indicates the global accuracy of an ADC at
a specific input frequency and sampling rate. An ideal
ADC’s error consists of quantization noise only. With an
input range equal to the full-scale range of the ADC,
calculate the ENOB as follows:
V
/65,536 above GND for 16-bit devices or 0.5 x
REF
(5/4.096) x V
/16384 above GND for 14-bit devices,
REF
expressed in LSBs.
Gain Error
SINAD − 1.76
Gain error is defined as the difference between the
change in analog input voltage required to produce a
top code transition minus a bottom code transition,
subtracted from the ideal change in analog input volt-
ENOB =
6.02
Total Harmonic Distortion (THD)
THD is the ratio of the RMS of the first five harmonics of
the input signal to the fundamental itself. This is
expressed as:
age on (5/4.096) x V
x (65,534/65,536) for 16-bit or
x (16382/16384) for 14-bit devices.
REF
(5/4.096) x V
REF
For the devices, top code transition is 0x7FFE to
0x7FFF in two’s complement mode and 0xFFFE to
0xFFFF in offset binary mode. The bottom code transi-
tion is 0x8000 and 0x8001 in two’s complement mode
and 0x0000 and 0x0001 in offset binary mode. For the
MAX11057/MAX11058/MAX11059, top code transition
is 0x1FFE to 0x1FFF in two’s complement mode and
0x3FFE to 0x3FFF in offset binary mode. The bottom
code transition is 0x2000 and 0x2001 in two’s
⎡
⎢
⎤
⎥
2
2
2
2
V2 + V3 + V4 + V5
THD = 20 × log
V
⎢
⎣
⎥
⎦
1
where V is the fundamental amplitude and V through
V are the 2nd- through 5th-order harmonics.
1
2
5
______________________________________________________________________________________ 23
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
Spurious-Free Dynamic Range (SFDR)
Full-Power Bandwidth
SFDR is the ratio of the RMS amplitude of the funda-
mental (maximum signal component) to the RMS value
of the next-largest frequency component.
A large -0.5dBFS analog input signal is applied to an
ADC, and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by 3dB. This point is defined as full-
power input bandwidth frequency.
Aperture Delay
Aperture delay (t ) is the time delay from the sampling
AD
clock edge to the instant when an actual sample is taken.
Chip Information
Aperture Jitter
PROCESS: BiCMOS
Aperture Jitter (t ) is the sample-to-sample variation in
AJ
aperture delay.
Channel-to-Channel Isolation
Channel-to-channel isolation indicates how well each
analog input is isolated from the other channels. Channel-
to-channel isolation is measured by applying DC to chan-
nels 1 to 7, while a -0.4dBFS sine wave at 60Hz is applied
to channel 0. A 10ksps FFT is taken for channel 0 and
channel 1. Channel-to-channel isolation is expressed in
dB as the power ratio of the two 60Hz magnitudes.
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
Small-Signal Bandwidth
A small -20dBFS analog input signal is applied to an
ADC in a manner that ensures that the signal’s slew
rate does not limit the ADC’s performance. The input
frequency is then swept up to the point where the
amplitude of the digitized conversion result has
decreased 3dB.
56 TQFN-EP
64 TQFP-EP
T5688+2
C64E+6
21-0135
21-0084
90-0046
90-0328
4/7–MAX1059
24 ______________________________________________________________________________________
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
4/7–MAX1059
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
0
1
12/09
6/10
Initial release
—
Released MAX11047, MAX11048, and MAX11049 in TQFP packages
1–20
Released MAX11057, MAX11058, and MAX11059. Updated Electrical
Characteristics and Typical Operating Characteristics.
2
1/11
1–8
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 25
© 2011 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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