MAX1040_08 [MAXIM]
10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports; 10位，多通道ADC / DAC，带有FIFO ，温度传感器和GPIO端口
| 型号： | MAX1040_08 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports |
| 文件： | 总39页 (文件大小：406K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3294; Rev 3; 3/08
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
26/MAX1048
General Description
Features
♦ 10-Bit, 225ksps ADC
The MAX1040/MAX1042/MAX1046/MAX1048 integrate a
multichannel, 10-bit, analog-to-digital converter (ADC)
and a quad, 10-bit, digital-to-analog converter (DAC) in a
single IC. The devices also include a temperature sensor
and configurable general-purpose I/O ports (GPIOs) with
a 25MHz SPI™-/QSPI™-/MICROWIRE™-compatible seri-
al interface. The ADC is available in a four or an eight
input-channel version. The four DAC outputs settle within
2.0µs, and the ADC has a 225ksps conversion rate.
Analog Multiplexer with True-Differential
Track/Hold (T/H)
Eight Single-Ended Channels or Four
Differential
Channels (Unipolar or Bipolar)
(MAX1040/MAX1042)
Four Single-Ended Channels or Two Differential
Channels (Unipolar or Bipolar)
(MAX1046/MAX1048)
Excellent Accuracy: 0ꢀ5 ꢁSB ꢂIꢁ, 0ꢀ5 ꢁSB
DIꢁ, Io Missing Codes Over Temperature
All devices include an internal reference (4.096V) provid-
ing a well-regulated, low-noise reference for both the
ADC and DAC. Programmable reference modes for the
ADC and DAC allow the use of an internal reference, an
external reference, or a combination of both. Features
such as an internal 1ꢀC accurate temperature sensor,
FIFO, scan modes, programmable internal or external
clock modes, data averaging, and AutoShutdown™ allow
users to minimize both power consumption and proces-
sor requirements. The low glitch energy (4nV•s) and low
digital feedthrough (0.5nV•s) of the integrated quad
DACs make these devices ideal for digital control of fast-
response closed-loop systems.
♦ 10-Bit, Quad, 2µs Settling DAC
Ultra-ꢁow-Glitch Energy (4nV•s)
Power-Up Options from Zero Scale or Full Scale
Excellent Accuracy: 0ꢀ5 ꢁSB ꢂIꢁ
♦ ꢂnternal Reference or External Single-Ended/
Differential Reference
ꢂnternal Reference Voltage (4ꢀ096V)
♦ ꢂnternal 1ꢃC Accurate Temperature Sensor
♦ On-Chip FꢂFO Capable of Storing 16 ADC
Conversion Results and One Temperature Result
♦ On-Chip Channel-Scan Mode and ꢂnternal
Data-Averaging Features
The devices are guaranteed to operate with a supply volt-
age from +4.75V to +5.25V. These devices consume
2.5mA at 225ksps throughput, only 22µA at 1ksps
throughput, and under 0.2µA in the shutdown mode. The
MAX1042/MAX1048 offer four GPIOs that can be config-
ured as inputs or outputs.
♦ Analog Single-Supply Operation: +4ꢀ75V to +5ꢀ25V
♦ Digital Supply: +2ꢀ7V to AV
DD
♦ 25MHz, SPꢂ/QSPꢂ/MꢂCROWꢂRE Serial ꢂnterface
♦ AutoShutdown Between Conversions
♦ ꢁow-Power ADC
2ꢀ5mA at 225ksps
22µA at 1ksps
The MAX1040/MAX1042/MAX1046/MAX1048 are avail-
able in 36-pin thin QFN packages. All devices are speci-
fied over the -40ꢀC to +85ꢀC temperature range.
0ꢀ2µA at Shutdown
♦ ꢁow-Power DAC: 1ꢀ5mA
Applications
♦ Evaluation Kit Available (Order MAX1258EVKꢂT)
Closed-Loop Controls for Optical Components
and Base Stations
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
System Supervision and Control
Data-Acquisition Systems
Pin Configurations appear at end of data sheetꢀ
Ordering Information/Selector Guide
REF
VOꢁTAGE (V)
AIAꢁOG SUPPꢁY RESOꢁUTꢂOI
ADC
CHAIIEꢁS
DAC
CHAIIEꢁS
PART
PꢂI-PACKAGE
GPꢂOs
VOꢁTAGE (V)
BꢂTS**
MAX1040BETX
MAX1042BETX
MAX1046BETX
MAX1048BETX
36 Thin QFN-EP*
36 Thin QFN-EP*
36 Thin QFN-EP*
36 Thin QFN-EP*
4.096
4.096
4.096
4.096
4.75 to 5.25
4.75 to 5.25
4.75 to 5.25
4.75 to 5.25
10
10
10
10
8
8
4
4
4
4
4
4
0
4
0
4
Iote: All devices are specified over the -40ꢀC to +85ꢀC operating temperature range.
*EP = Exposed pad.
**Number of resolution bits refers to both DAC and ADC.
________________________________________________________________ Maxim ꢂntegrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at wwwꢀmaxim-icꢀcomꢀ
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
ABSOꢁUTE MAXꢂMUM RATꢂIGS
AV
to AGND .........................................................-0.3V to +6V
Maximum Current into OUT_.............................................100mA
DD
DGND to AGND.....................................................-0.3V to +0.3V
DV to AV .......................................................-3.0V to +0.3V
Digital Inputs to DGND.............................................-0.3V to +6V
Continuous Power Dissipation (T = +70ꢀC)
36-Pin Thin QFN (6mm x 6mm)
(derate 26.3mW/ꢀC above +70ꢀC)..........................2105.3mW
Operating Temperature Range ...........................-40ꢀC to +85ꢀC
Storage Temperature Range.............................-60ꢀC to +150ꢀC
Junction Temperature......................................................+150ꢀC
Lead Temperature (soldering, 10s) .................................+300ꢀC
A
DD
DD
Digital Outputs to DGND .........................-0.3V to (DV + 0.3V)
DD
Analog Inputs, Analog Outputs and REF_
to AGND...............................................-0.3V to (AV + 0.3V)
DD
Maximum Current into Any Pin (except AGND, DGND, AV
,
DD
DV , and OUT_) ...........................................................50mA
DD
Iote: If the package power dissipation is not exceeded, one output at a time can be shorted to AV , DV , AGND, or DGND
DD
DD
indefinitely.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
EꢁECTRꢂCAꢁ CHARACTERꢂSTꢂCS
(AV
= DV
= 4.75V to 5.25V, external reference V
= 4.096V, f = 3.6MHz (50% duty cycle), T = -40ꢀC to +85ꢀC, unless
CLK A
DD
DD
REF
otherwise noted. Typical values are at AV
= DV
= 5V, T = +25ꢀC. Outputs are unloaded, unless otherwise noted.)
DD A
DD
PARAMETER
SYMBOꢁ
COIDꢂTꢂOIS
ADC
MꢂI
TYP
MAX
UIꢂTS
DC ACCURACY (Iote 1)
Resolution
10
Bits
LSB
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
0.5
0.5
1.0
1
DNL
LSB
0.25
0.025
1.4
2.0
2.0
LSB
Gain Error
(Note 2)
LSB
Gain Temperature Coefficient
Channel-to-Channel Offset
ppm/ꢀC
LSB
0.1
DYIAMꢂC SPECꢂFꢂCATꢂOIS (10kHz sine-wave input, V = 4ꢀ096V
225ksps, f = 3ꢀ6MHz)
CꢁK
ꢂI
P-P,
Signal-to-Noise Plus Distortion
SINAD
61
dB
Total Harmonic Distortion
(Up to the Fifth Harmonic)
THD
-70
dBc
26/MAX1048
Spurious-Free Dynamic Range
Intermodulation Distortion
Full-Linear Bandwidth
SFDR
IMD
66
72
100
1
dBc
dBc
kHz
f
= 9.9kHz, f
= 10.2kHz
IN1
IN2
SINAD > 70dB
-3dB point
Full-Power Bandwidth
MHz
COIVERSꢂOI RATE (Iote 3)
External reference
0.8
µs
Conversion
clock
Power-Up Time
t
PU
Internal reference (Note 4)
218
cycles
2
_______________________________________________________________________________________
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
26/MAX1048
EꢁECTRꢂCAꢁ CHARACTERꢂSTꢂCS (continued)
(AV
= DV
= 4.75V to 5.25V, external reference V
= 4.096V, f
= 3.6MHz (50% duty cycle), T = -40ꢀC to +85ꢀC, unless
DD
DD
REF
CLK A
otherwise noted. Typical values are at AV
= DV
= 5V, T = +25ꢀC. Outputs are unloaded, unless otherwise noted.)
DD A
DD
PARAMETER
Acquisition Time
SYMBOꢁ
COIDꢂTꢂOIS
MꢂI
TYP
MAX
UIꢂTS
t
(Note 5)
0.6
µs
ACQ
Internally clocked
5.5
Conversion Time
t
µs
CONV
Externally clocked
3.6
0.1
40
External Clock Frequency
Duty Cycle
f
Externally clocked conversion (Note 5)
3.6
60
MHz
%
CLK
Aperture Delay
30
ns
Aperture Jitter
< 50
ps
AIAꢁOG ꢂIPUTS
Unipolar
Bipolar
0
V
REF
Input Voltage Range (Note 6)
V
-V
/ 2
+V
/ 2
REF
REF
1
Input Leakage Current
Input Capacitance
0.01
24
µA
pF
ꢂITERIAꢁ TEMPERATURE SEISOR
T
T
= +25ꢀC
0.7
1.0
1/8
A
Measurement Error (Notes 5, 7)
ꢀC
= T
to T
3.0
A
MIN
MAX
Temperature Resolution
ꢂITERIAꢁ REFEREICE
REF1 Output Voltage
ꢀC/LSB
(Note 8)
V
4.066
4.096
30
4.126
REF1 Voltage Temperature
Coefficient
TC
ppm/ꢀC
REF
REF1 Output Impedance
REF1 Short-Circuit Current
EXTERIAꢁ REFEREICE
6.5
kΩ
mA
V
= 4.096V
0.63
REF
AV
0.05
+
DD
REF1 Input Voltage Range
V
V
REF mode 11 (Note 4)
1
V
V
REF1
REF2
AV
+
DD
REF mode 01
REF mode 11
1
0
REF2 Input Voltage Range
(Note 4)
0.05
1
80
1
V
= 4.096V, f
= 225ksps
SAMPLE
40
REF
REF1 Input Current (Note 9)
REF2 Input Current
I
I
µA
µA
REF1
REF2
Acquisition between conversions
= 4.096V, f = 225ksps
0.01
40
V
80
1
REF
SAMPLE
Acquisition between conversions
0.01
_______________________________________________________________________________________
3
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
EꢁECTRꢂCAꢁ CHARACTERꢂSTꢂCS (continued)
(AV
= DV
= 4.75V to 5.25V, external reference V
= 4.096V, f
= 3.6MHz (50% duty cycle), T = -40ꢀC to +85ꢀC, unless
DD
DD
REF
CLK A
otherwise noted. Typical values are at AV
= DV
= 5V, T = +25ꢀC. Outputs are unloaded, unless otherwise noted.)
DD A
DD
PARAMETER
SYMBOꢁ
COIDꢂTꢂOIS
DAC
MꢂI
TYP
MAX
UIꢂTS
DC ACCURACY (Iote 10)
Resolution
10
Bits
LSB
LSB
mV
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
0.5
1
DNL
Guaranteed monotonic
0.5
10
V
3
10
1.25
8
OS
ppm of
FS/ꢀC
Offset-Error Drift
Gain Error
GE
10
LSB
ppm of
FS/ꢀC
Gain Temperature Coefficient
DAC OUTPUT
AV
0.02
-
-
DD
No load
0.02
0.1
Output Voltage Range
V
AV
DD
10kΩ load to either rail
0.1
DC Output Impedance
Capacitive Load
0.5
Ω
(Note 11)
1
nF
AV = 4.75V, V
DD
gain error < 2%
= 4.096V,
REF
Resistive Load to AGND
R
500
Ω
L
From power-down mode, AV
From power-down mode, AV
= 5V
25
21
1
DD
Wake-Up Time (Note 12)
1kΩ Output Termination
100kΩ Output Termination
µs
kΩ
kΩ
= 2.7V
DD
Programmed in power-down mode
At wake-up or programmed in
power-down mode
100
DYIAMꢂC PERFORMAICE (Iotes 5, 13)
Output-Voltage Slew Rate
Output-Voltage Settling Time
Digital Feedthrough
SR
Positive and negative
3
V/µs
µs
26/MAX1048
t
To 1 LSB, 400 - C00 hex (Note 7)
Code 0, all digital inputs from 0 to DV
2
5
S
0.5
nV•s
DD
Major Code Transition Glitch
Impulse
Between codes 2047 and 2048
4
nV•s
From V
660
720
260
320
REF
Output Noise (0.1Hz to 50MHz)
Output Noise (0.1Hz to 500kHz)
µV
µV
P-P
P-P
Using internal reference
From V
REF
Using internal reference
DAC-to-DAC Transition
Crosstalk
0.5
nV•s
4
_______________________________________________________________________________________
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
26/MAX1048
EꢁECTRꢂCAꢁ CHARACTERꢂSTꢂCS (continued)
(AV
= DV
= 4.75V to 5.25V, external reference V
= 4.096V, f
= 3.6MHz (50% duty cycle), T = -40ꢀC to +85ꢀC, unless
DD
DD
REF
CLK A
otherwise noted. Typical values are at AV
= DV
= 5V, T = +25ꢀC. Outputs are unloaded, unless otherwise noted.)
DD A
DD
PARAMETER
SYMBOꢁ
COIDꢂTꢂOIS
MꢂI
TYP
MAX
UIꢂTS
ꢂITERIAꢁ REFEREICE
REF1 Output Voltage
V
4.066
4.096
30
4.126
REF1 Temperature Coefficient
REF1 Short-Circuit Current
EXTERIAꢁ REFEREICE ꢂIPUT
REF1 Input Voltage Range
REF1 Input Impedance
TC
ppm/ꢀC
mA
REF
V
= 4.096V
0.63
REF
V
R
REF modes 01, 10, and 11 (Note 4)
0.7
70
AV
V
REF1
DD
100
130
kΩ
REF1
DꢂGꢂTAꢁ ꢂITERFACE
DꢂGꢂTAꢁ ꢂIPUTS (SCꢁK, DꢂI, CS, CNVST, LDAC)
DV = 2.7V to 5.25V
2.4
2.0
DD
Input-Voltage High
V
V
V
IH
DV = 3.6V to 5.25V
DD
DV = 2.7V to 3.6V
DD
0.8
0.6
0.5
10
Input-Voltage Low
V
DV = 3V to 3.6V
DD
IL
DV = 2.7V to 3V
DD
Input Leakage Current
Input Capacitance
I
0.01
15
µA
pF
L
C
IN
DꢂGꢂTAꢁ OUTPUT (DOUT) (Iote 14)
Output-Voltage Low
V
I
I
= 2mA
0.4
10
V
V
OL
SINK
DV
0.5
-
-
DD
Output-Voltage High
V
= 2mA
= 2mA
OH
SOURCE
Tri-State Leakage Current
µA
pF
Tri-State Output Capacitance
DꢂGꢂTAꢁ OUTPUT (EOC) (Iote 14)
Output-Voltage Low
C
15
15
OUT
V
I
I
= 2mA
0.4
10
V
V
OL
SINK
DV
0.5
DD
Output-Voltage High
V
OH
SOURCE
Tri-State Leakage Current
µA
pF
Tri-State Output Capacitance
C
OUT
DꢂGꢂTAꢁ OUTPUTS (GPꢂO_) (Iote 14)
I
I
= 2mA
0.4
0.8
SINK
GPIOC_ Output-Voltage Low
V
= 4mA
SINK
DV
0.5
-
-
DD
GPIOC_ Output-Voltage High
GPIOA_ Output-Voltage Low
GPIOA_ Output-Voltage High
Tri-State Leakage Current
I
I
I
= 2mA
V
V
V
SOURCE
= 15mA
0.8
10
SINK
DV
0.8
DD
= 15mA
SOURCE
µA
pF
Tri-State Output Capacitance
C
15
OUT
_______________________________________________________________________________________
5
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
EꢁECTRꢂCAꢁ CHARACTERꢂSTꢂCS (continued)
(AV
= DV
= 4.75V to 5.25V, external reference V
= 4.096V, f
= 3.6MHz (50% duty cycle), T = -40ꢀC to +85ꢀC, unless
DD
DD
REF
CLK A
otherwise noted. Typical values are at AV
= DV
= 5V, T = +25ꢀC. Outputs are unloaded, unless otherwise noted.)
DD A
DD
PARAMETER
SYMBOꢁ
COIDꢂTꢂOIS
MꢂI
TYP
MAX
UIꢂTS
POWER REQUꢂREMEITS (Iote 15)
Digital Positive-Supply Voltage
Digital Positive-Supply Current
Analog Positive-Supply Voltage
DV
2.7
AV
V
µA
mA
V
DD
DD
Idle, all blocks shut down
0.2
1
4
DI
AV
DD
Only ADC on, external reference
4.75
5.25
2
DD
Idle, all blocks shut down
0.2
2.8
2.6
1.5
-80
µA
f
f
= 225ksps
= 100ksps
4.2
SAMPLE
SAMPLE
Only ADC on,
external reference
Analog Positive-Supply Current
A
IDD
mA
All DACs on, no load, internal reference
AV = 4.75V
4.0
REF1 Positive-Supply Rejection
DAC Positive-Supply Rejection
ADC Positive-Supply Rejection
PSRR
PSRD
PSRA
dB
mV
mV
DD
Output code = FFFhex, AV = 4.75V to
DD
5.25V
0.1
0.5
0.5
Full-scale input, AV = 4.75V to 5.25V
DD
0.06
TꢂMꢂIG CHARACTERꢂSTꢂCS (Figures 6–13)
SCLK Clock Period
t
40
16
16
ns
ns
ns
CP
CH
SCLK Pulse-Width High
SCLK Pulse-Width Low
t
40/60 duty cycle
60/40 duty cycle
t
CL
GPIO Output Rise/Fall After
CS Rise
t
C
= 20pF
100
ns
GOD
LOAD
GPIO Input Setup Before CS Fall
LDAC Pulse Width
t
0
ns
ns
GSU
t
20
1.8
10
1.8
10
10
LDACPWL
C
C
C
C
= 20pF, SLOW = 0
= 20pF, SLOW = 1
= 20pF, SLOW = 0
= 20pF, SLOW = 1
12.0
40
LOAD
LOAD
LOAD
LOAD
SCLK Fall to DOUT Transition
(Note 16)
t
t
ns
DOT
12.0
40
SCLK Rise to DOUT Transition
(Notes 16, 17)
ns
ns
ns
DOT
CS Fall to SCLK Fall Setup Time
t
CSS
CSH
26/MAX1048
SCLK Fall to CS Rise Setup
Time
t
0
2000
DIN to SCLK Fall Setup Time
DIN to SCLK Fall Hold Time
CS Pulse-Width High
t
10
0
ns
ns
ns
ns
ns
ns
DS
t
DH
t
50
CSPWH
CS Rise to DOUT Disable
CS Fall to DOUT Enable
EOC Fall to CS Fall
t
C
C
= 20pF
= 20pF
25
DOD
LOAD
LOAD
t
1.5
30
25.0
DOE
t
RDS
6
_______________________________________________________________________________________
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
26/MAX1048
EꢁECTRꢂCAꢁ CHARACTERꢂSTꢂCS (continued)
(AV
= DV
= 4.75V to 5.25V, external reference V
= 4.096V, f
= 3.6MHz (50% duty cycle), T = -40ꢀC to +85ꢀC, unless
DD
DD
REF
CLK A
otherwise noted. Typical values are at AV
= DV
= 5V, T = +25ꢀC. Outputs are unloaded, unless otherwise noted.)
DD A
DD
PARAMETER
SYMBOꢁ
COIDꢂTꢂOIS
MꢂI
TYP
MAX
UIꢂTS
CKSEL = 01 (temp sense) or CKSEL =
10 (temp sense), internal reference on
65
CKSEL = 01 (temp sense) or CKSEL =
10 (temp sense), internal reference
initially off
140
CS or CNVST Rise to EOC
Fall—Internally Clocked
Conversion Time
t
µs
DOV
CKSEL = 01 (voltage conversion)
9
9
CKSEL = 10 (voltage conversion),
internal reference on
CKSEL = 10 (voltage conversion),
internal reference initially off
80
CKSEL = 00, CKSEL = 01 (temp sense)
CKSEL = 01 (voltage conversion)
40
ns
µs
CNVST Pulse Width
t
CSW
1.4
Iote 1: Tested at DV
= AV
= 5.25V.
DD
DD
Iote 2: Offset nulled.
Iote 3: No bus activity during conversion. Conversion time is defined as the number of conversion clock cycles multiplied by the
clock period.
Iote 4: See Table 5 for reference-mode details.
Iote 5: Not production tested. Guaranteed by design.
Iote 6: See the ADC/DAC References section.
Iote 7: Fast automated test, excludes self-heating effects.
Iote 8: Specified over the -40ꢀC to +85ꢀC temperature range.
Iote 9: REFSEL[1:0] = 00 or when DACs are not powered up.
Iote 10: DAC linearity, gain, and offset measurements are made between codes 115 and 3981.
Iote 11: The DAC buffers are guaranteed by design to be stable with a 1nF load.
Iote 12: Time required by the DAC output to power up and settle within 1 LSB in the external reference mode.
Iote 13: All DAC dynamic specifications are valid for a load of 100pF and 10kΩ.
Iote 14: Only one digital output (either DOUT, EOC, or the GPIOs) can be indefinitely shorted to either supply at one time.
Iote 15: All digital inputs at either DV
or DGND. DV
should not exceed AV
.
DD
DD
DD
Iote 16: See the Reset Register section and Table 9 for details on programming the SLOW bit.
Iote 17: Clock mode 11 only.
_______________________________________________________________________________________
7
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Typical Operating Characteristics
(AV
= DV
= 5V, external V
= 4.096V, f
= 3.6MHz (50% duty cycle), f
= 225ksps, C
= 50pF, 0.1µF capacitor
LOAD
DD
DD
REF
CLK
SAMPLE
at REF, T = +25ꢀC, unless otherwise noted.)
A
ANALOG SHUTDOWN CURRENT
vs. TEMPERATURE
ANALOG SHUTDOWN CURRENT
vs. ANALOG SUPPLY VOLTAGE
ADC INTEGRAL NONLINEARITY
vs. OUTPUT CODE
0.4
0.5
0.3
0.2
0.1
0
0.4
0.3
0.2
0.1
0
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-40
-15
10
35
60
85
4.750
4.875
5.000
5.125
5.250
0
256
512
768
1024
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
OUTPUT CODE
ADC OFFSET ERROR
vs. ANALOG SUPPLY VOLTAGE
ADC OFFSET ERROR
vs. TEMPERATURE
ADC DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
0.3
0.2
0.1
0
0.4
0.3
0.2
0.1
0
1.0
0.5
0
-0.1
-0.2
-0.3
-0.5
-1.0
4.750
4.875
5.000
5.125
5.250
-40
-15
10
35
60
85
0
256
512
768
1024
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
OUTPUT CODE
ADC GAIN ERROR
vs. ANALOG SUPPLY VOLTAGE
ADC GAIN ERROR
vs. TEMPERATURE
ADC EXTERNAL REFERENCE
INPUT CURRENT vs. SAMPLING RATE
26/MAX1048
60
50
40
30
20
10
0
0.50
0.25
0
1.0
0.5
0
-0.25
-0.5
-1.0
-0.50
4.750
4.875
5.000
5.125
5.250
-40
-15
10
35
60
85
0
50
100
150
200
250
300
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
SAMPLING RATE (ksps)
8
_______________________________________________________________________________________
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
26/MAX1048
Typical Operating Characteristics (continued)
(AV
= DV
= 5V, external V
= 4.096V, f
= 3.6MHz (50% duty cycle), f
= 225ksps, C
= 50pF, 0.1µF capacitor
LOAD
DD
DD
REF
CLK
SAMPLE
at REF, T = +25ꢀC, unless otherwise noted.)
A
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
ANALOG SUPPLY CURRENT
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
vs. SAMPLING RATE
2.02
2.00
1.98
1.96
1.94
1.92
1.90
3.0
2.04
2.02
2.00
1.98
1.96
1.94
1.92
1.90
2.5
2.0
1.5
1.0
0.5
0
1.88
-40
-15
10
35
60
85
0
50
100
150
200
250
300
4.750
4.875
5.000
5.125
5.250
TEMPERATURE (°C)
SAMPLING RATE (ksps)
SUPPLY VOLTAGE (V)
DAC DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
DAC FULL-SCALE ERROR
vs. ANALOG SUPPLY VOLTAGE
DAC INTEGRAL NONLINEARITY
vs. OUTPUT CODE
0.10
0.05
0
0.3
0.2
0.1
0
0.25
0.20
0.15
0.10
0.05
-0.1
-0.2
-0.3
-0.05
-0.10
0
1023
1026
1029
1032
1035
1038
4.750
4.875
5.000
5.125
5.250
0
256
512
768
1024
OUTPUT CODE
SUPPLY VOLTAGE (V)
OUTPUT CODE
DAC FULL-SCALE ERROR
vs. TEMPERATURE
DAC FULL-SCALE ERROR
vs. LOAD CURRENT
DAC FULL-SCALE ERROR
vs. REFERENCE VOLTAGE
1
0
3
2
1.00
0.75
0.50
0.25
0
INTERNAL
REFERENCE
1
-1
-2
-3
0
EXTERNAL
REFERENCE
-0.25
-0.50
-0.75
-1.00
-1
-2
-3
-4
0
-40
-15
10
35
60
85
5
10
15
20
25
30
0
1
2
3
4
5
TEMPERATURE (°C)
LOAD CURRENT (mA)
REFERENCE VOLTAGE (V)
_______________________________________________________________________________________
9
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Typical Operating Characteristics (continued)
(AV
= DV
= 5V, external V
= 4.096V, f
= 3.6MHz (50% duty cycle), f
= 225ksps, C
= 50pF, 0.1µF capacitor
LOAD
DD
DD
REF
CLK
SAMPLE
at REF, T = +25ꢀC, unless otherwise noted.)
A
ADC REFERENCE SUPPLY CURRENT
vs. TEMPERATURE
INTERNAL REFERENCE VOLTAGE
ADC REFERENCE SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
vs. TEMPERATURE
4.12
41.0
40.9
40.8
40.7
40.6
40.5
24.96
24.94
24.92
24.90
24.88
24.86
24.84
4.11
4.10
4.09
4.08
-40
-15
10
35
60
85
-40
-15
10
35
60
85
4.750
4.875
5.000
5.125
5.250
TEMPERATURE (°C)
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
ADC FFT PLOT
ADC IMD PLOT
ADC CROSSTALK PLOT
0
-20
0
-20
0
-20
f
f
f
= 32.768kHz
= 10.080kHz
= 5.24288MHz
f
f
f
= 5.24288MHz
f
f
f
= 5.24288MHz
= 10.080kHz
= 8.0801kHz
SAMPLE
ANALOG_)N
CLK
CLK
IN1
IN2
CLK
IN1
IN2
= 9.0kHz
= 11.0kHz
= -6dBFS
SINAD = 61.21dBc
SNR = 61.21dBc
THD = 73.32dBc
SFDR = 81.25dBc
A
SNR = 61.11dBc
THD = 73.32dBc
ENOB = 9.86 BITS
SFDR = 86.34dBc
-40
-40
-40
IN
IMD = 78.0dBc
-60
-60
-60
-80
-80
-80
-100
-120
-140
-160
-100
-120
-140
-160
-100
-120
-140
-160
0
50
100
150
200
0
50
100
150
200
0
50
100
150
200
ANALOG INPUT FREQUENCY (kHz)
ANALOG INPUT FREQUENCY (kHz)
ANALOG INPUT FREQUENCY (kHz)
DAC OUTPUT LOAD REGULATION
vs. OUTPUT CURRENT
GPIO OUTPUT VOLTAGE
vs. SOURCE CURRENT
GPIO OUTPUT VOLTAGE
vs. SINK CURRENT
26/MAX1048
2.08
2.07
2.06
2.05
2.04
2.03
2.02
2.01
2.00
5
4
3
2
1
0
1500
1200
900
600
300
0
GPIOB0–B3, C0–C3
OUTPUTS
GPIOA0–A3 OUTPUTS
GPIOB0–B3,
C0–C3 OUTPUTS
SINKING
GPIOA0–A3 OUTPUTS
SOURCING
DAC OUTPUT = MIDSCALE
-30
0
30
60
90
0
20
40
60
80
100
0
20
40
60
80
100
OUTPUT CURRENT (mA)
SOURCE CURRENT (mA)
SINK CURRENT (mA)
10 ______________________________________________________________________________________
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
26/MAX1048
Typical Operating Characteristics (continued)
(AV
= DV
= 5V, external V
= 4.096V, f
= 3.6MHz (50% duty cycle), f
= 225ksps, C
= 50pF, 0.1µF capacitor
LOAD
DD
DD
REF
CLK
SAMPLE
at REF, T = +25ꢀC, unless otherwise noted.)
A
TEMPERATURE SENSOR ERROR
DAC-TO-DAC CROSSTALK
DYNAMIC RESPONSE RISE TIME
= 10kΩ, C = 100pF
vs. TEMPERATURE
R
= 10kΩ, C
= 100pF
R
LOAD
LOAD
LOAD
LOAD
MAX1040 toc29
MAX1040 toc30
1.00
0.75
0.50
0.25
0
CS
2V/div
V
OUTA
2V/div
-0.25
-0.50
-0.75
-1.00
V
OUTB
V
10mV/div
AC-COUPLED
OUT
2V/div
-40
-15
10
35
60
85
100μs
1μs
TEMPERATURE (°C)
MAJOR CARRY TRANSITION
= 10kΩ, C = 100pF
DAC DIGITAL FEEDTHROUGH R
= 10kΩ,
LOAD
DYNAMIC RESPONSE FALL TIME
= 10kΩ, C = 100pF
R
C = 100pF, CS = HIGH, DIN = LOW
LOAD
MAX1040 toc33
R
LOAD
LOAD
LOAD
LOAD
MAX1040 toc32
MAX1040 toc31
SCLK
2V/div
CS
2V/div
CS
2V/div
V
V
OUT
100mV/div
AC-COUPLED
OUT
V
OUT
20mV/div
AC-COUPLED
2V/div
1μs
200ns
1μs
NEGATIVE FULL-SCALE SETTLING TIME
= 10kΩ, C = 100pF
POSITIVE FULL-SCALE SETTLING TIME
= 10kΩ, C = 100pF
ADC REFERENCE FEEDTHROUGH
= 10kΩ, C = 100pF
MAX1040 toc36
R
R
R
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
MAX1040 toc34
MAX1040 toc35
V
REF2
V
LDAC
V
LDAC
2V/div
2V/div
2V/div
V
OUT_
V
OUT_
2V/div
2V/div
V
DAC-OUT
2mV/div
AC-COUPLED
ADC REFERENCE SWITCHING
2μs
1μs
200μs
______________________________________________________________________________________ 11
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Pin Description
PꢂI
IAME
D.C.
FUICTꢂOI
MAX1040
MAX1042
MAX1046
MAX1048
1, 2, 16–19,
24, 25, 31,
34
1, 2, 16–19,
24, 25
16–19, 31,
34
16–19
Do Not Connect. Do not connect to this pin.
Active-Low End-of-Conversion Output. Data is valid after the
falling edge of EOC.
3
3
3
3
EOC
Digital Positive Power Input. Bypass DV
0.1µF capacitor.
to DGND with a
DD
4
5
4
5
4
5
4
5
DV
DD
DGND
DOUT
Digital Ground. Connect DGND to AGND.
Serial Data Output. Data is clocked out on the falling edge of
the SCLK clock in clock modes 00, 01, and 10. Data is
clocked out on the rising edge of the SCLK clock in clock
mode 11. High impedance when CS is high.
6
7
6
7
6
7
6
7
Serial Clock Input. Clocks data in and out of the serial
interface. (Duty cycle must be 40% to 60%.) See Table 4 for
details on programming the clock mode.
SCLK
DIN
Serial Data Input. DIN data is latched into the serial interface
on the falling edge of SCLK.
8
8
8
8
OUT0–
OUT3
9–12
9–12
9–12
9–12
DAC Outputs
Positive Analog Power Input. Bypass AV
0.1µF capacitor.
to AGND with a
DD
13
14
13
14
13
14
13
14
AV
DD
AGND
N.C.
Analog Ground
15, 23, 32, 15, 23, 32, 15, 23, 32, 15, 23, 32,
No Connection. Not internally connected.
33
33
33
33
Active-Low Load DAC. LDAC is an asynchronous active-low
input that updates the DAC outputs. Drive LDAC low to make
the DAC registers transparent.
20
20
20
20
LDAC
CS
Active-Low Chip-Select Input. When CS is low, the serial
interface is enabled. When CS is high, DOUT is high
impedance.
21
21
21
21
26/MAX1048
12 ______________________________________________________________________________________
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
26/MAX1048
Pin Description (continued)
PꢂI
IAME
FUICTꢂOI
MAX1040
MAX1042
MAX1046
MAX1048
Reset Select. Selects DAC wake-up mode. Set RES_SEL low
to wake up the DAC outputs with a 100kΩ resistor to GND or
set RES_SEL high to wake up the DAC outputs with a 100kΩ
22
22
22
22
RES_SEL
resistor to V
. Set RES_SEL high to power up the DAC input
REF
register to FFFh. Set RES_SEL low to power up the DAC input
register to 000h.
Reference 1 Input. Reference voltage. Leave unconnected to
use the internal 4.096V reference, REF1 is the positive
reference in ADC external differential mode. Bypass REF1 to
AGND with a 0.1µF capacitor in external reference mode only.
See the ADC/DAC References section.
26
26
26
26
REF1
27–31, 34
35
27–31, 34
35
—
—
—
—
AIN0–AIN5 Analog Inputs
Reference 2 Input/Analog Input Channel 6. See Table 5 for
details on programming the setup register. REF2 is the negative
reference in the ADC external differential reference mode.
REF2/AIN6
CNVST/
AIN7
Active-Low Conversion Start Input/Analog Input 7. See Table 5
for details on programming the setup register.
36
—
36
—
—
—
GPIOA0,
GPIOA1
General-Purpose I/O A0, A1. GPIOA0, GPIOA1 can sink and
source 15mA.
1, 2
1, 2
GPIOC0,
GPIOC1
General-Purpose I/O C0, C1. GPIOC0, GPIOC1 can sink 4mA
and source 2mA.
—
—
24, 25
—
—
24, 25
27–30
27–30
AIN0–AIN3 Analog Inputs
Reference 2 Input. See Table 5 for details on programming the
setup register. REF2 is the negative reference in the ADC
external differential reference mode.
—
—
—
—
35
36
35
36
REF2
Active-Low Conversion Start Input. See Table 5 details on
programming the setup register.
CNVST
______________________________________________________________________________________ 13
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
CPOL = CPHA = 1. Set CS low to latch any input data
Detailed Description
at DIN on the falling edge of SCLK. Output data at
The MAX1040/MAX1042/MAX1046/MAX1048 integrate
DOUT is updated on the falling edge of SCLK in clock
a multichannel 10-bit ADC and a quad 10-bit DAC in a
modes 00, 01, and 10. Output data at DOUT is updated
single IC. These devices also include a temperature
on the rising edge of SCLK in clock mode 11. See
sensor and configurable GPIOs with a 25MHz SPI-
Figures 6–11. Bipolar true-differential results and tem-
/QSPI-/MICROWIRE-compatible serial interface. The
perature-sensor results are available in two’s comple-
ADC is available in a 4 or an 8 input-channel version.
ment format, while all other results are in binary.
The four DAC outputs settle within 2.0µs, and the ADC
has a 225ksps conversion rate.
A high-to-low transition on CS initiates the data-input
operation. Serial communications to the ADC always
begin with an 8-bit command byte (MSB first) loaded
from DIN. The command byte and the subsequent data
bytes are clocked from DIN into the serial interface on
the falling edge of SCLK. The serial-interface and fast-
interface circuitry is common to the ADC, DAC, and
GPIO sections. The content of the command byte
determines whether the SPI port should expect 8, 16, or
24 bits and whether the data is intended for the ADC,
DAC, or GPIOs (if applicable). See Table 1. Driving CS
high resets the serial interface.
All devices include an internal reference (4.096V) pro-
viding a well-regulated, low-noise reference for both the
ADC and DAC. Programmable reference modes for the
ADC and DAC allow the use of an internal reference, an
external reference, or a combination of both. Features
such as an internal 1ꢀC accurate temperature sensor,
FIFO, scan modes, programmable internal or external
clock modes, data averaging, and AutoShutdown allow
users to minimize both power consumption and proces-
sor requirements. The low glitch energy (4nV•s) and
low digital feedthrough (0.5nV•s) of the integrated quad
DACs make these devices ideal for digital control of
fast-response closed-loop systems.
The conversion register controls ADC channel selec-
tion, ADC scan mode, and temperature-measurement
requests. See Table 4 for information on writing to the
conversion register. The setup register controls the
clock mode, reference, and unipolar/bipolar ADC con-
figuration. Use a second byte, following the first, to
write to the unipolar-mode or bipolar-mode registers.
See Table 5 for details of the setup register and see
Tables 6, 7, and 8 for setting the unipolar- and bipolar-
mode registers. Hold CS low between the command
byte and the second and third byte. The ADC averag-
ing register is specific to the ADC. See Table 9 to
address that register. Table 11 shows the details of the
reset register.
The devices are guaranteed to operate with a supply
voltage from +4.75V to +5.25V. These devices con-
sume 2.5mA at 225ksps throughput, only 0.22µA at
1ksps throughput, and under 0.2µA in the shutdown
mode. The MAX1042/MAX1048 offer four GPIOs that
can be configured as inputs or outputs.
Figure 1 shows the MAX1042 functional diagram. The
MAX1042/MAX1048 only include the GPIOA0, GPIOA1
and GPIOC0, GPIOC1 blocks. The MAX1040/MAX1046
exclude the GPIOs. The output-conditioning circuitry
takes the internal parallel data bus and converts it to a
serial data format at DOUT, with the appropriate wake-up
timing. The arithmetic logic unit (ALU) performs the aver-
aging function.
Begin a write to the DAC by writing 0001XXXX as a
command byte. The last 4 bits of this command byte
are don’t-care bits. Write another 2 bytes (holding CS
low) to the DAC interface register following the com-
mand byte to select the appropriate DAC and the data
to be written to it. See the DAC Serial Interface section
and Tables 10, 17, and 18.
26/MAX1048
SPI-Compatible Serial Interface
The MAX1040/MAX1042/MAX1046/MAX1048 feature a
serial interface that is compatible with SPI and
MICROWIRE devices. For SPI, ensure the SPI bus mas-
ter (typically a microcontroller (µC)) runs in master
mode so that it generates the serial clock signal. Select
the SCLK frequency of 25MHz or less, and set the
clock polarity (CPOL) and phase (CPHA) in the µC con-
trol registers to the same value. The MAX1040/
MAX1042/MAX1046/MAX1048 operate with SCLK idling
high or low, and thus operate with CPOL = CPHA = 0 or
Write to the GPIOs (if applicable) by issuing a com-
mand byte to the appropriate register. Writing to the
MAX1042/MAX1048 GPIOs requires 1 additional byte
following the command byte. See Tables 12–16 for
details on GPIO configuration, writes, and reads. See
the GPIO Command section. Command bytes written to
the GPIOs on devices without GPIOs are ignored.
14 ______________________________________________________________________________________
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
26/MAX1048
DV
DD
AV
DD
GPIOC0,
GPIOC1
GPIOA0,
GPIOA1
MAX1042
GPIO
CONTROL
USER-PROGRAMMABLE
I/O
OUTPUT
CONDITIONING
10-BIT
DAC
INPUT
REGISTER
DAC
REGISTER
OUT0
OUT1
OUT2
OUT3
BUFFER
OSCILLATOR
SCLK
CS
OUTPUT
CONDITIONING
10-BIT
DAC
INPUT
REGISTER
DAC
REGISTER
BUFFER
BUFFER
BUFFER
SPI
PORT
DIN
DOUT
OUTPUT
CONDITIONING
10-BIT
DAC
INPUT
REGISTER
DAC
REGISTER
TEMPERATURE
SENSOR
OUTPUT
CONDITIONING
10-BIT
DAC
INPUT
REGISTER
DAC
REGISTER
EOC
LOGIC
CONTROL
CNVST
AIN0
10-BIT
SAR
ADC
FIFO AND
ALU
T/H
AIN5
REF2/
AIN6
CNVST/
AIN7
REF2
INTERNAL
REFERENCE
REF1
RES_SEL
LDAC
AGND
DGND
Figure 1. MAX1042 Functional Diagram
______________________________________________________________________________________ 15
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Table 1ꢀ Command Byte (MSB First)
REGꢂSTER IAME
Conversion*
Setup
BꢂT 7
BꢂT 6
BꢂT 5
BꢂT 4
BꢂT 3
BꢂT 2
BꢂT 1
BꢂT 0
1
0
0
0
0
0
0
0
0
X
1
0
0
0
0
0
0
0
CHSEL2
CHSEL1
CHSEL0
SCAN1
SCAN0
TEMP
CKSEL1
CKSEL0
REFSEL1
REFSEL0
DIFFSEL1
DIFFSEL0
ADC Averaging
DAC Select
Reset
1
0
0
0
0
0
0
AVGON
NAVG1
NAVG0
NSCAN1
NSCAN0
1
0
0
0
0
0
X
1
0
0
0
0
X
X
X
RESET
SLOW
FBGON
GPIO Configure**
GPIO Write**
GPIO Read**
No Operation
0
0
0
0
1
1
0
0
1
0
1
0
X = Don’t care.
*CHESL2 bit is only valid on the MAX1040/MAX1042. Set CHSEL2 to 0 on the MAX1046/MAX1048.
**Only applicable on the MAX1042/MAX1048.
Power-Up Default State
The MAX1040/MAX1042/MAX1046/MAX1048 power up
with all blocks in shutdown (including the reference). All
registers power up in state 00000000, except for the
setup register and the DAC input register. The setup
register powers up at 0010 1000 with CKSEL1 = 1 and
REFSEL1 = 1. The DAC input register powers up to
FFFh when RES_SEL is high, and it powers up to 000h
when RES_SEL is low.
timed conversions through the serial interface by writ-
ing to the conversion register in the default clock mode,
10. Use clock mode 11 with SCLK up to 3.6MHz for
externally timed acquisitions to achieve sampling rates
up to 225ksps. Clock mode 11 disables scanning and
averaging. See Figures 6–9 for timing specifications on
how to begin a conversion.
These devices feature an active-low, end-of-conversion
output. EOC goes low when the ADC completes the last
requested operation and is waiting for the next com-
mand byte. EOC goes high when CS or CNVST go low.
EOC is always high in clock mode 11.
10-Bit ADC
The MAX1040/MAX1042/MAX1046/MAX1048 ADCs use
a fully differential successive-approximation register
(SAR) conversion technique and on-chip track-and-
hold (T/H) circuitry to convert temperature and voltage
signals into 10-bit digital results. The analog inputs
accept both single-ended and differential input signals.
Single-ended signals are converted using a unipolar
transfer function, and differential signals are converted
using a selectable bipolar or unipolar transfer function.
See the ADC Transfer Functions section for more data.
Single-Ended or Differential Conversions
The MAX1040/MAX1042/MAX1046/MAX1048 use a fully
differential ADC for all conversions. When a pair of
inputs are connected as a differential pair, each input is
connected to the ADC. When configured in single-
ended mode, the positive input is the single-ended
channel and the negative input is referred to AGND.
See Figure 2.
26/MAX1048
In differential mode, the T/H samples the difference
between two analog inputs, eliminating common-mode
DC offsets and noise. IN+ and IN- are selected from the
following pairs: AIN0/AIN1, AIN2/AIN3, AIN4/AIN5,
AIN6/AIN7. AIN0–AIN3 are available on all devices.
AIN0–AIN7 are available on the MAX1040/MAX1042.
See Tables 5–8 for more details on configuring the
inputs. For the inputs that are configurable as CNVST,
REF2, and an analog input, only one function can be
used at a time.
ADC Clock Modes
When addressing the setup, register bits 5 and 4 of the
command byte (CKSEL1 and CKSEL0, respectively)
control the ADC clock modes. See Table 5. Choose
between four different clock modes for various ways to
start a conversion and determine whether the acquisi-
tions are internally or externally timed. Select clock
mode 00 to configure CNVST/AIN_ to act as a conver-
sion start and use it to request internally timed conver-
sions, without tying up the serial bus. In clock mode 01,
use CNVST to request conversions one channel at a
time, thereby controlling the sampling speed without
tying up the serial bus. Request and start internally
16 ______________________________________________________________________________________
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
26/MAX1048
Unipolar or Bipolar Conversions
Address the unipolar- and bipolar-mode registers
through the setup register (bits 1 and 0). See Table 5 for
the setup register. See Figures 3 and 4 for the transfer-
function graphs. Program a pair of analog inputs for dif-
ferential operation by writing a one to the appropriate bit
of the bipolar- or unipolar-mode register. Unipolar mode
determines the time required for the T/H to acquire an
input signal. If the input signal’s source impedance is
high, the required acquisition time lengthens.
Any source impedance below 300Ω does not signifi-
cantly affect the ADC’s AC performance. A high-imped-
ance source can be accommodated either by
lengthening t
(only in clock mode 01) or by placing
ACQ
sets the differential input range from 0 to V
A nega-
REF1.
a 1µF capacitor between the positive and negative ana-
log inputs. The combination of the analog-input source
impedance and the capacitance at the analog input cre-
ates an RC filter that limits the analog input bandwidth.
tive differential analog input in unipolar mode causes the
digital output code to be zero. Selecting bipolar mode
sets the differential input range to
V
REF1
/ 2. The digital
output code is binary in unipolar mode and two’s com-
plement in bipolar mode.
ꢂnput Bandwidth
The ADC’s input-tracking circuitry has a 1MHz small-sig-
nal bandwidth, making it possible to digitize high-speed
transient events and measure periodic signals with
bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. Anti-alias prefiltering
of the input signals is necessary to avoid high-frequency
signals aliasing into the frequency band of interest.
In single-ended mode, the MAX1040/MAX1042/
MAX1046/MAX1048 always operate in unipolar mode.
The analog inputs are internally referenced to AGND
with a full-scale input range from 0 to the selected refer-
ence voltage.
Analog ꢂnput (T/H)
The equivalent circuit of Figure 2 shows the ADC input
architecture of the MAX1040/MAX1042/MAX1046/
MAX1048. In track mode, a positive input capacitor is
connected to AIN0–AIN7 in single-ended mode and
AIN0, AIN2, AIN4, and AIN6 in differential mode.
A negative input capacitor is connected to AGND in
single-ended mode or AIN1, AIN3, AIN5, and AIN7 in
differential mode. For external T/H timing, use clock
mode 01. After the T/H enters hold mode, the difference
between the sampled positive and negative input volt-
ages is converted. The input capacitance charging rate
Analog ꢂnput Protection
Internal electrostatic-discharge (ESD) protection diodes
clamp all analog inputs to AV
and AGND, allowing
DD
the inputs to swing from (AGND - 0.3V) to (AV
+
DD
0.3V) without damage. However, for accurate conver-
sions near full scale, the inputs must not exceed AV
DD
by more than 50mV or be lower than AGND by 50mV. If
an analog input voltage exceeds the supplies, limit the
input current to 2mA.
ꢂnternal FꢂFO
The MAX1040/MAX1042/MAX1046/MAX1048 contain a
first-in/first-out (FIFO) buffer that holds up to 16 ADC
results plus one temperature result. The internal FIFO
allows the ADC to process and store multiple internally
clocked conversions and a temperature measurement
without being serviced by the serial bus.
AIN0–AIN7
(SINGLE-ENDED),
AIN0, AIN2,
REF1
DAC
ACQ
AGND
AIN4, AIN6
(DIFFERENTIAL)
CIN+
If the FIFO is filled and further conversions are request-
ed without reading from the FIFO, the oldest ADC
results are overwritten by the new ADC results. Each
result contains 2 bytes, with the MSB preceded by four
leading zeros. After each falling edge of CS, the oldest
available pair of bytes of data is available at DOUT,
MSB first. When the FIFO is empty, DOUT is zero.
COMPARATOR
HOLD
CIN-
AGND
(SINGLE-ENDED),
AIN1, AIN3,
AIN5, AIN7
(DIFFERENTIAL)
ACQ
The first 2 bytes of data read out after a temperature
measurement always contain the 10-bit temperature
result, preceded by four leading zeros, MSB first. The
LSB is followed by 2 sub-bits. If another temperature
measurement is performed before the first temperature
result is read out, the old measurement is overwritten
by the new result. Temperature results are in degrees
ACQ
HOLD
HOLD
AV / 2
DD
Figure 2. Equivalent Input Circuit
______________________________________________________________________________________ 17
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Celsius (two’s complement), at a resolution of 8 LSB
per degree. See the Temperature Measurements sec-
tion for details on converting the digital code to a tem-
perature.
DAC Transfer Function
See Table 2 for various analog outputs from the DAC.
DAC Power-On Wake-Up Modes
The state of the RES_SEL input determines the wake-up
10-Bit DAC
In addition to the 10-bit ADC, the MAX1040/MAX1042/
MAX1046/MAX1048 also include four voltage-output,
10-bit, monotonic DACs with less than 1 LSB integral
nonlinearity error and less than 0.5 LSB differential non-
linearity error. Each DAC has a 2µs settling time and
ultra-low glitch energy (4nV•s). The 10-bit DAC code is
state of the DAC outputs. Connect RES_SEL to AV
or
DD
AGND upon power-up to be sure the DAC outputs
wake up to a known state. Connect RES_SEL to AGND
to wake up all DAC outputs at 000h. While RES_SEL is
low, the 100kΩ internal resistor pulls the DAC outputs to
AGND and the output buffers are powered down.
Connect RES_SEL to AV
to wake up all DAC outputs
at FFFh. While RES_SEL is high, the 100kΩ pullup
DD
unipolar binary with 1 LSB = V
/ 1024.
REF
resistor pulls the DAC outputs to V
buffers are powered down.
and the output
REF1
DAC Digital ꢂnterface
Figure 1 shows the functional diagram of the MAX1042.
The shift register converts a serial 16-bit word to parallel
data for each input register operating with a clock rate
up to 25MHz. The SPI-compatible digital interface to the
shift register consists of CS, SCLK, DIN, and DOUT.
Serial data at DIN is loaded on the falling edge of SCLK.
Pull CS low to begin a write sequence. Begin a write to
the DAC by writing 0001XXXX as a command byte. The
last 4 bits of the DAC select register are don’t-care bits.
See Table 10. Write another 2 bytes to the DAC inter-
face register following the command byte to select the
appropriate DAC and the data to be written to it. See
Tables 17 and 18.
DAC Power-Up Modes
See Table 18 for a description of the DAC power-up
and power-down modes.
GPIOs
In addition to the internal ADC and DAC, the
MAX1042/MAX1048 also provide four GPIO channels,
GPIOA0, GPIOA1, GPIOC0, and GPIOC1. Read and write
to the GPIOs as detailed in Table 1 and Tables 12–16.
Also, see the GPIO Command section. See Figures 11 and
12 for GPIO timing.
The four double-buffered DACs include an input and a
DAC register. The input registers are directly connect-
ed to the shift register and hold the result of the most
recent write operation. The four 10-bit DAC registers
hold the current output code for the respective DAC.
Data can be transferred from the input registers to the
DAC registers by pulling LDAC low or by writing the
appropriate DAC command sequence at DIN. See
Table 17. The outputs of the DACs are buffered through
four rail-to-rail op amps.
Table 2ꢀ DAC Output Code Table
DAC COITEITS
AIAꢁOG OUTPUT
MSB
ꢁSB
⎛
⎞
1023
1024
+V
11
1111
0000
0000
0111
1111
REF
⎜
⎟
⎝
⎠
⎛
⎞
1023
1024
26/MAX1048
10
10
01
0001
0000
0111
+V
REF
The MAX1040/MAX1042/MAX1046/MAX1048 DAC out-
put voltage range is based on the internal reference or
an external reference. Write to the setup register (see
Table 5) to program the reference. If using an external
voltage reference, bypass REF1 with a 0.1µF capacitor
to AGND. The internal reference is 4.096V. When using
⎜
⎟
⎝
⎠
⎛
⎞
⎛
⎞
512
+V
REF
+V
=
REF
⎜
⎟
⎜
⎟
1024
2
⎝
⎠
⎝
⎠
an external reference, the voltage range is 0.7V to AV
.
DD
⎛
⎞
511
+V
REF
⎜
⎟
1024
⎝
⎠
⎛
⎞
1
1024
0
00
00
0000
0000
0001
0000
+V
REF
⎜
⎟
⎝
⎠
18 ______________________________________________________________________________________
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
26/MAX1048
Write to the GPIOs by writing a command byte to the
GPIO command register. Write a single data byte to the
MAX1042/MAX1048 following the command byte.
When REFSEL[1:0] = 00 or 10, REF2/AIN_ functions as
an analog input channel. When REFSEL[1:0] = 01 or 11,
REF2/AIN_ functions as the device’s negative reference.
The GPIOs can sink and source current. The
MAX1042/MAX1048 GPIOA0 and GPIOA1 can sink and
source up to 15mA. GPIOC0 and GPIOC1 can sink 4mA
and source 2mA. See Table 3.
Temperature Measurements
Issue a command byte setting bit 0 of the conversion
register to one to take a temperature measurement.
See Table 4. The MAX1040/MAX1042/MAX1046/
MAX1048 perform temperature measurements with an
internal diode-connected transistor. The diode bias cur-
rent changes from 68µA to 4µA to produce a tempera-
ture-dependent bias voltage difference. The second
conversion result at 4µA is subtracted from the first at
68µA to calculate a digital value that is proportional to
absolute temperature. The output data appearing at
DOUT is the digital code above, minus an offset to
adjust from Kelvin to Celsius.
Clock Modes
ꢂnternal Clock
The MAX1040/MAX1042/MAX1046/MAX1048 can oper-
ate from an internal oscillator. The internal oscillator is
active in clock modes 00, 01, and 10. Figures 6, 7, and
8 show how to start an ADC conversion in the three
internally timed conversion modes.
Read out the data at clock speeds up to 25MHz
through the SPI interface.
The reference voltage used for the temperature mea-
surements is always derived from the internal reference
source to ensure that 1 LSB corresponds to 1/8th of a
degree Celsius. On every scan where a temperature
measurement is requested, the 12-bit temperature con-
version is carried out first. The first 2 bytes of data read
from the FIFO contain the result of the 12-bit tempera-
ture measurement. If another temperature measure-
ment is performed before the first temperature result is
read out, the old measurement is overwritten by the
new result. Temperature results are in degrees Celsius
(two’s complement). See the Applications Information
section for information on how to perform temperature
measurements in each clock mode.
External Clock
Set CKSEL1 and CKSEL0 in the setup register to 11 to
set up the interface for external clock mode 11. See
Table 5. Pulse SCLK at speeds from 0.1MHz to
3.6MHz. Write to SCLK with a 40% to 60% duty cycle.
The SCLK frequency controls the conversion timing.
See Figure 9 for clock mode 11 timing. See the ADC
Conversions in Clock Mode 11 section.
ADC/DAC References
Address the reference through the setup register, bits 3
and 2. See Table 5. Following a wake-up delay, set
REFSEL[1:0] = 00 to program both the ADC and DAC
for internal reference use. Set REFSEL[1:0] = 10 to pro-
gram the ADC for internal reference. Set REFSEL[1:0] =
10 to program the DAC for external reference, REF1.
When using REF1 or REF2/AIN_ in external-reference
mode, connect a 0.1µF capacitor to AGND. Set
REFSEL[1:0] = 01 to program the ADC and DAC for
external-reference mode. The DAC uses REF1 as its
external reference, while the ADC uses REF2 as its
external reference. Set REFSEL[1:0] = 11 to program
the ADC for external differential-reference mode. REF1
is the positive reference and REF2 is the negative refer-
ence in the ADC external differential mode.
Register Descriptions
The MAX1040/MAX1042/MAX1046/MAX1048 communi-
cate between the internal registers and the external cir-
cuitry through the SPI-compatible serial interface. Table
1 details the command byte, the registers, and the bit
names. Tables 4–12 show the various functions within
the conversion register, setup register, unipolar-mode
register, bipolar-mode register, ADC averaging regis-
ter, DAC select register, reset register, and GPIO com-
mand register, respectively.
Conversion Register
Select active analog input channels, scan modes, and
a single temperature measurement per scan by issuing
a command byte to the conversion register. Table 4
details channel selection, the four scan modes, and
how to request a temperature measurement. Start a
scan by writing to the conversion register when in clock
mode 10 or 11, or by applying a low pulse to the
CNVST pin when in clock mode 00 or 01. See Figures 6
Table 3ꢀ GPꢂO Maximum Sink/Source
Current
MAX1042/MAX1048
(mA)
CURREIT
GPꢂOA0, GPꢂOA1 GPꢂOC0, GPꢂOC1
Sink
15
15
4
2
Source
______________________________________________________________________________________ 19
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
and 7 for timing specifications for starting a scan with
Table 4ꢀ Conversion Register*
CNVST.
BꢂT
IAME
BꢂT
FUICTꢂOI
A conversion is not performed if it is requested on a
channel or one of the channel pairs that has been con-
figured as CNVST or REF2. For channels configured as
differential pairs, the CHSEL0 bit is ignored and the two
pins are treated as a single differential channel. For the
MAX1046/MAX1048, the CHSEL2 bit must be zero.
Channels 4–7 are invalid. Any scans or averages on
these channels can cause corrupt data.
—
X
7 (MSB)
6
Set to one to select conversion register.
Don’t care.
Analog-input channel select
(MAX1040/MAX1042). Set to 0 on
MAX1046/MAX1048.
CHSEL2
5
CHSEL1
CHSEL0
SCAN1
SCAN0
4
3
2
1
Analog-input channel select.
Analog-input channel select.
Scan-mode select.
Select scan mode 00 or 01 to return one result per sin-
gle-ended channel and one result per differential pair
within the selected scanning range (set by bits 2 and 1,
SCAN1 and SCAN0), plus one temperature result if
selected. Select scan mode 10 to scan a single input
channel numerous times, depending on NSCAN1 and
NSCAN0 in the ADC averaging register (Table 9).
Select scan mode 11 to return only one result from a
single channel.
Scan-mode select.
Set to one to take a single temp-
erature measurement. The first
conversion result of a scan contains
temperature information.
TEMP
0 (LSB)
*See below for bit details.
Setup Register
Issue a command byte to the setup register to config-
ure the clock, reference, power-down modes, and ADC
single-ended/differential modes. Table 5 details the bits
in the setup-register command byte. Bits 5 and 4
(CKSEL1 and CKSEL0) control the clock mode, acqui-
sition and sampling, and the conversion start. Bits 3
and 2 (REFSEL1 and REFSEL0) set the device for either
internal or external reference. Bits 1 and 0 (DIFFSEL1
and DIFFSEL0) address the ADC unipolar-mode and
bipolar-mode registers and configure the analog input
channels for differential operation.
SEꢁECTED
CHAIIEꢁ
(I)
CHSEꢁ2**
CHSEꢁ1
CHSEꢁ0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
The ADC reference is always on if any of the following
conditions are true:
**Channels 4–7 are invalid on the MAX1046/MAX1048. Set
CHSEL2 bit to 0 on those devices.
1)The FBGON bit is set to one in the reset register.
2)At least one DAC output is powered up and
REFSEL[1:0] (in the setup register) = 00.
SCAI MODE
26/MAX1048
SCAI1 SCAI0
(CHAIIEꢁ I ꢂS SEꢁECTED BY
3)At least one DAC is powered down through the
BꢂTS CHSEꢁ2, CHSEꢁ1, AID CHSEꢁ0)
100kΩ to V
and REFSEL[1:0] = 00.
REF
0
0
0
1
Scans channels 0 through N.
If any of the above conditions exist, the ADC reference
is always on, but there is a 188 clock-cycle delay
before temperature-sensor measurements begin, if
requested.
Scans channels N through the highest
numbered channel.
Scans channel N repeatedly. The ADC
averaging register sets the number of
results.
1
1
0
1
No scan. Converts channel N once only.
20 ______________________________________________________________________________________
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
26/MAX1048
Table 5ꢀ Setup Register*
BꢂT IAME
—
BꢂT
FUICTꢂOI
7 (MSB)
Set to zero to select setup register.
Set to one to select setup register.
—
6
CKSEL1
CKSEL0
REFSEL1
REFSEL0
DIFFSEL1
DIFFSEL0
5
Clock mode and CNVST configuration; resets to one at power-up.
Clock mode and CNVST configuration.
4
3
Reference-mode configuration.
2
1
Reference-mode configuration.
Unipolar-/bipolar-mode register configuration for differential mode.
Unipolar-/bipolar-mode register configuration for differential mode.
0 (LSB)
*See below for bit details.
Table 5aꢀ Clock Modes (see the Clock Modes section)
CKSEꢁ1
CKSEꢁ0
COIVERSꢂOI CꢁOCK
Internal
ACQUꢂSꢂTꢂOI/SAMPꢁꢂIG
Internally timed.
CNVST COIFꢂGURATꢂOI
0
0
1
1
0
1
0
1
CNVST
CNVST
AIN7
Internal
Externally timed by CNVST.
Internally timed.
Internal
External (3.6MHz max)
Externally timed by SCLK.
AIN7
Table 5bꢀ Clock Modes 00, 01, and 10
VOꢁTAGE
REFEREICE COIDꢂTꢂOIS
OVERRꢂDE
REF2
COIFꢂGURATꢂOI
REFSEꢁ1 REFSEꢁ0
AUTOSHUTDOWI
Internal reference turns off after scan is complete. If
internal reference is turned off, there is a programmed
delay of 218 internal-conversion clock cycles.
AIN
Internal (DAC
and ADC)
0
0
0
1
AIN6
REF2
Internal reference required. There is a programmed
Temperature delay of 244 internal-conversion clock cycles for the
internal reference to settle after wake-up.
AIN
Internal reference not used.
External single-
ended (REF1
for DAC and
Internal reference required. There is a programmed
Temperature delay of 244 internal-conversion clock cycles for the
internal reference to settle after wake-up.
REF2 for ADC)
Default reference mode. Internal reference turns off
after scan is complete. If internal reference is turned
off, there is a programmed delay of 218 internal-
AIN
Internal (ADC)
and external
REF1 (DAC)
conversion clock cycles.
1
1
0
1
AIN6
Internal reference required. There is a programmed
delay of 244 internal-conversion clock cycles for the
internal reference to settle after wake-up.
Temperature
AIN
Internal reference not used.
External
differential
(ADC), external
REF1 (DAC)
Internal reference required. There is a programmed
delay of 244 internal-conversion clock cycles for the
internal reference to settle after wake-up.
REF2
Temperature
______________________________________________________________________________________ 21
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Table 5cꢀ Clock Mode 11
VOꢁTAGE
REFEREICE COIDꢂTꢂOIS
OVERRꢂDE
REF2
COIFꢂGURATꢂOI
REFSEꢁ1 REFSEꢁ0
AUTOSHUTDOWI
Internal reference turns off after scan is complete. If
internal reference is turned off, there is a programmed
delay of 218 external conversion clock cycles.
AIN
Internal (DAC
and ADC)
0
0
0
1
AIN6
REF2
Internal reference required. There is a programmed
delay of 244 external conversion clock cycles for the
internal reference. Temperature-sensor output appears
at DOUT after 188 further external clock cycles.
Temperature
AIN
External single-
ended (REF1
Internal reference not used.
Internal reference required. There is a programmed
delay of 244 external conversion clock cycles for the
internal reference. Temperature-sensor output appears
at DOUT after 188 further external clock cycles.
for DAC and
Temperature
REF2 for ADC)
Default reference mode. Internal reference turns off
after scan is complete. If internal reference is turned
off, there is a programmed delay of 218 external
conversion clock cycles.
AIN
Internal (ADC)
and external
REF1 (DAC)
1
1
0
1
AIN6
REF2
Internal reference required. There is a programmed
delay of 244 external conversion clock cycles for the
internal reference. Temperature-sensor output appears
at DOUT after 188 further external clock cycles.
Temperature
AIN
Internal reference not used.
External
differential
(ADC), external
REF1 (DAC)
Internal reference required. There is a programmed
delay of 244 external conversion clock cycles for the
internal reference. Temperature-sensor output appears
at DOUT after 188 further external clock cycles.
Temperature
Table 5dꢀ Differential Select Modes
26/MAX1048
DꢂFFSEꢁ1 DꢂFFSEꢁ0
FUICTꢂOI
0
0
1
1
0
1
0
1
No data follows the command setup byte. Unipolar-mode and bipolar-mode registers remain unchanged.
No data follows the command setup byte. Unipolar-mode and bipolar-mode registers remain unchanged.
1 byte of data follows the command setup byte and is written to the unipolar-mode register.
1 byte of data follows the command setup byte and is written to the bipolar-mode register.
22 ______________________________________________________________________________________
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
26/MAX1048
Table 6ꢀ Unipolar-Mode Register (Addressed Through the Setup Register)
BꢂT IAME
UCH0/1
BꢂT
7 (MSB)
6
FUICTꢂOI
Configure AIN0 and AIN1 for unipolar differential conversion.
Configure AIN2 and AIN3 for unipolar differential conversion.
UCH2/3
Configure AIN4 and AIN5 for unipolar differential conversion (MAX1040/MAX1042). Set UCH4/5 to 0
on the MAX1046/MAX1048.
UCH4/5
UCH6/7
5
4
Configure AIN6 and AIN7 for unipolar differential conversion (MAX1040/MAX1042). Set UCH6/7 to 0
on the MAX1046/MAX1048.
X
X
X
X
3
Don’t care.
Don’t care.
Don’t care.
Don’t care.
2
1
0 (LSB)
Table 7ꢀ Bipolar-Mode Register (Addressed Through the Setup Register)
BꢂT IAME
BꢂT
FUICTꢂOI
Set to one to configure AIN0 and AIN1 for bipolar differential conversion. Set the corresponding bits
in the unipolar-mode and bipolar-mode registers to zero to configure AIN0 and AIN1 for unipolar
single-ended conversion.
BCH0/1
7 (MSB)
Set to one to configure AIN2 and AIN3 for bipolar differential conversion. Set the corresponding bits
in the unipolar-mode and bipolar-mode registers to zero to configure AIN2 and AIN3 for unipolar
single-ended conversion.
BCH2/3
BCH4/5
BCH6/7
6
5
4
Set to one to configure AIN4 and AIN5 for bipolar differential conversion (MAX1040/MAX1042). Set
the corresponding bits in the unipolar-mode and bipolar-mode registers to zero to configure AIN4
and AIN5 for unipolar single-ended conversion. Set BCH4/5 to 0 on the MAX1046/MAX1048.
Set to one to configure AIN6 and AIN7 for bipolar differential conversion (MAX1040/MAX1042). Set
the corresponding bits in the unipolar-mode and bipolar-mode registers to zero to configure AIN6
and AIN7 for unipolar single-ended conversion. Set BCH6/7 to 0 on the MAX1046/MAX1048.
X
X
X
X
3
Don’t care.
Don’t care.
Don’t care.
Don’t care.
2
1
0 (LSB)
______________________________________________________________________________________ 23
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Unipolar/Bipolar Registers
The final 2 bits (LSBs) of the setup register control the
unipolar-/bipolar-mode address registers. Set
DIFFSEL[1:0] = 10 to write to the unipolar-mode regis-
ter. Set bits DIFFSEL[1:0] = 11 to write to the bipolar-
mode register. In both cases, the setup command byte
must be followed by 1 byte of data that is written to the
unipolar-mode register or bipolar-mode register. Hold
CS low and run 16 SCLK cycles before pulling CS high.
If the last 2 bits of the setup register are 00 or 01, nei-
ther the unipolar-mode register nor the bipolar-mode
register is written. Any subsequent byte is recognized
as a new command byte. See Tables 6, 7, and 8 to pro-
gram the unipolar- and bipolar-mode registers.
Both registers power up at all zeros to set the inputs as
eight unipolar single-ended channels. To configure a
channel pair as single-ended unipolar, bipolar differen-
tial, or unipolar differential, see Table 8.
In unipolar mode, AIN+ can exceed AIN- by up to
REF
bipolar mode, either input can exceed the other by up
Table 8ꢀ Unipolar/Bipolar Channel Function
V
. The output format in unipolar mode is binary. In
UIꢂPOꢁAR-
to V
/ 2. The output format in bipolar mode is two’s
REF
BꢂPOꢁAR-MODE
REGꢂSTER BꢂT
CHAIIEꢁ PAꢂR
FUICTꢂOI
MODE
complement (see the ADC Transfer Functions section).
REGꢂSTER BꢂT
ADC Averaging Register
Write a command byte to the ADC averaging register to
configure the ADC to average up to 32 samples for
each requested result, and to independently control the
number of results requested for single-channel scans.
0
0
1
1
0
1
0
1
Unipolar single ended
Bipolar differential
Unipolar differential
Unipolar differential
Table 9ꢀ ADC Averaging Register*
BꢂT IAME
BꢂT
FUICTꢂOI
—
7 (MSB)
Set to zero to select ADC averaging register.
—
—
6
Set to zero to select ADC averaging register.
5
Set to one to select ADC averaging register.
AVGON
4
Set to one to turn averaging on. Set to zero to turn averaging off.
Configures the number of conversions for single-channel scans.
Configures the number of conversions for single-channel scans.
Single-channel scan count. (Scan mode 10 only.)
Single-channel scan count. (Scan mode 10 only.)
NAVG1
3
NAVG0
2
1
NSCAN1
NSCAN0
0 (LSB)
*See below for bit details.
AVGOI
IAVG1
IAVG0
FUICTꢂOI
26/MAX1048
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
Performs one conversion for each requested result.
Performs four conversions and returns the average for each requested result.
Performs eight conversions and returns the average for each requested result.
Performs 16 conversions and returns the average for each requested result.
Performs 32 conversions and returns the average for each requested result.
ISCAI1
ISCAI0
FUICTꢂOI (APPꢁꢂES OIꢁY ꢂF SCAI MODE 10 ꢂS SEꢁECTED)
Scans channel N and returns four results.
0
0
1
1
0
1
0
1
Scans channel N and returns eight results.
Scans channel N and returns 12 results.
Scans channel N and returns 16 results.
24 ______________________________________________________________________________________
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
26/MAX1048
Table 9 details the four scan modes available in the
ADC conversion register. All four scan modes allow
averaging as long as the AVGON bit, bit 4 in the
averaging register, is set to 1. Select scan mode 10 to
scan the same channel multiple times. Clock mode 11
disables averaging. For example, if AVGON = 1,
NAVG[1:0] = 00, NSCAN[1:0] = 11, and SCAN[1:0] =
10, 16 results are written to the FIFO, with each result
being the average of four conversions of channel N.
byte controls the DAC serial interface. See Table 17
and the DAC Serial Interface section.
Reset Register
Write to the reset register (as shown in Table 11) to
clear the FIFO or reset all registers (excluding the DAC
and GPIO registers) to their default states. When the
RESET bit in the reset register is set to 0, the FIFO is
cleared. Set the RESET bit to one to return all the
device registers to their default power-up state. All reg-
isters power up in state 00000000, except for the setup
register that powers up in clock mode 10 (CKSEL1 = 1
and REFSEL1 = 1). The DAC and GPIO registers are
not reset by writing to the reset register. Set the SLOW
bit to one to add a 15ns delay in the DOUT signal path
to provide a longer hold time. Writing a one to the
SLOW bit also clears the contents of the FIFO. Set the
FBGON bit to one to force the bias block and bandgap
reference to power up regardless of the state of the
DAC and activity of the ADC block. Setting the FBGON
bit high also removes the programmed wake-up delay
between conversions in clock modes 01 and 11.
Setting the FBGON bit high also clears the FIFO.
DAC Select Register
Write a command byte 0001XXXX to the DAC select
register (as shown in Table 9) to set up the DAC inter-
face and indicate that another word will follow. The last
4 bits of the DAC select register are don’t-care bits. The
word that follows the DAC select-register command
Table 10ꢀ DAC Select Register
BꢂT
IAME
BꢂT
FUICTꢂOI
—
—
—
—
X
7 (MSB) Set to zero to select DAC select register.
GPꢂO Command
Write a command byte to the GPIO command register
to configure, write, or read the GPIOs, as detailed in
Table 12.
6
5
4
3
2
1
0
Set to zero to select DAC select register.
Set to zero to select DAC select register.
Set to one to select DAC select register.
Don’t care.
Table 12ꢀ GPꢂO Command Register
X
Don’t care.
BꢂT IAME
BꢂT
FUICTꢂOI
X
Don’t care.
—
7 (MSB)
Set to zero to select GPIO register.
Set to zero to select GPIO register.
Set to zero to select GPIO register.
Set to zero to select GPIO register.
Set to zero to select GPIO register.
Set to zero to select GPIO register.
GPIO configuration bit.
X
Don’t care.
—
6
—
5
Table 11ꢀ Reset Register
—
—
4
3
BꢂT
BꢂT
FUICTꢂOI
—
2
1
IAME
GPIOSEL1
GPIOSEL2
—
—
—
—
—
7 (MSB) Set to zero to select ADC reset register.
0 (LSB)
GPIO write bit.
6
5
4
3
Set to zero to select ADC reset register.
Set to zero to select ADC reset register.
Set to zero to select ADC reset register.
Set to one to select ADC reset register.
GPꢂOSEꢁ1 GPꢂOSEꢁ2
FUICTꢂOI
GPIO configuration; written data is
entered in the GPIO configuration
register.
1
1
0
1
0
1
Set to zero to clear the FIFO only. Set to
one to set the device in its power-on
condition.
RESET
SLOW
2
1
GPIO write; written data is entered
in the GPIO write register.
Set to one to turn on slow mode.
GPIO read; the next 8 SCLK cycles
transfer the state of all GPIO
drivers into DOUT.
Set to one to force internal bias block and
bandgap reference to be always powered
up.
FBGON 0 (LSB)
______________________________________________________________________________________ 25
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Write the command byte 00000011 to configure the
GPIOs. The eight SCLK cycles following the command
byte load data from DIN to the GPIO configuration reg-
ister in the MAX1042/MAX1048. See Tables 13 and 14.
The register bits are updated after the last CS rising
edge. All GPIOs default to inputs upon power-up.
DAC Serial ꢂnterface
Write a command byte 0001XXXX to the DAC select
register to indicate the word to follow is written to the
DAC serial interface, as detailed in Tables 1, 10, 17, and
18. Write the next 16 bits to the DAC interface register,
as shown in Tables 17 and 18. Following the high-to-low
transition of CS, the data is shifted synchronously and
latched into the input register on each falling edge of
SCLK. Each word is 16 bits. The first 4 bits are the con-
trol bits, followed by 10 data bits (MSB first), followed by
2 sub-bits. See Figures 9–12 for DAC timing specifica-
tions.
The data in the register controls the function of each
GPIO, as shown in Tables 13, 14, and 16.
GPꢂO Write
Write the command byte 00000010 to indicate a GPIO
write operation. The eight SCLK cycles following the
command byte load data from DIN into the GPIO write
register in the MAX1042/MAX1048. See Tables 14 and
15. The register bits are updated after the last CS rising
edge.
If CS goes high prior to completing 16 SCLK cycles, the
command is discarded. To initiate a new transfer, drive
CS low again.
For example, writing the DAC serial interface word 1111
0000 and 0011 0100 disconnects DAC outputs 2 and 3
and forces them to a high-impedance state. DAC out-
puts 0 and 1 remain in their previous state.
GPꢂO Read
Write the command byte 00000001 to indicate a GPIO
read operation. The eight SCLK cycles following the
command byte transfer the state of the GPIOs to DOUT
in the MAX1042/MAX1048. See Table 16.
Table 13ꢀ MAX1042/MAX1048 GPꢂO Configuration
DATA PꢂI
DꢂI
DOUT
GPꢂO COMMAID BYTE
DATA BYTE
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
GPIOC1
0
GPIOC0
0
GPIOA1
0
GPIOA0
0
X
0
X
0
X
0
X
0
Table 14ꢀ MAX1042/MAX1048 GPꢂO Write
DATA PꢂI
GPꢂO COMMAID BYTE
DATA BYTE
DꢂI
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
GPIOC1
GPIOC0
0
GPIOA1
0
GPIOA0
0
X
0
X
X
X
0
DOUT
0
0
0
Table 15ꢀ GPꢂO-Mode Control
26/MAX1048
COIFꢂGURATꢂOI
BꢂT
WRꢂTE
BꢂT
OUTPUT
STATE
GPꢂO
FUICTꢂOI
1
1
0
1
0
1
1
0
Output
Output
Input
Tri-state
Pulldown
(open drain)
0
0
0
Table 16ꢀ MAX1042/MAX1048 GPꢂO Read
DATA PꢂI
DꢂI
GPꢂO COMMAID BYTE
DATA BYTE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
X
0
X
0
X
0
X
0
X
X
X
X
DOUT
GPIOC1
GPIOC0
GPIOA1
GPIOA0
26 ______________________________________________________________________________________
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
26/MAX1048
Table 17ꢀ DAC Serial-ꢂnterface Configuration
16-BꢂT SERꢂAꢁ WORD
MSB
COITROꢁ
BꢂTS
C3 C2 C1 C0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ꢁSB
DESCRꢂPTꢂOI
FUICTꢂOI
DATA BꢂTS
X
X
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
NOP
No Operation.
Reset all internal registers to 000h and
leave output buffers in their present
state.
Preset all internal registers to FFFh and
leave output buffers in their present
state.
0
0
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
RESET
0
0
0
1
1
X
X
X
X
X
X
X
X
X
Pull-High
D9–D0 to input register 0, DAC output
unchanged.
0
0
0
0
0
0
1
1
1
1
0
0
0
1
0
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
DAC0
DAC1
DAC2
DAC3
D9–D0 to input register 1, DAC output
unchanged.
D9–D0 to input register 2, DAC output
unchanged.
D9–D0 to input register 3, DAC output
unchanged.
0
0
1
1
1
1
0
0
1
1
0
0
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NOP
NOP
NOP
NOP
No Operation.
No Operation.
No Operation.
No Operation.
D9–D0 to input registers 0–3 and DAC
1
1
1
0
0
1
1
1
0
0
1
0
—
X
—
X
—
X
—
X
—
X
—
X
—
X
—
X
—
X
—
X
X
X
X
X
X
X
DAC0–DAC3 register 0–3. DAC outputs updated
(write-through).
NOP
No Operation.
D9–D0 to input registers 0–3 and DAC
DAC0–DAC3 Register 0–3. DAC outputs updated
(write-through).
—
—
—
—
—
—
—
—
—
—
D9–D0 to input registers 0–3. DAC
DAC0–DAC3
1
1
1
1
0
1
1
0
—
X
—
X
—
X
—
X
—
—
—
—
—
X
—
X
X
X
X
X
outputs unchanged.
Input registers to DAC registers
indicated by ones, DAC outputs
updated, equivalent to software LDAC
DAC0–DAC3
.
(No effect on DACs indicated by zeros.)
______________________________________________________________________________________ 27
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Table 18ꢀ DAC Power-Up and Power-Down Commands
COITROꢁ
DATA BꢂTS
BꢂTS
DESCRꢂPTꢂOI
FUICTꢂOI
C3 C2 C1 C0 X
X
X
X
D3 D2 D1 D0
Power up individual DAC buffers indicated by data
in DAC0 through DAC3. A one indicates the DAC
output is connected and active. A zero does not
affect the DAC’s present state.
1
1
1
1
1
1
1
1
X
X
X
X
X
— — — —
— — — —
0
0
0
1
1
0
X
X
Power-Up
Power down individual DAC buffers indicated by
data in DAC0 through DAC3. A one indicates the
DAC output is disconnected and high impedance.
A zero does not affect the DAC’s present state.
X
X
X
X
X
X
Power-Down 1
Power down individual DAC buffers indicated by
data in DAC0 through DAC3. A one indicates the
DAC output is disconnected and pulled to AGND
1
1
1
1
1
1
1
1
1
1
1
1
X
X
X
— — — —
— — — —
— — — —
1
0
1
0
0
1
0
0
1
X
X
X
Power-Down 2
with a 1kΩ resistor. A zero does not affect the DAC’s
present state.
Power down individual DAC buffers indicated by
data in DAC0 through DAC3. A one indicates the
X
X
X
X
X
X
Power-Down 3 DAC output is disconnected and pulled to AGND
with a 100k resistor. A zero does not affect the
Ω
DAC’s present state.
Power down individual DAC buffers indicated by
data in DAC0 through DAC3. A one indicates the
Power-Down 4 DAC output is disconnected and pulled to REF1 with
a 100kΩ resistor. A zero does not affect the DAC’s
present state.
transfer function for differential inputs. Code transitions
occur halfway between successive-integer LSB values.
Output-Data Format
Figures 6–9 illustrate the conversion timing for the
MAX1040/MAX1042/MAX1046/MAX1048. All 10-bit con-
version results are output in 2-byte format, MSB first,
with four leading zeros and the LSB followed by 2 sub-
bits. Data appears on DOUT on the falling edges of
SCLK. Data is binary for unipolar mode and two’s com-
plement for bipolar mode and temperature results. See
Figures 3, 4, and 5 for input/output and temperature-
transfer functions.
Output coding is binary, with 1 LSB = V
/ 1024 for
REF1
26/MAX1048
unipolar and bipolar operation, and 1 LSB = +0.125ꢀC
for temperature measurements. Bipolar true-differential
results and temperature-sensor results are available in
two’s complement format, while all others are in binary.
See Tables 6, 7, and 8 for details on which setting
(unipolar or bipolar) takes precedence.
In unipolar mode, AIN+ can exceed AIN- by up to
V
. In bipolar mode, either input can exceed the
REF1
other by up to V
ADC Transfer Functions
Figure 3 shows the unipolar transfer function for single-
ended or differential inputs. Figure 4 shows the bipolar
/2.
REF1
28 ______________________________________________________________________________________
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
26/MAX1048
MAX1046/MAX1048 then wake up, scan all requested
channels, store the results in the FIFO, and shut down.
After the scan is complete, EOC is pulled low and the
results are available in the FIFO. Wait until EOC goes
low before pulling CS low to communicate with the seri-
al interface. EOC stays low until CS or CNVST is pulled
low again. A temperature-conversion result, if request-
ed, precedes all other FIFO results. Temperature
results are available in 12-bit format.
Partial Reads and Partial Writes
If the first byte of an entry in the FIFO is partially read
(CS is pulled high after fewer than eight SCLK cycles),
the remaining bits are lost for that byte. The next byte of
data that is read out contains the next 8 bits. If the first
byte of an entry in the FIFO is read out fully, but the
second byte is read out partially, the rest of that byte is
lost. The remaining data in the FIFO is unaffected and
can be read out normally after taking CS low again, as
long as the 4 leading bits (normally zeros) are ignored.
If CS is pulled low before EOC goes low, a conversion
may not be completed and the FIFO data may not be
correct. Incorrect writes (pulling CS high before com-
pleting eight SCLK cycles) are ignored and the register
remains unchanged.
V
= V
- V
REF+ REF-
REF
V
V
REF
REF
011....111
011....110
011....101
FS = V / 2 + V
REF
COM
ZS = COM
-FS = -V / 2
REF
V
REF
Applications Information
1 LSB = V / 1024
REF
000....001
000....000
111....111
Internally Timed Acquisitions and
(COM)
Conversions Using CNVST
ADC Conversions in Clock Mode 00
In clock mode 00, the wake-up, acquisition, conversion,
and shutdown sequence is initiated through CNVST
and performed automatically using the internal oscilla-
tor. Results are added to the internal FIFO to be read
out later. See Figure 6 for clock mode 00 timing after a
command byte is issued. See Table 5 for details on
programming the clock mode in the setup register.
V
REF
100....011
100....010
100....001
100....000
-FS
-1 0 +1
(COM)
+FS - 1 LSB
INPUT VOLTAGE (LSB)
Initiate a scan by setting CNVST low for at least 40ns
before pulling it high again. The MAX1040/MAX1042/
Figure 4. Bipolar Transfer Function—Full Scale ( FS) =
V
REF
/ 2
OUTPUT CODE
FULL-SCALE
TRANSITION
111....111
011....111
011....110
FS = V
REF
111....110
111....101
1 LSB = V / 1024
REF
000....010
000....001
000....000
111....111
111....110
111....101
000....011
000....010
000....001
000....000
100....001
100....000
0
1
2
3
FS
INPUT VOLTAGE (LSB)
0
-256
+255.5
FS - 3/2 LSB
TEMPERATURE (°C)
Figure 5. Temperature Transfer Function
Figure 3. Unipolar Transfer Function—Full Scale (FS) = V
REF
______________________________________________________________________________________ 29
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
CNVST
(UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS)
CS
SCLK
DOUT
LSB1
MSB2
MSB1
t
RDS
EOC
Figure 6. Clock Mode 00—After writing a command byte, set CNVST low for at least 40ns to begin a conversion.
t
CSW
CNVST
(CONVERSION 2)
(ACQUISITION 1)
(ACQUISITION 2)
CS
t
DOV
(CONVERSION 1)
SCLK
DOUT
LSB1
MSB2
MSB1
EOC
Figure 7. Clock Mode 01—After writing a command byte, request multiple conversions by setting CNVST low for each conversion.
mode 00 or 10 is selected, an additional 45µs is
required for the internal reference to power up. If a tem-
perature measurement is being requested, reference
power-up and temperature measurement is internally
timed. In this case, hold CNVST low for at least 40ns.
Do not issue a second CNVST signal before EOC goes
low; otherwise, the FIFO can be corrupted. Wait until all
conversions are complete before reading the FIFO. SPI
communications to the DAC and GPIO registers are per-
mitted during conversion. However, coupled noise may
result in degraded ADC signal-to-noise ratio (SNR).
26/MAX1048
Set CNVST high to begin a conversion. Sampling is
completed approximately 500ns after CNVST goes
high. After the conversion is complete, the ADC shuts
down and pulls EOC low. EOC stays low until CS or
CNVST is pulled low again. Wait until EOC goes low
before pulling CS or CNVST low. The number of CNVST
signals must equal the number of conversions request-
ed by the scan and averaging registers to correctly
update the FIFO. Wait until all conversions are com-
plete before reading the FIFO. SPI communications to
the DAC and GPIO registers are permitted during con-
Externally Timed Acquisitions and
Internally Timed Conversions with CNVST
ADC Conversions in Clock Mode 01
In clock mode 01, conversions are requested one at a
time using CNVST and performed automatically using
the internal oscillator. See Figure 7 for clock mode 01
timing after a command byte is issued.
Setting CNVST low begins an acquisition, wakes up the
ADC, and places it in track mode. Hold CNVST low for
at least 1.4µs to complete the acquisition. If reference
30 ______________________________________________________________________________________
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
26/MAX1048
(CONVERSION BYTE)
DIN
(UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS)
CS
SCLK
DOUT
EOC
MSB1
LSB1
MSB2
t
DOV
Figure 8. Clock Mode 10—The command byte to the conversion register begins the acquisition (CNVST is not required).
version. However, coupled noise may result in degrad-
ed ADC SNR.
Internally Timed Acquisitions and
Conversions Using the Serial Interface
If averaging is turned on, multiple CNVST pulses need to
be performed before a result is written to the FIFO. Once
the proper number of conversions has been performed
to generate an averaged FIFO result (as specified to the
averaging register), the scan logic automatically switch-
es the analog input multiplexer to the next requested
channel. If a temperature measurement is programmed,
it is performed after the first rising edge of CNVST follow-
ing the command byte written to the conversion register.
The temperature-conversion result is available on DOUT
once EOC has been pulled low. Temperature results are
available in 12-bit format.
ADC Conversions in Clock Mode 10
In clock mode 10, the wake-up, acquisition, conversion,
and shutdown sequence is initiated by writing a com-
mand byte to the conversion register, and is performed
automatically using the internal oscillator. This is the
default clock mode upon power-up. See Figure 8 for
clock mode 10 timing.
Initiate a scan by writing a command byte to the conver-
sion register. The MAX1040/MAX1042/MAX1046/
MAX1048 then power up, scan all requested channels,
store the results in the FIFO, and shut down. After the
scan is complete, EOC is pulled low and the results are
available in the FIFO. If a temperature measurement is
requested, the temperature result precedes all other
FIFO results. Temperature results are available in 12-bit
format. EOC stays low until CS is pulled low again. Wait
until all conversions are complete before reading the
FIFO. SPI communications to the DAC and GPIO regis-
ters are permitted during conversion. However, coupled
noise may result in degraded ADC SNR.
______________________________________________________________________________________ 31
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
(CONVERSION BYTE)
(ACQUISITION1)
DIN
(CONVERSION1)
(ACQUISITION2)
CS
SCLK
DOUT
MSB1
LSB1
MSB2
EOC
X = DON'T CARE.
Figure 9. Clock Mode 11—Externally Timed Acquisition, Sampling, and Conversion without CNVST
Conversion-Time Calculations
The conversion time for each scan is based on a num-
ber of different factors: conversion time per sample,
samples per result, results per scan, if a temperature
measurement is requested, and if the external refer-
ence is in use. Use the following formula to calculate
the total conversion time for an internally timed conver-
sion in clock mode 00 and 10 (see the Electrical
Characteristics, as applicable):
Externally Clocked Acquisitions and
Conversions Using the Serial Interface
ADC Conversions in Clock Mode 11
In clock mode 11, acquisitions and conversions are ini-
tiated by writing a command byte to the conversion
register and are performed one at a time using SCLK
as the conversion clock. Scanning, averaging and the
FIFO are disabled, and the conversion result is avail-
able at DOUT during the conversion. Output data is
updated on the rising edge of SCLK in clock mode 11.
See Figure 9 for clock mode 11 timing.
Total conversion time =
t
x n
x n + t + t
SCAN TS INT-REF,SU
CNV
AVG
where:
= t
Initiate a conversion by writing a command byte to the
conversion register followed by 16 SCLK cycles. If CS
is pulsed high between the eighth and ninth cycles, the
pulse width must be less than 100µs. To continuously
convert at 16 cycles per conversion, alternate 1 byte of
zeros (NOP byte) between each conversion byte. If 2
NOP bytes follow a conversion byte, the analog cells
power down at the end of the second NOP. Set the
FBGON bit to one in the reset register to keep the inter-
nal bias block powered.
t
(where t
is dependent on clock mode
DOV
CNV
DOV
and reference mode selected)
n
AVG
= samples per result (amount of averaging)
n
= number of times each channel is scanned; set
SCAN
to one unless [SCAN1, SCAN0] = 10
t
= time required for temperature measurement
TS
(53.1µs); set to zero if temperature measurement is not
requested
26/MAX1048
If reference mode 00 is requested, or if an external refer-
ence is selected but a temperature measurement is being
requested, wait 45µs with CS high after writing the con-
version byte to extend the acquisition and allow the inter-
nal reference to power up. To perform a temperature
measurement, write 24 bytes (192 cycles) of zeros after
the conversion byte. The temperature result appears on
DOUT during the last 2 bytes of the 192 cycles.
Temperature results are available in 12-bit format.
t
= t
(external-reference wake-up); if a
WU
INT-REF,SU
conversion using the external reference is requested
In clock mode 01, the total conversion time depends on
how long CNVST is held low or high. Conversion time in
externally clocked mode (CKSEL1, CKSEL0 = 11)
depends on the SCLK period and how long CS is held
high between each set of eight SCLK cycles. In clock
mode 01, the total conversion time does not include the
time required to turn on the internal reference.
32 ______________________________________________________________________________________
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
26/MAX1048
t
CH
t
CL
32
16
8
SCLK
DIN
5
1
2
3
4
t
DH
t
DS
D13
D12
D11
D15
D14
D1
D0
t
DOT
t
DOD
t
DOE
D15
D7
D14
D6
D12
D4
D13
D5
DOUT
D1
D0
t
CSS
t
CSPWH
t
CSH
CS
Figure 10. DAC/GPIO Serial-Interface Timing (Clock Modes 00, 01, and 10)
DAC/GPꢂO Timing
Figures 10–13 detail the timing diagrams for writing to
the DAC and GPIOs. Figure 10 shows the timing speci-
fications for clock modes 00, 01, and 10. Figure 11
shows the timing specifications for clock mode 11.
Figure 12 details the timing specifications for the DAC
input select register and 2 bytes to follow. Output data
is updated on the rising edge of SCLK in clock mode
11. Figure 13 shows the GPIO timing. Figure 14 shows
the timing details of a hardware LDAC command DAC-
register update. For a software-command DAC-register
update, t is valid from the rising edge of CS, which fol-
S
lows the last data bit in the software command word.
______________________________________________________________________________________ 33
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
t
CH
t
CL
32
16
8
SCLK
5
1
2
3
4
t
DH
t
DS
D15
D14
D13
D12
D11
D1
D0
DIN
DOUT
CS
t
t
DOT
DOE
t
DOD
D15
D7
D14
D6
D13
D5
D12
D4
D1
D0
t
CSS
t
CSPWH
t
CSH
Figure 11. DAC/GPIO Serial-Interface Timing (Clock Mode 11)
SCLK
10
24
1
2
8
9
26/MAX1048
DIN
BIT 7 (MSB)
BIT 6
BIT 0 (LSB)
BIT 15
BIT 14
BIT 1
BIT 0
DOUT
CS
THE COMMAND BYTE
INITIALIZES THE DAC SELECT
REGISTER
THE NEXT 16 BITS SELECT THE DAC
AND THE DATA WRITTEN TO IT
Figure 12. DAC-Select Register Byte and DAC Serial-Interface Word
34 ______________________________________________________________________________________
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
26/MAX1048
CS
t
GOD
t
GSU
GPIO INPUT/OUTPUT
Figure 13. GPIO Timing
t
LDACPWL
LDAC
t
S
1 LSB
OUT_
Figure 14. LDAC Functionality
The MAX1040/MAX1042/MAX1046/MAX1048 thin QFN
packages contain an exposed pad on the underside of
the device. Connect this exposed pad to AGND. Refer to
the MAX1258EVKIT for an example of proper layout.
LDAC Functionality
Drive LDAC low to transfer the content of the input reg-
isters to the DAC registers. Drive LDAC permanently
low to make the DAC register transparent. The DAC
output typically settles from zero to full scale within
LSB after 2µs. See Figure 14.
1
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. INL for
the MAX1040/MAX1042/MAX1046/MAX1048 is mea-
sured using the end-point method.
Layout, Grounding, and Bypassing
For best performance, use PC boards. Ensure that digi-
tal and analog signal lines are separated from each
other. Do not run analog and digital signals parallel to
one another (especially clock signals) or do not run dig-
ital lines underneath the MAX1040/MAX1042/
MAX1046/MAX1048 package. High-frequency noise in
the AV
power supply may affect performance.
DD
Bypass the AV
AGND, close to the AV
with a 0.1µF capacitor to DGND, close to the DV
supply with a 0.1µF capacitor to
DD
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A
DNL error specification of less than 1 LSB guarantees
no missing codes and a monotonic transfer function.
pin. Bypass the DV
supply
DD
DD
pin.
DD
Minimize capacitor lead lengths for best supply-noise
rejection. If the power supply is very noisy, connect a
10Ω resistor in series with the supply to improve power-
supply filtering.
______________________________________________________________________________________ 35
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Unipolar ADC Offset Error
For an ideal converter, the first transition occurs at 0.5
LSB, above zero. Offset error is the amount of deviation
between the measured first transition point and the
ideal first transition point.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all other ADC output signals:
SINAD(dB) = 20 x log (Signal
/ Noise
)
RMS
RMS
Bipolar ADC Offset Error
While in bipolar mode, the ADC’s ideal midscale transi-
tion occurs at AGND -0.5 LSB. Bipolar offset error is the
measured deviation from this ideal value.
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quanti-
zation noise only. With an input range equal to the full-
scale range of the ADC, calculate the ENOB as follows:
ADC Gain Error
Gain error is defined as the amount of deviation
between the ideal transfer function and the measured
transfer function, with the offset error removed and with
a full-scale analog input voltage applied to the ADC,
resulting in all ones at DOUT.
ENOB = (SINAD - 1.76) / 6.02
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
DAC Offset Error
DAC offset error is determined by loading a code of
all zeros into the DAC and measuring the analog
output voltage.
⎡
⎢
⎣
⎤
⎥
⎦
2
2
2
2
2
THD = 20 x log
V
+ V3 + V4 + V5 + V6 /V
2 1
(
)
DAC Gain Error
DAC gain error is defined as the amount of deviation
between the ideal transfer function and the measured
transfer function, with the offset error removed, when
loading a code of all ones into the DAC.
where V is the fundamental amplitude, and V through
6
1
2
V are the amplitudes of the first five harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next largest distortion
component.
Aperture Jitter
Aperture jitter (t ) is the sample-to-sample variation in
AJ
the time between the samples.
ADC Channel-to-Channel Crosstalk
Bias the ON channel to midscale. Apply a full-scale sine
wave test tone to all OFF channels. Perform an FFT on
the ON channel. ADC channel-to-channel crosstalk is
expressed in dB as the amplitude of the FFT spur at the
frequency associated with the OFF channel test tone.
Aperture Delay
Aperture delay (t ) is the time between the rising
AD
edge of the sampling clock and the instant when an
actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital sam-
ples, signal-to-noise ratio (SNR) is the ratio of full-scale
analog input (RMS value) to the RMS quantization error
(residual error). The ideal, theoretical minimum analog-
to-digital noise is caused by quantization error only and
results directly from the ADC’s resolution (N bits):
Intermodulation Distortion (IMD)
IMD is the total power of the intermodulation products
relative to the total input power when two tones, f1 and
f2, are present at the inputs. The intermodulation prod-
ucts are (f1 f2), (2 x f1), (2 x f2), (2 x f1 f2), (2 x f2
f1). The individual input tone levels are at -7dBFS.
26/MAX1048
SNR = (6.02 x N + 1.76)dB
Small-Signal Bandwidth
A small -20dBFS analog input signal is applied to an
ADC so the signal’s slew rate does not limit the ADC’s
performance. The input frequency is then swept up to
the point where the amplitude of the digitized conver-
sion result has decreased by -3dB. Note that the T/H
performance is usually the limiting factor for the small-
signal input bandwidth.
In reality, there are other noise sources besides quanti-
zation noise, including thermal noise, reference noise,
clock jitter, etc. Therefore, SNR is calculated by taking
the ratio of the RMS signal to the RMS noise. RMS noise
includes all spectral components to the Nyquist fre-
quency excluding the fundamental, the first five har-
monics, and the DC offset.
36 ______________________________________________________________________________________
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
26/MAX1048
Full-Power Bandwidth
A large -0.5dBFS analog input signal is applied to an
ADC, and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by -3dB. This point is defined as full-
power input bandwidth frequency.
DAC Power-Supply Rejection
DAC PSR is the amount of change in the converter’s
value at full-scale as the power-supply voltage changes
from its nominal value. PSR assumes the converter’s lin-
earity is unaffected by changes in the power-
supply voltage.
DAC Digital Feedthrough
DAC digital feedthrough is the amount of noise that
appears on the DAC output when the DAC digital con-
trol lines are toggled.
Chip Information
TRANSISTOR COUNT: 58,141
PROCESS: BiCMOS
ADC Power-Supply Rejection
ADC power-supply rejection (PSR) is defined as the
shift in offset error when the power supply is moved
from the minimum operating voltage to the maximum
operating voltage.
Package Information
For the latest package outline information, go to
wwwꢀmaxim-icꢀcom/packages.
PACKAGE TYPE PACKAGE CODE DOCUMEIT IOꢀ
36 TQFN
T3666-3
21-0141
______________________________________________________________________________________ 37
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Pin Configurations
TOP VIEW
TOP VIEW
36 35 34 33 32 31 30 29 28
36 35 34 33 32 31 30 29 28
D.C.
D.C.
EOC
1
2
3
4
5
6
7
8
9
27 AIN0
26 REF1
25 D.C.
24 D.C.
23 N.C.
22 RES_SEL
21 CS
GPIOA0
1
2
3
4
5
6
7
8
9
27 AIN0
GPIOA1
EOC
26 REF1
25 GPIOC1
24 GPIOC0
23 N.C.
DV
DV
DD
DD
DGND
DOUT
SCLK
DIN
DGND
DOUT
SCLK
DIN
MAX1040
MAX1042
22 RES_SEL
21 CS
20 LDAC
19 D.C.
20 LDAC
19 D.C.
OUT0
OUT0
10 11 12 13 14 15 16 17 18
10 11 12 13 14 15 16 17 18
THꢂI QFI
6mm x 6mm x 0ꢀ8mm
THꢂI QFI
6mm x 6mm x 0ꢀ8mm
TOP VIEW
TOP VIEW
36 35 34 33 32 31 30 29 28
36 35 34 33 32 31 30 29 28
D.C.
D.C.
EOC
1
2
3
4
5
6
7
8
9
27 AIN0
26 REF1
25 D.C.
24 D.C.
23 N.C.
22 RES_SEL
21 CS
GPIOA0
GPIOA1
EOC
1
2
3
4
5
6
7
8
9
27 AIN0
26 REF1
25 GPIOC1
24 GPIOC0
23 N.C.
DV
DV
DD
DD
DGND
DOUT
SCLK
DIN
DGND
DOUT
SCLK
DIN
MAX1046
MAX1048
22 RES_SEL
21 CS
26/MAX1048
20 LDAC
19 D.C.
20 LDAC
19 D.C.
OUT0
OUT0
10 11 12 13 14 15 16 17 18
10 11 12 13 14 15 16 17 18
THꢂI QFI
6mm x 6mm x 0ꢀ8mm
THꢂI QFI
6mm x 6mm x 0ꢀ8mm
38 ______________________________________________________________________________________
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
26/MAX1048
Revision History
REVꢂSꢂOI
IUMBER
REVꢂSꢂOI
DATE
DESCRꢂPTꢂOI
PAGES CHAIGED
4
3/08
Changed timing characteristic specification
7
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 39
© 2008 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products.
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