MAX1043BETX [MAXIM]
10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports; 10位，多通道ADC / DAC，带有FIFO ，温度传感器和GPIO端口
| 型号： | MAX1043BETX |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports |
| 文件： | 总44页 (文件大小：622K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3294; Rev 1; 8/04
1 0 -Bit , Mu lt ic h a n n e l ADCs /DACs w it h FIFO,
Te m p e ra t u re S e n s in g , a n d GP IO P o rt s
Ge n e ra l De s c rip t io n
Fe a t u re s
♦ 10-Bit, 300ksps ADC
The MAX1040–MAX1043/MAX1046–MAX1049 integrate a
multichannel, 10-bit, analog-to-digital converter (ADC)
and a quad, 10-bit, digital-to-analog converter (DAC) in a
single IC. The devices also include a temperature sensor
and configurable general-purpose I/O ports (GPIOs) with
a 25MHz SPI™-/QSPI™-/MICROWIRE™-compatible seri-
al interface. The ADC is available in a 4 or an 8 input-
channel version. The four DAC outputs settle within 2.0µs,
and the ADC has a 300ksps conversion rate.
Analog Multiplexer with True-Differential
Track/Hold (T/H)
8 Single-Ended Channels or 4 Differential
Channels (Unipolar or Bipolar)
4 Single-Ended Channels or 2 Differential
Channels (Unipolar or Bipolar)
Excellent Accuracy: ±0.5 LSB INL, ±0.5 LSB
DNL, No Missing Codes Over Temperature
♦ 10-Bit, Quad, 2µs Settling DAC
Ultra-Low-Glitch Energy (4nV•s)
All devices include an internal reference (2.5V or 4.096V)
providing a well-regulated, low-noise reference for both
the ADC and DAC. Programmable reference modes for
the ADC and DAC allow the use of an internal reference,
an external reference, or a combination of both. Features
such as an internal ±1°C accurate temperature sensor,
FIFO, scan modes, programmable internal or external
clock modes, data averaging, and AutoShutdown™ allow
users to minimize both power consumption and proces-
sor requirements. The low glitch energy (4nV•s) and low
digital feedthrough (0.5nV• s) of the integrated quad
DACs make these devices ideal for digital control of fast-
response closed-loop systems.
Power-Up Options from Zero Scale or Full Scale
Excellent Accuracy: ±0.5 LSB INL
♦ Internal Reference or External Single-Ended/
Differential Reference
Internal Reference Voltage 2.5V or 4.096V
♦ Internal ±1°C Accurate Temperature Sensor
♦ On-Chip FIFO Capable of Storing 16 ADC
Conversion Results and One Temperature Result
♦ On-Chip Channel-Scan Mode and Internal
Data-Averaging Features
♦ Analog Single-Supply Operation
+2.7V to +3.6V or +4.75V to +5.25V
♦ 25MHz, SPI/QSPI/MICROWIRE Serial Interface
♦ AutoShutdown Between Conversions
♦ Low-Power ADC
2.5mA at 300ksps
22µA at 1ksps
0.2µA at Shutdown
♦ Low-Power DAC: 1.5µA
The devices are guaranteed to operate with a supply volt-
age from +2.7V to +3.6V (MAX1041/MAX1043/MAX1047/
MAX1049) a nd from +4.75V to +5.25V (MAX1040/
MAX1042/MAX1046/MAX1048). These devices consume
2.5mA a t 300ks p s throug hp ut, only 22µA a t 1ks p s
throughput, and under 0.2µA in the shutdown mode. The
MAX1042/MAX1043/MAX1048/MAX1049 offer four GPIOs
that can be configured as inputs or outputs.
♦ Evaluation Kit Available (Order MAX1258EVKIT)
The MAX1040–MAX1043/MAX1046–MAX1049 are avail-
able in 36-pin thin QFN packages. All devices are speci-
fied over the -40°C to +85°C temperature range.
Ap p lic a t io n s
Closed-Loop Controls for Optical Components
and Base Stations
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
System Supervision and Control
Data-Acquisition Systems
Ord e rin g In fo rm a t io n /S e le c t o r Gu id e
REF
VOLTAGE
(V)
ANALOG
SUPPLY
VOLTAGE (V)
RESOLUTION
BITS***
ADC
DAC
PART
TEMP RANGE
PIN-PACKAGE
GPIOs
CHANNELS CHANNELS
MAX1040BETX -40°C to +85°C 36 Thin QFN-EP**
MAX1041BETX* -40°C to +85°C 36 Thin QFN-EP**
MAX1042BETX -40°C to +85°C 36 Thin QFN-EP**
MAX1043BETX* -40°C to +85°C 36 Thin QFN-EP**
4.096
2.5
4.75 to 5.25
2.7 to 3.6
10
10
10
10
8
8
8
8
4
4
4
4
0
0
4
4
4.096
2.5
4.75 to 5.25
2.7 to 3.6
*Future product—contact factory for availability.
Ordering Information/Selector Guide continued on last page.
Pin Configurations appear at end of data sheet.
**EP = Exposed pad.
***Number of resolution bits refers to both DAC and ADC.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 0 -Bit , Mu lt ic h a n n e l ADCs /DACs w it h FIFO,
Te m p e ra t u re S e n s in g , a n d GP IO P o rt s
ABSOLUTE MAXIMUM RATINGS
AV to AGND .........................................................-0.3V to +6V
Maximum Current into OUT_.............................................100mA
DD
DGND to AGND.....................................................-0.3V to +0.3V
Continuous Power Dissipation (T = +70°C)
A
DV to AV .......................................................-3.0V to +0.3V
36-Pin Thin QFN (6mm x 6mm)
DD
DD
Digital Inputs to DGND.............................................-0.3V to +6V
(derate 26.3mW/°C above +70°C)..........................2105.3mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-60°C to +150°C
Junction Temperature ......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Digital Outputs to DGND .........................-0.3V to (DV + 0.3V)
DD
Analog Inputs, Analog Outputs and REF_
to AGND...............................................-0.3V to (AV + 0.3V)
DD
Maximum Current into Any Pin (except AGND, DGND, AV
,
DD
DV , and OUT_) ...........................................................50mA
DD
Note: If the package power dissipation is not exceeded, one output at a time can be shorted to AV , DV , AGND, or DGND
DD
DD
indefinitely.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AV
= DV
= 2.7V to 3.6V (MAX1041/MAX1043/MAX1047/MAX1049), external reference V
= 2.5V (MAX1041/MAX1043/
DD
DD
REF
MAX1047/MAX1049), AV = DV = 4.75V to 5.25V (MAX1040/MAX1042/MAX1046/MAX1048), external reference V = 4.096V
DD
DD
REF
(MAX1040/MAX1042/MAX1046/MAX1048), f
= 4.8MHz (50% duty cycle), T = -40°C to +85°C, unless otherwise noted. Typical
A
SCLK
va lue s a re a t AV
= DV
= 3V (MAX1041/MAX1043/MAX1047/MAX1049), AV
= DV
= 5V (MAX1040/MAX1042/
DD
DD
DD
DD
MAX1046/MAX1048), T = +25°C. Outputs are unloaded, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
ADC
MIN
TYP
MAX
UNITS
DC ACCURACY (Note 1)
Resolution
10
Bits
LSB
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
±0.5
±0.5
±1.0
±1
DNL
LSB
±0.25
±2.0
±2.0
LSB
Gain Error
(Note 2)
±0.025
±1.4
LSB
Gain Temperature Coefficient
Channel-to-Channel Offset
ppm/°C
LSB
±0.1
DYNAMIC SPECIFICATIONS (10kHz sine wave input, V = 2.5V
(MAX1041/MAX1043/MAX1047/MAX1049), V = 4.096V
IN P-P
IN
P-P
(MAX1040/MAX1042/MAX1046/MAX1048), 300ksps, f
= 4.8MHz)
SCLK
Signal-to-Noise Plus Distortion
SINAD
61
dB
Total Harmonic Distortion
(Up to the Fifth Harmonic)
THD
-70
dBc
Spurious-Free Dynamic Range
Intermodulation Distortion
Full-Linear Bandwidth
SFDR
IMD
66
72
100
1
dBc
dBc
kHz
MHz
f
= 9.9kHz, f
= 10.2kHz
IN1
IN2
SINAD > 70dB
-3dB point
Full-Power Bandwidth
CONVERSION RATE (Note 3)
External reference
0.8
µs
Conversion
clock
Power-Up Time
t
PU
Internal reference (Note 4)
218
cycles
2
_______________________________________________________________________________________
1 0 -Bit , Mu lt ic h a n n e l ADCs /DACs w it h FIFO,
Te m p e ra t u re S e n s in g , a n d GP IO P o rt s
ELECTRICAL CHARACTERISTICS (continued)
(AV
= DV
= 2.7V to 3.6V (MAX1041/MAX1043/MAX1047/MAX1049), external reference V
= 2.5V (MAX1041/MAX1043/
DD
DD
REF
MAX1047/MAX1049), AV = DV = 4.75V to 5.25V (MAX1040/MAX1042/MAX1046/MAX1048), external reference V = 4.096V
DD
DD
REF
(MAX1040/MAX1042/MAX1046/MAX1048), f
= 4.8MHz (50% duty cycle), T = -40°C to +85°C, unless otherwise noted. Typical
A
SCLK
va lue s a re a t AV
= DV
= 3V (MAX1041/MAX1043/MAX1047/MAX1049), AV
= DV
= 5V (MAX1040/MAX1042/
DD
DD
DD
DD
MAX1046/MAX1048), T = +25°C. Outputs are unloaded, unless otherwise noted.)
A
PARAMETER
Acquisition Time
SYMBOL
CONDITIONS
MIN
TYP
3.5
MAX
UNITS
t
(Note 5)
0.6
µs
ACQ
Internally clocked
Conversion Time
t
µs
CONV
Externally clocked
2.7
Internal Clock Frequency
External Clock Frequency
Duty Cycle
Internally clocked conversion
Externally clocked conversion (Note 5)
4.3
MHz
MHz
%
f
0.1
40
4.8
60
CLK
Aperture Delay
30
ns
Aperture Jitter
<50
ps
ANALOG INPUTS
Unipolar
Bipolar
0
V
REF
Input Voltage Range (Note 6)
V
-V
/ 2
V
/ 2
REF
REF
Input Leakage Current
Input Capacitance
±0.01
24
±1
µA
pF
INTERNAL TEMPERATURE SENSOR
T
= +25°C
±0.7
±1.0
1/8
A
Measurement Error (Notes 5, 7)
°C
T
A
= T
to T
MAX
±3.0
MIN
Temperature Resolution
°C/LSB
INTERNAL REFERENCE
MAX1041/MAX1043/MAX1047/MAX1049
MAX1040/MAX1042/MAX1046/MAX1048
2.482
4.066
2.50
2.518
4.126
REF1 Output Voltage
V
4.096
REF1 Voltage Temperature
Coefficient
TC
±30
6.5
ppm/°C
REF
REF1 Output Impedance
REF1 Short-Circuit Current
EXTERNAL REFERENCE
kΩ
V
= 2.5V (MAX1041/MAX1043/
REF
0.39
MAX1047/MAX1049)
mA
V
= 4.096V (MAX1040/MAX1042/
REF
0.63
MAX1046/MAX1048)
AV
0.05
+
DD
REF1 Input Voltage Range
V
REF mode 11 (Note 4)
1
V
V
REF1
AV
+
DD
REF mode 01
REF mode 11
1
0
REF2 Input Voltage Range
(Note 4)
0.05
V
REF2
1
_______________________________________________________________________________________
3
1 0 -Bit , Mu lt ic h a n n e l ADCs /DACs w it h FIFO,
Te m p e ra t u re S e n s in g , a n d GP IO P o rt s
ELECTRICAL CHARACTERISTICS (continued)
(AV
= DV
= 2.7V to 3.6V (MAX1041/MAX1043/MAX1047/MAX1049), external reference V
= 2.5V (MAX1041/MAX1043/
DD
DD
REF
MAX1047/MAX1049), AV = DV = 4.75V to 5.25V (MAX1040/MAX1042/MAX1046/MAX1048), external reference V = 4.096V
DD
DD
REF
(MAX1040/MAX1042/MAX1046/MAX1048), f
= 4.8MHz (50% duty cycle), T = -40°C to +85°C, unless otherwise noted. Typical
A
SCLK
va lue s a re a t AV
= DV
= 3V (MAX1041/MAX1043/MAX1047/MAX1049), AV
= DV
= 5V (MAX1040/MAX1042/
DD
DD
DD
DD
MAX1046/MAX1048), T = +25°C. Outputs are unloaded, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
= 2.5V (MAX1041/MAX1043/
REF
25
80
MAX1047/MAX1049), f
= 300ksps
SAMPLE
REF1 Input Current (Note 9)
I
µA
REF1
V
= 4.096V (MAX1040/MAX1042/
REF
40
±0.01
25
80
±1
80
MAX1046/MAX1048), f
= 300ksps
SAMPLE
Acquisition between conversions
V
= 2.5V (MAX1041/MAX1043/
REF
MAX1047/MAX1049), f
= 300ksps
SAMPLE
REF2 Input Current
I
µA
REF2
V
= 4.096V (MAX1040/MAX1042/
REF
40
80
±1
MAX1046/MAX1048), f
= 300ksps
SAMPLE
Acquisition between conversions
±0.01
DAC
DC ACCURACY (Note 10)
Resolution
10
Bits
LSB
LSB
mV
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
±0.5
±1
DNL
Guaranteed monotonic
±0.5
±10
V
OS
±3
±10
±1.25
±8
ppm of
FS/°C
Offset-Error Drift
Gain Error
GE
±10
LSB
ppm of
FS/°C
Gain Temperature Coefficient
DAC OUTPUT
AV
0.02
-
-
DD
No load
0.02
0.1
Output Voltage Range
V
AV
DD
0.1
10kΩ load to either rail
DC Output Impedance
Capacitive Load
0.5
Ω
(Note 11)
1
nF
AV = 2.7V, V
= 2.5V (MAX1041/
DD
REF
R
L
MAX1043/MAX1047/MAX1049),
gain error < 1%
2000
500
Resistive Load to AGND
Ω
AV = 4.75V, V
= 4.096V (MAX1040/
DD
REF
MAX1042/MAX1046/MAX1048),
gain error < 2%
4
_______________________________________________________________________________________
1 0 -Bit , Mu lt ic h a n n e l ADCs /DACs w it h FIFO,
Te m p e ra t u re S e n s in g , a n d GP IO P o rt s
ELECTRICAL CHARACTERISTICS (continued)
(AV
= DV
= 2.7V to 3.6V (MAX1041/MAX1043/MAX1047/MAX1049), external reference V
= 2.5V (MAX1041/MAX1043/
DD
DD
REF
MAX1047/MAX1049), AV = DV = 4.75V to 5.25V (MAX1040/MAX1042/MAX1046/MAX1048), external reference V = 4.096V
DD
DD
REF
(MAX1040/MAX1042/MAX1046/MAX1048), f
= 4.8MHz (50% duty cycle), T = -40°C to +85°C, unless otherwise noted. Typical
A
SCLK
va lue s a re a t AV
= DV
= 3V (MAX1041/MAX1043/MAX1047/MAX1049), AV
= DV
= 5V (MAX1040/MAX1042/
DD
DD
DD
DD
MAX1046/MAX1048), T = +25°C. Outputs are unloaded, unless otherwise noted.)
A
PARAMETER
Wake-Up Time (Note 12)
1kΩ Output Termination
100kΩ Output Termination
SYMBOL
CONDITIONS
From power-down mode, AV = 5V
MIN
TYP
25
21
1
MAX
UNITS
µs
DD
From power-down mode, AV = 2.7V
DD
Programmed in power-down mode
kΩ
At wake-up or programmed in
power-down mode
100
kΩ
DYNAMIC PERFORMANCE (Notes 5, 13)
Output-Voltage Slew Rate
Output-Voltage Settling Time
Digital Feedthrough
SR
Positive and negative
3
V/µs
µs
t
To 1 LSB, 400 - C00 hex (Note 7)
2
5
S
Code 0, all digital inputs from 0 to DV
0.5
nV•s
DD
Major Code Transition Glitch
Impulse
Between codes 2047 and 2048
From V
4
nV•s
660
720
260
320
REF
Output Noise (0.1Hz to 50MHz)
Output Noise (0.1Hz to 500kHz)
µV
P-P
Using internal reference
From V
REF
µV
P-P
Using internal reference
DAC-to-DAC Transition
Crosstalk
0.5
nV•s
INTERNAL REFERENCE
MAX1041/MAX1043/MAX1047/MAX1049
MAX1040/MAX1042/MAX1046/MAX1048
2.482
4.066
2.50
4.096
±30
2.518
4.126
REF1 Output Voltage
V
REF1 Temperature Coefficient
TC
ppm/°C
REF
V
= 2.5V (MAX1041/MAX1043/
REF
0.39
0.63
MAX1047/MAX1049)
REF1 Short-Circuit Current
mA
V
= 4.096V (MAX1040/MAX1042/
REF
MAX1046/MAX1048)
EXTERNAL REFERENCE INPUT
REF1 Input Voltage Range
REF1 Input Impedance
V
REF modes 01, 10, and 11 (Note 4)
DIGITAL INTERFACE
0.7
70
AV
V
REF1
DD
R
100
130
kΩ
REF1
DIGITAL INPUTS (SCLK, DIN, CS, CNVST, LDAC)
DV = 2.7V to 5.25V
2.4
2.0
DD
Input-Voltage High
V
IH
V
DV = 3.6V to 5.25V
DD
DV = 2.7V to 3.6V
DD
0.8
0.6
Input-Voltage Low
V
IL
V
DV = 3V to 3.6V
DD
DV = 2.7V to 3V
0.5
DD
Input Leakage Current
I
L
0.01
±10
µA
_______________________________________________________________________________________
5
1 0 -Bit , Mu lt ic h a n n e l ADCs /DACs w it h FIFO,
Te m p e ra t u re S e n s in g , a n d GP IO P o rt s
ELECTRICAL CHARACTERISTICS (continued)
(AV
= DV
= 2.7V to 3.6V (MAX1041/MAX1043/MAX1047/MAX1049), external reference V
= 2.5V (MAX1041/MAX1043/
DD
DD
REF
MAX1047/MAX1049), AV = DV = 4.75V to 5.25V (MAX1040/MAX1042/MAX1046/MAX1048), external reference V = 4.096V
DD
DD
REF
(MAX1040/MAX1042/MAX1046/MAX1048), f
= 4.8MHz (50% duty cycle), T = -40°C to +85°C, unless otherwise noted. Typical
A
SCLK
va lue s a re a t AV
= DV
= 3V (MAX1041/MAX1043/MAX1047/MAX1049), AV
= DV
= 5V (MAX1040/MAX1042/
DD
DD
DD
DD
MAX1046/MAX1048), T = +25°C. Outputs are unloaded, unless otherwise noted.)
A
PARAMETER
Input Capacitance
SYMBOL
CONDITIONS
MIN
TYP
MAX
0.4
UNITS
C
15
pF
IN
DIGITAL OUTPUT (DOUT) (Note 14)
Output-Voltage Low
V
OL
I
= 2mA
V
V
SINK
DV
-
-
DD
Output-Voltage High
V
OH
I
= 2mA
SOURCE
0.5
Tri-State Leakage Current
±10
0.4
µA
pF
Tri-State Output Capacitance
DIGITAL OUTPUT (EOC) (Note 14)
Output-Voltage Low
C
15
OUT
V
OL
I
= 2mA
V
V
SINK
DV
DD
Output-Voltage High
V
OH
I
= 2mA
SOURCE
0.5
Tri-State Leakage Current
±10
µA
pF
Tri-State Output Capacitance
C
15
OUT
DIGITAL OUTPUTS (GPIO_) (Note 14)
I
= 2mA
= 4mA
0.4
0.8
SINK
GPIOC_ Output-Voltage Low
V
I
SINK
DV
0.5
-
-
DD
GPIOC_ Output-Voltage High
GPIOA_ Output-Voltage Low
GPIOA_ Output-Voltage High
Tri-State Leakage Current
I
= 2mA
V
V
V
SOURCE
I
= 15mA
0.8
SINK
DV
DD
I
= 15mA
SOURCE
0.8
±10
µA
pF
Tri-State Output Capacitance
C
15
OUT
DD
POWER REQUIREMENTS (Note 15)
Digital Positive-Supply Voltage
Digital Positive-Supply Current
DV
2.7
AV
V
DD
Idle, all blocks shut down
0.2
1
4
µA
mA
DI
DD
Only ADC on, external reference
MAX1041/MAX1043/MAX1047/MAX1049
MAX1040/MAX1042/MAX1046/MAX1048
Idle, all blocks shut down
2.7
3.6
5.25
2
Analog Positive-Supply Voltage
Analog Positive-Supply Current
AV
V
DD
4.75
0.2
2.8
2.6
1.5
µA
f
= 300ksps
= 100ksps
4.2
SAMPLE
Only ADC on,
external reference
A
IDD
mA
dB
f
SAMPLE
All DACs on, no load, internal reference
4.0
AV = 2.7V (MAX1041/MAX1043/
DD
MAX1047/MAX1049)
-77
-80
REF1 Positive-Supply Rejection
PSRR
AV = 4.75V (MAX1040/MAX1042/
DD
MAX1046/MAX1048)
6
_______________________________________________________________________________________
1 0 -Bit , Mu lt ic h a n n e l ADCs /DACs w it h FIFO,
Te m p e ra t u re S e n s in g , a n d GP IO P o rt s
ELECTRICAL CHARACTERISTICS (continued)
(AV
= DV
= 2.7V to 3.6V (MAX1041/MAX1043/MAX1047/MAX1049), external reference V
= 2.5V (MAX1041/MAX1043/
DD
DD
REF
MAX1047/MAX1049), AV = DV = 4.75V to 5.25V (MAX1040/MAX1042/MAX1046/MAX1048), external reference V = 4.096V
DD
DD
REF
(MAX1040/MAX1042/MAX1046/MAX1048), f
= 4.8MHz (50% duty cycle), T = -40°C to +85°C, unless otherwise noted. Typical
A
SCLK
va lue s a re a t AV
= DV
= 3V (MAX1041/MAX1043/MAX1047/MAX1049), AV
= DV
= 5V (MAX1040/MAX1042/
DD
DD
DD
DD
MAX1046/MAX1048), T = +25°C. Outputs are unloaded, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
AV = 2.7V to 3.6V (MAX1041/
DD
MAX1043/MAX1047/MAX1049)
±0.1
±0.5
Output
code =
FFFhex
DAC Positive-Supply Rejection
PSRD
mV
AV = 4.75V to 5.25V (MAX1040/
DD
MAX1042/MAX1046/MAX1048)
±0.1
±0.06
±0.06
±0.5
±0.5
±0.5
AV = 2.7V to 3.6V (MAX1041/
DD
MAX1043/MAX1047/MAX1049)
Full-
scale
input
ADC Positive-Supply Rejection
PSRA
mV
AV = 4.75V to 5.25V (MAX1040/
DD
MAX1042/MAX1046/MAX1048)
TIMING CHARACTERISTICS (Figures 6–13)
SCLK Clock Period
t
40
16
16
ns
ns
ns
CP
SCLK Pulse-Width High
SCLK Pulse-Width Low
t
40/60 duty cycle
60/40 duty cycle
CH
t
CL
GPIO Output Rise/Fall After
CS Rise
t
C
= 20pF
100
ns
GOD
LOAD
GPIO Input Setup Before CS Fall
LDAC Pulse Width
t
0
20
1.8
10
1.8
10
10
0
ns
ns
GSU
t
LDACPWL
C
C
C
C
= 20pF, SLOW = 0
= 20pF, SLOW = 1
= 20pF, SLOW = 0
= 20pF, SLOW = 1
12.0
40
LOAD
LOAD
LOAD
LOAD
SCLK Fall to DOUT Transition
(Note 16)
t
t
ns
ns
DOT
DOT
12.0
40
SCLK Rise to DOUT Transition
(Notes 16, 17)
CS Fall to SCLK Fall Setup Time
SCLK Fall to CS Rise Setup Time
DIN to SCLK Fall Setup Time
DIN to SCLK Fall Hold Time
CS Pulse-Width High
t
ns
ns
ns
ns
ns
ns
ns
ns
CSS
t
CSH
t
10
0
DS
t
DH
t
50
CSPWH
CS Rise to DOUT Disable
CS Fall to DOUT Enable
EOC Fall to CS Fall
t
C
C
= 20pF
= 20pF
25
DOD
LOAD
LOAD
t
1.5
30
25.0
DOE
t
RDS
CKSEL = 01 (temp sense) or CKSEL =
10 (temp sense), internal reference on
55
CKSEL = 01 (temp sense) or CKSEL =
10 (temp sense), internal reference
initially off
120
CS or CNVST Rise to EOC Fall
t
µs
DOV
CKSEL = 01 (voltage conversion)
8
8
CKSEL = 10 (voltage conversion),
internal reference on
CKSEL = 10 (voltage conversion),
internal reference initially off
80
_______________________________________________________________________________________
7
1 0 -Bit , Mu lt ic h a n n e l ADCs /DACs w it h FIFO,
Te m p e ra t u re S e n s in g , a n d GP IO P o rt s
ELECTRICAL CHARACTERISTICS (continued)
(AV
= DV
= 2.7V to 3.6V (MAX1041/MAX1043/MAX1047/MAX1049), external reference V
= 2.5V (MAX1041/MAX1043/
DD
DD
REF
MAX1047/MAX1049), AV = DV = 4.75V to 5.25V (MAX1040/MAX1042/MAX1046/MAX1048), external reference V = 4.096V
DD
DD
REF
(MAX1040/MAX1042/MAX1046/MAX1048), f
= 4.8MHz (50% duty cycle), T = -40°C to +85°C, unless otherwise noted. Typical
A
SCLK
va lue s a re a t AV
= DV
= 3V (MAX1041/MAX1043/MAX1047/MAX1049), AV
= DV
= 5V (MAX1040/MAX1042/
DD
DD
DD
DD
MAX1046/MAX1048), T = +25°C. Outputs are unloaded, unless otherwise noted.)
A
PARAMETER
CNVST Pulse Width
Note 1: Tested at DV
SYMBOL
CONDITIONS
MIN
40
TYP
MAX
UNITS
ns
CKSEL = 00, CKSEL = 01 (temp sense)
CKSEL = 01 (voltage conversion)
t
CSW
1.4
µs
= AV
= 3.6V (MAX1041/MAX1043/MAX1047/MAX1049), DV
= AV
= 5.25V (MAX1040/MAX1042/
DD
DD
DD
DD
MAX1046/MAX1048).
Note 2: Offset nulled.
Note 3: No bus activity during conversion. Conversion time is defined as the number of conversion clock cycles multiplied by the
clock period.
Note 4: See Table 5 for reference-mode details.
Note 5: Not production tested. Guaranteed by design.
Note 6: See the ADC/DAC References section.
Note 7: Fast automated test, excludes self-heating effects.
Note 8: Specified over the -40°C to +85°C temperature range.
Note 9: REFSEL[1:0] = 00 or when DACs are not powered up.
Note 10: DAC linearity, gain, and offset measurements are made between codes 115 and 3981.
Note 11: The DAC buffers are guaranteed by design to be stable with a 1nF load.
Note 12: Time required by the DAC output to power up and settle within 1 LSB in the external reference mode.
Note 13: All DAC dynamic specifications are valid for a load of 100pF and 10kΩ.
Note 14: Only one digital output (either DOUT, EOC, or the GPIOs) can be indefinitely shorted to either supply at one time.
Note 15: All digital inputs at either DV or DGND. DV should not exceed AV .
DD
DD
DD
Note 16: See the Reset Register section and Table 9 for details on programming the SLOW bit.
Note 17: Clock mode 11 only.
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(AV
= DV
= DV
= 3V (MAX1041/MAX1043/MAX1047/MAX1049), external V
= 2.5V (MAX1041/MAX1043/MAX1047/MAX1049),
= 4.096V (MAX1040/MAX1042/MAX1046/MAX1048),
DD
DD
REF
AV
= 5V (MAX1040/MAX1042/MAX1046/MAX1048), external V
DD REF
DD
f
= 4.8MHz (50% duty cycle), f
= 300ksps, C
= 50pF, 0.1µF capacitor at REF, T = +25°C, unless otherwise noted.)
LOAD A
CLK
SAMPLE
SHUTDOWN CURRENT
vs. TEMPERATURE
SHUTDOWN CURRENT
vs. ANALOG SUPPLY VOLTAGE
SHUTDOWN CURRENT
vs. ANALOG SUPPLY VOLTAGE
0.20
0.18
0.16
0.14
0.12
0.6
0.5
0.4
0.3
0.2
0.1
0
0.30
0.25
0.20
0.15
0.10
0.05
0
MAX1041/MAX1043/MAX1047/MAX1049
MAX1040/MAX1042/MAX1046/MAX1048
0.10
2.7
3.0
3.3
3.6
-40
-15
10
35
60
85
4.75
4.85
4.95
5.05
5.15
5.25
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
8
_______________________________________________________________________________________
1 0 -Bit , Mu lt ic h a n n e l ADCs /DACs w it h FIFO,
Te m p e ra t u re S e n s in g , a n d GP IO P o rt s
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(AV
= DV
= DV
= 3V (MAX1041/MAX1043/MAX1047/MAX1049), external V
= 2.5V (MAX1041/MAX1043/MAX1047/MAX1049),
= 4.096V (MAX1040/MAX1042/MAX1046/MAX1048),
DD
DD
REF
AV
= 5V (MAX1040/MAX1042/MAX1046/MAX1048), external V
DD REF
DD
f
= 4.8MHz (50% duty cycle), f
= 300ksps, C
= 50pF, 0.1µF capacitor at REF, T = +25°C, unless otherwise noted.)
LOAD A
CLK
SAMPLE
INTERNAL OSCILLATOR FREQUENCY
vs. ANALOG SUPPLY VOLTAGE
INTERNAL OSCILLATOR FREQUENCY
vs. ANALOG SUPPLY VOLTAGE
INTERNAL OSCILLATOR FREQUENCY
vs. TEMPERATURE
4.5
4.90
4.85
4.80
4.75
4.70
4.65
4.60
5.0
4.8
4.6
4.4
4.2
4.0
3.8
4.4
4.3
4.2
4.1
4.0
MAX1041/MAX1043/MAX1047/MAX1049
MAX1040/MAX1042/MAX1046/MAX1048
MAX1040/MAX1042/MAX1046/MAX1048
MAX1041/MAX1043/MAX1047/MAX1049
4.75
4.85
4.95
5.05
5.15
5.25
2.7
3.0
3.3
3.6
-40
-15
10
35
60
85
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
ADC INTEGRAL NONLINEARITY
vs. OUTPUT CODE
ADC INTEGRAL NONLINEARITY
vs. OUTPUT CODE
ADC DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
0.3
0.2
0.1
0
0.3
0.2
0.1
0
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.1
-0.2
-0.3
-0.1
-0.2
-0.3
MAX1041/MAX1043/MAX1047/MAX1049
MAX1040/MAX1042/MAX1046/MAX1048
MAX1040/MAX1042/MAX1046/MAX1048
0
256
512
768
1024
0
256
512
768
1024
0
256
512
768
1024
OUTPUT CODE
OUTPUT CODE
OUTPUT CODE
ADC OFFSET ERROR
vs. ANALOG SUPPLY VOLTAGE
ADC OFFSET ERROR
vs. ANALOG SUPPLY VOLTAGE
ADC DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
0
-0.5
-1.0
-1.5
-2.0
-0.4
-0.5
-0.6
-0.7
-0.8
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
MAX1041/MAX1043/MAX1047/MAX1049
MAX1041/MAX1043/MAX1047/MAX1049
MAX1040/MAX1042/MAX1046/MAX1048
2.7
3.0
3.3
3.6
4.75
4.85
4.95
5.05
5.15
5.25
0
256
512
768
1024
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
OUTPUT CODE
_______________________________________________________________________________________
9
1 0 -Bit , Mu lt ic h a n n e l ADCs /DACs w it h FIFO,
Te m p e ra t u re S e n s in g , a n d GP IO P o rt s
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(AV
= DV
= DV
= 3V (MAX1041/MAX1043/MAX1047/MAX1049), external V
= 2.5V (MAX1041/MAX1043/MAX1047/MAX1049),
= 4.096V (MAX1040/MAX1042/MAX1046/MAX1048),
DD
DD
REF
AV
= 5V (MAX1040/MAX1042/MAX1046/MAX1048), external V
DD REF
DD
f
= 4.8MHz (50% duty cycle), f
= 300ksps, C
= 50pF, 0.1µF capacitor at REF, T = +25°C, unless otherwise noted.)
LOAD A
CLK
SAMPLE
ADC GAIN ERROR
vs. ANALOG SUPPLY VOLTAGE
ADC GAIN ERROR
vs. ANALOG SUPPLY VOLTAGE
ADC OFFSET ERROR
vs. TEMPERATURE
0.050
0.025
0
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0
MAX1040/MAX1042/MAX1046/MAX1048
MAX1041/MAX1043/MAX1047/MAX1049
-0.5
-1.0
-1.5
-2.0
-0.025
-0.050
MAX1041/MAX1043/MAX1047/MAX1049
MAX1040/MAX1042/MAX1046/MAX1048
-0.075
4.75
4.85
4.95
5.05
5.15
5.25
2.7
3.0
3.3
3.6
-40
-15
10
35
60
85
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
ADC GAIN ERROR
vs. TEMPERATURE
ADC EXTERNAL REFERENCE
INPUT CURRENT vs. SAMPLING RATE
ANALOG SUPPLY CURRENT
vs. SAMPLING RATE
60
50
40
30
20
10
0
1.00
0.75
0.50
0.25
0
3.0
2.5
2.0
1.5
1.0
0.5
0
MAX1040/MAX1042/MAX1046/MAX1048
MAX1040/MAX1042/MAX1046/MAX1048
MAX1041/MAX1043/MAX1047/MAX1049
MAX1040/MAX1042/MAX1046/MAX1048
-0.25
-0.50
MAX1041/MAX1043/MAX1047/MAX1049
MAX1041/MAX1043/MAX1047/MAX1049
0
50
100
150
200
250
300
-40
-15
10
35
60
85
0
50
100
150
200
250
300
SAMPLING RATE (ksps)
TEMPERATURE (°C)
SAMPLING RATE (ksps)
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
2.7
2.6
2.5
2.4
2.3
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.6
2.5
2.4
2.3
2.2
2.1
2.0
1.9
MAX1040/MAX1042/MAX1046/MAX1048
MAX1041/MAX1043/MAX1047/MAX1049
MAX1040/MAX1042/MAX1046/MAX1048
-40
-15
10
35
60
85
4.75
4.85
4.95
5.05
5.15
5.25
2.7
3.0
3.3
3.6
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
10 ______________________________________________________________________________________
1 0 -Bit , Mu lt ic h a n n e l ADCs /DACs w it h FIFO,
Te m p e ra t u re S e n s in g , a n d GP IO P o rt s
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(AV
= DV
= DV
= 3V (MAX1041/MAX1043/MAX1047/MAX1049), external V
= 2.5V (MAX1041/MAX1043/MAX1047/MAX1049),
= 4.096V (MAX1040/MAX1042/MAX1046/MAX1048),
DD
DD
REF
AV
= 5V (MAX1040/MAX1042/MAX1046/MAX1048), external V
DD REF
DD
f
= 4.8MHz (50% duty cycle), f
= 300ksps, C
= 50pF, 0.1µF capacitor at REF, T = +25°C, unless otherwise noted.)
LOAD A
CLK
SAMPLE
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
DAC INTEGRAL NONLINEARITY
vs. OUTPUT CODE
DAC INTEGRAL NONLINEARITY
vs. OUTPUT CODE
2.16
0.3
0.2
0.1
0
0.3
0.2
0.1
0
2.15
2.14
2.13
2.12
2.11
2.10
-0.1
-0.2
-0.1
-0.2
-0.3
MAX1041/MAX1043/MAX1047/MAX1049
MAX1040/MAX1042/MAX1046/MAX1048
MAX1041/MAX1043/MAX1047/MAX1049
-0.3
-40
-15
10
35
60
85
0
256
512
768
1024
0
256
512
768
1024
TEMPERATURE (°C)
OUTPUT CODE
OUTPUT CODE
DAC DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
DAC DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
DAC FULL-SCALE ERROR
vs. ANALOG SUPPLY VOLTAGE
0.10
0.05
0
0.10
0.05
0
0.04
0.03
0.02
0.01
0
-0.05
-0.10
-0.05
-0.10
MAX1041/MAX1043/MAX1047/MAX1049
MAX1040/MAX1042/MAX1046/MAX1048
MAX1040/MAX1042/MAX1046/MAX1048
1023
1026
1029
1032
1035
1038
1023
1026
1029
1032
1035
1038
4.75
4.85
4.95
5.05
5.15
5.25
OUTPUT CODE
OUTPUT CODE
SUPPLY VOLTAGE (V)
DAC FULL-SCALE ERROR
vs. ANALOG SUPPLY VOLTAGE
DAC FULL-SCALE ERROR
vs. TEMPERATURE
DAC FULL-SCALE ERROR
vs. TEMPERATURE
-0.50
-0.55
-0.60
-0.65
-0.70
2.0
1.5
1.0
0.5
0
0
-0.25
-0.50
-0.75
-1.00
-1.25
-1.50
-1.75
-2.00
INTERNAL REFERENCE
EXTERNAL REFERENCE = 2.500V
INTERNAL REFERENCE
EXTERNAL REFERENCE = 4.096V
-0.5
-1.0
MAX1041/MAX1043/MAX1047/MAX1049
MAX1041/MAX1043/MAX1047/MAX1049
MAX1040/MAX1042/MAX1046/MAX1048
2.7
3.0
3.3
3.6
-40
-15
10
35
60
85
-40
-15
10
35
60
85
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
______________________________________________________________________________________ 11
1 0 -Bit , Mu lt ic h a n n e l ADCs /DACs w it h FIFO,
Te m p e ra t u re S e n s in g , a n d GP IO P o rt s
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(AV
= DV
= DV
= 3V (MAX1041/MAX1043/MAX1047/MAX1049), external V
= 2.5V (MAX1041/MAX1043/MAX1047/MAX1049),
= 4.096V (MAX1040/MAX1042/MAX1046/MAX1048),
DD
DD
REF
AV
= 5V (MAX1040/MAX1042/MAX1046/MAX1048), external V
DD REF
DD
f
= 4.8MHz (50% duty cycle), f
= 300ksps, C
= 50pF, 0.1µF capacitor at REF, T = +25°C, unless otherwise noted.)
LOAD A
CLK
SAMPLE
DAC FULL-SCALE ERROR
vs. LOAD CURRENT
DAC FULL-SCALE ERROR
vs. REFERENCE VOLTAGE
DAC FULL-SCALE ERROR
vs. REFERENCE VOLTAGE
1
0
1.00
0
-0.5
-1.0
-1.5
-2.0
-2.5
0.75
0.50
0.25
0
-1
-2
-3
-4
-0.25
-0.50
-0.75
-1.00
MAX1040/MAX1042/MAX1046/MAX1048
MAX1041/MAX1043/MAX1047/MAX1049
MAX1040/MAX1042/MAX1046/MAX1048
-3.0
0
5
10
15
20
25
30
0
1
2
3
4
5
0
0.5
1.0
1.5
2.0
2.5
3.0
LOAD CURRENT (mA)
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
DAC FULL-SCALE ERROR
vs. LOAD CURRENT
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
1
0
4.12
4.11
4.10
4.09
4.08
2.52
2.51
2.50
2.49
2.48
MAX1041/MAX1043/MAX1047/MAX1049
-1
-2
-3
-4
MAX1041/MAX1043/MAX1047/MAX1049
MAX1040/MAX1042/MAX1046/MAX1048
0
0.5
1.0
1.5
2.0
2.5
3.0
-40
-15
10
35
60
85
-40
-15
10
35
60
85
LOAD CURRENT (mA)
TEMPERATURE (°C)
TEMPERATURE (°C)
ADC REFERENCE SUPPLY CURRENT
vs. TEMPERATURE
ADC REFERENCE SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
ADC REFERENCE SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
50
48
46
44
42
40
43.0
42.8
42.6
42.4
42.2
42.0
25.8
25.7
25.6
25.5
25.4
MAX1040/MAX1042/MAX1046/MAX1048
MAX1040/MAX1042/MAX1046/MAX1048
MAX1041/MAX1043/MAX1047/MAX1049
-40
-15
10
35
60
85
4.75
4.85
4.95
5.05
5.15
5.25
2.7
3.0
3.3
3.6
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
12 ______________________________________________________________________________________
1 0 -Bit , Mu lt ic h a n n e l ADCs /DACs w it h FIFO,
Te m p e ra t u re S e n s in g , a n d GP IO P o rt s
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(AV
= DV
= DV
= 3V (MAX1041/MAX1043/MAX1047/MAX1049), external V
= 2.5V (MAX1041/MAX1043/MAX1047/MAX1049),
= 4.096V (MAX1040/MAX1042/MAX1046/MAX1048),
DD
DD
REF
AV
= 5V (MAX1040/MAX1042/MAX1046/MAX1048), external V
DD REF
DD
f
= 4.8MHz (50% duty cycle), f
= 300ksps, C
= 50pF, 0.1µF capacitor at REF, T = +25°C, unless otherwise noted.)
LOAD A
CLK
SAMPLE
ADC REFERENCE SUPPLY CURRENT
vs. TEMPERATURE
ADC FFT PLOT
ADC IMD PLOT
27.00
0
-20
0
-20
f
= 32.768kHz
= 10.080kHz
= 5.24288MHz
f
= 5.24288MHz
= 9.0kHz
SAMPLE
CLK
f
f
26.75
26.50
26.25
26.00
25.75
25.50
25.25
25.00
ANALOG_)N
IN1
f
f
= 11.0kHz
A = -6dBFS
IN
CLK
IN2
SINAD = 61.21dBc
SNR = 61.21dBc
THD = 73.32dBc
SFDR = 81.25dBc
-40
-40
IMD = 78.0dBc
-60
-60
-80
-80
-100
-120
-140
-100
-120
-140
-160
MAX1041/MAX1043/MAX1047/MAX1049
-160
0
-40
-15
10
35
60
85
50
100
150
200
0
50
100
150
200
TEMPERATURE (°C)
ANALOG INPUT FREQUENCY (kHz)
ANALOG INPUT FREQUENCY (kHz)
DAC OUTPUT LOAD REGULATION
vs. OUTPUT CURRENT
DAC OUTPUT LOAD REGULATION
vs. OUTPUT CURRENT
ADC CROSSTALK PLOT
0
-20
2.08
2.07
2.06
2.05
2.04
1.29
1.28
1.27
1.26
1.25
1.24
1.23
1.22
1.21
f
= 5.24288MHz
= 10.080kHz
= 8.0801kHz
MAX1040/MAX1042/MAX1046/MAX1048
CLK
f
IN1
f
IN2
SNR = 61.11dBc
THD = 73.32dBc
ENOB = 9.86 BITS
SFDR = 86.34dBc
-40
-60
-80
-100
-120
-140
-160
2.03
2.02
2.01
2.00
SINKING
SINKING
SOURCING
SOURCING
DAC OUTPUT = MIDSCALE
MAX1041/MAX1043/MAX1047/MAX1049
DAC OUTPUT = MIDSCALE
0
50
100
150
200
-30
0
30
60
90
-30
-20
0
10
20
30
-10
ANALOG INPUT FREQUENCY (kHz)
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
GPIO OUTPUT VOLTAGE
vs. SINK CURRENT
GPIO OUTPUT VOLTAGE
vs. SOURCE CURRENT
GPIO OUTPUT VOLTAGE
vs. SOURCE CURRENT
1500
1200
900
600
300
0
3.0
2.5
2.0
1.5
1.0
0.5
0
5
4
3
2
1
0
MAX1041/MAX1043/MAX1047/MAX1049
GPIOA0–A3 OUTPUTS
GPIOB0–B3, C0–C3
OUTPUTS
GPIOA0–A3 OUTPUTS
GPIOB0–B3, C0–C3
OUTPUTS
GPIOB0–B3,
C0–C3 OUTPUTS
GPIOA0–A3 OUTPUTS
MAX1040/MAX1042/
MAX1046/MAX1048
MAX1040/MAX1042/MAX1046/MAX1048
0
20
40
60
80
100
0
20
40
60
80
100
0
20
40
60
80
100
SINK CURRENT (mA)
SOURCE CURRENT (mA)
SOURCE CURRENT (mA)
______________________________________________________________________________________ 13
1 0 -Bit , Mu lt ic h a n n e l ADCs /DACs w it h FIFO,
Te m p e ra t u re S e n s in g , a n d GP IO P o rt s
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(AV
= DV
= DV
= 3V (MAX1041/MAX1043/MAX1047/MAX1049), external V
= 2.5V (MAX1041/MAX1043/MAX1047/MAX1049),
= 4.096V (MAX1040/MAX1042/MAX1046/MAX1048),
DD
DD
REF
AV
= 5V (MAX1040/MAX1042/MAX1046/MAX1048), external V
DD REF
DD
f
= 4.8MHz (50% duty cycle), f
= 300ksps, C
= 50pF, 0.1µF capacitor at REF, T = +25°C, unless otherwise noted.)
LOAD A
CLK
SAMPLE
GPIO OUTPUT VOLTAGE
vs. SINK CURRENT
DAC-TO-DAC CROSSTALK
= 10kΩ, C = 100pF
TEMPERATURE SENSOR ERROR
vs. TEMPERATURE
R
LOAD
LOAD
MAX1040 toc51
1500
1200
900
600
300
0
1.00
0.75
0.50
0.25
0
GPIOB0–B3, C0–C3
OUTPUTS
V
1V/div
OUTA
-0.25
-0.50
-0.75
V
OUTB
10mV/div
AC-COUPLED
GPIOA0–A3 OUTPUTS
MAX1041/MAX1043/MAX1047/MAX1049
MAX1041/MAX1043/MAX1047/MAX1049
10 20 30 40 50 60
SINK CURRENT (mA)
-1.00
-40
100µs
0
-15
10
35
60
85
TEMPERATURE (°C)
DAC-TO-DAC CROSSTALK
= 10kΩ, C = 100pF
DYNAMIC RESPONSE RISE TIME
= 10kΩ, C = 100pF
DYNAMIC RESPONSE RISE TIME
R
R
R
= 10kΩ, C
= 100pF
LOAD
MAX1040 toc54
LOAD
LOAD
LOAD
LOAD
LOAD
MAX1040 toc52
MAX1040 toc53
MAX1041/MAX1043/MAX1047/MAX1049
V
OUTA
CS
2V/div
2V/div
V
OUT
1V/div
V
OUTB
10mV/div
AC-COUPLED
V
OUT
2V/div
CS
1V/div
MAX1040/MAX1042/MAX1046/MAX1048
MAX1040/MAX1042/MAX1046/MAX1048
100µs
1µs
1µs
DYNAMIC RESPONSE FALL TIME
DYNAMIC RESPONSE FALL TIME
MAJOR CARRY TRANSITION
R
LOAD
= 10kΩ, C
= 100pF
R
LOAD
= 10kΩ, C
= 100pF
LOAD
MAX1040 toc56
R
LOAD
= 10kΩ, C
= 100pF
LOAD
MAX1040 toc57
LOAD
MAX1040 toc55
MAX1041/MAX1043/MAX1047/MAX1049
CS
2V/div
CS
1V/div
V
1V/div
OUT
V
OUT
V
2V/div
OUT
10mV/div
AC-COUPLED
CS
1V/div
MAX1040/MAX1042/MAX1046/MAX1048
MAX1041/MAX1043/MAX1047/MAX1049
1µs
1µs
1µs
14 ______________________________________________________________________________________
1 0 -Bit , Mu lt ic h a n n e l ADCs /DACs w it h FIFO,
Te m p e ra t u re S e n s in g , a n d GP IO P o rt s
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(AV
= DV
= DV
= 3V (MAX1041/MAX1043/MAX1047/MAX1049), external V
= 2.5V (MAX1041/MAX1043/MAX1047/MAX1049),
= 4.096V (MAX1040/MAX1042/MAX1046/MAX1048),
DD
DD
REF
AV
= 5V (MAX1040/MAX1042/MAX1046/MAX1048), external V
DD REF
DD
f
= 4.8MHz (50% duty cycle), f
= 300ksps, C
= 50pF, 0.1µF capacitor at REF, T = +25°C, unless otherwise noted.)
LOAD A
CLK
SAMPLE
DAC DIGITAL FEEDTHROUGH R
= 10kΩ,
MAJOR CARRY TRANSITION
= 10kΩ, C = 100pF
DAC DIGITAL FEEDTHROUGH R
= 10kΩ,
LOAD
LOAD
C
= 100pF, CS = HIGH, DIN = LOW
R
C = 100pF, CS = HIGH, DIN = LOW
LOAD
MAX1040 toc59
LOAD
LOAD
LOAD
MAX1040 toc60
MAX1040 toc58
SCLK
2V/div
CS
2V/div
SCLK
1V/div
V
OUT
V
OUT
V
OUT
20mV/div
100mV/div
100mV/div
AC-COUPLED
AC-COUPLED
AC-COUPLED
MAX1040/MAX1042/MAX1046/MAX1048
200ns
MAX1041/MAX1043/MAX1047/MAX1049
200ns
MAX1040/MAX1042/MAX1046/MAX1048
1µs
NEGATIVE FULL-SCALE SETTLING TIME
NEGATIVE FULL-SCALE SETTLING TIME
POSITIVE FULL-SCALE SETTLING TIME
R
LOAD
= 10kΩ, C
= 100pF
R
LOAD
= 10kΩ, C
= 100pF
LOAD
MAX1040 toc62
R
LOAD
= 10kΩ, C
= 100pF
LOAD
MAX1040 toc63
LOAD
MAX1040 toc61
MAX1041/MAX1043/MAX1047/MAX1049
MAX1041/MAX1043/MAX1047/MAX1049
V
2V/div
LDAC
V
1V/div
OUT
V
OUT_
1V/div
V
OUT_
2V/div
V
1V/div
V
1V/div
LDAC
LDAC
MAX1040/MAX1042/MAX1046/MAX1048
1µs
2µs
1µs
ADC REFERENCE FEEDTHROUGH
= 10kΩ, C = 100pF
ADC REFERENCE FEEDTHROUGH
POSITIVE FULL-SCALE SETTLING TIME
R
R
= 10kΩ, C
= 100pF
LOAD
MAX1040 toc65
R
= 10kΩ, C
= 100pF
LOAD
MAX1040 toc64
LOAD
LOAD
LOAD
LOAD
MAX1040 toc66
V
1V/div
REF2
V
2V/div
REF2
V
LDAC
2V/div
V
2V/div
OUT_
V
DAC-OUT
V
DAC-OUT
10mV/div
2mV/div
AC-COUPLED
AC-COUPLED
MAX1040/MAX1042/MAX1046/MAX1048
ADC REFERENCE SWITCHING
MAX1041/MAX1043/MAX1047/MAX1049
MAX1040/MAX1042/MAX1046/MAX1048
ADC REFERENCE SWITCHING
200µs
200µs
1µs
______________________________________________________________________________________ 15
1 0 -Bit , Mu lt ic h a n n e l ADCs /DACs w it h FIFO,
Te m p e ra t u re S e n s in g , a n d GP IO P o rt s
P in De s c rip t io n
MAX1040
MAX1041
MAX1042
MAX1043
MAX1046
MAX1047
MAX1048
MAX1049
NAME
N.C.
FUNCTION
1, 2, 15–19,
23, 24, 25,
32, 33
1, 2, 15–19,
23, 24, 25,
31–34
15–19, 23,
32, 33
15–19, 23,
31–34
No Connection. Not internally connected.
Active-Low End-of-Conversion Output. Data is valid after the
falling edge of EOC.
3
3
3
3
EOC
Digital Positive Power Input. Bypass DV to DGND with a
DD
0.1µF capacitor.
4
5
4
5
4
5
4
5
DV
DD
DGND
DOUT
Digital Ground. Connect DGND to AGND.
Serial Data Output. Data is clocked out on the falling edge of
the SCLK clock in clock modes 00, 01, and 10. Data is
clocked out on the rising edge of the SCLK clock in clock
mode 11. High impedance when CS is high.
6
7
6
7
6
7
6
7
Serial Clock Input. Clocks data in and out of the serial
interface. (Duty cycle must be 40% to 60%.) See Table 4 for
details on programming the clock mode.
SCLK
DIN
Serial Data Input. DIN data is latched into the serial interface
on the falling edge of SCLK.
8
8
8
8
OUT0–
OUT3
9–12
9–12
9–12
9–12
DAC Outputs
Positive Analog Power Input. Bypass AV to AGND with a
DD
0.1µF capacitor.
13
14
13
14
13
14
13
14
AV
DD
AGND
Analog Ground
Active-Low Load DAC. LDAC is an asynchronous active-low
input that updates the DAC outputs. Drive LDAC low to make
the DAC registers transparent.
20
21
20
21
20
21
20
21
LDAC
Active-Low Chip-Select Input. When CS is low, the serial
interface is enabled. When CS is high, DOUT is high
impedance.
CS
16 ______________________________________________________________________________________
1 0 -Bit , Mu lt ic h a n n e l ADCs /DACs w it h FIFO,
Te m p e ra t u re S e n s in g , a n d GP IO P o rt s
P in De s c rip t io n (c o n t in u e d )
MAX1040
MAX1041
MAX1042
MAX1043
MAX1046
MAX1047
MAX1048
MAX1049
NAME
FUNCTION
Reset Select. Selects DAC wake-up mode. Set RES_SEL low
to wake up the DAC outputs with a 100kΩ resistor to GND or
set RES_SEL high to wake up the DAC outputs with a 100kΩ
22
26
22
26
22
26
22
26
RES_SEL
resistor to V . Set RES_SEL high to power up the DAC input
REF
register to FFFh. Set RES_SEL low to power up the DAC input
register to 000h.
Reference 1 Input. Reference voltage. Leave unconnected to
use the internal reference (2.5V for the
MAX1041/MAX1043/MAX1047/MAX1049 or 4.096V for the
MAX1040/MAX1042/MAX1046/MAX1048). REF1 is the positive
reference in ADC external differential mode. Bypass REF1 to
AGND with a 0.1µF capacitor in external reference mode only.
See the ADC/DAC References section.
REF1
27–31, 34
35
27–31, 34
35
—
—
—
—
AIN0–AIN5 Analog Inputs
Reference 2 Input/Analog Input Channel 6. See Table 5 for
details on programming the setup register. REF2 is the negative
reference in the ADC external differential reference mode.
REF2/AIN6
CNVST/
AIN7
Active-Low Conversion Start Input/Analog Input 7. See Table 5
for details on programming the setup register.
36
—
36
—
—
—
GPIOA0,
GPIOA1
General-Purpose I/O A0, A1. GPIOA0, GPIOA1 can sink and
source 15mA.
1, 2
1, 2
GPIOC0,
GPIOC1
General-Purpose I/O C0, C1. GPIOC0, GPIOC1 can sink 4mA
and source 2mA.
—
—
24, 25
—
—
24, 25
27–30
27–30
AIN0–AIN3 Analog Inputs
Reference 2 Input. See Table 5 for details on programming the
—
—
35
35
REF2
setup register. REF2 is the negative reference in the ADC
external differential reference mode.
Active-Low Conversion Start Input. See Table 5 details on
programming the setup register.
—
—
—
—
36
—
36
—
CNVST
Exposed Paddle. Must be externally connected to AGND. Do
not use as a ground connect.
EP
______________________________________________________________________________________ 17
1 0 -Bit , Mu lt ic h a n n e l ADCs /DACs w it h FIFO,
Te m p e ra t u re S e n s in g , a n d GP IO P o rt s
trol re g is te rs to the s a me va lue . The MAX1040–
De t a ile d De s c rip t io n
MAX1043/MAX1046–MAX1049 op e ra te with SCLK
The MAX1040–MAX1043/MAX1046–MAX1049 integrate
idling high or low, and thus operate with CPOL = CPHA
a multichannel 10-bit ADC and a quad 10-bit DAC in a
= 0 or CPOL = CPHA = 1. Set CS low to latch any input
single IC. These devices also include a temperature
data at DIN on the falling edge of SCLK. Output data at
sensor and configurable GPIOs with a 25MHz SPI-
DOUT is updated on the falling edge of SCLK in clock
/QSPI-/MICROWIRE-compatible serial interface. The
modes 00, 01, and 10. Output data at DOUT is updated
ADC is available in a 4 or an 8 input-channel version.
on the rising edge of SCLK in clock mode 11. See
The four DAC outputs settle within 2.0µs, and the ADC
Figures 6–11. Bipolar true-differential results and tem-
has a 300ksps conversion rate.
perature-sensor results are available in two’s comple-
ment format, while all other results are in binary.
All d e vic e s inc lud e a n inte rna l re fe re nc e (2.5V or
4.096V) providing a well-regulated, low-noise reference
for both the ADC and DAC. Programmable reference
modes for the ADC and DAC allow the use of an inter-
nal reference, an external reference, or a combination
of both. Features such as an internal ±1°C accurate
temperature sensor, FIFO, scan modes, programmable
internal or external clock modes, data averaging, and
AutoShutdown allow users to minimize both power con-
sumption and processor requirements. The low glitch
energy (4nV•s) and low digital feedthrough (0.5nV•s) of
the integrated quad DACs make these devices ideal for
digital control of fast-response closed-loop systems.
A high-to-low transition on CS initiates the data-input
operation. Serial communications to the ADC always
begin with an 8-bit command byte (MSB first) loaded
from DIN. The command byte and the subsequent data
bytes are clocked from DIN into the serial interface on
the falling edge of SCLK. The serial-interface and fast-
interface circuitry is common to the ADC, DAC, and
GPIO s e c tions . The c onte nt of the c omma nd b yte
determines whether the SPI port should expect 8, 16, or
24 bits and whether the data is intended for the ADC,
DAC, or GPIOs (if applicable). See Table 1. Driving CS
high resets the serial interface.
The devices are guaranteed to operate with a supply
volta g e from +2.7V to +3.6V (MAX1041/MAX1043/
MAX1047/MAX1049) a nd from + 4.5V to + 5.5V
(MAX1040/MAX1042/MAX1046/MAX1048). The s e
devices consume 2.5mA at 300ksps throughput, only
0.22µA at 1ksps throughput, and under 0.2µA in the
shutdown mode. The MAX1042/MAX1043/MAX1048/
MAX1049 offer four GPIOs that can be configured as
inputs or outputs.
The conversion register controls ADC channel selec-
tion, ADC scan mode, and temperature-measurement
requests. See Table 4 for information on writing to the
conversion register. The setup register controls the
clock mode, reference, and unipolar/bipolar ADC con-
figuration. Use a second byte, following the first, to
write to the unipolar-mode or bipolar-mode registers.
See Table 5 for details of the setup register and see
Tables 6, 7, and 8 for setting the unipolar- and bipolar-
mode registers. Hold CS low between the command
byte and the second and third byte. The ADC averag-
ing re g is te r is s p e c ific to the ADC. Se e Ta b le 9 to
address that register. Table 11 shows the details of the
reset register.
Figure 1 shows the MAX1042/MAX1043 functional dia-
gram. The MAX1042/MAX1043/MAX1048/MAX1049 only
include the GPIO A0, A1, GPIO C0, C1 blocks. The
MAX1040/MAX1041/MAX1046/MAX1047 exclude the
GPIOs. The output-conditioning circuitry takes the internal
parallel data bus and converts it to a serial data format at
DOUT, with the appropriate wake-up timing. The arith-
metic logic unit (ALU) performs the averaging function.
Begin a write to the DAC by writing 0001XXXX as a
command byte. The last 4 bits of this command byte
are don’t-care bits. Write another 2 bytes (holding CS
low) to the DAC interface register following the com-
mand byte to select the appropriate DAC and the data
to be written to it. See the DAC Serial Interface section
and Tables 10, 17, and 18.
S P I-Co m p a t ib le S e ria l In t e rfa c e
The MAX1040–MAX1043/MAX1046–MAX1049 feature a
s e ria l inte rfa c e tha t is c omp a tib le with SPI a nd
MICROWIRE devices. For SPI, ensure the SPI bus mas-
ter (typically a microcontroller (µC)) runs in master
mode so that it generates the serial clock signal. Select
the SCLK frequency of 25MHz or less, and set the
clock polarity (CPOL) and phase (CPHA) in the µC con-
Write to the GPIOs (if applicable) by issuing a com-
mand byte to the appropriate register. Writing to the
MAX1042/MAX1043/MAX1048/MAX1049 GPIOs
requires 1 additional byte following the command byte.
18 ______________________________________________________________________________________
1 0 -Bit , Mu lt ic h a n n e l ADCs /DACs w it h FIFO,
Te m p e ra t u re S e n s in g , a n d GP IO P o rt s
DV
DD
AV
DD
GPIOC0,
GPIOC1
GPIOA0,
GPIOA1
MAX1042
MAX1043
GPIO
CONTROL
USER-PROGRAMMABLE
I/O
OUTPUT
CONDITIONING
10-BIT
DAC
INPUT
REGISTER
DAC
REGISTER
OUT0
OUT1
OUT2
OUT3
BUFFER
BUFFER
BUFFER
BUFFER
OSCILLATOR
SCLK
CS
OUTPUT
CONDITIONING
10-BIT
DAC
INPUT
REGISTER
DAC
REGISTER
SPI
PORT
DIN
DOUT
OUTPUT
CONDITIONING
10-BIT
DAC
INPUT
REGISTER
DAC
REGISTER
TEMPERATURE
SENSOR
OUTPUT
CONDITIONING
10-BIT
DAC
INPUT
REGISTER
DAC
REGISTER
EOC
AIN0
LOGIC
CONTROL
CNVST
10-BIT
SAR
ADC
FIFO AND
ALU
T/H
AIN5
REF2/
AIN6
CNVST/
AIN7
REF2
INTERNAL
REFERENCE
REF1
RES_SEL
LDAC
AGND
DGND
Figure 1. MAX1042/MAX1043 Functional Diagram
______________________________________________________________________________________ 19
1 0 -Bit , Mu lt ic h a n n e l ADCs /DACs w it h FIFO,
Te m p e ra t u re S e n s in g , a n d GP IO P o rt s
Table 1. Command Byte (MSB First)
REGISTER NAME
Conversion*
Setup
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
1
0
0
0
0
0
0
0
0
X
1
0
0
0
0
0
0
0
CHSEL2
CHSEL1
CHSEL0
SCAN1
SCAN0
TEMP
CKSEL1
CKSEL0
REFSEL1
REFSEL0
DIFFSEL1
DIFFSEL0
ADC Averaging
DAC Select
1
0
0
0
0
0
0
AVGON
NAVG1
NAVG0
NSCAN1
NSCAN0
1
0
0
0
0
0
X
1
0
0
0
0
X
X
X
Reset
RESET
SLOW
FBGON
GPIO Configure**
GPIO Write**
GPIO Read**
No Operation
0
0
0
0
1
1
0
0
1
0
1
0
X = Don’t care.
*CHESL2 bit is only valid on the MAX1040–MAX1043. Set CHSEL2 to 0 on the MAX1046–MAX1049.
**Only applicable on the MAX1042/MAX1043/MAX1048/MAX1049.
See Tables 12–16 for details on GPIO configuration,
writes, and reads. See the GPIO Command section.
Command bytes written to the GPIOs on devices with-
out GPIOs are ignored.
sion start and use it to request internally timed conver-
sions, without tying up the serial bus. In clock mode 01,
use CNVST to request conversions one channel at a
time, thereby controlling the sampling speed without
tying up the serial bus. Request and start internally
timed conversions through the serial interface by writ-
ing to the conversion register in the default clock mode,
10. Use clock mode 11 with SCLK up to 4.8MHz for
externally timed acquisitions to achieve sampling rates
up to 300ksps. Clock mode 11 disables scanning and
averaging. See Figures 6–9 for timing specifications on
how to begin a conversion.
Power-Up Default State
The MAX1040–MAX1043/MAX1046–MAX1049 power
up with all blocks in shutdown (including the refer-
ence). All registers power up in state 00000000, except
for the setup register and the DAC input register. The
setup register powers up at 0010 1000 with CKSEL1 =
1 and REFSEL1 = 1. The DAC input register powers up
to FFFh when RES_SEL is high, and it powers up to
000h when RES_SEL is low.
These devices feature an active-low, end-of-conversion
output. EOC goes low when the ADC completes the
last requested operation and is waiting for the next
command byte. EOC goes high when CS or CNVST go
low. EOC is always high in clock mode 11.
1 0 -Bit ADC
The MAX1040–MAX1043/MAX1046–MAX1049 ADCs
use a fully differential successive-approximation regis-
ter (SAR) conversion technique and on-chip track-and-
hold (T/H) circuitry to convert temperature and voltage
signals into 10-bit digital results. The analog inputs
accept both single-ended and differential input signals.
Single-ended signals are converted using a unipolar
transfer function, and differential signals are converted
using a selectable bipolar or unipolar transfer function.
See the ADC Transfer Functions section for more data.
Single-Ended or Differential Conversions
The MAX1040–MAX1043/MAX1046–MAX1049 use a
fully differential ADC for all conversions. When a pair of
inputs are connected as a differential pair, each input is
connected to the ADC. When configured in single-
ended mode, the positive input is the single-ended
channel and the negative input is referred to AGND.
See Figure 2.
ADC Clock Modes
When addressing the setup, register bits 5 and 4 of the
command byte (CKSEL1 and CKSEL0, respectively)
control the ADC clock modes. See Table 5. Choose
between four different clock modes for various ways to
start a conversion and determine whether the acquisi-
tions are internally or externally timed. Select clock
mode 00 to configure CNVST/AIN_ to act as a conver-
In differential mode, the T/H samples the difference
between two analog inputs, eliminating common-mode
DC offsets and noise. IN+ and IN- are selected from
the following pairs: AIN0/AIN1, AIN2/AIN3, AIN4/AIN5,
AIN6/AIN7. AIN0–AIN3 are available on all devices.
AIN0–AIN7 are available on the MAX1040–MAX1043.
See Tables 5–8 for more details on configuring the
20 ______________________________________________________________________________________
1 0 -Bit , Mu lt ic h a n n e l ADCs /DACs w it h FIFO,
Te m p e ra t u re S e n s in g , a n d GP IO P o rt s
differential mode. For external T/H timing, use clock
mode 01. After the T/H enters hold mode, the differ-
ence between the sampled positive and negative input
voltages is converted. The input capacitance charging
rate determines the time required for the T/H to acquire
an input signal. If the input signal’s source impedance
is high, the required acquisition time lengthens.
inputs. For the inputs that are configurable as CNVST,
REF2, and an analog input, only one function can be
used at a time.
Unipolar or Bipolar Conversions
Ad d re s s the unip ola r- a nd b ip ola r-mod e re g is te rs
through the setup register (bits 1 and 0). See Table 5 for
the setup register. See Figures 3 and 4 for the transfer-
function graphs. Program a pair of analog inputs for dif-
ferential operation by writing a one to the appropriate bit
of the bipolar- or unipolar-mode register. Unipolar mode
Any source impedance below 300Ω does not signifi-
cantly affect the ADC’s AC performance. A high-imped-
a nc e s ourc e c a n b e a c c ommod a te d e ithe r b y
lengthening t
(only in clock mode 01) or by placing
ACQ
sets the differential input range from 0 to V
A nega-
REF1.
a 1µF capacitor between the positive and negative ana-
log inputs. The combination of the analog-input source
impedance and the capacitance at the analog input cre-
ates an RC filter that limits the analog input bandwidth.
tive differential analog input in unipolar mode causes
the digital output code to be zero. Selecting bipolar
mode sets the differential input range to ±V
/2. The
REF1
digital output code is binary in unipolar mode and two’s
complement in bipolar mode.
Input Bandwidth
The ADC’s input-tracking circuitry has a 1MHz small-
signal bandwidth, making it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. Anti-alias prefiltering
of the input signals is necessary to avoid high-frequency
signals aliasing into the frequency band of interest.
In s ing le -e nd e d mod e , the MAX1040–MAX1043/
MAX1046–MAX1049 always operate in unipolar mode.
The analog inputs are internally referenced to AGND
with a full-scale input range from 0 to the selected ref-
erence voltage.
Analog Input (T/H)
The equivalent circuit of Figure 2 shows the ADC input
a rc hite c ture of the MAX1040–MAX1043/MAX1046–
MAX1049. In track mode, a positive input capacitor is
connected to AIN0–AIN7 in single-ended mode and
AIN0, AIN2, AIN4, a nd AIN6 in d iffe re ntia l mod e .
A negative input capacitor is connected to AGND in
single-ended mode or AIN1, AIN3, AIN5, and AIN7 in
Analog-Input Protection
Internal electrostatic-discharge (ESD) protection diodes
clamp all analog inputs to AV
and AGND, allowing
DD
the inputs to swing from (AGND - 0.3V) to (AV
+
DD
0.3V) without damage. However, for accurate conver-
sions near full scale, the inputs must not exceed AV
DD
by more than 50mV or be lower than AGND by 50mV. If
an analog input voltage exceeds the supplies, limit the
input current to 2mA.
AIN0–AIN7
(SINGLE-ENDED),
AIN0, AIN2,
AIN4, AIN6
(DIFFERENTIAL)
REF1
DAC
ACQ
AGND
Internal FIFO
The MAX1040–MAX1043/MAX1046–MAX1049 contain
a first-in/first-out (FIFO) buffer that holds up to 16 ADC
results plus one temperature result. The internal FIFO
allows the ADC to process and store multiple internally
clocked conversions and a temperature measurement
without being serviced by the serial bus.
CIN+
CIN-
COMPARATOR
HOLD
If the FIFO is filled and further conversions are request-
e d without re a d ing from the FIFO, the old e s t ADC
results are overwritten by the new ADC results. Each
result contains 2 bytes, with the MSB preceded by four
leading zeros. After each falling edge of CS, the oldest
available pair of bytes of data is available at DOUT,
MSB first. When the FIFO is empty, DOUT is zero.
AGND
(SINGLE-ENDED),
AIN1, AIN3,
AIN5, AIN7
(DIFFERENTIAL)
ACQ
ACQ
HOLD
HOLD
The first 2 bytes of data read out after a temperature
measurement always contain the 10-bit temperature
result, preceded by four leading zeros, MSB first. The
AV / 2
DD
Figure 2. Equivalent Input Circuit
______________________________________________________________________________________ 21
1 0 -Bit , Mu lt ic h a n n e l ADCs /DACs w it h FIFO,
Te m p e ra t u re S e n s in g , a n d GP IO P o rt s
LSB is followed by 2 sub-bits. If another temperature
measurement is performed before the first temperature
result is read out, the old measurement is overwritten
by the new result. Temperature results are in degrees
Celsius (two’s complement), at a resolution of 8 LSB
per degree. See the Temperature Measurements sec-
tion for details on converting the digital code to a tem-
perature.
MAX1049 internal reference is 2.5V. The MAX1040/
MAX1042/MAX1046/MAX1048 inte rna l re fe re nc e is
4.096V. When using an external reference on any of
these devices, the voltage range is 0.7V to AV
.
DD
DAC Transfer Function
See Table 2 for various analog outputs from the DAC.
DAC Power-On Wake-Up Modes
The state of the RES_SEL input determines the wake-up
1 0 -Bit DAC
In addition to the 10-bit ADC, the MAX1040–MAX1043/
MAX1046–MAX1049 also include four voltage-output,
10-bit, monotonic DACs with less than 1 LSB integral
nonlinearity error and less than 0.5 LSB differential non-
linearity error. Each DAC has a 2µs settling time and
ultra-low glitch energy (4nV•s). The 10-bit DAC code is
state of the DAC outputs. Connect RES_SEL to AV or
DD
AGND upon powe r-up to be sure the DAC outputs
wake up to a known state. Connect RES_SEL to AGND
to wake up all DAC outputs at 000h. While RES_SEL is
low, the 100kΩ internal resistor pulls the DAC outputs to
AGND a nd the outp ut b uffe rs a re p owe re d d own.
Connect RES_SEL to AV to wake up all DAC outputs
DD
unipolar binary with 1 LSB = V
/ 1024.
REF
a t FFFh. While RES_SEL is hig h, the 100kΩ p ullup
DAC Digital Interface
resistor pulls the DAC outputs to V
and the output
REF1
Figure 1 shows the functional diagram of the MAX1042/
MAX1043. The shift register converts a serial 16-bit
word to parallel data for each input register operating
with a clock rate up to 25MHz. The SPI-compatible digi-
tal interface to the shift register consists of CS, SCLK,
DIN, and DOUT. Serial data at DIN is loaded on the
fa lling e d g e of SCLK. Pull CS low to b e g in a write
s e q ue nc e . Be g in a write to the DAC b y writing
0001XXXX as a command byte. The last 4 bits of the
DAC select register are don’t-care bits. See Table 10.
Write another 2 bytes to the DAC interface register fol-
lowing the command byte to select the appropriate DAC
and the data to be written to it. See Tables 17 and 18.
buffers are powered down.
DAC Power-Up Modes
See Table 18 for a description of the DAC power-up
and power-down modes.
GP IOs
In a d d ition to the inte rna l ADC a nd DAC, the
MAX1042/MAX1043/MAX1048/MAX1049 also provide four
GPIO channels, GPIOA0, GPIOA1, GPIOC0, and GPIOC1.
Table 2. DAC Output Code Table
DAC CONTENTS
ANALOG OUTPUT
The four double-buffered DACs include an input and a
DAC register. The input registers are directly connect-
ed to the shift register and hold the result of the most
recent write operation. The four 10-bit DAC registers
hold the current output code for the respective DAC.
Data can be transferred from the input registers to the
DAC registers by pulling LDAC low or by writing the
a p p rop ria te DAC c omma nd s e q ue nc e a t DIN. Se e
Table 17. The outputs of the DACs are buffered through
four rail-to-rail op amps.
MSB
LSB
⎛
⎞
1023
1024
+V
11
1111
0000
0000
0111
1111
REF
⎜
⎟
⎝
⎠
⎛
⎞
1023
1024
10
10
01
0001
0000
0111
+V
REF
⎜
⎟
⎝
⎠
⎛
⎞
⎛
⎞
512
+V
REF
The MAX1040–MAX1043/MAX1046–MAX1049 DAC
output-voltage range is based on the internal reference
or an external reference. Write to the setup register
(see Table 5) to program the reference. If using an
external voltage reference, bypass REF1 with a 0.1µF
capacitor to AGND. The MAX1041/MAX1043/MAX1047/
+V
=
REF
⎜
⎟
⎜
⎟
1024
2
⎝
⎠
⎝
⎠
⎛
⎞
511
+V
REF
⎜
⎟
1024
⎝
⎠
⎛
⎞
1
1024
0
00
00
0000
0000
0001
0000
+V
REF
⎜
⎟
⎝
⎠
22 ______________________________________________________________________________________
1 0 -Bit , Mu lt ic h a n n e l ADCs /DACs w it h FIFO,
Te m p e ra t u re S e n s in g , a n d GP IO P o rt s
Read and write to the GPIOs as detailed in Table 1 and
Tables 12–16. Also, see the GPIO Command section. See
Figures 11 and 12 for GPIO timing.
external reference mode. The DAC uses REF1 as its
external reference, while the ADC uses REF2 as its
external reference. Set REFSEL[1:0] = 11 to program
the ADC for external differential-reference mode. REF1
is the positive reference and REF2 is the negative refer-
ence in the ADC external differential mode.
Write to the GPIOs by writing a command byte to the
GPIO command register. Write a single data byte to the
MAX1042/MAX1043/MAX1048/MAX1049 following the
command byte.
When REFSEL[1:0] = 00 or 10, REF2/AIN_ functions as
an analog input channel. When REFSEL[1:0] = 01 or 11,
REF2/AIN_ functions as the device’s negative reference.
The GPIOs c a n s ink a nd s ourc e c urre nt. The
MAX1042/MAX1043/MAX1048/MAX1049 GPIOA0 and
GPIOA1 can sink and source up to 15mA. GPIOC0 and
GPIOC1 can sink 4mA and source 2mA. See Table 3.
Te m p e ra t u re Me a s u re m e n t s
Issue a command byte setting bit 0 of the conversion
register to one to take a temperature measurement.
Se e Ta b le 4. The MAX1040–MAX1043/MAX1046–
MAX1049 perform temperature measurements with an
internal diode-connected transistor. The diode bias cur-
rent changes from 68µA to 4µA to produce a tempera-
ture-dependent bias voltage difference. The second
conversion result at 4µA is subtracted from the first at
68µA to calculate a digital value that is proportional to
absolute temperature. The output data appearing at
DOUT is the digital code above, minus an offset to
adjust from Kelvin to Celsius.
Clo c k Mo d e s
Internal Clock
The MAX1040–MAX1043/MAX1046–MAX1049 c a n
operate from an internal oscillator. The internal oscilla-
tor is active in clock modes 00, 01, and 10. Figures 6,
7, and 8 show how to start an ADC conversion in the
three internally timed conversion modes.
Re a d out the d a ta a t c loc k s p e e d s up to 25MHz
through the SPI interface.
External Clock
Set CKSEL1 and CKSEL0 in the setup register to 11 to
set up the interface for external clock mode 11. See
Ta b le 5. Puls e SCLK a t s p e e d s from 0.1MHz to
4.8MHz. Write to SCLK with a 40% to 60% duty cycle.
The SCLK frequency controls the conversion timing.
See Figure 9 for clock mode 11 timing. See the ADC
Conversions in Clock Mode 11 section.
The reference voltage used for the temperature mea-
surements is always derived from the internal reference
source to ensure that 1 LSB corresponds to 1/8th of a
degree Celsius. On every scan where a temperature
measurement is requested, the 12-bit temperature con-
version is carried out first. The first 2 bytes of data read
from the FIFO contain the result of the 12-bit tempera-
ture measurement. If another temperature measure-
ment is performed before the first temperature result is
read out, the old measurement is overwritten by the
new result. Temperature results are in degrees Celsius
(two’s complement). See the Applications Information
section for information on how to perform temperature
measurements in each clock mode.
ADC/DAC Re fe re n c e s
Address the reference through the setup register, bits 3
and 2. See Table 5. Following a wake-up delay, set
REFSEL[1:0] = 00 to program both the ADC and DAC
for internal reference use. Set REFSEL[1:0] = 10 to pro-
gram the ADC for internal reference. Set REFSEL[1:0] =
10 to program the DAC for external reference, REF1.
When using REF1 or REF2/AIN_ in external reference
mod e , c onne c t a 0.1µF c a p a c itor to AGND. Se t
REFSEL[1:0] = 01 to program the ADC and DAC for
Re g is t e r De s c rip t io n s
The MAX1040–MAX1043/MAX1046–MAX1049 commu-
nicate between the internal registers and the external
circuitry through the SPI-compatible serial interface.
Table 1 details the command byte, the registers, and
the bit names. Tables 4–12 show the various functions
within the conversion register, setup register, unipolar-
mode register, bipolar-mode register, ADC averaging
register, DAC select register, reset register, and GPIO
command register, respectively.
Table 3. GPIO Maximum Sink/Source
Current
MAX1042/MAX1043/
MAX1048/MAX1049
CURRENT
GPIOA0, GPIOA1 GPIOC0, GPIOC1
Conversion Register
Select active analog input channels, scan modes, and
a single temperature measurement per scan by issuing
15mA
15mA
4mA
2mA
SINK CURRENT
SOURCE CURRENT
______________________________________________________________________________________ 23
1 0 -Bit , Mu lt ic h a n n e l ADCs /DACs w it h FIFO,
Te m p e ra t u re S e n s in g , a n d GP IO P o rt s
a command byte to the conversion register. Table 4
details channel selection, the four scan modes, and
Table 4. Conversion Register*
BIT
NAME
BIT
FUNCTION
how to request a temperature measurement. Start a
scan by writing to the conversion register when in clock
mod e 10 or 11, or b y a p p lying a low p uls e to the
CNVST pin when in clock mode 00 or 01. See Figures 6
and 7 for timing specifications for starting a scan with
CNVST.
—
7 (MSB)
6
Set to one to select conversion register.
Don’t care.
X
Analog-input channel select.
(MAX1040–MAX1043). Set to 0 on
MAX1046–MAX1049
CHSEL2
5
A conversion is not performed if it is requested on a
channel or one of the channel pairs that has been con-
figured as CNVST or REF2. For channels configured as
differential pairs, the CHSEL0 bit is ignored and the two
pins are treated as a single differential channel. For the
MAX1046–MAX1049, the CHSEL2 bit must be zero.
Channels 4–7 are invalid. Any scans or averages on
these channles can cause corrupt data.
CHSEL1
CHSEL0
SCAN1
SCAN0
4
3
2
1
Analog-input channel select.
Analog-input channel select.
Scan-mode select.
Scan-mode select.
Set to one to take a single temp-
erature measurement. The first
conversion result of a scan contains
temperature information.
TEMP
0 (LSB)
Select scan mode 00 or 01 to return one result per sin-
gle-ended channel and one result per differential pair
within the selected scanning range (set by bits 2 and 1,
SCAN1 and SCAN0), plus one temperature result if
selected. Select scan mode 10 to scan a single input
channel numerous times, depending on NSCAN1 and
NSCAN0 in the ADC a ve ra g ing re g is te r (Ta b le 9).
Select scan mode 11 to return only one result from a
single channel.
*See below for bit details.
SELECTED
CHANNEL
(N)
CHSEL2**
CHSEL1
CHSEL0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
Setup Register
Issue a command byte to the setup register to config-
ure the clock, reference, power-down modes, and ADC
single-ended/differential modes. Table 5 details the bits
in the s e tup -re g is te r c omma nd b yte . Bits 5 a nd 4
(CKSEL1 and CKSEL0) control the clock mode, acqui-
sition and sampling, and the conversion start. Bits 3
and 2 (REFSEL1 and REFSEL0) set the device for either
internal or external reference. Bits 1 and 0 (DIFFSEL1
and DIFFSEL0) address the ADC unipolar-mode and
bipolar-mode registers and configure the analog-input
channels for differential operation.
**Channels 4–7 are invalid on the MAX1046–MAX1049. Set
CHSEL2 bit to 0 on those devices.
SCAN MODE
SCAN1 SCAN0
(CHANNEL N IS SELECTED BY
BITS CHSEL2, CHSEL1, AND CHSEL0)
The ADC reference is always on if any of the following
conditions are true:
0
0
0
1
Scans channels 0 through N.
1)The FBGON bit is set to one in the reset register.
Scans channels N through the highest
numbered channel.
2)At le a s t one DAC outp ut is p owe re d up a nd
REFSEL[1:0] (in the setup register) = 00.
Scans channel N repeatedly. The ADC
averaging register sets the number of
results.
3)At le a s t one DAC is p owe re d d own throug h the
1
1
0
1
100kΩ to V
and REFSEL[1:0] = 00.
REF
If any of the above conditions exist, the ADC reference
is a lwa ys on, b ut the re is a 188 c loc k-c yc le d e la y
be fore te mpe ra ture -se nsor me a sure me nts be gin, if
requested.
No scan. Converts channel N once only.
24 ______________________________________________________________________________________
1 0 -Bit , Mu lt ic h a n n e l ADCs /DACs w it h FIFO,
Te m p e ra t u re S e n s in g , a n d GP IO P o rt s
Table 5. Setup Register*
BIT NAME
—
BIT
FUNCTION
7 (MSB)
Set to zero to select setup register.
Set to one to select setup register.
—
6
CKSEL1
CKSEL0
REFSEL1
REFSEL0
DIFFSEL1
DIFFSEL0
5
Clock mode and CNVST configuration; resets to one at power-up.
Clock mode and CNVST configuration.
4
3
Reference-mode configuration.
2
1
Reference-mode configuration.
Unipolar-/bipolar-mode register configuration for differential mode.
Unipolar-/bipolar-mode register configuration for differential mode.
0 (LSB)
*See below for bit details.
Table 5a. Clock Modes (see the Clock Modes section)
CKSEL1
CKSEL0
CONVERSION CLOCK
Internal
ACQUISITION/SAMPLING
Internally timed.
CNVST CONFIGURATION
0
0
1
1
0
1
0
1
CNVST
CNVST
AIN7
Internal
Externally timed by CNVST.
Internally timed.
Internal
External (4.8MHz max)
Externally timed by SCLK.
AIN7
Table 5b. Clock Modes 00, 01, and 10
VOLTAGE
REFERENCE CONDITIONS
OVERRIDE
REF2
CONFIGURATION
REFSEL1 REFSEL0
AUTOSHUTDOWN
Internal reference turns off after scan is complete. If
internal reference is turned off, there is a programmed
delay of 218 internal-conversion clock cycles.
AIN
Internal (DAC
and ADC)
0
0
0
1
AIN6
REF2
Internal reference required. There is a programmed
Temperature delay of 244 internal-conversion clock cycles for the
internal reference to settle after wake-up.
AIN
Internal reference not used.
External single-
ended (REF1
for DAC and
Internal reference required. There is a programmed
Temperature delay of 244 internal-conversion clock cycles for the
internal reference to settle after wake-up.
REF2 for ADC)
Default reference mode. Internal reference turns off
after scan is complete. If internal reference is turned
off, there is a programmed delay of 218 internal-
AIN
Internal (ADC)
and external
REF1 (DAC)
conversion clock cycles.
1
1
0
1
AIN6
Internal reference required. There is a programmed
delay of 244 internal-conversion clock cycles for the
internal reference to settle after wake-up.
Temperature
AIN
Internal reference not used.
External
differential
(ADC), external
REF1 (DAC)
Internal reference required. There is a programmed
delay of 244 internal-conversion clock cycles for the
internal reference to settle after wake-up.
REF2
Temperature
______________________________________________________________________________________ 25
1 0 -Bit , Mu lt ic h a n n e l ADCs /DACs w it h FIFO,
Te m p e ra t u re S e n s in g , a n d GP IO P o rt s
Table 5c. Clock Mode 11
VOLTAGE
REFERENCE CONDITIONS
OVERRIDE
REF2
CONFIGURATION
REFSEL1 REFSEL0
AUTOSHUTDOWN
Internal reference turns off after scan is complete. If
internal reference is turned off, there is a programmed
delay of 218 external conversion clock cycles.
AIN
Internal (DAC
and ADC)
0
0
0
1
AIN6
REF2
Internal reference required. There is a programmed
delay of 244 external conversion clock cycles for the
internal reference. Temperature-sensor output appears
at DOUT after 188 further external clock cycles.
Temperature
AIN
External single-
ended (REF1
for DAC and
REF2 for ADC)
Internal reference not used.
Internal reference required. There is a programmed
delay of 244 external conversion clock cycles for the
internal reference. Temperature-sensor output appears
at DOUT after 188 further external clock cycles.
Temperature
Default reference mode. Internal reference turns off
after scan is complete. If internal reference is turned
off, there is a programmed delay of 218 external
conversion clock cycles.
AIN
Internal (ADC)
and external
REF1 (DAC)
1
0
AIN6
Internal reference required. There is a programmed
delay of 244 external conversion clock cycles for the
internal reference. Temperature-sensor output appears
at DOUT after 188 further external clock cycles.
Temperature
AIN
Internal reference not used.
External
differential
(ADC), external
REF1 (DAC)
Internal reference required. There is a programmed
delay of 244 external conversion clock cycles for the
internal reference. Temperature-sensor output appears
at DOUT after 188 further external clock cycles.
1
1
REF2
Temperature
Table 5d. Differential Select Modes
DIFFSEL1 DIFFSEL0
FUNCTION
0
0
1
1
0
1
0
1
No data follows the command setup byte. Unipolar-mode and bipolar-mode registers remain unchanged.
No data follows the command setup byte. Unipolar-mode and bipolar-mode registers remain unchanged.
1 byte of data follows the command setup byte and is written to the unipolar-mode register.
1 byte of data follows the command setup byte and is written to the bipolar-mode register.
26 ______________________________________________________________________________________
1 0 -Bit , Mu lt ic h a n n e l ADCs /DACs w it h FIFO,
Te m p e ra t u re S e n s in g , a n d GP IO P o rt s
Table 6. Unipolar-Mode Register (Addressed Through the Setup Register)
BIT NAME
UCH0/1
BIT
7 (MSB)
6
FUNCTION
Configure AIN0 and AIN1 for unipolar differential conversion.
Configure AIN2 and AIN3 for unipolar differential conversion.
UCH2/3
Configure AIN4 and AIN5 for unipolar differential conversion (MAX1040–MAX1043). Set UCH4/5 to
0 on the MAX1046–MAX1049.
UCH4/5
UCH6/7
5
4
Configure AIN6 and AIN7 for unipolar differential conversion (MAX1040–MAX1043). Set UCH6/7 to
0 on the MAX1046–MAX1049.
X
X
X
X
3
Don’t care.
Don’t care.
Don’t care.
Don’t care.
2
1
0 (LSB)
Table 7. Bipolar-Mode Register (Addressed Through the Setup Register)
BIT NAME
BIT
FUNCTION
Set to one to configure AIN0 and AIN1 for bipolar differential conversion. Set the corresponding bits
in the unipolar-mode and bipolar-mode registers to zero to configure AIN0 and AIN1 for unipolar
single-ended conversion.
BCH0/1
7 (MSB)
Set to one to configure AIN2 and AIN3 for bipolar differential conversion. Set the corresponding bits
in the unipolar-mode and bipolar-mode registers to zero to configure AIN2 and AIN3 for unipolar
single-ended conversion.
BCH2/3
BCH4/5
BCH6/7
6
5
4
Set to one to configure AIN4 and AIN5 for bipolar differential conversion (MAX1040–MAX1043). Set
the corresponding bits in the unipolar-mode and bipolar-mode registers to zero to configure AIN4
and AIN5 for unipolar single-ended conversion. Set BCH4/5 to 0 on the MAX1046–MAX1049.
Set to one to configure AIN6 and AIN7 for bipolar differential conversion (MAX1040–MAX1043). Set
the corresponding bits in the unipolar-mode and bipolar-mode registers to zero to configure AIN6
and AIN7 for unipolar single-ended conversion. Set BCH6/7 to 0 on the MAX1046–MAX1049.
X
X
X
X
3
Don’t care.
Don’t care.
Don’t care.
Don’t care.
2
1
0 (LSB)
______________________________________________________________________________________ 27
1 0 -Bit , Mu lt ic h a n n e l ADCs /DACs w it h FIFO,
Te m p e ra t u re S e n s in g , a n d GP IO P o rt s
Unipolar/Bipolar Registers
The final 2 bits (LSBs) of the setup register control the
unip ola r-/b ip ola r-mod e a d d re s s re g is te rs . Se t
DIFFSEL[1:0] = 10 to write to the unipolar-mode regis-
ter. Set bits DIFFSEL[1:0] = 11 to write to the bipolar-
mode register. In both cases, the setup command byte
must be followed by 1 byte of data that is written to the
unipolar-mode register or bipolar-mode register. Hold
CS low and run 16 SCLK cycles before pulling CS high.
If the last 2 bits of the setup register are 00 or 01, nei-
ther the unipolar-mode register nor the bipolar-mode
register is written. Any subsequent byte is recognized
as a new command byte. See Tables 6, 7, and 8 to pro-
gram the unipolar- and bipolar-mode registers.
Both registers power up at all zeros to set the inputs as
eight unipolar single-ended channels. To configure a
channel pair as single-ended unipolar, bipolar differen-
tial, or unipolar differential, see Table 8.
In unip ola r mod e , AIN+ c a n e xc e e d AIN- b y up to
Table 8. Unipolar/Bipolar Channel Function
V . The output format in unipolar mode is binary. In
REF
bipolar mode, either input can exceed the other by up
to V /2. The output format in bipolar mode is two’s
UNIPOLAR-
REF
BIPOLAR-MODE
REGISTER BIT
CHANNEL PAIR
FUNCTION
MODE
complement (see the ADC Transfer Functions section).
REGISTER BIT
ADC Averaging Register
Write a command byte to the ADC averaging register to
configure the ADC to average up to 32 samples for
each requested result, and to independently control the
number of results requested for single-channel scans.
0
0
1
1
0
1
0
1
Unipolar single ended
Bipolar differential
Unipolar differential
Unipolar differential
Table 9. ADC Averaging Register*
BIT NAME
BIT
FUNCTION
—
7 (MSB)
Set to zero to select ADC averaging register.
—
—
6
Set to zero to select ADC averaging register.
5
Set to one to select ADC averaging register.
AVGON
4
Set to one to turn averaging on. Set to zero to turn averaging off.
Configures the number of conversions for single-channel scans.
Configures the number of conversions for single-channel scans.
Single-channel scan count. (Scan mode 10 only.)
Single-channel scan count. (Scan mode 10 only.)
NAVG1
3
NAVG0
2
1
NSCAN1
NSCAN0
0 (LSB)
*See below for bit details.
FUNCTION
AVGON
NAVG1
NAVG0
0
1
1
1
1
X
0
0
1
1
X
0
Performs one conversion for each requested result.
Performs four conversions and returns the average for each requested result.
Performs eight conversions and returns the average for each requested result.
Performs 16 conversions and returns the average for each requested result.
Performs 32 conversions and returns the average for each requested result.
1
0
1
NSCAN1
NSCAN0
FUNCTION (APPLIES ONLY IF SCAN MODE 10 IS SELECTED)
Scans channel N and returns four results.
0
0
1
1
0
1
0
1
Scans channel N and returns eight results.
Scans channel N and returns 12 results.
Scans channel N and returns 16 results.
28 ______________________________________________________________________________________
1 0 -Bit , Mu lt ic h a n n e l ADCs /DACs w it h FIFO,
Te m p e ra t u re S e n s in g , a n d GP IO P o rt s
Table 9 details the four scan modes available in the
ADC conversion register. All four scan modes allow
a ve ra g ing a s long a s the AVGON b it, b it 4 in the
averaging register, is set to 1. Select scan mode 10 to
scan the same channel multiple times. Clock mode 11
d is a b le s a ve ra g ing . For e xa mp le , if AVGON = 1,
NAVG[1:0] = 00, NSCAN [1:0] = 11 and SCAN [1:0] =
10, 16 results are written to the FIFO, with each result
being the average of four conversions of channel N.
Reset Register
Write to the reset register (as shown in Table 11) to
clear the FIFO or to reset all registers to their default
states. Set the RESET bit to one to reset the FIFO. Set
the RESET bit to zero to return the MAX1040–MAX1043/
MAX1046–MAX1049 to their default power-up state. All
registers power up in state 00000000, except for the
s e tup re g is te r tha t p owe rs up in c loc k mod e 10
(CKSEL1 = 1). Set the SLOW bit to one to add a 15ns
delay in the DOUT signal path to provide a longer hold
time. Writing a one to the SLOW bit also clears the con-
tents of the FIFO. Set the FBGON bit to one to force the
bias block and bandgap reference to power up regard-
less of the state of the DAC and activity of the ADC
block. Setting the FBGON bit high also removes the
programmed wake-up delay between conversions in
clock modes 01 and 11. Setting the FBGON bit high
also clears the FIFO.
DAC Select Register
Write a command byte 0001XXXX to the DAC select
register (as shown in Table 9) to set up the DAC inter-
face and indicate that another word will follow. The last
4 bits of the DAC select register are don’t-care bits. The
word that follows the DAC select-register command
byte controls the DAC serial interface. See Table 17
and the DAC Serial Interface section.
GPIO Command
Write a command byte to the GPIO command register
to configure, write, or read the GPIOs, as detailed in
Table 12.
Table 10. DAC Select Register
BIT
BIT
FUNCTION
NAME
—
—
—
—
X
7 (MSB) Set to zero to select DAC select register.
Write the command byte 00000011 to configure the
GPIOs. The eight SCLK cycles following the command
byte load data from DIN to the GPIO configuration reg-
ister in the MAX1042/MAX1043/MAX1048/MAX1049.
6
5
4
3
2
1
0
Set to zero to select DAC select register.
Set to zero to select DAC select register.
Set to one to select DAC select register.
Don’t care.
Table 12. GPIO Command Register
X
Don’t care.
BIT NAME
BIT
FUNCTION
X
Don’t care.
—
7 (MSB)
Set to zero to select GPIO register.
Set to zero to select GPIO register.
Set to zero to select GPIO register.
Set to zero to select GPIO register.
Set to zero to select GPIO register.
Set to zero to select GPIO register.
GPIO configuration bit.
X
Don’t care.
—
6
—
5
Table 11. Reset Register
—
—
4
3
BIT
BIT
FUNCTION
—
2
1
NAME
GPIOSEL1
GPIOSEL2
—
—
—
—
—
7 (MSB) Set to zero to select ADC reset register.
0 (LSB)
GPIO write bit.
6
5
4
3
Set to zero to select ADC reset register.
Set to zero to select ADC reset register.
Set to zero to select ADC reset register.
Set to one to select ADC reset register.
GPIOSEL1 GPIOSEL2
FUNCTION
GPIO configuration; written data is
entered in the GPIO configuration
register.
1
1
0
1
0
1
Set to zero to clear the FIFO only. Set to
one to set the device in its power-on
condition.
RESET
SLOW
2
1
GPIO write; written data is entered
in the GPIO write register.
Set to one to turn on slow mode.
GPIO read; the next 8 SCLK cycles
transfer the state of all GPIO
drivers into DOUT.
Set to one to force internal bias block and
bandgap reference to be always powered
up.
FBGON 0 (LSB)
______________________________________________________________________________________ 29
1 0 -Bit , Mu lt ic h a n n e l ADCs /DACs w it h FIFO,
Te m p e ra t u re S e n s in g , a n d GP IO P o rt s
See Tables 13 and 14. The register bits are updated
after the last CS rising edge. All GPIOs default to inputs
upon power-up.
DAC Serial Interface
Write a command byte 0001XXXX to the DAC select
register to indicate the word to follow is written to the
DAC serial interface, as detailed in Tables 1, 10, 17, and
18. Write the next 16 bits to the DAC interface register,
as shown in Tables 17 and 18. Following the high-to-low
transition of CS, the data is shifted synchronously and
latched into the input register on each falling edge of
SCLK. Each word is 16 bits. The first 4 bits are the con-
trol bits, followed by 10 data bits (MSB first), followed by
2 sub-bits. See Figures 9–12 for DAC timing specifica-
tions.
The data in the register controls the function of each
GPIO, as shown in Tables 13, 14, and 16.
GPIO Write
Write the command byte 00000010 to indicate a GPIO
write operation. The eight SCLK cycles following the
command byte load data from DIN into the GPIO write
register in the MAX1042/MAX1043/MAX1048/MAX1049.
See Tables 14 and 15. The register bits are updated
after the last CS rising edge.
If CS goes high prior to completing 16 SCLK cycles,
the command is discarded. To initiate a new transfer,
drive CS low again.
GPIO Read
Write the command byte 00000001 to indicate a GPIO
read operation. The eight SCLK cycles following the
command byte transfer the state of the GPIOs to DOUT
in the MAX1042/MAX1043/MAX1048/MAX1049. See
Table 16.
For example, writing the DAC serial interface word 1111
0000 and 0011 0100 disconnects DAC outputs 2 and 3
and forces them to a high-impedance state. DAC out-
puts 0 and 1 remain in their previous state.
Table 13. MAX1042/MAX1043/MAX1048/MAX1049 GPIO Configuration
DATA PIN
DIN
DOUT
GPIO COMMAND BYTE
DATA BYTE
GPIOA1 GPIOA0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
GPIOC1
0
GPIOC0
0
X
0
X
0
X
0
X
0
0
0
Table 14. MAX1042/MAX1043/MAX1048/MAX1049 GPIO Write
DATA PIN
DIN
GPIO COMMAND BYTE
DATA BYTE
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
GPIOC1
0
GPIOC0
0
GPIOA1
0
GPIOA0
0
X
X
X
X
0
DOUT
0
0
0
Table 15. GPIO-Mode Control
CONFIGURATION
BIT
WRITE
BIT
OUTPUT
STATE
GPIO
FUNCTION
1
1
0
1
0
1
1
0
Output
Output
Input
Tri-state
Pulldown
(open drain)
0
0
0
Table 16. MAX1042/MAX1043/MAX1048/MAX1049 GPIO Read
DATA PIN
DIN
GPIO COMMAND BYTE
DATA BYTE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
X
0
X
0
X
0
X
0
X
X
X
X
DOUT
GPIOC1
GPIOC0
GPIOA1
GPIOA0
30 ______________________________________________________________________________________
1 0 -Bit , Mu lt ic h a n n e l ADCs /DACs w it h FIFO,
Te m p e ra t u re S e n s in g , a n d GP IO P o rt s
Table 17. DAC Serial-Interface Configuration
16-BIT SERIAL WORD
MSB
CONTROL
BITS
C3 C2 C1 C0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LSB
DESCRIPTION
FUNCTION
DATA BITS
X
X
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
NOP
No Operation.
Reset all internal registers to 000h and
leave output buffers in their present
state.
Preset all internal registers to FFFh and
leave output buffers in their present
state.
0
0
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
RESET
0
0
0
1
1
X
X
X
X
X
X
X
X
X
Pull-High
D9–D0 to input register 0, DAC output
unchanged.
0
0
0
0
0
0
1
1
1
1
0
0
0
1
0
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
DAC0
DAC1
DAC2
DAC3
D9–D0 to input register 1, DAC output
unchanged.
D9–D0 to input register 2, DAC output
unchanged.
D9–D0 to input register 3, DAC output
unchanged.
0
0
1
1
1
1
0
0
1
1
0
0
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NOP
NOP
NOP
NOP
No Operation.
No Operation.
No Operation.
No Operation.
D9–D0 to input registers 0–3 and DAC
register 0–3. DAC outputs updated
(write-through).
1
1
1
0
0
1
1
1
0
0
1
0
—
X
—
X
—
X
—
X
—
X
—
X
—
X
—
X
—
X
—
X
X
X
X
X
X
X
DAC0–DAC3
NOP
No Operation.
D9–D0 to input registers 0–3 and DAC
Register 0–3. DAC outputs updated
(write-through).
—
—
—
—
—
—
—
—
—
—
DAC0–DAC3
D9–D0 to input registers 0–3. DAC
outputs unchanged.
1
1
1
1
0
1
1
0
—
X
—
X
—
X
—
X
—
—
—
—
—
X
—
X
X
X
X
X
DAC0–DAC3
DAC0–DAC3
Input registers to DAC registers
indicated by ones, DAC outputs
updated, equivalent to software LDAC.
(No effect on DACs indicated by zeros.)
______________________________________________________________________________________ 31
1 0 -Bit , Mu lt ic h a n n e l ADCs /DACs w it h FIFO,
Te m p e ra t u re S e n s in g , a n d GP IO P o rt s
Table 18. DAC Power-Up and Power-Down Commands
CONTROL
DATA BITS
BITS
DESCRIPTION
FUNCTION
C3 C2 C1 C0 X
X
X
X
D3 D2 D1 D0
Power up individual DAC buffers indicated by data
in DAC0 through DAC3. A one indicates the DAC
output is connected and active. A zero does not
affect the DAC’s present state.
1
1
1
1
1
1
1
1
X
X
X
X
X
—
—
—
—
—
—
—
—
0
0
0
1
1
0
X
X
Power-Up
Power down individual DAC buffers indicated by
data in DAC0 through DAC3. A one indicates the
DAC output is disconnected and high impedance.
A zero does not affect the DAC’s present state.
X
X
X
X
X
X
Power-Down 1
Power down individual DAC buffers indicated by
data in DAC0 through DAC3. A one indicates the
DAC output is disconnected and pulled to AGND
with a 1kΩ resistor. A zero does not affect the DAC’s
present state.
1
1
1
1
1
1
1
1
1
1
1
1
X
X
X
—
—
—
—
—
—
—
—
—
—
—
—
1
0
1
0
0
1
0
0
1
X
X
X
Power-Down 2
Power down individual DAC buffers indicated by
data in DAC0 through DAC3. A one indicates the
Power-Down 3 DAC output is disconnected and pulled to AGND
with a 100kΩ resistor. A zero does not affect the
DAC’s present state.
X
X
X
X
X
X
Power down individual DAC buffers indicated by
data in DAC0 through DAC3. A one indicates the
Power-Down 4 DAC output is disconnected and pulled to REF1 with
a 100kΩ resistor. A zero does not affect the DAC’s
present state.
transfer function for differential inputs. Code transitions
occur halfway between successive-integer LSB values.
Ou t p u t -Da t a Fo rm a t
Fig ure s 6–9 illus tra te the c onve rs ion timing for the
MAX1040–MAX1043/MAX1046–MAX1049. All 10-bit
conversion results are output in 2-byte format, MSB
first, with four leading zeros and the LSB followed by 2
sub-bits. Data appears on DOUT on the falling edges
of SCLK. Data is binary for unipolar mode and two’s
complement for bipolar mode and temperature results.
See Figures 3, 4, and 5 for input/output and tempera-
ture-transfer functions.
Output coding is binary, with 1 LSB = V
/ 1024 for
REF1
unipolar and bipolar operation, and 1 LSB = +0.125°C
for temperature measurements. Bipolar true-differential
results and temperature-sensor results are available in
two’s complement format, while all others are in binary.
See Tables 6, 7, and 8 for details on which setting
(unipolar or bipolar) takes precedence.
In unip ola r mod e , AIN+ c a n e xc e e d AIN- b y up to
V
. In bipolar mode, either input can exceed the
REF1
ADC Tra n s fe r Fu n c t io n s
Figure 3 shows the unipolar transfer function for single-
ended or differential inputs. Figure 4 shows the bipolar
other by up to V
/2.
REF1
32 ______________________________________________________________________________________
1 0 -Bit , Mu lt ic h a n n e l ADCs /DACs w it h FIFO,
Te m p e ra t u re S e n s in g , a n d GP IO P o rt s
MAX1046–MAX1049 then wake up, scan all requested
channels, store the results in the FIFO, and shut down.
After the scan is complete, EOC is pulled low and the
results are available in the FIFO. Wait until EOC goes
low before pulling CS low to communicate with the seri-
al interface. EOC stays low until CS or CNVST is pulled
low again. A temperature-conversion result, if request-
e d , p re c e d e s a ll othe r FIFO re s ults . Te mp e ra ture
results are available in 12-bit format.
P a rt ia l Re a d s a n d P a rt ia l Writ e s
If the first byte of an entry in the FIFO is partially read
(CS is pulled high after fewer than eight SCLK cycles),
the remaining bits are lost for that byte. The next byte of
data that is read out contains the next 8 bits. If the first
byte of an entry in the FIFO is read out fully, but the
second byte is read out partially, the rest of that byte is
lost. The remaining data in the FIFO is unaffected and
can be read out normally after taking CS low again, as
long as the 4 leading bits (normally zeros) are ignored.
If CS is pulled low before EOC goes low, a conversion
may not be completed and the FIFO data may not be
correct. Incorrect writes (pulling CS high before com-
pleting eight SCLK cycles) are ignored and the register
remains unchanged.
V
REF
= V - V
REF+ REF-
V
REF
V
REF
011....111
011....110
011....101
FS = V / 2 + V
REF
COM
ZS = COM
-FS = -V / 2
REF
V
REF
Ap p lic a t io n s In fo rm a t io n
1 LSB = V / 1024
REF
000....001
000....000
111....111
In t e rn a lly Tim e d Ac q u is it io n s a n d
(COM)
Co n ve rs io n s Us in g CNVST
ADC Conversions in Clock Mode 00
In clock mode 00, the wake-up, acquisition, conversion,
and shutdown sequence is initiated through CNVST
and performed automatically using the internal oscilla-
tor. Results are added to the internal FIFO to be read
out later. See Figure 6 for clock mode 00 timing after a
command byte is issued. See Table 5 for details on
programming the clock mode in the setup register.
V
REF
100....011
100....010
100....001
100....000
-FS
-1 0 +1
(COM)
+FS - 1 LSB
INPUT VOLTAGE (LSB)
Initiate a scan by setting CNVST low for at least 40ns
before pulling it high again. The MAX1040–MAX1043/
±
±
V
REF
Figure 4. Bipolar Transfer Function—Full Scale ( FS) =
/ 2
OUTPUT CODE
FULL-SCALE
TRANSITION
111....111
011....111
011....110
FS = V
REF
111....110
111....101
1 LSB = V / 1024
REF
000....010
000....001
000....000
111....111
111....110
111....101
000....011
000....010
000....001
000....000
100....001
100....000
0
1
2
3
FS
INPUT VOLTAGE (LSB)
0
-256
+255.5
FS - 3/2 LSB
TEMPERATURE (°C)
Figure 5. Temperature Transfer Function
Figure 3. Unipolar Transfer Function—Full Scale (FS) = V
REF
______________________________________________________________________________________ 33
1 0 -Bit , Mu lt ic h a n n e l ADCs /DACs w it h FIFO,
Te m p e ra t u re S e n s in g , a n d GP IO P o rt s
CNVST
(UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS)
CS
SCLK
DOUT
LSB1
MSB2
MSB1
t
RDS
EOC
Figure 6. Clock Mode 00—After writing a command byte, set CNVST low for at least 40ns to begin a conversion.
t
CSW
CNVST
(CONVERSION 2)
(ACQUISITION 1)
(ACQUISITION 2)
CS
t
DOV
(CONVERSION 1)
SCLK
DOUT
LSB1
MSB2
MSB1
EOC
Figure 7. Clock Mode 01—After writing a command byte, request multiple conversions by setting CNVST low for each conversion.
at least 1.4µs to complete the acquisition. If reference
mod e 00 or 10 is s e le c te d , a n a d d itiona l 45µs is
required for the internal reference to power up. If a tem-
perature measurement is being requested, reference
power-up and temperature measurement is internally
timed. In this case, hold CNVST low for at least 40ns.
Do not issue a second CNVST signal before EOC goes
low; otherwise, the FIFO can be corrupted. Wait until all
conversions are complete before reading the FIFO. SPI
communications to the DAC and GPIO registers are per-
mitted during conversion. However, coupled noise may
result in degraded ADC signal-to-noise ratio (SNR).
Set CNVST high to begin a conversion. Sampling is
c omp le te d a p p roxima te ly 500ns a fte r CNVST g oe s
high. After the conversion is complete, the ADC shuts
down and pulls EOC low. EOC stays low until CS or
CNVST is pulled low again. Wait until EOC goes low
before pulling CS or CNVST low. The number of CNVST
signals must equal the number of conversions request-
ed by the scan and averaging registers to correctly
update the FIFO. Wait until all conversions are com-
plete before reading the FIFO. SPI communications to
the DAC and GPIO registers are permitted during con-
Ex t e rn a lly Tim e d Ac q u is it io n s a n d
In t e rn a lly Tim e d Co n ve rs io n s w it h CNVST
ADC Conversions in Clock Mode 01
In clock mode 01, conversions are requested one at a
time using CNVST and performed automatically using
the internal oscillator. See Figure 7 for clock mode 01
timing after a command byte is issued.
Setting CNVST low begins an acquisition, wakes up the
ADC, and places it in track mode. Hold CNVST low for
34 ______________________________________________________________________________________
1 0 -Bit , Mu lt ic h a n n e l ADCs /DACs w it h FIFO,
Te m p e ra t u re S e n s in g , a n d GP IO P o rt s
(CONVERSION BYTE)
DIN
(UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS)
CS
SCLK
DOUT
EOC
MSB1
LSB1
MSB2
t
DOV
Figure 8. Clock Mode 10—The command byte to the conversion register begins the acquisition (CNVST is not required).
version. However, coupled noise may result in degrad-
ed ADC SNR.
In t e rn a lly Tim e d Ac q u is it io n s a n d
Co n ve rs io n s Us in g t h e S e ria l In t e rfa c e
If averaging is turned on, multiple CNVST pulses need to
be performed before a result is written to the FIFO. Once
the proper number of conversions has been performed
to generate an averaged FIFO result (as specified to the
averaging register), the scan logic automatically switch-
es the analog-input multiplexer to the next requested
channel. If a temperature measurement is programmed,
it is performed after the first rising edge of CNVST follow-
ing the command byte written to the conversion register.
The temperature-conversion result is available on DOUT
once EOC has been pulled low. Temperature results are
available in 12-bit format.
ADC Conversions in Clock Mode 10
In clock mode 10, the wake-up, acquisition, conversion,
and shutdown sequence is initiated by writing a com-
mand byte to the conversion register, and is performed
automatically using the internal oscillator. This is the
default clock mode upon power-up. See Figure 8 for
clock mode 10 timing.
Initiate a scan by writing a command byte to the conver-
s ion re g is te r. The MAX1040–MAX1043/MAX1046–
MAX1049 then power up, scan all requested channels,
store the results in the FIFO, and shut down. After the
scan is complete, EOC is pulled low and the results are
available in the FIFO. If a temperature measurement is
requested, the temperature result precedes all other
FIFO results. Temperature results are available in 12-bit
format. EOC stays low until CS is pulled low again. Wait
until all conversions are complete before reading the
FIFO. SPI communications to the DAC and GPIO regis-
ters are permitted during conversion. However, coupled
noise may result in degraded ADC SNR.
______________________________________________________________________________________ 35
1 0 -Bit , Mu lt ic h a n n e l ADCs /DACs w it h FIFO,
Te m p e ra t u re S e n s in g , a n d GP IO P o rt s
(CONVERSION BYTE)
(ACQUISITION1)
DIN
(CONVERSION1)
(ACQUISITION2)
CS
SCLK
DOUT
EOC
MSB1
LSB1
MSB2
Figure 9. Clock Mode 11—Externally Timed Acquisition, Sampling, and Conversion without CNVST
Conversion-Time Calculations
The conversion time for each scan is based on a num-
ber of different factors: conversion time per sample,
samples per result, results per scan, if a temperature
measurement is requested, and if the external refer-
ence is in use. Use the following formula to calculate
the total conversion time for an internally timed conver-
s ion in c loc k mod e 00 a nd 10 (s e e the Ele c tric a l
Characteristics, as applicable):
Ex t e rn a lly Clo c k e d Ac q u is it io n s a n d
Co n ve rs io n s Us in g t h e S e ria l In t e rfa c e
ADC Conversions in Clock Mode 11
In clock mode 11, acquisitions and conversions are ini-
tiated by writing a command byte to the conversion
register and are performed one at a time using the
SCLK as the conversion clock. Scanning, averaging
and the FIFO are disabled, and the conversion result is
available at DOUT during the conversion. Output data
is updated on the rising edge of SCLK in clock mode
11. See Figure 9 for clock mode 11 timing.
Total conversion time =
t
x n
x n
+ t + t
SCAN TS INT-REF,SU
CNV
AVG
where:
= t
and reference mode selected).
Initiate a conversion by writing a command byte to the
conversion register followed by 16 SCLK cycles. If CS
is pulsed high between the eighth and ninth cycles, the
pulse width must be less than 100µs. To continuously
convert at 16 cycles per conversion, alternate 1 byte of
zeros (NOP byte) between each conversion byte. If 2
NOP bytes follow a conversion byte, the analog cells
power down at the end of the second NOP. Set the
FBGON bit to one in the reset register to keep the inter-
nal bias block powered.
t
(where t
is dependent on clock mode
DOV
CNV
DOV
n
= samples per result (amount of averaging)
AVG
n
= number of times each channel is scanned; set
SCAN
to one unless [SCAN1, SCAN0] = 10
t
= time re q uire d for te mp e ra ture me a s ure me nt
TS
(53.1µs); set to zero if temperature measurement is not
requested
If reference mode 00 is requested, or if an external refer-
ence is selected but a temperature measurement is being
requested, wait 45µs with CS high after writing the con-
version byte to extend the acquisition and allow the inter-
nal reference to power up. To perform a temperature
measurement, write 24 bytes (192 cycles) of zeros after
the conversion byte. The temperature result appears on
DOUT d uring the la s t 2 b yte s of the 192 c yc le s .
Temperature results are available in 12-bit format.
t
= t
(external-reference wake-up); if a
WU
INT-REF,SU
conversion using the external reference is requested
In clock mode 01, the total conversion time depends on
how long CNVST is held low or high. Conversion time in
e xte rna lly c loc ke d mod e (CKSEL1, CKSEL0 = 11)
depends on the SCLK period and how long CS is held
high between each set of eight SCLK cycles. In clock
mode 01, the total conversion time does not include the
time required to turn on the internal reference.
36 ______________________________________________________________________________________
1 0 -Bit , Mu lt ic h a n n e l ADCs /DACs w it h FIFO,
Te m p e ra t u re S e n s in g , a n d GP IO P o rt s
t
CH
t
CL
32
16
8
SCLK
DIN
5
1
2
3
4
t
DH
t
DS
D13
D12
D11
D15
D14
D1
D0
t
DOT
t
DOD
t
DOE
D15
D7
D14
D6
D12
D4
D13
D5
DOUT
CS
D1
D0
t
CSS
t
CSPWH
t
CSH
Figure 10. DAC/GPIO Serial-Interface Timing (Clock Modes 00, 01, and 10)
DAC/GPIO Timing
Figures 10–13 detail the timing diagrams for writing to
the DAC and GPIOs. Figure 10 shows the timing speci-
fications for clock modes 00, 01, and 10. Figure 11
shows the timing specifications for clock mode 11.
Figure 12 details the timing specifications for the DAC
input select register and 2 bytes to follow. Output data
is updated on the rising edge of SCLK in clock mode
11. Figure 13 shows the GPIO timing. Figure 14 shows
the timing details of a hardware LDAC command DAC-
register update. For a software-command DAC-register
update, t is valid from the rising edge of CS, which fol-
S
lows the last data bit in the software command word.
______________________________________________________________________________________ 37
1 0 -Bit , Mu lt ic h a n n e l ADCs /DACs w it h FIFO,
Te m p e ra t u re S e n s in g , a n d GP IO P o rt s
t
CH
t
CL
32
16
8
SCLK
5
1
2
3
4
t
DH
t
DS
D15
D14
D13
D12
D11
D1
D0
DIN
DOUT
CS
t
t
DOT
DOE
t
DOD
D15
D7
D14
D6
D13
D5
D12
D4
D1
D0
t
CSS
t
CSPWH
t
CSH
Figure 11. DAC/GPIO Serial-Interface Timing (Clock Mode 11)
SCLK
DIN
10
24
1
2
8
9
BIT 7 (MSB)
BIT 6
BIT 0 (LSB)
BIT 15
BIT 14
BIT 1
BIT 0
DOUT
CS
THE COMMAND BYTE
INITIALIZES THE DAC SELECT
REGISTER
THE NEXT 16 BITS SELECT THE DAC
AND THE DATA WRITTEN TO IT
Figure 12. DAC-Select Register Byte and DAC Serial-Interface Word
38 ______________________________________________________________________________________
1 0 -Bit , Mu lt ic h a n n e l ADCs /DACs w it h FIFO,
Te m p e ra t u re S e n s in g , a n d GP IO P o rt s
CS
t
GOD
t
GSU
GPIO INPUT/OUTPUT
Figure 13. GPIO Timing
t
LDACPWL
LDAC
t
S
1 LSB
OUT_
Figure 14. LDAC Functionality
The MAX1040–MAX1043/MAX1046–MAX1049 thin QFN
packages contain an exposed pad on the underside of
the device. Connect this exposed pad to AGND. Refer to
the MAX1258EVKIT for an example of proper layout.
LDAC Functionality
Drive LDAC low to transfer the content of the input reg-
isters to the DAC registers. Drive LDAC permanently
low to make the DAC register transparent. The DAC
output typically settles from zero to full scale within ±1
LSB after 2µs. See Figure 14.
De fin it io n s
In t e g ra l No n lin e a rit y
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. INL for
the MAX1040–MAX1043/MAX1046–MAX1049 is mea-
sured using the end-point method.
La yo u t , Gro u n d in g , a n d Byp a s s in g
For best performance, use PC boards. Ensure that digi-
tal and analog signal lines are separated from each
other. Do not run analog and digital signals parallel to
one another (especially clock signals) or do not run
d ig ita l line s und e rne a th the MAX1040–MAX1043/
MAX1046–MAX1049 package. High-frequency noise in
the AV
p owe r s up p ly ma y a ffe c t p e rforma nc e .
DD
Bypass the AV
AGND, close to the AV pin. Bypass the DV supply
with a 0.1µF capacitor to DGND, close to the DV pin.
Minimize capacitor lead lengths for best supply-noise
rejection. If the power supply is very noisy, connect a
10Ω resistor in series with the supply to improve power-
supply filtering.
supply with a 0.1µF capacitor to
DD
Diffe re n t ia l No n lin e a rit y
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A
DNL error specification of less than 1 LSB guarantees
no missing codes and a monotonic transfer function.
DD
DD
DD
______________________________________________________________________________________ 39
1 0 -Bit , Mu lt ic h a n n e l ADCs /DACs w it h FIFO,
Te m p e ra t u re S e n s in g , a n d GP IO P o rt s
Un ip o la r ADC Offs e t Erro r
For an ideal converter, the first transition occurs at 0.5
LSB, above zero. Offset error is the amount of deviation
between the measured first transition point and the
ideal first transition point.
S ig n a l-t o -No is e P lu s Dis t o rt io n
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all other ADC output signals:
SINAD(dB) = 20 x log (Signal
/ Noise
)
RMS
RMS
Bip o la r ADC Offs e t Erro r
While in bipolar mode, the ADC’s ideal midscale transi-
tion occurs at AGND -0.5 LSB. Bipolar offset error is the
measured deviation from this ideal value.
Effe c t ive Nu m b e r o f Bit s
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quanti-
zation noise only. With an input range equal to the full-
scale range of the ADC, calculate the ENOB as follows:
ADC Ga in Erro r
Ga in e rror is d e fine d a s the a mount of d e via tion
between the ideal transfer function and the measured
transfer function, with the offset error removed and with
a full-scale analog input voltage applied to the ADC,
resulting in all ones at DOUT.
ENOB = (SINAD - 1.76) / 6.02
To t a l Ha rm o n ic Dis t o rt io n
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
DAC Offs e t Erro r
DAC offset error is determined by loading a code of
a ll ze ros into the DAC a nd me a s uring the a na log
output voltage.
⎡
⎤
1
2
2
2
2
2
THD = 20 x log
V
2
+ V3 + V4 + V5 + V6 /V
(
)
⎢
⎣
⎥
⎦
DAC Ga in Erro r
DAC gain error is defined as the amount of deviation
between the ideal transfer function and the measured
transfer function, with the offset error removed, when
loading a code of all ones into the DAC.
where V is the fundamental amplitude, and V through
V are the amplitudes of the first five harmonics.
6
1
2
S p u rio u s -Fre e Dyn a m ic Ra n g e
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next largest distortion
component.
Ap e rt u re J it t e r
Aperture jitter (t ) is the sample-to-sample variation in
AJ
the time between the samples.
ADC Ch a n n e l-t o -Ch a n n e l Cro s s t a lk
Bias the ON channel to midscale. Apply a full-scale sine
wave test tone to all OFF channels. Perform an FFT on
the ON channel. ADC channel-to-channel crosstalk is
expressed in dB as the amplitude of the FFT spur at the
frequency associated with the OFF channel test tone.
Ap e rt u re De la y
Aperture delay (t ) is the time between the rising
edge of the sampling clock and the instant when an
actual sample is taken.
AD
S ig n a l-t o -No is e Ra t io
For a waveform perfectly reconstructed from digital sam-
ples, signal-to-noise ratio (SNR) is the ratio of full-scale
analog input (RMS value) to the RMS quantization error
(residual error). The ideal, theoretical minimum analog-
to-digital noise is caused by quantization error only and
results directly from the ADC’s resolution (N bits):
In t e rm o d u la t io n Dis t o rt io n (IMD)
IMD is the total power of the intermodulation products
relative to the total input power when two tones, f1 and
f2, are present at the inputs. The intermodulation prod-
ucts are (f1 ± f2), (2 x f1), (2 x f2), (2 x f1 ± f2), (2 x f2 ±
f1). The individual input tone levels are at -7dB FS.
SNR = (6.02 x N + 1.76)dB
S m a ll-S ig n a l Ba n d w id t h
A small -20dB FS analog input signal is applied to an
ADC so the signal’s slew rate does not limit the ADC’s
performance. The input frequency is then swept up to
the point where the amplitude of the digitized conver-
sion result has decreased by -3dB. Note that the T/H
performance is usually the limiting factor for the small-
signal input bandwidth.
In reality, there are other noise sources besides quanti-
zation noise, including thermal noise, reference noise,
clock jitter, etc. Therefore, SNR is calculated by taking
the ratio of the RMS signal to the RMS noise. RMS noise
includes all spectral components to the Nyquist fre-
quency excluding the fundamental, the first five har-
monics, and the DC offset.
40 ______________________________________________________________________________________
1 0 -Bit , Mu lt ic h a n n e l ADCs /DACs w it h FIFO,
Te m p e ra t u re S e n s in g , a n d GP IO P o rt s
Fu ll-P o w e r Ba n d w id t h
A large -0.5dB FS analog input signal is applied to an
ADC, and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by -3dB. This point is defined as full-
power input bandwidth frequency.
DAC P o w e r-S u p p ly Re je c t io n
DAC PSR is the amount of change in the converter’s
value at full-scale as the power-supply voltage changes
from its nominal value. PSR assumes the converter’s
line a rity is una ffe c te d b y c ha ng e s in the p owe r-
supply voltage.
DAC Dig it a l Fe e d t h ro u g h
DAC digital feedthrough is the amount of noise that
appears on the DAC output when the DAC digital con-
trol lines are toggled.
ADC P o w e r-S u p p ly Re je c t io n
ADC power-supply rejection (PSR) is defined as the
shift in offset error when the power-supply is moved
from the minimum operating voltage to the maximum
operating voltage.
Ch ip In fo rm a t io n
TRANSISTOR COUNT: 58,141
PROCESS: BiCMOS
Ord e rin g In fo rm a t io n /S e le c t o r Gu id e
REF
VOLTAGE
(V)
ANALOG
SUPPLY
VOLTAGE (V)
RESOLUTION
BITS***
ADC
DAC
PART
TEMP RANGE
PIN-PACKAGE
GPIOs
CHANNELS CHANNELS
MAX1046BETX -40°C to +85°C 36 Thin QFN-EP**
MAX1047BETX* -40°C to +85°C 36 Thin QFN-EP**
MAX1048BETX -40°C to +85°C 36 Thin QFN-EP**
MAX1049BETX* -40°C to +85°C 36 Thin QFN-EP**
4.096
2.5
4.75 to 5.25
2.7 to 3.6
10
10
10
10
4
4
4
4
4
4
4
4
0
0
4
4
4.096
2.5
4.75 to 5.25
2.7 to 3.6
*Future product—contact factory for availability.
**EP = Exposed pad.
***Number of resolution bits refers to both DAC and ADC.
______________________________________________________________________________________ 41
1 0 -Bit , Mu lt ic h a n n e l ADCs /DACs w it h FIFO,
Te m p e ra t u re S e n s in g , a n d GP IO P o rt s
P in Co n fig u ra t io n s
TOP VIEW
TOP VIEW
36 35 34 33 32 31 30 29 28
36 35 34 33 32 31 30 29 28
N.C.
N.C.
EOC
1
2
3
4
5
6
7
8
9
27 AIN0
26 REF1
25 N.C.
24 N.C.
23 N.C.
22 RES_SEL
21 CS
GPIOA0
1
2
3
4
5
6
7
8
9
27 AIN0
GPIOA1
EOC
26 REF1
25 GPIOC1
24 GPIOC0
23 N.C.
DV
DD
DV
DD
DGND
DOUT
SCLK
DIN
DGND
DOUT
SCLK
DIN
MAX1040
MAX1041
MAX1042
MAX1043
22 RES_SEL
21 CS
20 LDAC
19 N.C.
20 LDAC
19 N.C.
OUT0
OUT0
10 11 12 13 14 15 16 17 18
10 11 12 13 14 15 16 17 18
6mm x 6mm x 0.8mm
THIN QFN
6mm x 6mm x 0.8mm
THIN QFN
TOP VIEW
TOP VIEW
36 35 34 33 32 31 30 29 28
36 35 34 33 32 31 30 29 28
N.C.
N.C.
EOC
1
2
3
4
5
6
7
8
9
27 AIN0
26 REF1
25 N.C.
24 N.C.
23 N.C.
22 RES_SEL
21 CS
GPIOA0
GPIOA1
EOC
1
2
3
4
5
6
7
8
9
27 AIN0
26 REF1
25 GPIOC1
24 GPIOC0
23 N.C.
DV
DV
DD
DD
DGND
DOUT
SCLK
DIN
DGND
DOUT
SCLK
DIN
MAX1046
MAX1047
MAX1048
MAX1049
22 RES_SEL
21 CS
20 LDAC
19 N.C.
20 LDAC
19 N.C.
OUT0
OUT0
10 11 12 13 14 15 16 17 18
10 11 12 13 14 15 16 17 18
6mm x 6mm x 0.8mm
THIN QFN
6mm x 6mm x 0.8mm
THIN QFN
42 ______________________________________________________________________________________
1 0 -Bit , Mu lt ic h a n n e l ADCs /DACs w it h FIFO,
Te m p e ra t u re S e n s in g , a n d GP IO P o rt s
P a c k a g e In fo rm a t io n
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
D2
D
C
L
b
D/2
D2/2
k
E/2
E2/2
(NE-1) X
e
C
L
E
E2
k
L
e
(ND-1) X
e
e
L
C
C
L
L
L1
L
L
e
e
A
A1
A2
PACKAGE OUTLINE
36, 40, 48L THIN QFN, 6x6x0.8mm
1
E
21-0141
2
______________________________________________________________________________________ 43
1 0 -Bit , Mu lt ic h a n n e l ADCs /DACs w it h FIFO,
Te m p e ra t u re S e n s in g , a n d GP IO P o rt s
P a c k a g e In fo rm a t io n (c o n t in u e d )
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1
SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT FOR 0.4mm LEAD PITCH PACKAGE T4866-1.
PACKAGE OUTLINE
36, 40, 48L THIN QFN, 6x6x0.8mm
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
2
E
21-0141
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
44 ____________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 4 0 8 -7 3 7 -7 6 0 0
© 2004 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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