DS8023-RRX+ [MAXIM]
Microprocessor Circuit, CMOS, PDSO28, 0.300 INCH, ROHS COMPLIANT, SOP-28;
| 型号： | DS8023-RRX+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Microprocessor Circuit, CMOS, PDSO28, 0.300 INCH, ROHS COMPLIANT, SOP-28 光电二极管 外围集成电路 |
| 文件： | 总17页 (文件大小：275K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS8023
Smart Card Interface
General Description
Features
The DS8023 smart card interface IC is a low-cost, low-
power, analog front-end for a smart card reader designed
for all ISO 7816, EMV*, and GSM11-11 applications. The
DS8023 supports 5V, 3V, and 1.8V smart cards, and pro-
vides an option for ultra-low stop-mode power consump-
tion. The DS8023 is available in 28-pin TSSOP and SO
packages, and can often be used as a replacement for
the TDA8024 with little or no application changes.
o Analog Interface and Level Shifting for IC Card
Communication
o
8ꢀk ꢁminꢂ ꢃSD ꢁIꢃCꢂ ꢄrotection on Card Interface
ꢄins
o Ultra-Low Stop-Mode Current, Less Than 10nA ꢁtypꢂ
o Internal IC Card-Supply koltage Generation
5.0k 5ꢅ, 80mA ꢁmaxꢂ
The DS8023 is designed to interface between a system
microcontroller and the smart card interface, providing
all power supply, protection, and level shifting required
for IC card applications.
3.0k 8ꢅ, 65mA ꢁmaxꢂ
1.8k 10ꢅ, 30mA ꢁmaxꢂ
o Automatic Card Activation and Deactivation
Controlled by Dedicated Internal Sequencer
Applications
Set-Top Box Conditional Access
Access Control
o I/O Lines from Host Directly Level Shifted for
Smart Card Communication
o Flexible Card Clocꢀ Generation, Supporting
ꢃxternal Crystal Frequency Divided by 1, 2, 4, or 8
Banking Applications
o High-Current/Short-Circuit and High-Temperature
POS Terminals
ꢄrotection
Debit/Credit Payment Terminals
PIN Pads
Pin Configuration
Automated Teller Machines
Telecommunications
TOP VIEW
Pay/Premium Television
CLKDIV1
CLKDIV2
5V/3V
1
2
3
4
5
6
7
8
9
28 AUX2IN
27 AUX1IN
26 I/OIN
25 XTAL2
24 XTAL1
23 OFF
Ordering Information
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
28 TSSOP
28 SO
PGND
DS8023-RJX+
DS8023-RRX+
CP2
V
DDA
DS8023
Note: Contact the factory for availability of other variants and
package options.
+Denotes a lead(Pb)-free/RoHS-compliant package.
CP1
22 GND
V
21 V
DD
UP
PRES
20 RSTIN
19 CMDVCC
18 1_8V
PRES 10
I/O 11
Selector Guide appears at end of data sheet.
AUX2 12
AUX1 13
CGND 14
17 V
CC
16 RST
15 CLK
SO/TSSOP
*EMV is a trademark owned by EMVCo LLC. EMV Level 1 library and hardware reference design available. Contact factory for details.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be
simultaneously available through various sales channels. For information about device errata, go to: www.maximintegrated.com/errata.
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
19-6380; Rev 1; 4/13
DS8023
Smart Card Interface
ABSOLUTꢃ MAXIMUM RATINGS
Voltage Range on V
Voltage Range on V
Relative to GND ...............-0.5V to +6.5V
Maximum Junction Temperature .....................................+125°C
DD
DDA
Relative to PGND...........-0.5V to +6.5V
Maximum Power Dissipation (T = -40°C to +85°C) .......700mW
A
Voltage Range on CP1, CP2, and V
Relative to PGND...............................................-0.5V to +7.5V
Voltage Range on All Other Pins
Storage Temperature Range.............................-55°C to +150°C
Soldering Temperature.........Refer to the IPC/JEDEC J-STD-020
Specification.
UP
Relative to GND......................................-0.5V to (V
+ 0.5V)
DD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RꢃCOMMꢃNDꢃD DC OꢄꢃRATING CONDITIONS
(V
= +3.3V, V = +5.0V, T = +25°C, unless otherwise noted.) (Note 1)
DDA A
DD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
POWER SUPPLY
Digital Supply Voltage
V
2.7
4.0
3.0
2.30
50
6.0
6.0
V
V
DD
V
V
= 5V, |I | < 80mA
CC
CC
Card-Voltage-Generator Supply Voltage
V
DDA
= 5V, |I | < 30mA
6.0
CC
CC
V
TH2
Threshold voltage (falling)
Hysteresis
2.45
100
2.60
150
V
Reset Voltage Thresholds
V
HYS2
mV
CURRENT CONSUMPTION
Active V Current 5V Cards
DD
(Including 80mA Draw from 5V Card)
I
f
= 80mA, f
= 20MHz,
XTAL
CC
I
I
I
215
135
100
35
mA
mA
mA
mA
mA
DD_50V
= 10MHz, V
= 5.0V
CLK
DDA
Active V Current 5V Cards
DD
(Current Consumed by DS8023 Only)
I
= 80mA, f
= 20MHz,
CC
XTAL
I
DD_IC
f
= 10MHz, V
= 5.0V (Note 2)
CLK
DDA
Active V Current 3V Cards
DD
(Including 65mA Draw from 3V Card)
I
f
= 65mA, f
= 10MHz, V
= 20MHz,
XTAL
CC
DD_30V
= 5.0V
CLK
DDA
Active V Current 3V Cards
DD
(Current Consumed by DS8023 Only)
I
= 65mA, f
= 20MHz,
CC
XTAL
I
DD_IC
f
= 10MHz, V
= 5.0V (Note 2)
CLK
DDA
Active V Current 1.8V Cards
DD
(Including 30mA Draw from 1.8V Card)
I
= 30mA, f
= 20MHz,
CC
XTAL
70
DD_18V
f
= 10MHz, V
= 5.0V
CLK
DDA
Active V Current 1.8V Cards
DD
(Current Consumed by DS8023 Only)
I
= 30mA, f
= 10MHz, V
= 20MHz,
CC
XTAL
I
35
mA
μA
nA
DD_IC
f
= 5.0V (Note 2)
CLK
DDA
Inactive-Mode Current
I
Card inactive
500
DD
DD_STOP
DS8023 in ultra-low-power stop
mode (Note 3)
Stop-Mode Current
I
10
CLOCK SOURCE
Crystal Frequency
f
External crystal
0
0
20
20
MHz
MHz
XTAL
f
XTAL1
0.3 x
V
-0.3
IL_XTAL1
V
DD
XTAL1 Operating Conditions
V
0.7 x
V
+
0.3
DD
V
IH_XTAL1
V
DD
C
C
,
XTAL1
External Capacitance for Crystal
Internal Oscillator
15
pF
XTAL2
f
2.7
MHz
INT
2
Maxim Integrated
DS8023
Smart Card Interface
RꢃCOMMꢃNDꢃD DC OꢄꢃRATING CONDITIONS ꢁcontinuedꢂ
(V
= +3.3V, V = +5.0V, T = +25°C, unless otherwise noted.) (Note 1)
DDA A
DD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
SHUTDOWN TEMPERATURE
Shutdown Temperature
RST PIN
T
+150
°C
SD
Output Low Voltage
V
I
= 1mA
OL_RST
0
0
0
0.3
-1
V
mA
V
OL_RST1
Card-Inactive Mode
Card-Active Mode
Output Current
I
V
= 0V
OL_RST1
O_LRST
OL_RST
Output Low Voltage
V
I
= 200μA
0.3
OL_RST2
Output High
Voltage
V
-
CC
0.5
V
I
= -200μA
V
CC
V
OH_RST2
OH_RST
Rise Time
Fall Time
t
C = 30pF
0.1
0.1
μs
μs
R_RST
L
t
C = 30pF
L
F_RST
Shutdown Current
Threshold
I
-20
mA
RST(SD)
Current Limitation
RSTIN to RST Delay
I
-20
+20
2
mA
μs
RST(LIMIT)
t
D(RSTIN-RST)
CLK PIN
Output Low Voltage
Output Current
V
I
= 1mA
= 0V
0
0
0
0.3
-1
V
mA
V
OL_CLK1
OLCLK
Card-Inactive Mode
I
V
OL_CLK1
OLCLK
Output Low Voltage
V
I
= 200μA
0.3
OL_CLK2
OLCLK
Output High
Voltage
V
0.5
-
CC
V
I
= -200μA
V
CC
V
OH_CLK2
OHCLK
Rise Time
t
C = 30pF (Note 4)
L
8
8
ns
ns
R_CLK
Fall Time
t
C = 30pF (Note 4)
L
Card-Active Mode
F_CLK
Current Limitation
Clock Frequency
Duty Factor
Slew Rate
I
-70
0
+70
10
mA
MHz
%
CLK(LIMIT)
f
Operational
CLK
ꢀ
C = 30pF
L
45
0.2
55
SR
C = 30pF
L
V/ns
V
CC
PIN
Output Low Voltage
Output Current
V
I
= 1mA
= 0V
0
0
0.3
-1
V
CC1
CC
Card-Inactive Mode
I
V
mA
CC1
CC
I
I
I
< 80mA
< 65mA
4.75
2.78
1.65
5.00
3.00
1.8
5.25
3.22
1.95
CC(5V)
CC(3V)
CC(1.8V)
< 30mA
5V card: current pulses of 40nC
with I < 200mA, t < 400ns,
f < 20MHz
4.6
5.4
Card-Active Mode
Output Low Voltage
V
CC2
V
3V card: current pulses of 24nC
with I < 200mA, t < 400ns,
f < 20MHz
2.75
3.25
1.8V card: current pulses of 12nC
with I < 200mA, t < 400ns,
f < 20MHz
1.62
1.98
Maxim Integrated
3
DS8023
Smart Card Interface
RꢃCOMMꢃNDꢃD DC OꢄꢃRATING CONDITIONS ꢁcontinuedꢂ
(V
= +3.3V, V = +5.0V, T = +25°C, unless otherwise noted.) (Note 1)
DDA A
DD
PARAMETER
SYMBOL
CONDITIONS
= 0 to 5V
MIN
TYP
MAX UNITS
V
V
V
-80
CC(5V)
CC(3V)
CC(1.8V)
Output Current
I
mA
= 0 to 3V
-65
-30
CC2
= 0 to 1.8V
Card-Active Mode
Shutdown Current
Threshold
I
120
mA
CC(SD)
Slew Rate
V
CCSR
Up/down, C < 300nF (Note 5)
0.05
0.16
0.22
V/μs
DATA LINES (I/O AND I/OIN)
I/O ꢁ I/OIN Falling Edge Delay
Pullup Pulse Active Time
Maximum Frequency
t
200
100
1
ns
ns
D(IO-IOIN)
t
PU
f
MHz
pF
IOMAX
Input Capacitance
C
10
I
I/O, AUX1, AUX2 PINS
Output Low Voltage
V
I
= 1mA
= 0V
0
0
0.3
-1
V
OL_IO1
OL_IO
Output Current
I
V
mA
OL_IO1
OL_IO
Card-Inactive Mode
Internal Pullup
Resistor
R
To V
7
11
15
kꢀ
V
PU_IO
OL_IO2
OH_IO2
CC
Output Low Voltage
V
I
I
= 1mA
0
0.3
OL_IO
OH_IO
Output High
Voltage
V
= < -40μA (3V/5V)
0.75 x V
V
CC
V
CC
Output Rise/Fall
Time
Input Low Voltage
t
C = 30pF (Note 3)
0.1
μs
V
OT
L
V
-0.3
1.5
+0.8
IL_IO
IH_IO
IL_IO
Input High Voltage
Input Low Current
Input High Current
Input Rise/Fall Time
Current Limitation
V
V
CC
Card-Active Mode
I
V
V
= 0V
700
20
μA
μA
μs
IL_IO
IH_IO
I
= V
CC
IH_IO
t
1.2
+15
IT
IO(LIMIT)
I
C = 30pF
L
-15
-1
mA
Current When
Pullup Active
I
C = 80pF, V
L
= 0.9 x V
DD
mA
PU
OH
I/OIN, AUX1IN, AUX2IN PINS
Output Low Voltage
V
I
= 1mA
OL
0
0.3
V
OL
OH
OT
0.9 x
V
+
DD
No load
V
DD
0.1
Output High Voltage
V
V
0.75 x
V
+
DD
I
< -40μA
OH
V
DD
0.1
Output Rise/Fall Time
Input Low Voltage
t
C = 30pF, 10% to 90%
0.1
μs
V
L
0.3 x
V
-0.3
IL
V
DD
0.7 x
V
+
0.3
DD
Input High Voltage
V
V
IH
V
DD
4
Maxim Integrated
DS8023
Smart Card Interface
RꢃCOMMꢃNDꢃD DC OꢄꢃRATING CONDITIONS ꢁcontinuedꢂ
(V
= +3.3V, V = +5.0V, T = +25°C, unless otherwise noted.) (Note 1)
DDA A
DD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Input Low Current
I
V
V
V
= 0V
600
10
μA
μA
μs
IL_IO
IL
IH
IL
Input High Current
I
= V
IH_IO
DD
IH
Input Rise/Fall Time
Integrated Pullup Resistor
Current When Pullup Active
t
to V
1.2
15
IT
R
Pullup to V
7
11
kꢀ
mA
PU
PU
DD
I
C = 30pF, V
= 0.9 x V
DD
-1
L
OH
CONTROL PINS (CLKDIV1, CLKDIV2, CMDVCC, RSTIN, 5V/3V)
0.3 x
Input Low Voltage
Input High Voltage
V
-0.3
V
V
IL
V
DD
0.7 x
V
DD
+
V
IH
V
DD
0.3
5
Input Low Current
I
0 < V < V
DD
μA
μA
IL_IO
IL
Input High Current
I
0 < V < V
DD
5
IH_IO
IH
INTERRUPT OUTPUT PIN (OFF)
Output Low Voltage
V
I
I
= 2mA
0
0.3
V
V
OL
OL
0.75 x
Output High Voltage
V
= -15μA
OH
OH
V
DD
Integrated Pullup Resistor
R
Pullup to V
15
24
33
kꢀ
PU
DD
PRES, PRES PINS
0.3 x
Input Low Voltage
Input High Voltage
V
V
V
IL_PRES
V
DD
0.7 x
V
IH_PRES
V
DD
Input Low Current
Input High Current
TIMING
I
V
V
= 0V
5
5
μA
μA
IL_PRES
IL_PRES
IH_PRES
I
= V
DD
IH_PRES
Activation Time
Deactivation Time
t
160
80
μs
μs
ACT
t
DEACT
Window Start
Window End
t
t
95
CLK to Card Start
Time
3
μs
160
8
5
PRES/PRES Debounce Time
t
ms
DEBOUNCE
Note 1: Operation guaranteed at T = -40°C and T = +85°C, but not tested.
A
A
Note 2: I
measures the amount of current used by the DS8023 to provide the smart card current minus the load.
DD_IC
Note 3: Stop mode is enabled by setting CMDVCC, 5V/3V, and 1_8V to logic-high.
Note 4: Parameters are guaranteed to meet all ISO 7816, GSM11-11, and EMV 2000 requirements. For the 1.8V card, the maximum
rise time and fall time is 10ns.
Note 5: Parameter is guaranteed to meet all ISO 7816, GSM11-11, and EMV 2000 requirements. For the 1.8V card, the minimimum
slew rate is 0.05V/µs and the maximum slew rate is 0.5V/µs.
Maxim Integrated
5
DS8023
Smart Card Interface
Pin Description
PIN
NAME
FUNCTION
CLKDIV1, Clock Divider. Determines the divided-down input clock frequency (presented at XTAL1 or from a
1, 2
CLKDIV2
crystal at XTAL1 and XTAL2) on the CLK output pin. Dividers of 1, 2, 4, and 8 are available.
5V/3V Selection Pin. Allows selection of 5V or 3V for communication with an IC card. Logic-high
selects 5V operation; logic-low selects 3V operation. See Table 3 for a complete description of
choosing card voltages.
3
5V/3V
4
PGND
Analog Ground
Step-Up Converter Contact. Charge-pump capacitor. Connect a 100nF capacitor (ESR < 100mĀ)
between CP1 and CP2.
5, 7
CP2, CP1
6
8
V
Charge-Pump Supply. Must be equal to or higher than V . Connect a supply of at least 3.0V.
DD
DDA
V
Charge-Pump Output. Connect a 100nF capacitor (ESR < 100mĀ) between V and GND.
UP
UP
Card Presence Indicator. Active-low card presence inputs. When the presence indicator becomes
active, a debounce timeout begins. After 8ms (typ) the OFF signal becomes active.
9
PRES
Card Presence Indicator. Active-high card presence inputs. When the presence indicator becomes
active, a debounce timeout begins. After 8ms (typ) the OFF signal becomes active.
10
11
PRES
I/O
Smart Card Data-Line Output. Card data communication line, contact C7.
AUX2,
AUX1
Smart Card Auxiliary Line (C4, C8) Output. Data line connected to card reader contacts C4 (AUX1)
and C8 (AUX2).
12, 13
14
15
16
CGND
CLK
Smart Card Ground
Smart Card Clock. Card clock, contact C3.
Smart Card Reset. Card reset output from contact C2.
RST
Smart Card Supply Voltage. Decouple to CGND (card ground) with 2 x 100nF or 100 + 220nF
capacitors (ESR < 100mꢀ).
17
18
V
CC
1.8V Operation Selection. Active-high selection for 1.8V smart card communication. An active-high
signal on this pin overrides any setting on the 5V/3V pin.
1_8V
19
20
21
22
23
CMDVCC Activation Sequence Initiate. Active-low input from host.
RSTIN
Card Reset Input. Reset input from the host.
V
DD
Supply Voltage
GND
Digital Ground
OFF
Status Output. Active-low interrupt output to the host. Use a 20kꢀ integrated pullup resistor to V
.
DD
Crystal/Clock Input. Connect an input from an external clock to XTAL1 or connect a crystal across
XTAL1 and XTAL2. For the low idle-mode current variant, an external clock must be driven on
XTAL1.
XTAL1,
XTAL2
24, 25
26
I/OIN
I/O Input. Host-to-interface chip data I/O line.
AUX1IN,
AUX2IN
27, 28
C4/C8 Input. Host-to-interface I/O line for auxiliary connections to C4 and C8.
6
Maxim Integrated
DS8023
Smart Card Interface
mode. (Note that the PORADJ pin is not present in the
DS8023. It is replaced by the 1_8V selection pin.)
Detailed Description
The DS8023 is an analog front-end for communicating
with 1.8V, 3V, and 5V smart cards. Using an integrated
charge pump, the DS8023 can operate from a single
input voltage. The device translates all communication
lines to the correct voltage level and provides power for
smart card operation. It can operate from a wide input
voltage range (3.0V to 6.0V) and provides an extremely
low-power stop mode, consuming only 10nA while in
stop mode. The DS8023 is very compatible with the
NXP TDA8024. Many applications can upgrade with
very minor hardware changes, and only need to add
support in software to activate the ultra-low-power stop
Power Supply
The DS8023 can operate from a single supply or a dual
supply. The supply pins for the device are V , GND,
DD
V
, and PGND. V
should be in the 2.7V to 6.0V
DDA
DD
range, and is the supply for signals that interface with
the host controller. It should, therefore, be the same
supply as used by the host controller. All smart card
contacts remain inactive during power on or power off.
The internal circuits are kept in the reset state until V
DD
reaches V
+ V
and for the duration of the inter-
TH2
HYS2
nal power-on reset pulse, t . A deactivation sequence
W
is executed when V
falls below V
.
DD
TH2
An internal charge pump and regulator generate the
3V or 5V card supply voltage (V ). The charge pump
V
DDA
CARD VOLTAGE
GENERATOR
AND
CC
PGND
CP1
CP2
V
GND
POWER-SUPPLY
SUPERVISOR
DD
and regulator are supplied by V
and PGND. V
DDA
DDA
should be connected to a minimum 3.0V (maximum
6.0V) supply and should be at a potential that is equal
CHARGE PUMP
V
UP
XTAL1
XTAL2
CLKDIV1
CLKDIV2
to or higher than V
.
DD
CLOCK
GENERATION
TEMPERATURE
MONITOR
The charge pump operates in a 1x (voltage follower) or
2x (voltage doubler) mode depending on the input
V
and the selected card voltage (5V or 3V).
DDA
1_8V
V
CC
CGND
RST
CLK
• For 5V cards, the DS8023 operates in a 1x mode
for V > 5.8V and in a 2x mode for V < 5.8V.
5V/3V
CMDVCC
RSTIN
CONTROL
SEQUENCER
DDA
DDA
• For 3V cards, the DS8023 operates in a 1x mode
for V > 4.1V and in a 2x mode for V < 4.1V.
PRES
PRES
OFF
DDA
DDA
• For 1.8V cards, the DS8023 operates in a 1x mode
for V > 2.9V and in a 2x mode for V < 2.9V.
I/O
AUX1
AUX2
I/OIN
AUX1IN
AUX2IN
I/O TRANSCEIVER
DDA
DDA
Voltage Supervisor
DS8023
The voltage supervisor monitors the V
supply. A
DD
220µs reset pulse (t ) is used internally to keep the
W
device inactive during power on or power off of the V
supply. See Figure 2.
DD
Figure 1. Functional Diagram
V
TH2
V
TH2
+ V
HYS2
V
DD
ALARM
(INTERNAL SIGNAL)
t
t
W
W
POWER ON
SUPPLY DROPOUT
POWER OFF
Figure 2. Voltage Supervisor Behavior
Maxim Integrated
7
DS8023
Smart Card Interface
The DS8023 card interface remains inactive no matter
I/O Transceivers
the levels on the command lines until duration t after
W
The three data lines I/O, AUX1, and AUX2 are identical.
This section describes the characteristics of I/O and
I/OIN, but also applies to AUX1, AUX1IN, AUX2, and
AUX2IN.
V
has reached a level higher than V
+ V
.
DD
When V
TH2
HYS2
falls below V
, the DS8023 executes a
DD
TH2
card deactivation sequence if its card interface is active.
Clock Circuitry
I/O and I/OIN are pulled high with an 11kΩ resistor (I/O
to V
and I/OIN to V ) in the inactive state. The first
DD
CC
The clock signal from the DS8023 to the smart card
(CLK) is generated from the clock input on XTAL1 or
from a crystal operating at up to 20MHz connected
between pins XTAL1 and XTAL2. The inputs CLKDIV1
and CLKDIV2 determine the frequency of the CLK sig-
side of the transceiver to receive a falling edge
becomes the master. When the master is decided, the
opposite side switches to slave mode, ignoring subse-
quent edges until the master releases. After a time delay
t
, an n transistor on the slave side is turned on,
D(EDGE)
nal, which can be f
, f
, f
, or f
.
XTAL/8
XTAL XTAL/2 XTAL/4
thus transmitting the logic 0 present on the master side.
Table 1 shows the relationship between CLKDIV1 and
CLKDIV2 and the frequency of CLK.
When the master side asserts a logic 1, a p transistor
on the slave side is activated during the time delay,
Do not change the state of pins CLKDIV1 and CLKDIV2
simultaneously; a delay of 10ns minimum between
changes is required. The minimum duration of any state
of CLK is 8 periods of XTAL1.
t
, and then both sides return to their inactive (pulled
PU
up) states. This active pullup provides fast low-to-high
transitions. After the duration of t , the output voltage
PU
depends only on the internal pullup resistor and the
load current. Current to and from the card I/O lines is
limited internally to 15mA. The maximum frequency on
these lines is 1MHz.
The hardware in the DS8023 guarantees that the fre-
quency change is synchronous. During a transition of
the clock divider, no pulse is shorter than 45% of the
smallest period, and the clock pulses before and after
the instant of change have the correct width.
Inactive Mode
The DS8023 powers up with the card interface in the
inactive mode. Minimal circuitry is active while waiting
for the host to initiate a smart card session.
To achieve a 45% to 55% duty factor on pin CLK when
no crystal is present, the input signal on XTAL1 should
have a 48% to 52% duty factor. Transition time on
XTAL1 should be less than 5% of the period.
• All card contacts are inactive (approximately 200Ω
With a crystal, the duty factor on pin CLK may be 45%
to 55% depending on the circuit layout and on the crys-
tal characteristics and frequency.
to GND).
• Pins I/OIN, AUX1IN, and AUX2IN are in the high-
impedance state (11kΩ pullup resistor to V ).
DD
The DS8023 crystal oscillator runs when the device is
powered up. If the crystal oscillator is used or the clock
pulse on pin XTAL1 is permanent, the clock pulse is
• Voltage generators are stopped.
• XTAL oscillator is running (if included in the device).
• Voltage supervisor is active.
applied to the card at time t (see Figures 7 and 8). If
4
the signal applied to XTAL1 is controlled by the host
microcontroller, the clock pulse is applied to the card
when it is sent by the system microcontroller (after
completion of the activation sequence).
• The internal oscillator is running at its low frequency.
Activation Sequence
After power-on and the reset delay, the host microcon-
troller can monitor card presence with signals OFF and
CMDVCC, as shown in Table 2.
Table 1. Clocꢀ Frequency Selection
CLKDIV1
CLKDIV2
f
CLK
Table 2. Card ꢄresence Indication
0
0
1
1
0
1
1
0
f
f
f
/8
/4
/2
XTAL
XTAL
XTAL
OFF
High
Low
CMDVCC
High
STATUS
Card present.
High
Card not present.
f
XTAL
8
Maxim Integrated
DS8023
Smart Card Interface
When a card is inserted into the reader (if PRES is
active), the host microcontroller can begin an activation
sequence (start a card session) by pulling CMDVCC
low. The following events form an activation sequence
(Figure 3):
An alternate sequence allows the application to control
when the clock is applied to the card.
1) Host: Set RSTIN high.
2) Host: Set CMDVCC low.
3) Host: Set RSTIN low between t and t ; CLK will now
3
5
1) Host: CMDVCC is pulled low.
start.
2) DS8023: The internal oscillator changes to high
4) DS8023: RST stays low until t , then RST becomes
5
frequency (t ).
0
the copy of RSTIN.
3) DS8023: The voltage generator is started simulta-
5) DS8023: RSTIN has no further effect on CLK after t .
5
neously (t = t ).
1
0
If the applied clock is not needed, set CMDVCC low
4) DS8023: Raise V
from 0 to 5V, 3V, or 1.8V with
CC
with RSTIN low. In this case, CLK starts at t (minimum
3
a controlled slope (t = t + 1.5 × T). T is 64 times
2
1
200ns after the transition on I/O, see Figure 4); after t ,
5
the internal oscillator period (approximately 25µs).
RSTIN can be set high to obtain an answer to request
(ATR) from an inserted smart card. Do not perform acti-
vation with RSTIN held permanently high.
5) DS8023: I/O, AUX1, and AUX2 are enabled
(t = t + 4T).
3
1
6) DS8023: The CLK signal is applied to the C3 con-
tact (t ).
4
7) DS8023: RST is enabled simulataneously (t = t =
5
4
t
+ 7T).
11
CMDVCC
V
CC
ATR
I/O
CLK
RSTIN
RST
I/OIN
t
t
1
t
2
t
t
4
t = t
5 ACT
0
3
Figure 3. Activation Sequence Using RSTIN and CMDVCC
Maxim Integrated
9
DS8023
Smart Card Interface
CMDVCC
V
CC
ATR
I/O
CLK
200ns
RSTIN
RST
I/OIN
t
t
t
2
t
t
4
t = t
5 ACT
0
1
3
Figure 4. Activation Sequence at t
3
CMDVCC
RST
CLK
I/O
V
CC
t
10
t
12
t
13
t
14
t
15
t
DE
Figure 5. Deactivation Sequence
10
Maxim Integrated
DS8023
Smart Card Interface
There are two different cases for how the DS8023
reacts to fault detection (Figure 6):
Deactivation Sequence
When the host microcontroller is done communicating
with the smart card, it sets the CMDVCC line high to
execute an automatic deactivation sequence and
returns the card interface to the inactive mode.
• Outside a Card Session ꢁCMDVCC Highꢂ. Output
OFF is low if a card is not in the card reader and
high if a card is in the reader. The V
supply is
DD
monitored—a decrease in input voltage generates
an internal power-on reset pulse but does not
affect the OFF signal. Short-circuit and tempera-
ture detection are disabled because the card is
not powered up.
The following sequence of events occurs during a
deactivation sequence (Figure 5):
1) RST goes low (t ).
10
2) CLK is held low (t = t + 0.5 × T), where T is 64
12
10
times the period of the internal oscillator (approxi-
mately 25µs).
• Within a Card Session ꢁCMDVCC Lowꢂ. Output
OFF goes low when a fault condition is detected,
and an emergency deactivation is performed auto-
matically (Figure 7). When the system controller
resets CMDVCC to high, it may sense the OFF
level again after completing the deactivation
sequence. This distinguishes between a card
extraction and a hardware problem (OFF goes high
again if a card is present).
3) I/O, AUX1, and AUX2 are pulled low (t = t + T).
13
10
4) V
starts to fall (t = t + 3T).
14 10
CC
5) When V
reaches its inactive state, the deactiva-
CC
tion sequence is complete (at t ).
DE
6) All card contacts become low impedance to GND;
I/OIN, AUX1IN, and AUX2IN remain at V
(pulled
DD
up through an internal 11kΩ resistor).
Depending on the connector’s card-present switch
(normally closed or normally open) and the mechanical
characteristics of the switch, bouncing can occur on
the PRES signals at card insertion or withdrawal. The
DS8023 has a debounce feature with an 8ms typical
duration (Figure 6). When a card is inserted, output
OFF goes high after the debounce time delay. When
the card is extracted, an automatic deactivation
sequence of the card is performed on the first true/false
transition on PRES and output OFF goes low.
7) The internal oscillator returns to its lower frequency.
V
CC
Generator
The card voltage (V ) generator can supply up to
CC
80mA continuously at 5V, 65mA at 3V, or 30mA at 1.8V.
An internal overload detector triggers at approximately
120mA. Current samples to the detector are filtered.
This allows spurious current pulses (with a duration of a
few µs) up to 200mA to be drawn without causing
deactivation. The average current must stay below the
specified maximum current value.
Stop Mode (Low-Power Mode)
A low-power state, stop mode, can be entered by forc-
ing the CMDVCC, 5V/3V, and 1_8V input pins to a
logic-high state. Stop mode can only be entered when
the smart card interface is inactive. In stop mode all
internal analog circuits are disabled. The OFF pin fol-
lows the status of the PRES pin. To exit stop mode,
change the state of one or more of the three control
pins to a logic-low. An internal 220µs (typ) power-up
delay and the 8ms PRES debounce delay are in effect
and OFF is asserted to allow the internal circuitry to sta-
bilize. This prevents smart card access from occurring
after leaving the stop mode. Figure 8 shows the control
sequence for entering and exiting stop mode. Note that
an in-progress deactivation sequence always finishes
before the DS8023 enters low-power stop mode.
See the Applications Information section for recommen-
dations to help maintain V
voltage accuracy.
CC
Fault Detection
The DS8023 integrates circuitry to monitor the following
fault conditions:
• Short circuit or high current on V
CC
• Card removal while the interface is activated
• V dropping below threshold
DD
• Card voltage generator operating out of the speci-
fied values (V
too high)
too low or current consumption
DDA
• Overheating
Maxim Integrated
11
DS8023
Smart Card Interface
PRES
OFF
CMDVCC
DEBOUNCE
DEBOUNCE
V
CC
DEACTIVATION CAUSED
BY CARDS WITHDRAWAL
DEACTIVATION CAUSED
BY SHORT CIRCUIT
Figure 6. Behavior of PRES, OFF, CMDVCC, and V
CC
OFF
PRES
RST
CLK
I/O
V
CC
t
10
t
12
t
13
t
14
t
15
t
DE
Figure 7. Emergency Deactivation Sequence (Card Extraction)
12
Maxim Integrated
DS8023
Smart Card Interface
DEACTIVATE INTERFACE
CMDVCC
1_8V
5V/3V
DEACTIVATE
STOP MODE
ACTIVATE
STOP MODE
8ms
WARMUP DELAY
8ms DEBOUNCE
STOP MODE
OFF ASSERTED TO
WAIT FOR DELAY
OFF
OFF FOLLOWS
PRES IN STOP MODE
PRES
V
CC
Figure 8. Stop-Mode Sequence
Maxim Integrated
13
DS8023
Smart Card Interface
logic-low state. Care must be exercised when switching
from one V power selection to the other. If both 1_8V
Smart Card Power Select
CC
The DS8023 supports three smart card V
voltages:
CC
and 5V/3V are high with CMDVCC high at the same
time, the DS8023 enters stop mode. To avoid acciden-
tal entry into stop mode, the state of 1_8V and 5V/3V
must not be changed simultaneously. A minimum delay
of 100ns should be observed between changing the
states of 1_8V and 5V/3V. See Figure 9 for the recom-
1.8V, 3V, and 5V. The power select is controlled by the
1_8V and 5V/3V signals as shown in Table 3. The 1_8V
signal has priority over 5V/3V. When 1_8V is asserted
high, 1.8V is applied to V
when the smart card is
CC
active. When 1_8V is deasserted, 5V/3V dictates V
CC
power range. V
is 5V if 5V/3V is asserted to a logic-
CC
mended sequence of changing the V
range.
CC
high state, and V
is 3V if 5V/3V is pulled to a
CC
Table 3. k
Select and Operation Mode
CC
1_8V
5V/3V
CMDVCC
V
CC
SELECT (V)
CARD INTERFACE STATUS
Activated
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
3
3
Deactivated
5
Activated
5
Deactivated
1.8
1.8
1.8
1.8
Activated
Deactivated
Reserved (Activated)
Not Applicable—Stop Mode
V
CC
SELECT
1.8V
3V
5V
3V
1.8V
STOP MODE
CMDVCC
1_8V
5V/3V
Figure 9. Smart Card Power Select
14
Maxim Integrated
DS8023
Smart Card Interface
V
DD
100nF
+3.3V
100nF
33pF
33pF
100nF
+3.3V
100nF
+10μF
PGND V
DDA
100kΩ**
XTAL1
XTAL2
GND
V
CP1
CP2 V
DD
UP
GPIO
...
CLKDIV1
CLKDIV2
5V/3V
PRES
V
CC
RST
CLK
I/O
AUX1
AUX2
1_8V
...
...
OFF
DS8023
100nF*
220nF*
RSTIN
CMDVCC
AUX2IN
AUX1IN
I/OIN
...
GPIO
ISOIO0
CGND
MAXQ1103
CLKDIV1
CLKDIV2
5V/3V
V
CC
GPIO
...
RST
CLK
I/O
AUX1
AUX2
1_8V
100nF*
220nF*
OFF
DS8023
...
...
RSTIN
CMDVCC
AUX2IN
AUX1IN
I/OIN
CGND
PRES
GPIO
ISOIO1
XTAL1
XTAL2
GND
V
CP1
CP2 V
PGND
V
DDA
DD
UP
100kΩ**
+10μF
100nF
+3.3V
100nF
+3.3V
100nF
33pF
33pF
100nF
V
DD
*PLACE A 100nF CAPACITOR CLOSE TO DS8023 AND PLACE A 220nF CAPACITOR CLOSE TO CARD CONTACT.
**SCHEMATIC ASSUMES A NORMALLY CLOSED CONNECTION TO GROUND IN THE SOCKET. INSERTING A CARD
BREAKS THE CONNECTION AND PULLS PRES HIGH.
Figure 10. Typical Application Diagram
Maxim Integrated
15
DS8023
Smart Card Interface
• Connect a 100nF capacitor (ESR < 100mΩ)
Applications Information
between V
and CGND and place near the
pin.
CC
CC
Performance can be affected by the layout of the appli-
cation. For example, an additional cross-capacitance of
1pF between card reader contacts C2 (RST) and C3
(CLK) or C2 (RST) and C7 (I/O) can cause contact C2
to be polluted with high-frequency noise from C3 (or
C7). In this case, include a 100pF capacitor between
contacts C2 and CGND.
DS8023’s V
• Connect a 100nF or 220nF capacitor (220nF pre-
ferred, ESR < 100mΩ) between V
and CGND
CC
and place near the smart card socket’s C1 contact.
With all these layout precautions, noise should be kept
to an acceptable level and jitter on C3 (CLK) should be
less than 100ps.
Application recommendations include the following:
• Ensure there is ample ground area around the
DS8023 and the connector; place the DS8023
Technical Support
For technical support, go to https://support.maxim-
integrated.com/micro.
very near to the connector; decouple the V
and
DD
V
DDA
lines separately. These lines are best posi-
Selector Guide
tioned under the connector.
• The DS8023 and the host microcontroller must use
the same V supply. Pins CLKDIV1, CLKDIV2,
CURRENT
VOLTAGES
SUPPORTED (V)
SUPPORTS
STOP
MODE?
PIN-
PACKAGE
DD
PART
RSTIN, PRES, AUX1IN, I/OIN, AUX2IN, 5V/3V,
CMDVCC, and OFF are referenced to V ; if pin
DD
DS8023-RJX+
DS8023-RRX+
1.8, 3.0, 5.0
1.8, 3.0, 5.0
Yes
Yes
28 TSSOP
28 SO
XTAL1 is to be driven by an external clock, also
reference this pin to V
.
DD
Note: Contact the factory for availability of other variants and
package options.
+Denotes a lead(Pb)-free/RoHS-compliant package.
• Trace C3 (CLK) should be placed as far as possi-
ble from the other traces.
• The trace connecting CGND to C5 (GND) should
be straight (the two capacitors on C1 (V ) should
CC
Package Information
be connected to this ground trace).
For the latest package outline information and land patterns (foot-
prints), go to www.maximintegrated.com/pacꢀages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
• Avoid ground loops among CGND, PGND, and
GND.
• Decouple V
and V
separately; if the two
DD
DDA
supplies are the same in the application, they
should be connected in a star on the main trace.
LAND
ꢄATTꢃRN NO.
ꢄACKAGꢃ
TYꢄꢃ
ꢄACKAGꢃ
CODꢃ
OUTLINꢃ NO.
90-0109
90-0171
28 SO (300 mils)
28 TSSOP
W28+6
U28+1
21-0042
21-0066
16
Maxim Integrated
DS8023
Smart Card Interface
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
DESCRIPTION
0
8/08
Initial release
Clarified t , t , t , added note to Figure 10 describing PRES pin
—
1
5 14
1
4/13
9, 11, 15
operation, and added package information
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 ________________________________ 17
© 2013 Maxim Integrated Products, Inc.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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