DS8024_V3 [MAXIM]
Smart Card Interface; 智能卡接口型号: | DS8024_V3 |
厂家: | MAXIM INTEGRATED PRODUCTS |
描述: | Smart Card Interface |
文件: | 总15页 (文件大小:356K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
19-6220; Rev 3; 7/12
Smart Card Interface
DS8024
General Description
Features
The DS8024 smart card interface IC is a low-cost, analog
front-end for a smart card reader, designed for all ISO
♦ Analog Interface and Level Shifting for IC Card
Communication
®
7816, EMV , and GSM11-11 applications. The DS8024
♦
8ꢀk ꢁminꢂ ꢃSD ꢁIꢃCꢂ ꢄrotection on Card
Interfaces
is a pin-for-pin drop-in replacement for the NXP
TDA8024 and is offered in 28-pin TSSOP and SO pack-
ages.
♦ Internal IC Card Supply-koltage Generation:
5.0k 5ꢅ, 80mA ꢁmaxꢂ
Applications requiring support for 1.8V smart cards or
requiring low power should consider the DS8113, which
achieves lower active- and stop-mode power with mini-
mal changes to application hardware and software.
3.0k 8ꢅ, 65mA ꢁmaxꢂ
♦ Automatic Card Activation and Deactivation
Controlled by Dedicated Internal Sequencer
♦ I/O Lines from Host Directly Level Shifted for
Applications
Set-Top Box Conditional Access
Access Control
Smart Card Communication
♦ Flexible Card Clocꢀ Generation, Supporting
ꢃxternal Crystal Frequency Divided by 1, 2, 4, or 8
Banking Applications
♦ High-Current, Short-Circuit and High-Temperature
POS Terminals
ꢄrotection
Debit/Credit Payment Terminals
PIN Pads
Pin Configuration
Automated Teller Machines
Telecommunications
TOP VIEW
Pay/Premium Television
CLKDIV1
CLKDIV2
5V/3V
1
2
3
4
5
6
7
8
9
28 AUX2IN
27 AUX1IN
26 I/OIN
25 XTAL2
24 XTAL1
23 OFF
Ordering Information
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
28 TSSOP
28 TSSOP
28 SO
PGND
DS8024-RJX+
DS8024-RJX/V+
DS8024-RRX+
CP2
V
DDA
DS8024
CP1
22 GND
Note: Contact the factory for availability of other variants and
package options.
+Denotes a lead(Pb)-free/RoHS-compliant package.
/V denotes an automotive-qualified part.
V
UP
21 V
DD
PRES
20 RSTIN
19 CMDVCC
18 N.C.
PRES 10
I/O 11
AUX2 12
AUX1 13
CGND 14
17 V
CC
16 RST
15 CLK
Selector Guide appears at end of data sheet.
SO/TSSOꢄ
EMV is a registered trademark of EMVCo LLC. EMV Level 1 library and hardware reference design available. Contact factory for
details.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be
simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata.
For pricing, delivery, and ordering information, please contact Maxim Direct
1
at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Smart Card Interface
ABSOLUTꢃ MAXIMUM RATINGS
Voltage Range on V
Voltage Range on V
Relative to GND ...............-0.5V to +6.5V
Continuous Power Dissipation (multilayer board, T = +70°C)
A
DD
DDA
Relative to PGND...........-0.5V to +6.5V
TSSOP (derate 14mW/°C above +70°C) .................1117.3mW
SO (derate 16.7mW/°C above +70°C).....................1355.9mW
Storage Temperature Range.............................-55°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Voltage Range on CP1, CP2, and V
UP
Relative to PGND...............................................-0.5V to +7.5V
Voltage Range on All Other Pins
Relative to GND......................................-0.5V to (V
+ 0.5V)
DD
DS8024
Maximum Junction Temperature .....................................+125°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RꢃCOMMꢃNDꢃD DC OꢄꢃRATING CONDITIONS
(V
DD
= +3.3V, V = +5.0V, T = +25°C, unless otherwise noted.) (Note 1)
DDA A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
POWER SUPPLY
Digital Supply Voltage
V
2.7
4.0
3.0
2.30
50
6.0
6.0
V
V
DD
V
V
= 5V, |I | < 80mA
CC
CC
CC
Card Voltage-Generator Supply Voltage
V
DDA
= 5V, |I | < 30mA
6.0
CC
V
Threshold voltage (falling)
Hysteresis
2.45
100
2.60
150
V
TH2
Reset Voltage Thresholds
V
mV
HYS2
CURRENT CONSUMPTION
Active V
Current 5V Cards
I
f
= 80mA, f
= 20MHz,
= 5.0V
DDA
DD
CC
XTAL
I
I
215
135
100
mA
mA
mA
DD_50V
(Including 80mA Draw from 5V Card)
= 10MHz, V
CLK
Active V Current 5V Cards
(Current Consumed by DS8024 Only)
I
= 80mA, f
= 20MHz,
= 5.0V (Note 2)
DDA
DD
CC
XTAL
I
DD_IC
f
= 10MHz, V
CLK
Active V Current 3V Cards
(Including 65mA Draw from 3V Card)
I
f
= 65mA, f
= 20MHz,
= 5.0V
DDA
DD
CC
XTAL
DD_30V
= 10MHz, V
CLK
Active V Current 3V Cards
I
= 65mA, f
= 10MHz, V
= 20MHz,
= 5.0V (Note 2)
DDA
DD
CC
XTAL
I
35
mA
μA
DD_IC
(Current Consumed by DS8024 Only)
Inactive-Mode Current
CLOCK SOURCE
f
CLK
I
Card inactive
500
DD
Crystal Frequency
f
External crystal
0
0
20
20
MHz
MHz
XTAL
f
XTAL1
0.3 x
V
Low-level input on XTAL1 (Note 3)
High-level input on XTAL1 (Note 3)
(Note 3)
-0.3
IL_XTAL1
V
XTAL1 Operating Conditions
DD
V
0.7 x
V
+
DD
V
IH_XTAL1
V
0.3
DD
C
C
,
XTAL1
External Capacitance for Crystal
15
pF
XTAL2
Internal Oscillator
f
2.7
MHz
INT
SHUTDOWN TEMPERATURE
Shutdown Temperature
T
SD
(Note 3)
+150
°C
2
Smart Card Interface
DS8024
RꢃCOMMꢃNDꢃD DC OꢄꢃRATING CONDITIONS ꢁcontinuedꢂ
(V
DD
= +3.3V, V = +5.0V, T = +25°C, unless otherwise noted.) (Note 1)
DDA A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
RST PIN
Output Low Voltage
Output Current
V
I
= 1mA
0
0
0
0.3
-1
V
mA
V
OL_RST1
OL_RST
Card-Inactive Mode
Card-Active Mode
I
V
= 0V
OL_RST1
O_LRST
OL_RST
Output Low Voltage
V
I
I
= 200μA
0.3
OL_RST2
Output High
Voltage
V
-
CC
0.5
V
= -200μA
V
V
OH_RST2
OH_RST
CC
Rise Time
Fall Time
t
C = 30pF (Note 3)
0.1
0.1
μs
μs
R_RST
L
t
C = 30pF (Note 3)
L
F_RST
Shutdown Current
Threshold
I
-20
mA
RST(SD)
Current Limitation
RSTIN to RST Delay
I
-20
+20
2
mA
μs
RST(LIMIT)
t
D(RSTIN-RST)
CLK PIN
Output Low Voltage
Output Current
V
I
= 1mA
= 0V
0
0
0
0.3
-1
V
mA
V
OL_CLK1
OLCLK
Card-Inactive Mode
I
V
OL_CLK1
OLCLK
OLCLK
Output Low Voltage
V
I
= 200μA
0.3
OL_CLK2
Output High
Voltage
V
0.5
-
CC
V
I
= -200μA
V
V
OH_CLK2
OHCLK
CC
Rise Time
t
C = 30pF (Note 3)
8
8
ns
ns
R_CLK
L
Card-Active Mode
Fall Time
t
C = 30pF (Note 3)
L
F_CLK
Current Limitation
Clock Frequency
Duty Factor
Slew Rate
I
-70
0
+70
10
mA
MHz
%
CLK(LIMIT)
f
Operational (Note 3)
CLK
ꢀ
C = 30pF (Note 3)
L
45
0.2
55
SR
C = 30pF (Note 3)
L
V/ns
V
CC
PIN
Output Low Voltage
Output Current
V
I
= 1mA
0
0
0.3
-1
V
CC1
CC
Card-Inactive Mode
I
V
= 0V
mA
CC1
CC
I
I
< 80mA
< 65mA
4.75
2.78
5.00
3.00
5.25
3.22
CC(5V)
CC(3V)
5V card: current pulses of 40nC
with I < 200mA, t < 400ns,
f < 20MHz (Note 3)
4.6
5.4
Output Low Voltage
V
V
CC2
3V card: current pulses of 24nC
with I < 200mA, t < 400ns,
f < 20MHz (Note 3)
Card-Active Mode
2.75
3.25
V
V
= 0 to 5V
= 0 to 3V
-80
-65
CC(5V)
CC(3V)
Output Current
I
mA
CC2
Shutdown Current
Threshold
I
120
mA
CC(SD)
Slew Rate
V
Up/down, C < 300nF
0.05
0.16
0.22
V/μs
CCSR
3
Smart Card Interface
RꢃCOMMꢃNDꢃD DC OꢄꢃRATING CONDITIONS ꢁcontinuedꢂ
(V
DD
= +3.3V, V = +5.0V, T = +25°C, unless otherwise noted.) (Note 1)
DDA A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
DATA LINES (I/O AND I/OIN)
I/O ꢁ I/OIN Falling Edge Delay
Pullup Pulse Active Time
Maximum Frequency
t
(Note 3)
(Note 3)
200
100
1
ns
ns
D(IO-IOIN)
t
PU
DS8024
f
MHz
pF
IOMAX
Input Capacitance
C
(Note 3)
10
I
I/O, AUX1, AUX2 PINS
Output Low Voltage
V
I
= 1mA
0
0
0.3
-1
V
OL_IO1
OL_IO
Output Current
I
V
= 0V
mA
OL_IO1
OL_IO
Card-Inactive Mode
Internal Pullup
Resistor
R
To V
9
11
19
kꢀ
V
PU_IO
CC
Output Low Voltage
V
I
= 1mA
0
0.3
OL_IO2
OH_IO2
OL_IO
OH_IO
Output High
Voltage
V
I
= < -40μA (3V/5V)
0.75 x V
V
V
CC
CC
Output Rise/Fall
Time
Input Low Voltage
t
C = 30pF (Note 3)
0.1
μs
V
OT
L
V
-0.3
1.5
+0.8
IL_IO
IH_IO
IL_IO
Input High Voltage
Input Low Current
Input High Current
Input Rise/Fall Time
Current Limitation
V
V
CC
Card-Active Mode
I
V
V
= 0V
700
20
μA
μA
μs
IL_IO
IH_IO
I
= V
CC
IH_IO
t
(Note 3)
C = 30pF
1.2
+15
IT
IO(LIMIT)
I
-15
-1
mA
L
Current When
Pullup Active
C = 80pF, V
L
= 0.9 x V
OH DD
I
mA
PU
(Note 3)
I/OIN, AUX1IN, AUX2IN PINS
Output Low Voltage
V
I
I
= 1mA
0
0.3
V
V
OL
OH
OT
OL
0.75 x
V
+
DD
0.1
Output High Voltage
Output Rise/Fall Time
Input Low Voltage
V
< -40μA
OH
V
DD
t
C = 30pF, 10% to 90% (Note 3)
0.1
μs
V
L
0.3 x
V
-0.3
IL
V
DD
0.7 x
V
+
DD
0.3
Input High Voltage
V
V
IH
V
DD
Input Low Current
I
V
V
V
= 0V
600
10
μA
μA
μs
IL_IO
IL
IH
IL
Input High Current
I
= V
DD
IH_IO
Input Rise/Fall Time
Integrated Pullup Resistor
t
IT
to V (Note 3)
1.2
13
IH
R
Pullup to V
9
11
kꢀ
PU
DD
C = 30pF, V
L
(Note 3)
= 0.9 x V
DD
OH
Current When Pullup Active
I
-1
mA
PU
4
Smart Card Interface
DS8024
RꢃCOMMꢃNDꢃD DC OꢄꢃRATING CONDITIONS ꢁcontinuedꢂ
(V
DD
= +3.3V, V = +5.0V, T = +25°C, unless otherwise noted.) (Note 1)
DDA A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
CONTROL PINS (CLKDIV1, CLKDIV2, CMDVCC, RSTIN, 5V/3V)
0.3 x
V
Input Low Voltage
Input High Voltage
V
-0.3
IL
V
DD
0.7 x
V
+
DD
V
V
IH
V
0.3
DD
Input Low Current
I
0 < V < V
5
μA
μA
kꢀ
IL_IO
IL
DD
DD
Input High Current
I
0 < V < V
5
IH_IO
IH
Integrated Pullup Resistor
INTERRUPT OUTPUT PIN (OFF)
Output Low Voltage
R
Pullup to V , 5V/3V only
50
85
20
120
PU
DD
V
I
I
= 2mA
0
0.3
V
V
OL
OL
0.75 x
Output High Voltage
V
= -15μA
OH
OH
V
DD
Integrated Pullup Resistor
R
Pullup to V
12
28
kꢀ
PU
DD
PRES, PRES PINS
0.3 x
Input Low Voltage
Input High Voltage
V
V
V
IL_PRES
V
DD
0.7 x
V
IH_PRES
V
DD
Input Low Current
Input High Current
TIMING
I
V
V
= 0V
40
40
μA
μA
IL_PRES
IL_PRES
IH_PRES
I
= V
DD
IH_PRES
Activation Time
Deactivation Time
t
160
80
95
160
8
μs
μs
ACT
t
DEACT
Window Start
Window End
t
3
t
5
CLK to Card Start
Time
μs
PRES/PRES Debounce Time
t
ms
DEBOUNCE
Note 1: Operation guaranteed at T = -40°C and T = +85°C, but not tested.
A
A
Note 2: IDD_IC measures the amount of current used by the DS8024 to provide the smart card current minus the load.
Note 3: Guaranteed by design, but not production tested.
5
Smart Card Interface
Pin Description
PIN
NAME
FUNCTION
CLKDIV1, Clock Divider. Determines the divided-down input clock frequency (presented at XTAL1 or from a
1, 2
CLKDIV2
crystal at XTAL1 and XTAL2) on the CLK output pin. Dividers of 1, 2, 4, and 8 are available.
5V/3V Selection Pin. Allows selection of 5V or 3V for communication with an IC card. Logic-high selects
5V operation; logic-low selects 3V operation. See Table 3 for a complete description of choosing card
voltages.
3
5V/3V
DS8024
4
PGND
Analog Ground
Step-Up Converter Contact. Charge-pump capacitor. Connect a 100nF capacitor (ESR < 100mꢀ)
between CP1 and CP2.
5, 7
CP2, CP1
6
8
V
Charge-Pump Supply. Must be equal to or higher than V . Connect a supply of at least 3.3V.
DD
DDA
V
Charge-Pump Output. Connect a 100nF capacitor (ESR < 100mꢀ) between V and GND.
UP
UP
Card Presence Indicator. Active-low card presence inputs. When the presence indicator becomes
active, a debounce timeout begins. After 8ms (typ) the OFF signal becomes active.
9
PRES
Card Presence Indicator. Active-high card presence inputs. When the presence indicator becomes
active, a debounce timeout begins. After 8ms (typ) the OFF signal becomes active.
10
11
PRES
I/O
Smart Card Data-Line Output. Card data communication line, contact C7.
AUX2,
AUX1
Smart Card Auxiliary Line (C4, C8) Output. Data line connected to card reader contacts C4 (AUX1) and
C8 (AUX2).
12, 13
14
15
16
CGND
CLK
Smart Card Ground
Smart Card Clock. Card clock, contact C3.
Smart Card Reset. Card reset output from contact C2.
RST
Smart Card Supply Voltage. Decouple to CGND (card ground) with 2 x 100nF or 100 + 220nF
capacitors (ESR < 100mꢀ).
17
V
CC
18
19
20
21
22
23
N.C.
No Connection. Unused on the DS8024.
CMDVCC Activation Sequence Initiate. Active-low input from host.
RSTIN
Card Reset Input. Reset input from the host.
V
Supply Voltage
DD
GND
Digital Ground
OFF
Status Output. Active-low interrupt output to the host. Use a 20kꢀ integrated pullup resistor to V
.
DD
XTAL1,
XTAL2
Crystal/Clock Input. Connect an input from an external clock to XTAL1 or connect a crystal across
XTAL1 and XTAL2. For the low idle-mode current variant, an external clock must be driven on XTAL1.
24, 25
26
I/OIN
I/O Input. Host-to-interface chip data I/O line.
AUX1IN,
AUX2IN
27, 28
C4/C8 Input. Host-to-interface I/O line for auxiliary connections to C4 and C8.
6
Smart Card Interface
DS8024
input pin, instead using the DS8024’s default reset
threshold.)
Detailed Description
The DS8024 is an analog front-end for communicating
with 3V and 5V smart cards. Using an integrated
charge pump, the DS8024 can operate from a single
input voltage. The device translates all communication
lines to the correct voltage level and provides power for
smart card operation. It can operate from a wide input
voltage range (3.3V to 6.0V). The DS8024 is compatible
with the NXP TDA8024 and is provided in the same
packages. (Note that the PORADJ pin is not present in
the DS8024. Most applications do not make use of this
Power Supply
The DS8024 can operate from a single supply or a dual
supply. The supply pins for the device are V , GND,
DD
V
DDA
, and PGND. V
should be in the range of 2.7V
DD
to 6.0V, and is the supply for signals that interface with
the host controller. It should, therefore, be the same
supply as used by the host controller. All smart card
contacts remain inactive during power on or power off.
The internal circuits are kept in the reset state until V
DD
reaches V
+ V
and for the duration of the inter-
TH2
HYS2
nal power-on reset pulse, t . A deactivation sequence
W
V
DDA
is executed when V
falls below V
.
DD
TH2
CARD VOLTAGE
PGND
V
GND
POWER-SUPPLY
SUPERVISOR
GENERATOR
AND
DD
An internal charge pump and regulator generate the
3V or 5V card supply voltage (V ). The charge pump
CP1
CP2
CC
CHARGE PUMP
V
UP
and regulator are supplied by V
and PGND. V
DDA
DDA
XTAL1
XTAL2
CLKDIV1
CLKDIV2
should be connected to a minimum 3.3V (maximum
6.0V) supply and should be at a potential that is equal
CLOCK
GENERATION
TEMPERATURE
MONITOR
to or higher than V
.
DD
The charge pump operates in a 1x (voltage follower) or
2x (voltage doubler) mode depending on the input
DDA
V
CC
5V/3V
CMDVCC
RSTIN
CGND
RST
CLK
PRES
PRES
V
and the selected card voltage (5V or 3V).
CONTROL
SEQUENCER
• For 5V cards, the DS8024 operates in a 1x mode
for V > 5.8V and in a 2x mode for V < 5.8V.
OFF
DDA
DDA
• For 3V cards, the DS8024 operates in a 1x mode
for V > 4.1V and in a 2x mode for V < 4.0V.
I/OIN
AUX1IN
AUX2IN
I/O
AUX1
AUX2
DDA
DDA
I/O TRANSCEIVER
Voltage Supervisor
The voltage supervisor monitors the V
supply. A
DD
DS8024
220µs reset pulse (t ) is used internally to keep the
W
device inactive during power on or power off of the V
supply. See Figure 2.
DD
Figure 1. Functional Diagram
V
TH2
V
TH2
+ V
HYS2
V
DD
ALARM
(INTERNAL SIGNAL)
t
W
t
W
POWER ON
SUPPLY DROPOUT
POWER OFF
Figure 2. Voltage Supervisor Behavior
7
Smart Card Interface
The DS8024 card interface remains inactive no matter
I/O Transceivers
the levels on the command lines until duration t after
W
The three data lines I/O, AUX1, and AUX2 are identical.
This section describes the characteristics of I/O and
I/OIN but also applies to AUX1, AUX1IN, AUX2, and
AUX2IN.
V
has reached a level higher than V
+ V
.
DD
When V
TH2
HYS2
falls below V
, the DS8024 executes a
DD
TH2
card deactivation sequence if its card interface is
active.
I/O and I/OIN are pulled high with an 11kΩ resistor (I/O
Clock Circuitry
2
to V
and I/OIN to V ) in the inactive state. The first
CC DD
side of the transceiver to receive a falling edge
becomes the master. When the master is decided, the
opposite side switches to slave mode, ignoring subse-
quent edges until the master releases. After a time delay
The clock signal from the DS8024 to the smart card
(CLK) is generated from the clock input on XTAL1 or
from a crystal operating at up to 20MHz connected
between pins XTAL1 and XTAL2. The inputs CLKDIV1
and CLKDIV2 determine the frequency of the CLK sig-
t
, an n transistor on the slave side is turned on,
thus transmitting the logic 0 present on the master side.
D(EDGE)
nal, which can be f
, f
/2, f
/4, or f
/8.
XTAL
XTAL XTAL
XTAL
Table 1 shows the relationship between CLKDIV1 and
CLKDIV2 and the frequency of CLK.
When the master side asserts a logic 1, a p transistor
on the slave side is activated during the time delay t
PU
and then both sides return to their inactive (pulled up)
states. This active pullup provides fast low-to-high tran-
Do not change the state of pins CLKDIV1 and CLKDIV2
simultaneously; a delay of 10ns minimum between
changes is required. The minimum duration of any state
of CLK is 8 periods of XTAL1.
sitions. After the duration of t , the output voltage
PU
depends only on the internal pullup resistor and the
load current. Current to and from the card I/O lines is
limited internally to 15mA. The maximum frequency on
these lines is 1MHz.
The hardware in the DS8024 guarantees that the fre-
quency change is synchronous. During a transition of
the clock divider, no pulse is shorter than 45% of the
smallest period, and the clock pulses before and after
the instant of change have the correct width.
Inactive Mode
The DS8024 powers up with the card interface in the
inactive mode. Minimal circuitry is active while waiting
for the host to initiate a smart card session.
To achieve a 45% to 55% duty factor on pin CLK when
no crystal is present, the input signal on XTAL1 should
have a 48% to 52% duty factor. Transition time on
XTAL1 should be less than 5% of the period.
• All card contacts are inactive (approximately 200Ω
to GND).
With a crystal, the duty factor on pin CLK may be 45%
to 55% depending on the circuit layout and on the crys-
tal characteristics and frequency.
• Pins I/OIN, AUX1IN, and AUX2IN are in the high-
impedance state (11kΩ pullup resistor to V ).
DD
• Voltage generators are stopped.
The DS8024 crystal oscillator runs when the device is
powered up. If the crystal oscillator is used or the clock
pulse on pin XTAL1 is permanent, the clock pulse is
• XTAL oscillator is running (if included in the device).
• Voltage supervisor is active.
applied to the card at time t (see Figures 7 and 8). If
4
• The internal oscillator is running at its low frequency.
the signal applied to XTAL1 is controlled by the host
microcontroller, the clock pulse is applied to the card
when it is sent by the system microcontroller (after
completion of the activation sequence).
Activation Sequence
After power-on and the reset delay, the host microcon-
troller can monitor card presence with signals OFF and
CMDVCC, as shown in Table 2.
Table 1. Clocꢀ Frequency Selection
CLKDIV1
CLKDIV2
f
Table 2. Card ꢄresence Indication
CLK
0
0
1
1
0
1
1
0
f
f
f
/8
/4
/2
XTAL
XTAL
XTAL
OFF
High
Low
CMDVCC
High
STATUS
Card present.
High
Card not present.
f
XTAL
8
Smart Card Interface
DS8024
When a card is inserted into the reader (if PRES is
active), the host microcontroller can begin an activation
sequence (start a card session) by pulling CMDVCC
low. The following events form an activation sequence
(Figure 3):
An alternate sequence allows the application to control
when the clock is applied to the card.
1) Host: Set RSTIN high.
2) Host: Set CMDVCC low.
3) Host: Set RSTIN low between t and t ; CLK will now
3
5
1) Host: CMDVCC is pulled low.
start.
2) DS8024: The internal oscillator changes to high
4) DS8024: RST stays low until t , then RST becomes
5
frequency (t ).
0
the copy of RSTIN.
3) DS8024: The voltage generator is started
5) DS8024: RSTIN has no further effect on CLK after t .
5
(between t and t ).
0
1
If the applied clock is not needed, set CMDVCC low
4) DS8024: V
rises from 0 to 5V or 3V with a con-
CC
with RSTIN low. In this case, CLK starts at t (minimum
3
trolled slope (t = t + 1.5 × T). T is 64 times the
2
1
200ns after the transition on I/O, see Figure 4); after t ,
5
internal oscillator period (approximately 25µs).
RSTIN can be set high to obtain an answer to request
(ATR) from an inserted smart card. Do not perform acti-
vation with RSTIN held permanently high.
5) DS8024: I/O, AUX1, and AUX2 are enabled (t =
3
t + 4T).
1
6) DS8024: The CLK signal is applied to the C3 con-
Active Mode
tact (t ).
4
When the activation sequence is completed, the
DS8024 card interface is in active mode. The host
microcontroller and the smart card exchange data on
the I/O lines.
7) DS8024: RST is enabled (t = t + 7T).
5
1
CMDVCC
V
CC
ATR
I/O
CLK
RSTIN
RST
I/OIN
t
0
t
1
t
2
t
t
4
t = t
5 ACT
3
Figure 3. Activation Sequence Using RSTIN and CMDVCC
9
Smart Card Interface
CMDVCC
V
CC
DS8024
ATR
I/O
CLK
200ns
RSTIN
RST
I/OIN
t
0
t
1
t
2
t
t
4
t = t
5 ACT
3
Figure 4. Activation Sequence at t
3
CMDVCC
RST
CLK
I/O
V
CC
t
10
t
12
t
t
14
t
15
13
t
DE
Figure 5. Deactivation Sequence
10
Smart Card Interface
DS8024
There are two different cases for how the DS8024
reacts to fault detection (Figure 6):
Deactivation Sequence
When the host microcontroller is done communicating
with the smart card, it sets the CMDVCC line high to
execute an automatic deactivation sequence and
returns the card interface to the inactive mode.
• Outside a Card Session ꢁCMDVCC Highꢂ. Output
OFF is low if a card is not in the card reader and
high if a card is in the reader. The V
supply is
DD
monitored—a decrease in input voltage generates
an internal power-on reset pulse but does not
affect the OFF signal. Short-circuit and tempera-
ture detection are disabled because the card is
not powered up.
The following sequence of events occurs during a
deactivation sequence (Figure 5):
1) RST goes low (t ).
10
2) CLK is held low (t = t + 0.5 × T), where T is 64
12
10
times the period of the internal oscillator (approxi-
mately 25µs).
• Within a Card Session ꢁCMDVCC Lowꢂ. Output
OFF goes low when a fault condition is detected,
and an emergency deactivation is performed auto-
matically (Figure 7). When the system controller
resets CMDVCC to high, it may sense the OFF
level again after completing the deactivation
sequence. This distinguishes between a card
extraction and a hardware problem (OFF goes high
again if a card is present). Depending on the con-
nector’s card-present switch (normally closed or
normally open) and the mechanical characteristics
of the switch, bouncing can occur on the PRES sig-
nals at card insertion or withdrawal.
3) I/O, AUX1, and AUX2 are pulled low (t = t + T).
13
10
4) V
starts to fall (t = t + 1.5 × T).
14 10
CC
5) When V
reaches its inactive state, the deactiva-
CC
tion sequence is complete (at t ).
DE
6) All card contacts become low impedance to GND;
I/OIN, AUX1IN, and AUX2IN remain at V
(pulled
DD
up through an 11kΩ resistor).
7) The internal oscillator returns to its lower frequency.
V
CC
Generator
The DS8024 has a debounce feature with an 8ms typi-
cal duration (Figure 6). When a card is inserted, output
OFF goes high after the debounce time delay. When
the card is extracted, an automatic deactivation
sequence of the card is performed on the first true/false
transition on PRES and output OFF goes low.
The card voltage (V ) generator can supply up to
CC
80mA continuously at 5V or 65mA at 3V. An internal
overload detector triggers at approximately 120mA.
Current samples to the detector are filtered. This allows
spurious current pulses (with a duration of a few µs) up
to 200mA to be drawn without causing deactivation.
The average current must stay below the specified
maximum current value.
Stop Mode (Low-Power Mode)
The DS8024 (like the TDA8024) does not support a low-
power stop mode. For applications requiring low-power
support, refer to the DS8113.
See the Applications Information section for recommen-
dations to help maintain V
voltage accuracy.
CC
Fault Detection
Smart Card Power Select
The DS8024 integrates circuitry to monitor the following
fault conditions:
The DS8024 supports two smart card V
voltages: 3V
CC
and 5V. The power select is controlled by the 5V/3V
signal as shown in Table 3. V is 5V if 5V/3V is assert-
• Short-circuit or high current on V
CC
CC
ed to a logic-high state, and V
to a logic-low state.
is 3V if 5V/3V is pulled
CC
• Card removal while the interface is activated
• V dropping below threshold
DD
• Card voltage generator operating out of the speci-
Table 3. k
Select and Operation Mode
CC
fied values (V
too high)
too low or current consumption
DDA
V
CC
CARD INTERFACE
STATUS
5V/3V
CMDVCC
SELECT (V)
• Overheating
0
0
1
1
0
1
0
1
3
3
5
5
Activated
Inactivated
Activated
Inactivated
11
Smart Card Interface
PRES
OFF
DS8024
CMDVCC
DEBOUNCE
DEBOUNCE
V
CC
DEACTIVATION CAUSED
BY CARDS WITHDRAWAL
DEACTIVATION CAUSED
BY SHORT CIRCUIT
Figure 6. Behavior of PRES, OFF, CMDVCC, and V
CC
OFF
PRES
RST
CLK
I/O
V
CC
t
t
12
t
13
t
t
15
10
14
t
DE
Figure 7. Emergency Deactivation Sequence (Card Extraction)
12
Smart Card Interface
DS8024
V
DD
100nF
+3.3V
100nF
33pF
33pF
100nF
+3.3V
100nF
+10μF
PGND V
DDA
100kΩ**
XTAL1
XTAL2
GND
V
DD
CP1
CP2 V
UP
GPIO
...
CLKDIV1
CLKDIV2
5V/3V
PRES
V
CC
...
...
...
RST
CLK
I/O
AUX1
AUX2
OFF
DS8024
RSTIN
CMDVCC
AUX2IN
AUX1IN
I/OIN
100nF*
220nF*
GPIO
ISOIO0
CGND
MAXQ1103
CLKDIV1
CLKDIV2
5V/3V
V
CC
GPIO
...
RST
CLK
OFF
DS8024
I/O
AUX1
AUX2
100nF*
220nF*
...
...
RSTIN
CMDVCC
AUX2IN
AUX1IN
I/OIN
GPIO
ISOIO1
CGND
PRES
XTAL1
XTAL2
GND
V
DD
CP1
CP2 V
PGND
V
DDA
UP
100kΩ**
+10μF
100nF
+3.3V
100nF
+3.3V
100nF
33pF
33pF
100nF
V
DD
*PLACE A 100nF CAPACITOR CLOSE TO DS8024 AND PLACE A 220nF CAPACITOR CLOSE TO CARD CONTACT.
**SCHEMATIC ASSUMES A NORMALLY CLOSED CONNECTION TO GROUND IN THE SOCKET. INSERTING A CARD BREAKS THE CONNECTION AND PULLS PRES HIGH.
Figure 8. Typical Application Diagram
13
Smart Card Interface
Applications Information
Technical Support
Performance can be affected by the layout of the appli-
cation. For example, an additional cross-capacitance of
1pF between card reader contacts C2 (RST) and C3
(CLK) or C2 (RST) and C7 (I/O) can cause contact C2
to be polluted with high-frequency noise from C3 (or
C7). In this case, include a 100pF capacitor between
contacts C2 and CGND.
For technical support, go to https://support.maxim-
ic.com/micro.
Selector Guide
CURRENT
VOLTAGES
SUPPORTED (V)
SUPPORTS
STOP
MODE?
PIN-
PACKAGE
DS8024
PART
Application recommendations include the following:
DS8024-RJX+
DS8024-RJX/V+
DS8024-RRX+
3.0, 5.0
3.0, 5.0
3.0, 5.0
No
No
No
28 TSSOP
28 TSSOP
28 SO
• Ensure there is ample ground area around the
DS8024 and the connector; place the DS8024
very near to the connector; decouple the V
and
DD
V
DDA
lines separately. These lines are best posi-
Note: Contact the factory for availability of other variants and
package options.
+Denotes a lead(Pb)-free/RoHS-compliant package.
/V denotes an automotive qualified part.
tioned under the connector.
• The DS8024 and the host microcontroller must use
the same V supply. Pins CLKDIV1, CLKDIV2,
DD
RSTIN, PRES, AUX1IN, I/OIN, AUX2IN, 5V/3V,
CMDVCC, and OFF are referenced to V ; if pin
DD
Package Information
XTAL1 is to be driven by an external clock, also
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/pacꢀages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
reference this pin to V
.
DD
• Trace C3 (CLK) should be placed as far as possi-
ble from the other traces.
• The trace connecting CGND to C5 (GND) should
ꢄACKAGꢃ
TYꢄꢃ
ꢄACKAGꢃ
CODꢃ
OUTLINꢃ
NO.
LAND
ꢄATTꢃRN NO.
be straight (the two capacitors on C1 (V ) should
CC
be connected to this ground trace).
28 SO (300 mils)
28 TSSOP
W28+6
U28+1
21-0042
21-0066
90-0109
90-0171
• Avoid ground loops among CGND, PGND, and
GND.
• Decouple V
and V
separately; if the two
DD
DDA
supplies are the same in the application, they
should be connected in a star on the main trace.
• Connect a 100nF capacitor (ESR < 100mΩ)
between V
and CGND and place near the
pin.
CC
CC
DS8024’s V
• Connect a 100nF or 220nF capacitor (220nF pre-
ferred, ESR < 100mΩ) between V
and CGND
CC
and place near the smart card socket’s C1 contact.
With all these layout precautions, noise should be kept
to an acceptable level and jitter on C3 (CLK) should be
less than 100ps.
14
Smart Card Interface
DS8024
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
Initial release
Clarified the V
—
2
0
1
6/08
specification in the Recommended DC Operating Conditions table
8/08
DDA
Added the automotive TSSOP version to the Ordering Information and Selector Guide;
updated the Absolute Maximum Ratings
1, 2, 14
13
2
3
2/12
7/12
Added footnote to the resistor value on the PRES pin in Figure 8
EMVCo approval of the interface module (IFM) contained in this Terminal shall mean only that the IFM has been tested in accordance and for sufficient
conformance with the EMV Specifications, Version 3.1.1, as of the date of testing. EMVCo approval is not in any way an endorsement or warranty regarding
the completeness of the approval process or the functionality, quality or performance of any particular product or service. EMVCo does not warrant any
products or services provided by third parties, including, but not limited to, the producer or provider of the IFM and EMVCo approval does not under any
circumstances include or imply any product warranties from EMVCo, including, without limitation, any implied warranties of merchantability, fitness for pur-
pose, or noninfringement, all of which are expressly disclaimed by EMVCo. All rights and remedies regarding products and services which have received
EMVCo approval shall be provided by the party providing such products or services, and not by EMVCo and EMVCo accepts no liability whatsoever in
connection therewith.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in
the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated Products Inc. 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 ________________ 15
© 2012 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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