DS3908N [MAXIM]
Dual, 64-Position Nonvolatile Digital Potentiometer with Buffered Outputs; 双通道， 64位，非易失数字电位器，提供缓冲输出
| 型号： | DS3908N |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Dual, 64-Position Nonvolatile Digital Potentiometer with Buffered Outputs |
| 文件： | 总11页 (文件大小：219K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Rev 0; 4/06
Dual, 64-Position Nonvolatile Digital
Potentiometer with Buffered Outputs
General Description
Features
The DS3908 contains two nonvolatile digital poten-
tiometers with programmable-gain amplifiers buffering
the wiper outputs. The potentiometer position and
ꢀ Two 64-Position Linear Taper Potentiometers
ꢀ Integral Wiper Buffering Amplifiers with
Selectable Gains of 1V/V, 2V/V, or 4V/V
2
amplifier gain are controlled through an I C*-compati-
ꢀ 100kΩ Potentiometer End-to-End Resistance
ꢀ Low Potentiometer Temperature Coefficient
ꢀ Nonvolatile Wiper and Gain Storage
ble serial bus. The DS3908 operates in both 3.3V and
5V systems and features a write-protect pin that locks
the position of the potentiometers and gain registers. Up
2
to eight DS3908s can be placed on a single I C bus.
2
ꢀ I C-Compatible Interface
ꢀ Write-Protect Pin Prevents Accidental Field
Reprogramming
ꢀ 3V to 5.5V Supply Voltage Range
ꢀ -40°C to +85°C Operating Temperature Range
ꢀ 14-Pin TDFN Package
Applications
Ordering Information
Pin-Diode Biasing
PART
DS3908N+
TEMP RANGE
PIN-PACKAGE
Power-Supply Calibration
Cell Phones and PDAs
Portable Electronics
-40°C to +85°C
14 TDFN
+Denotes lead-free package.
Typical Operating Circuit
Pin Configuration
TOP VIEW
V
CC
VOLTAGE
14
V
CC
SDA
SCL
A0
1
2
3
4
5
6
7
POT0
POT1
H0
V0
REFERENCE
DS3908
13 H1
NV ADJUSTABLE
REFERENCE
VOLTAGE
PGA0
PGA1
SDA
SCL
12
11
V1
L1
L0
H1
V1
2
A1
A0
A1
I C
DS3908
INTERFACE
A2
10 H0
A2
NV ADJUSTABLE
REFERENCE
VOLTAGE
WP
WP
GND
V0
L0
9
8
L1
TDFN (3mm x 3mm)
2
2
I C is a trademark of Philips Corp. Purchase of I C components from Maxim Integrated Products, Inc., or one of its sublicensed
2
2
Associated Companies, conveys a license under the Philips I C Patent Rights to use these components in an I C system, provided
that the system conforms to the I C Standard Specification as defined by Philips.
2
______________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Dual, 64-Position Nonvolatile Digital
Potentiometer with Buffered Outputs
ABSOLUTE MAXIMUM RATINGS
Voltage on V , SDA, and SCL Relative to GND .....-0.5V to +6.0V
Programming Temperature Range.........................0°C to +70°C
Storage Temperature Range.............................-55°C to +125°C
Soldering Temperature ............Refer to J-STD-020 Specification
CC
Voltage on A0, A1, A2, L0, L1, H0, H1, and WP Relative
to GND................-0.5V to (V
+ 0.5V) (not to exceed +6.0V)
CC
Operating Temperature Range ...........................-40°C to +85°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(T = -40°C to +85°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
+3.0
0.7 x
TYP
MAX
UNITS
Supply Voltage
V
(Note 1)
+5.5
V
CC
Input Logic 1
(SCL, SDA, A0, A1, A2, WP)
V
+
CC
V
V
V
V
IH
V
0.3
CC
Input Logic 0
(SCL, SDA, A0, A1, A2, WP)
0.3 x
V
CC
V
-0.3
-0.3
IL
Potentiometer Voltage
(L0, L1, H0, H1)
V
+
CC
V
= +3.0V to +5.5V
CC
0.3V
DC ELECTRICAL CHARACTERISTICS
(V
= +3.0V to +5.5V, T = -40°C to +85°C.)
A
CC
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
+1
UNITS
µA
Input Leakage
I
L
-1
Standby Supply Current
I
V
= 5.5V (Note 2)
CC
2
mA
STBY
V
3mA sink current
6mA sink current
0
0
0.4
0.6
10
OL1
OL2
Low-Level Output Voltage
(SDA)
V
V
I/O Capacitance
C
pF
I/O
WP Internal Pullup Resistance
R
WP
40
65
100
kΩ
ANALOG POTENTIOMETER CHARACTERISTICS
(V
= +3.0V to +5.5V, T = -40°C to +85°C.)
A
CC
PARAMETER
SYMBOL
CONDITIONS
MIN
79
TYP
MAX
121
UNITS
kΩ
End-to-End Resistance
Absolute Linearity
Relative Linearity
+25°C
100
INL
(Notes 3, 4)
(Notes 4, 5)
-0.6
-0.25
+0.6
+0.25
LSB
LSB
DNL
End-to-End Temperature
Coefficient
50
ppm/°C
2
_____________________________________________________________________
Dual, 64-Position Nonvolatile Digital
Potentiometer with Buffered Outputs
PROGRAMMABLE-GAIN AMPLIFIER CHARACTERISTICS
(V
= +3.0V to +5.5V, T = -40°C to +85°C.)
A
CC
PARAMETER
SYMBOL
CONDITIONS
MIN
0
TYP
MAX
- 1.5
CC
UNITS
Common-Mode Input Voltage
CMV
V
V
V
IN
R
R
R
≥ 2kΩ, G = 1V/V
0.975
1.925
3.850
0.3
1
2
4
1.025
2.05
4.10
L
L
L
Gain
G
V/V
≥ 2kΩ, G = 2V/V
≥ 2kΩ, G = 4V/V
Output Voltage Range
Power-Supply Rejection Ratio
Output Source Current
Output Sink Current
V
R = 2kΩ, -1mA < I
< 1mA
- 0.3
CC
V
dB
OUT
L
OUT
PSRR
60
90
3.5
800
I
V
V
= 0V, Hx = Lx = 1V
= 1V, Hx = Lx = 0V
-15
mA
OUT:SOURCE
OUT
OUT
I
15
mA
OUT:SINK
Unity-Gain Frequency
Amplifier Capacitive Loading
Input Offset Voltage
f
Gain = 1V/V, position 3Fh
MHz
pF
T
C
100
+9
L
V
-9
mV
OS
Load Regulation
-1mA < I
< 1mA
2200
840
µV/mA
V/ms
OUT
Output-Voltage Slew Rate
R = 10kΩ, C = 10pF
270
L
L
AC ELECTRICAL CHARACTERISTICS
(V
= +3.0V to +5.5V, T = -40°C to +85°C.) (See Figure 2.)
A
CC
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCL Clock Frequency
f
(Note 6)
400
kHz
SCL
Bus Free Time between STOP
and START Conditions
t
1.3
0.6
µs
µs
BUF
Hold Time (Repeated) START
Condition
t
HD:STA
Low Period of SCL
High Period of SCL
Data Hold Time
t
1.3
0.6
µs
µs
µs
ns
µs
ns
ns
µs
pF
ms
µs
LOW
t
HIGH
t
0
0.9
HD:DAT
Data Setup Time
t
100
SU:DAT
Start Setup Time
t
0.6
SU:STA
SDA and SCL Rise Time
SDA and SCL Fall Time
STOP Setup Time
t
(Note 7)
(Note 7)
20 + 0.1C
20 + 0.1C
0.6
300
300
R
B
B
t
F
t
SU:STO
SDA and SCL Capacitance
C
(Note 7)
(Note 8)
400
17
B
EEPROM Write Time
Startup Time
t
W
10
t
V
= 3.0V
CC
40
ST
_____________________________________________________________________
3
Dual, 64-Position Nonvolatile Digital
Potentiometer with Buffered Outputs
NONVOLATILE MEMORY CHARACTERISTICS
(V
= +3.0V to +5.5V.)
CC
PARAMETER
SYMBOL
CONDITIONS
At +70°C
MIN
MAX
UNITS
EEPROM Write Cycles
50,000
Note 1: All voltages are referenced to ground.
Note 2: specified assuming control pins are connected as follows: WP must be disconnected or connected high. H terminal
I
STBY
connected to V , L terminal connected to GND, potentiometer position 1Dh, PGA is at 2V/V, A0 to A2 connected to V
,
CC
CC
SDA and SCL connected to V , with no load.
CC
Note 3: Absolute linearity is used to measure expected wiper voltage as determined by wiper position in a voltage-divider
configuration.
Note 4: This specification only refers to the potentiometers, and does not include the gain and offset error due to the PGA.
Note 5: Relative linearity is used to determine the change of wiper voltage between two adjacent wiper positions in a voltage-
divider configuration.
2
2
Note 6: I C interface timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with I C stan-
dard-mode timing.
Note 7: C —total capacitance of one bus line in picofarads, timing referenced to 0.9 x V
and 0.1 x V
.
CC
B
CC
Note 8: EEPROM write begins after a stop condition occurs.
Typical Operating Characteristics
(T = +25°C, unless otherwise noted.)
A
STANDBY SUPPLY CURRENT
STANDBY SUPPLY CURRENT
vs. TEMPERATURE
STANDBY SUPPLY CURRENT
vs. SCL FREQUENCY
vs. SUPPLY VOLTAGE
2.0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.16400
1.16200
+85°C +25°C
1.8
5.5V
4.0V
3.3V
1.6
1.4
1.2
1.0
0.8
1.16000
1.15800
1.15600
1.15400
Hx = V , Lx = GND
CC
-40°C
A0 TO A2 = V
0.6
0.4
0.2
0
CC
SDA, SCL = V
POT AT 1Dh
GAIN = 2V/V
NO LOAD
CC
1.15200
1.15000
3.0
3.5
4.0
4.5
5.0
5.5
-40
-15
10
35
60
85
1
100
10,000
1,000,000
V
TEMPERATURE (°C)
SCL FREQUENCY (Hz)
CC
OUTPUT VOLTAGE vs. POT SETTING
V
vs. I
V
- V vs. I
OL
OUT:SINK
CC OH OUT:SOURCE
1.10000
10
1
10
1
GAIN = 1V/V
Hx = 1V
Lx = 0.3V
1.00000
1.90000
1.80000
1.70000
1.60000
1.50000
1.40000
1.30000
0.1
0.1
+85°C +25°C
+85°C
+25°C
0.01
0.01
-40°C
-40°C
0.001
0.001
0
10
20
30
40
50
60
0.001
0.01
0.1
1
10
100
0.001
0.01
0.1
1
10
100
POT SETTING (DEC)
I
(mA)
I
(mA)
OUT:SINK
OUT:SOURCE
4
_____________________________________________________________________
Dual, 64-Position Nonvolatile Digital
Potentiometer with Buffered Outputs
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
NORMALIZED POT END-END RESISTANCE
vs. TEMPERATURE
POT INL vs. SETTING
POT DNL vs. SETTING
1.0
0.8
0.6
0.4
0.2
0
0.25
0.20
0.15
0.10
0.05
0
0.25
0.20
0.15
0.10
0.05
0
V
= 5V
GAIN = 1V/V
CC
GAIN = 1V/V
-0.2
-0.4
-0.6
-0.8
-1.0
-0.05
-0.10
-0.15
-0.20
-1.25
-0.05
-0.10
-0.15
-0.20
-1.25
-40
-15
10
35
60
85
0
10
20
30
40
50
60
0
10
20
30
40
50
60
TEMPERATURE (°C)
POT0 SETTING (DEC)
POT0 SETTING (DEC)
TYPICAL PGA OFFSET
vs. TEMPERATURE
TYPICAL PGA OFFSET
vs. COMMON-MODE INPUT VOLTAGE
0.6
0.5
0.4
0.3
0.2
0.1
0
0.25
0.2
+85°C
CMV = 0.3V
IN
0.15
0.1
0.05
0
+25°C
-40°C
CMV = 2.0V
IN
-0.1
-0.2
-0.3
-0.4
-0.5
-0.05
-0.1
-0.15
-0.2
CMV = 3.5V
IN
GAIN = 1V/V
DATA OFFSET TO SHOW 0 AT 2V CMV
IN
0.3 0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5
COMMON-MODE INPUT VOLTAGE (V)
-40
-15
10
35
60
85
TEMPERATURE (°C)
Pin Description
TDFN PIN
NAME
SDA
FUNCTION
2
2
1
2
I C Serial Data. Input/output for I C data.
2
2
SCL
I C Serial Clock. Input for I C clock.
2
2
Address-Select Inputs. Determines I C address. Device address is 1010A A A . (See the I C Slave
2
1 0
3, 4, 5
6
A0, A1, A2
WP
Address and Address Pins section for more details.)
Write-Protect Input. Must be grounded to write to the registers. An internal pullup will lock the register
values if this pin is not connected.
7
GND
L0, L1
V0, V1
H0, H1
Ground Terminal
8, 11
9, 12
10, 13
14
Potentiometer Low Terminals. Voltages on these pins should remain between GND and V
Amplifier Outputs
.
CC
Potentiometer High Terminals. Voltages on these pins should remain between GND and V
Supply Voltage Terminal
.
CC
V
CC
_____________________________________________________________________
5
Dual, 64-Position Nonvolatile Digital
Potentiometer with Buffered Outputs
Functional Diagram
DS3908
EEPROM
F8h
POT0
POT1
V
H0
V0
CC
V
CC
POT0 REGISTER
PGA0
PGA1
SDA
SCL
A0
L0
2
F9h
FAh
I C
INTERFACE
H1
V1
A1
POT1 REGISTER
A2
L1
POT0/1 REGISTER
V
CC
1x, 2x, 4x GAIN
1x, 2x, 4x GAIN
R
WP
FBh
WP
G1
G0
GND
analog factory calibration because it prevents errant
Detailed Description
The DS3908 contains two nonvolatile digital poten-
tiometers with programmable-gain amplifiers buffering
the wiper outputs.
2
transactions on the I C bus from corrupting the settings
of the device. The WP pin contains an internal pullup
resistor that must be pulled low to write to the device.
The programmable-gain amplifiers can be indepen-
dently set to one of three different gains—1V/V, 2V/V, or
4V/V. The amplifiers’ common-mode input range is from
The potentiometers have 63 equally weighted (linear-
taper) resistive elements, for a total of 64 taps. The
resistive elements are built using a low-temperature-
drift material, and have a typical 100kΩ end-to-end
resistance. This produces an output that is highly lin-
ear, with the highest and lowest taps connected to high
(Hx) and low (Lx) terminals, respectively. The poten-
ground to 1.5V below V , and the output is rail-to-rail
CC
and capable of driving 1mA loads, 300mV from each
supply rail. The outputs are stable driving 100pF loads
for applications that require output filtering.
2
The addition of the amplifier to buffer the potentiometer
wiper offers distinct advantages over standard digital
potentiometers. The buffer provides a high-impedance
load for the potentiometer and a low-impedance volt-
age output. This improves the linearity of the output
voltage for systems that load the potentiometer by elim-
inating the changes in current through both the poten-
tiometer and the wiper impedance. It also allows
voltage gain from the potentiometer input to the output.
Because the amplifiers are integrated into the DS3908,
this is done without increasing the footprint of the
design or the complexity of the PC board.
tiometers are independently controlled using an I C-
compatible interface. Three address pins allow one of
eight slave addresses to be selected. The eight slave
addresses allow the DS3908 address to be customized
2
for applications with multiple I C devices, and allow up
2
to eight DS3908s to be placed on the same I C bus.
The potentiometer positions are saved in EEPROM, and
are recalled during each power-up to provide non-
volatile position settings. Once the settings are written,
the write-protect pin prevents accidental writes to the
potentiometers. The write-protection function is ideal for
6
_____________________________________________________________________
Dual, 64-Position Nonvolatile Digital
Potentiometer with Buffered Outputs
2
I C Slave Address and Address Pins
2
The DS3908’s I C slave address is determined by the
state of the A0, A1, and A2 address pins as shown in
the pin configuration (see Figure 1). Address pins con-
nected to GND result in a ‘0’ in the corresponding bit
position in the slave address. Conversely, address pins
MSB
1
LSB
R/W
0
1
0
A1
A0
A2
connected to V
result in a ‘1’ in the corresponding bit
CC
2
positions. I C communication is described in detail in
SLAVE
ADDRESS*
READ/WRITE
BIT
2
the I C Serial Interface Description section.
Potentiometer Control
The potentiometers of the DS3908 have 64 taps with 63
resistive elements separating them. Thus, the most and
least significant wiper positions connect the amplifier to
the voltages at the high and low terminals of the poten-
tiometer, respectively.
*THE SLAVE ADDRESS IS DETERMINED BY
ADDRESS PINS A0, A1, AND A2.
The potentiometers of the DS3908 are controlled by
communicating with the following registers:
Figure 1. DS3908 Slave Address Byte
Table 1. Potentiometer Registers
NUMBER OF
2
ADDRESS
POTENTIOMETER
I C FUNCTIONS
DEFAULTS
POSITIONS*
64 (00h to 3Fh)
64 (00h to 3Fh)
64 (00h to 3Fh)
F8h
F9h
FAh
Pot 0
Pot 1
Read/Write
Read/Write
Write Only
1Fh
1Fh
—
Pot 0 and Pot 1
*The two most significant bits of each potentiometer position register are ignored. Writing values greater than 3Fh to any of the
potentiometer registers will result in a valid 6-bit position, without regard to the value of the most significant two bits. Example:
Register values C2h, 82h, 42h, and 02h are all potentiometer position 2.
_____________________________________________________________________
7
Dual, 64-Position Nonvolatile Digital
Potentiometer with Buffered Outputs
When writing to the DS3908, the potentiometer will
adjust to the new setting once it has acknowledged the
new data that is being written, and the EEPROM (used
to make the setting nonvolatile) will be written following
the stop condition at the end of the write command. To
change the setting without changing the EEPROM, ter-
minate the write with a repeated start condition before
the next stop condition occurs. Using a repeated start
condition prevents the 20ms (maximum) delay required
for the EEPROM write cycle to finish.
Programmable Amplifier Control
The gain of both DS3908 amplifiers is controlled by
writing to register address FBh. The most significant
nibble of the FBh address controls the PGA1 gain, and
the least significant nibble controls the PGA0 gain. The
format of each nibble is shown in the tables below:
Table 2. Programmable Amplifier Register
REGISTER FORMAT (BINARY)
ADDRESS
PGA1
PGA0
R*
G1
G1
G1
R*
G0
G0
G0
0
2
1
0
2
1
FBh
bit7
bit0
Default value = 11h.
*Reserved for future use, write to zeros.
Table 3. Programmable Amplifier Gain Codes
Gx Gx Gx
AMPLIFIER GAIN (V/V)
2
1
00X
01X
1XX
0
1
2
4
X = Don’t care.
Writes to this register are similar to writes to the poten-
tiometer register. A stop condition must follow the write
to ensure that the EEPROM is modified. A repeated
start condition before a stop condition following a write
operation will prevent the settings from being stored in
Write Protection
The write-protect pin has an internal pullup resistor. To
adjust the potentiometers’ position, this pin must be
grounded. This pin can be left floating or connected to
V
to write protect the EEPROM memory. All registers
can be read when the device is write protected.
CC
2
EEPROM. (See the I C Communication section for
more details.)
8
_____________________________________________________________________
Dual, 64-Position Nonvolatile Digital
Potentiometer with Buffered Outputs
2
Bit Write: Transitions of SDA must occur during the low
I C Serial Interface Description
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL plus the
setup and hold-time requirements (see Figure 2). Data is
shifted into the device during the rising edge of the SCL.
2
I C Definitions
The following terminology is commonly used to describe
I C data transfers:
2
Master Device: The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses, and start and stop conditions.
Bit Read: At the end of a write operation, the master
must release the SDA bus line for the proper amount of
setup time (see Figure 2) before the next rising edge of
SCL during a bit read. The device shifts out each bit of
data on SDA at the falling edge of the previous SCL
pulse and the data bit is valid at the rising edge of the
current SCL pulse. Remember that the master gener-
ates all SCL clock pulses including when it is reading
bits from the slave.
Slave Devices: Slave devices send and receive data at
the master’s request.
Bus Idle or not Busy: Time between stop and start
conditions when both SDA and SCL are inactive and in
their logic-high states. When the bus is idle it often initi-
ates a low-power mode for slave devices.
Acknowledgement (ACK and NACK): An Acknowledge-
ment (ACK) or Not Acknowledge (NACK) is always the
9th bit transmitted during a byte transfer. The device
receiving data (the master during a read or the slave dur-
ing a write operation) performs an ACK by transmitting a
zero during the 9th bit. A device performs a NACK by
transmitting a one during the 9th bit. Timing (Figure 2)
for the ACK and NACK is identical to all other bit writes.
An ACK is the acknowledgment that the device is prop-
erly receiving data. A NACK is used to terminate a read
sequence or as an indication that the device is not
receiving data.
Start Condition: A start condition is generated by the
master to initiate a new data transfer with a slave.
Transitioning SDA from high to low while SCL remains
high generates a start condition. See the timing dia-
gram for applicable timing.
Stop Condition: A stop condition is generated by the
master to end a data transfer with a slave. Transitioning
SDA from low to high while SCL remains high generates
a stop condition. See the timing diagram for applicable
timing.
Repeated Start Condition: The master can use a
repeated start condition at the end of one data transfer to
indicate that it will immediately initiate a new data trans-
fer following the current one. Repeated starts are com-
monly used during read operations to identify a specific
memory address to begin a data transfer. A repeated
start condition is issued identically to a normal start
condition. See the timing diagram for applicable timing.
Byte Write: A byte write consists of 8 bits of information
transferred from the master to the slave (most signifi-
cant bit first) plus a 1-bit acknowledgement from the
slave to the master. The 8 bits transmitted by the mas-
ter are done according to the bit write definition and the
acknowledgement is read using the bit read definition.
SDA
t
BUF
t
SP
t
HD:STA
t
LOW
t
t
F
R
SCL
t
SU:STA
t
HD:STA
t
HIGH
t
REPEATED
START
t
SU:STO
SU:DAT
STOP
START
t
HD:DAT
NOTE: TIMING IS REFERENCE TO V
AND V
.
IH(MIN)
IL(MAX)
2
Figure 2. I C Timing Diagram
_____________________________________________________________________
9
Dual, 64-Position Nonvolatile Digital
Potentiometer with Buffered Outputs
Byte Read: A byte read is an 8-bit information transfer
from the slave to the master plus a 1-bit ACK or NACK
from the master to the slave. The 8 bits of information
that are transferred (most significant bit first) from the
slave to the master are read by the master using the bit
read definition above, and the master transmits an ACK
using the bit write definition to receive additional data
bytes. The master must NACK the last byte read to ter-
minated communication so the slave will return control
of SDA to the master.
condition prevents the 20ms (maximum) delay required
for the EEPROM write cycle to finish.
If the master continues to write data to the DS3908,
without generating a stop condition, then the same reg-
ister will be overwritten.
Acknowledge Polling: Any time an EEPROM byte is
written, the DS3908 requires the EEPROM write time
(t ) after the stop condition to write the contents of the
W
byte to EEPROM. During the EEPROM write time, the
device will not acknowledge its slave address because
it is busy. It is possible to take advantage of this phe-
nomenon by repeatedly addressing the DS3908, which
allows communication to continue as soon as the
DS3908 is ready. The alternative to acknowledge
2
Slave Address Byte: Each slave on the I C bus
responds to a slave address byte sent immediately fol-
lowing a start condition. The slave address byte con-
tains the slave address in the most significant 7 bits
and the R/W bit in the least significant bit.
polling is to wait for a maximum period of t to elapse
W
before attempting to access the device.
The DS3908’s slave address is determined by the state
of the A0, A1, and A2 address pins as shown in Figure 1.
Address pins connected to GND result in a ‘0’ in the
corresponding bit position in the slave address.
EEPROM Write Cycles: The DS3908’s EEPROM write
cycles are specified in the Nonvolatile Memory
Characteristics table. The specification shown is at the
worst-case temperature. It is capable of handling many
additional writes at room temperature.
Conversely, address pins connected to V
result in a
CC
‘1’ in the corresponding bit positions.
When the R/W bit is 0 (such as in A0h), the master is
indicating it will write data to the slave. If R/W = 1, (A1h
in this case), the master is indicating it wants to read
from the slave.
Reading a Single Byte from a Slave: Unlike the write
operation that uses the specified memory address byte
to define where the data is to be written, the read oper-
ation occurs at the present value of the memory
address pointer. To read a single byte from the slave,
the master generates a start condition, writes the slave
address byte with R/W = 1, reads the data byte with a
NACK to indicate the end of the transfer, and generates
a stop condition.
If an incorrect slave address is written, the DS3908 will
2
assume the master is communicating with another I C
device and ignore the communication until the next
start condition is sent.
2
Memory Address: During an I C write operation to the
DS3908, the master must transmit a memory address to
identify the memory location where the slave is to store
the data. The memory address is always the second
byte transmitted during a write operation following the
slave address byte.
Manipulating the Address Pointer for Reads: A
dummy write cycle can be used to force the address
pointer to a particular value. To do this, the master gen-
erates a start condition, writes the slave address byte
(R/W = 0), writes the memory address where it desires
to read, generates a repeated start condition, writes the
slave address byte (R/W = 1), reads data with ACK or
NACK as applicable, and generates a stop condition.
2
I C Communication
Writing a Single Byte to a Slave: The master must
generate a start condition, write the slave address byte
(R/W = 0), write the memory address, write the byte of
data, and generate a stop condition. The master must
read the slave’s acknowledgement during all byte write
operations.
See Figure 3 for a read example using the repeated
start condition to specify the memory location.
Applications Information
Power-Supply Decoupling
To achieve the best results when using the DS3908,
decouple the power supply with a 0.01µF or 0.1µF
capacitor. Use a high-quality, ceramic, surface-mount
capacitor if possible. Surface-mount components mini-
mize lead inductance, which improves performance,
and ceramic capacitors tend to have adequate high-
frequency response for decoupling applications.
When writing to the DS3908, the potentiometer will
adjust to the new setting once it has acknowledged the
new data that is being written, and the EEPROM (used
to make the setting nonvolatile) will be written following
the stop condition at the end of the write command. To
change the setting without changing the EEPROM, ter-
minate the write with a repeated start condition before
the next stop condition occurs. Using a repeated start
10
____________________________________________________________________
Dual, 64-Position Nonvolatile Digital
Potentiometer with Buffered Outputs
V
= PGA Input Voltage Offset Voltage (V)
Total Error
The total error in a reading from the DS3908 can be
calculated using the following formula:
OFF
INL
= Potentiometer Integral Non-Linearity (LSB)
ERR
For example, the worst-case error for V = 2V, V = 0.5V,
PGA Gain = 2V/V, PotCode = 31d (1Fh), is given by:
H
L
PotVoltage = (PotCode / 63) x (V – V ) + V
H
L
L
Error
Error
Error
= (INL
/ 63) x (V – V )
POT
ERR H L
PotVoltage = 31 / 63 x (2.0V - 0.5V) + 0.5V = 1.238V
= Gain x V
OFFSET
OFF
Error
Error
Error
= (0.6 / 63) x (2.0V - 0.5V) = 0.014V
POT
= PotVoltage x Gain
GAIN
ERR
= 2.0V/V x 9mV = 0.018V
OFFSET
Total Output Error = Error
where:
+ Error
+ Error
OFFSET GAIN
POT
= PotVoltage x Gain
= 0.0929V
GAIN
ERR
Total Output Error = Error
+ Error + Error
OFFSET GAIN
POT
PotCode = Potentiometer Setting (dec)
Gain = Amplifier Gain Deviation from Desired (V/V)
= 0.014V + 0.018V + 0.0929V = 0.125V
ERR
2
TYPICAL I C WRITE TRANSACTION
MSB
LSB
A2 A1 A0 R/W
MSB
LSB
MSB
LSB
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
START
1
0
1
0
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
STOP
READ/
WRITE
REGISTER/MEMORY ADDRESS
SLAVE
ADDRESS*
DATA
*THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0, A1, AND A2.
2
EXAMPLE I C TRANSACTIONS (WHEN A0, A1, AND A2 ARE CONNECTED TO GND)
A0h
F9h
A) SINGLE BYTE
NONVOLATILE WRITE
-WRITE POTENTIOMETER 1
TO 00h
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
1 0 1 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
1 1 1 1 1 0 0 1
START
START
STOP
A0h
F9h
A) SINGLE BYTE
VOLATILE WRITE
-WRITE POTENTIOMETER 1
TO 00h
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
REPEATED
START
1 0 1 0 0 0 0 0
1 1 1 1 1 0 0 1
STOP
A0h
F8h
DATA
POT 0
A1h
B) SINGLE BYTE READ
-READ POTENTIOMETER 0
SLAVE
ACK
SLAVE
ACK
REPEATED
START
SLAVE
ACK
MASTER
NACK
1 0 1 0 0 0 0 0
1 1 1 1 1 0 0 0
1 0 1 0 0 0 0 1
START
STOP
2
Figure 3. I C Communication Examples
Package Information
Chip Topology
For the latest package outline information, go to
TRANSISTOR COUNT: 9950
www.maxim-ic.com/DallasPackInfo.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11
© 2006 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
is a registered trademark of Dallas Semiconductor Corporation.
Heaney
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