DS3911T+T [MAXIM]
Temperature-Controlled, Nonvolatile, I2C Quad DAC; 温度控制，非易失， I²C四通道DAC
| 型号： | DS3911T+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Temperature-Controlled, Nonvolatile, I2C Quad DAC |
| 文件： | 总24页 (文件大小：1611K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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19-5933; Rev 0; 6/11
General Description
Features
The DS3911 is a quad, 10-bit delta-sigma output, nonvol-
atile (NV) controller that features an on-chip temperature
sensor and associated analog-to-digital converter (ADC).
The integrated temperature sensor indexes the up to
2NC resolution NV lookup tables (LUTs), encompassing
a -40NC to +100NC temperature range. The LUT directly
drives the delta-sigma digital-to-analog converter (DAC)
outputs. This flexible LUT-based architecture allows the
device to provide a temperature-compensated DAC out-
put with arbitrary slope. Programming is accomplished
SꢀFourꢀ10-BitꢀDelta-SigmaꢀOutputs
SꢀOn-ChipꢀTemperatureꢀSensorꢀandꢀADC
SꢀFourꢀTemperature-IndexedꢀLUTs,ꢀUpꢀtoꢀ2NCꢀ
Resolution
2
SꢀI C-CompatibleꢀSerialꢀInterface
SꢀAddressꢀPinsꢀAllowꢀUpꢀtoꢀFourꢀDS3911sꢀtoꢀShareꢀ
2
theꢀSameꢀI CꢀBus
Sꢀ2.8Vꢀtoꢀ5.5VꢀDigitalꢀSupply
2
Sꢀ-40NCꢀtoꢀ+100NCꢀOperatingꢀTemperatureꢀRange
Sꢀ3mmꢀxꢀ5mm,ꢀ14-PinꢀTDFNꢀPackage
by an I C-compatible interface that operates at speeds
of up to 400kHz.
Applications
Ordering Information appears at end of data sheet.
Active Optical Cables
For related parts and recommended products to use with this part,
refer to www.maxim-ic.com/DS3911.related.
Optical Transceivers
Linear and Nonlinear Compensation
Instrumentation and Industrial Controls
Typical Operating Circuit
3.3V
V
CC
3.3V
V
CC
R
PU
DS3911
0.1µF
3.3V
SDA
SCL
GND
2
I C
MASTER
100Ω
2
TEMP
SENSOR
I C
V
REF
SLAVE
V
A1
A0
REF
0.1µF
GND
2.5V
R1
R2
EEPROM
LUT
10-BIT DAC0
DAC
MODSET
APCSET
LASER
DRIVER
C1
C2
EEPROM
LUT
10-BIT DAC1
DAC
MODSET
APCSET
LASER
DRIVER
EEPROM
LUT
10-BIT DAC2
DAC
MODSET
APCSET
LASER
DRIVER
EEPROM
LUT
10-BIT DAC3
DAC
MODSET
APCSET
LASER
DRIVER
Forꢀpricing,ꢀdelivery,ꢀandꢀorderingꢀinformation,ꢀpleaseꢀcontactꢀMaximꢀDirectꢀatꢀ1-888-629-4642,ꢀ
orꢀvisitꢀMaxim’sꢀwebsiteꢀatꢀwww.maxim-ic.com.
����������������������������������������������������������������� ꢀMaxim Integrated Productsꢀ ꢀ 2
DS3911
Temperature-Controlled, Nonvolatile,
2
I C Quad DAC
ABSOLUTEꢀMAXIMUMꢀRATINGS
Voltage Range on SDA, SCL, and V
Operating Temperature Range........................ -40NC to +100NC
Programming Temperature Range .................... -40NC to +85NC
Storage Temperature Range............................ -55NC to +125NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
CC
Relative to GND ................................................-0.3V to +6.0V
Voltage Range on DAC0, DAC1, DAC2, DAC3,
V
, A0, A1 Relative to GND.............. -0.3V to (V
+ 0.3V)
REF
CC
Continuous Power Dissipation (T = +70NC)
A
TDFN (derate 21.7mW/NC above +70NC)...............1739.1mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
RECOMMENDEDꢀOPERATINGꢀCONDITIONS
(T = -40NC to +100NC, unless otherwise noted.)
A
PARAMETER
Supply Voltage
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
(Note 1)
2.8
5.5
V
CC
Input Logic 1
(SCL, SDA, A0, A1)
V
0.7 x V
V + 0.3
CC
V
V
IH
CC
Input Logic 0
(SCL, SDA, A0, A1)
V
-0.3
+0.3 x V
CC
IL
DCꢀELECTRICALꢀCHARACTERISTICS
(V
= +2.8V to +5.5V, T = -40NC to +100NC, unless otherwise noted.)
A
CC
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Leakage
(SDA, SCL, A0, A1)
I
-1
+1
FA
L
V
Supply Current
I
(Note 2)
0.9
5
2.0
0.4
10
2.7
5
mA
V
CC
CC
Low-Level Output Voltage (SDA)
I/O Capacitance
V
3mA sink current
0
OL
C
pF
V
I/O
Power-On Recall Voltage
Power-Up Recall Delay
V
(Note 3)
(Note 4)
1.6
POR
t
ms
D
DACꢀELECTRICALꢀCHARACTERISTICS
(V
= +2.8V to +5.5V, T = -40NC to +100NC, unless otherwise noted.)
A
CC
PARAMETER
Delta-Sigma Clock Frequency
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MHz
V
f
2.1
DS
Reference Voltage Input (V
)
V
Minimum 0.1FF to GND
2.4
0
V
CC
REF
REF
Output Range
V
V
REF
See the Delta-Sigma DAC Output and
Control section for details
Output Resolution
Output Impedance
10
Bits
R
35
100
I
DS
����������������������������������������������������������������� ꢀMaxim Integrated Productsꢀ ꢀ 3
DS3911
Temperature-Controlled, Nonvolatile,
2
I C Quad DAC
TEMPERATUREꢀSENSORꢀCHARACTERISTICS
(V
= +2.8V to +5.5V, T = -40NC to +100NC, unless otherwise noted.)
A
CC
PARAMETER
SYMBOL
CONDITIONS
= -40NC to +100NC
MIN
TYP
MAX
UNITS
Temperature Error
T
Q5
NC
A
Update Rate (Temperature and
Supply Conversion Time)
t
16
ms
FRAME
ANALOGꢀVOLTAGEꢀMONITORINGꢀCHARACTERISTICS
(V
= +2.8V to +5.5V, T = -40NC to +100NC, unless otherwise noted.)
A
CC
PARAMETER
SYMBOL
LSB
CONDITIONS
Full-scale voltage of 6.5536V
At factory setting
MIN
TYP
800
0.25
0
MAX
UNITS
FV
Supply Resolution
Input/Supply Accuracy
Input Supply Offset
ACC
1
5
%FS
LSB
V
(Note 5)
OS
Update Rate (Temperature and
Supply Conversion Time)
t
16
ms
FRAME
2
I CꢀACꢀELECTRICALꢀCHARACTERISTICS
(V
= +2.8V to +5.5V, T = -40NC to +100NC, timing referenced to V
and V
, unless otherwise noted.) (See Figure 1.)
CC
A
IL(MAX)
IH(MIN)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCL Clock Frequency
f
(Note 6)
0
400
kHz
SCL
Bus Free Time Between STOP
and START Conditions
t
1.3
0.6
Fs
Fs
BUF
Hold Time (Repeated) START
Condition
t
HD:STA
Low Period of SCL
High Period of SCL
Data Hold Time
t
1.3
0.6
Fs
Fs
Fs
ns
Fs
ns
ns
Fs
LOW
t
HIGH
t
0
0.9
HD:DAT
Data Setup Time
t
100
SU:DAT
START Set-Up Time
SDA and SCL Rise Time
SDA and SCL Fall Time
STOP Set-Up Time
t
0.6
SU:STA
t
(Note 7)
(Note 7)
20 + 0.1C
20 + 0.1C
0.6
300
300
R
B
t
F
B
t
SU:STO
SDA and SCL Capacitive
Loading
C
(Note 7)
400
20
pF
B
EEPROM Write Time
A0, A1 Setup Time
A0, A1 Hold Time
t
(Note 8)
10
5
ms
Fs
Fs
W
t
Before START
After STOP
0.6
0.6
SU:A
HD:A
t
Input Capacitance on A0, A1,
SDA, or SCL
C
10
2
pF
I
Startup time
t
ms
ST
����������������������������������������������������������������� ꢀMaxim Integrated Productsꢀ ꢀ 4
DS3911
Temperature-Controlled, Nonvolatile,
2
I C Quad DAC
NONVOLATILEꢀMEMORYꢀCHARACTERISTICS
(V
= +2.8V to +5.5V, unless otherwise noted.)
CC
PARAMETER
EEPROM Write Cycles (Note 9)
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
T
T
= +85NC
= +25NC
10,000
50,000
A
A
Writes
Noteꢀ1:ꢀ All voltages are referenced to ground. Currents entering the device are specified as positive, and currents exiting the
device are specified as negative.
Noteꢀ2:ꢀ I
Noteꢀ3:ꢀ This is the minimum V
Noteꢀ4:ꢀ This is the time from V
Noteꢀ5:ꢀ Guaranteed by design.
is specified with SCL = SDA = V , and EN bit = 1. Typical values are at V
= 3.3V and T = +25NC.
CC
CC
CC A
voltage that causes NV memory to be recalled.
CC
> V
until initial memory recall is complete.
CC
POR
2
2
Noteꢀ6:ꢀ I C interface timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I C stan-
dard-mode timing.
Noteꢀ7:ꢀ C = total capacitance of one bus line in pF.
B
Noteꢀ8:ꢀ EEPROM write time begins after a STOP condition occurs.
Noteꢀ9:ꢀ Guaranteed by characterization.
SDA
t
BUF
t
F
t
SP
t
HD:STA
t
LOW
SCL
t
HIGH
t
SU:STA
t
t
R
HD:STA
t
SU:STO
t
t
SU:DAT
HD:DAT
STOP
START
REPEATED
START
NOTE: TIMING IS REFERENCED TO V
AND V
.
IH(MIN)
IL(MAX)
2
Figure 1. I C Timing Diagram
����������������������������������������������������������������� ꢀMaxim Integrated Productsꢀ ꢀ 5
DS3911
Temperature-Controlled, Nonvolatile,
2
I C Quad DAC
Typical Operating Characteristics
(T = +25°C, unless otherwise noted.)
A
SUPPLY CURRENT vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. TEMPERATURE
INL vs. OUTPUT CODE (VOLTAGE OUTPUT FILTER)
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.5
0.4
0.3
0.2
V
= 3.3V
T = +25°C
A
0.1
DD
0
-0.1
-0.2
-0.3
-0.4
-0.5
2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4
-40 -20
0
20 40 60 80 100 120
TEMPERATURE (°C)
0
200
400
600
800
1000
V
(V)
DAC VALUE
DD
FILTERED DAC0 VOLTAGE VARIATION FROM IDEAL
vs. DAC2 CODE SWEEP
DAC1 DEVIATION FROM AVERAGE CURRENT
vs. DAC3 CODE SWEEP
INL vs. OUTPUT CODE
(CURRENT SINK FILTER)
(BOTH VOLTAGE OUTPUT FILTERS)
(BOTH CURRENT SINK FILTERS)
14
12
10
8
6
4
1200
600
1000
800
400
200
0
600
DAC1 VALUE = 0000h
400
200
DAC0 VALUE = 0000h
DAC0 VALUE = FFC0h
2
0
0
-2
-4
-6
-8
-10
-12
-14
-200
-400
-600
-800
-1000
-1200
-200
-400
-600
DAC0 VALUE = 8000h
DAC1 VALUE = FFC0h
DAC0 VALUE = 8000h
0
200
400
600
800
1000
0
200
400
600
800
1000
0
200
400
600
800
1000
DAC VALUE
DAC2 VALUE
DAC3 VALUE
V
REF
CURRENT vs. DAC0 CODE SWEEP
(VOLTAGE OUTPUT FILTER)
V
REF
CURRENT vs. DAC1 CODE SWEEP
(CURRENT SINK FILTER)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
200
400
600
800
1000
0
200
400
600
800
1000
DAC0 VALUE
DAC1 VALUE
����������������������������������������������������������������� ꢀMaxim Integrated Productsꢀ ꢀ 6
DS3911
Temperature-Controlled, Nonvolatile,
2
I C Quad DAC
Multiple Device Connection Diagram
3.3V
R
PU
DS3911
DS3911
SDA
SCL
SDA
2
I C
SCL
MASTER
2
2
TEMP
SENSOR
TEMP
SENSOR
I C
I C
3.3V
SLAVE
SLAVE
A1
A0
A1
A0
2
2
I C
I C
ADDRESS
ADDRESS
3.3V
V
V
CC
CC
3.3V
0.1µF
0.1µF
EEPROM
LUT LUT
EEPROM
LUT
LUT
LUT
LUT
LUT
LUT
63Ω
V
REF
V
REF
2.5V
10-BIT
DAC
10-BIT
DAC
10-BIT
DAC
10-BIT
DAC
10-BIT
DAC
10-BIT
DAC
10-BIT
DAC
10-BIT
DAC
LASER
DRIVER
LASER
DRIVER
LASER
DRIVER
LASER
DRIVER
����������������������������������������������������������������� ꢀMaxim Integrated Productsꢀ ꢀ 7
DS3911
Temperature-Controlled, Nonvolatile,
2
I C Quad DAC
Pin Configuration
TOP VIEW
DAC0
DAC1
1
2
3
4
5
6
7
14
V
CC
+
13 SCL
12 SDA
11 A0
10 A1
V
REF
GND
DAC2
DAC3
N.C.
DS3911
9
8
GND
N.C.
EP
TDFN
(3mm x 5mm)
Pin Description
PIN
1
NAME
DAC0
DAC1
TYPE
Output
Output
Input
Supply
Output
Output
—
FUNCTION
Delta-Sigma DAC Output
Delta-Sigma DAC Output
DAC Reference Voltage Input
Ground
2
3
V
REF
4
GND
DAC2
DAC3
N.C.
GND
A1
5
Delta-Sigma DAC Output
Delta-Sigma DAC Output
No Internal Connection
Ground
6
7, 8
9
Supply
Input
Input
I/O
2
10
11
12
13
14
—
I C Slave Address Input
2
A0
I C Slave Address Input
SDA
SCL
2-Wire Serial Data
2-Wire Clock
Input
Supply
—
V
Positive Supply
CC
EP
Exposed Pad. Connect to ground.
����������������������������������������������������������������� ꢀMaxim Integrated Productsꢀ ꢀ 8
DS3911
Temperature-Controlled, Nonvolatile,
2
I C Quad DAC
Delta-Sigma DAC Output and Control
Four delta-sigma DAC outputs are provided, DAC0 to
Detailed Description
The DS3911 operates in one of two modes: lookup table
DAC3. With the addition of an external RC filter, these
outputs provide four 10-bit resolution-analog outputs
(LUT) mode or digital-to-analog converter (DAC) mode.
In LUT mode, the DAC’s output is controlled as a func-
tion of the temperature measured by the device’s internal
temperature sensor and the pulse-density modulation
profile stored in the associated DAC’s LUT. In DAC mode,
the DAC’s output is controlled by the specific DAC’s DAC
VALUE register (DAC0 VALUE, DAC1 VALUE, DAC2
with the full-scale range set by the input V
pin. Each
REF
output is either manually controlled or controlled using a
temperature-indexed LUT. A delta-sigma converter pro-
duces a digital output using pulse-density modulation.
It provides much lower output ripple than a standard
digital PWM output, given the same clock rate and filter
components.
2
VALUE, and DAC3 VALUE) using the I C interface.
Detailed descriptions of these modes as well as additional
device features are discussed in subsequent sections.
Figure 2 shows two recommended filters. These external
RC filter components are chosen to greatly reduce the
output ripple while maintaining the desired response
time. Using resistors smaller than the recommended val-
ues can degrade the output accuracy.
1kΩ
1kΩ
0.1µF
DAC
DAC
VOLTAGE OUTPUT
0.1µF
The device’s delta-sigma outputs are 10 bits. For illus-
trative purposes, a 3-bit example is provided. Figure 3
shows each possible output of this 3-bit delta-sigma DAC.
DS3911
The reference input voltage, V , is the supply voltage
REF
1kΩ
1kΩ
0.1µF
for the output buffer of all DACs. The power supply con-
nected to V must be able to support the edge-rate
CURRENT SINK
REF
0.1µF
2kΩ
requirements of the delta-sigma outputs. In a typical
application, a 0.1FF capacitor should be connected
DS3911
between the V
and GND pins.
REF
Figure 2. Recommended RC Filter for DAC Outputs
0
1
2
3
4
5
6
7
DAC OUPUT
Figure 3. 3-Bit (8-Position) Delta-Sigma Example
����������������������������������������������������������������� ꢀMaxim Integrated Productsꢀ ꢀ 9
DS3911
Temperature-Controlled, Nonvolatile,
2
I C Quad DAC
DAC Power-On Values
Each 10-bit DAC is controlled directly by the value in its
corresponding DAC VALUE register. Each DAC also has
a DAC POR register that contains the power-on-reset
(POR) value for the associated DAC, along with two con-
trol bits: enable (EN) and polarity (POL). See the Lower
Memory Register Descriptions section for complete lower
memory descriptions.
Lookup Table Mode
The device has four nonvolatile memory tables, one for each
of the four DACs. Each memory table is associated with an
individual DAC as follows: Table 04h (DAC0), Table 05h
(DAC1), Table 06h (DAC2), Table 07h (DAC3), and selected
by setting the table select bits, TS[3:0], in the CTRL regis-
ter. Each DAC memory table consists of a DAC LUT table
(addresses 80h–AFh) (DAC0 LUT, DAC1 LUT, DAC2 LUT,
and DAC3 LUT) and a DAC OFFSET table (addresses
F8h–FFh) (DAC0 OFFSET, DAC1 OFFSET, DAC2 OFFSET,
and DAC3 OFFSET). Because these four memory tables all
share the same address and register mapping, the TS[3:0]
bits must be used to select among them.
The DAC POR (DAC0 POR, DAC1 POR, DAC2 POR, and
DAC3 POR) registers are shadowed EEPROM with func-
tionality controlled by the shadow EEPROM bit (SEE). If
the SEE bit is high, the DAC POR registers function as
SRAM only. If the SEE bit is low, the registers are shad-
owed EEPROM and EEPROM write timing, t , must be
observed.
Each LUT address represents as little as a 2N change
in temperature. Table 1 shows the full temperature-to-
register mapping.
W
On power-up, the initial DAC settings are always trans-
ferred from the DAC POR registers to the corresponding
DAC VALUE registers.
The first DAC OFFSET address corresponds to 32N of
temperature. After this, every 16N of temperature con-
verts into one DAC OFFSET address slot. Table 2 shows
the full temperature-to-register mapping.
Manual Control Mode
On power-up, the device starts performing temperature
conversions and the DAC VALUE register whose corre-
sponding EN bit is set is updated by the LUT controller as
described in the Lookup Table Mode section. Clearing the
The TINDEX register points to a LUT address slot. The
TINDEX register can operate in two modes, as defined
2
by the AEN bit. When the AEN bit is cleared, I C writes
2
to the TINDEX register are enabled, and updates from
the LUT controller are blocked. The register can be used
to force DAC updates to be based on the user-selected
index. The TINDEX register directly addresses the LUT
EN bit enables I C writes to the corresponding DAC VALUE
and disables LUT controller updates. This allows the indi-
vidual DACs whose EN bit is cleared to be controlled by
writing the corresponding DAC VALUE register directly.
Tableꢀ1.ꢀLUTꢀTemperatureꢀMapping
ROW
(HEX)
BYTEꢀ0
BYTEꢀ1
BYTEꢀ2
BYTEꢀ3
BYTEꢀ4
BYTEꢀ5
BYTEꢀ6
BYTEꢀ7
4NCꢀLUTꢀ
-28N
80h
88h
90h
< -36N
-8N
-36N
-4N
-32N
0N
-24N
+8N
-20N
+12N
+44N
-16N
+16N
+48N
-12N
+20N
+52N
+4N
+24N
+28N
+32N
+36N
+40N
2NCꢀLUT
+62N
98h
A0h
A8h
+56N
+72N
+88N
+58N
+74N
+90N
+60N
+76N
+92N
+64N
+80N
+96N
+66N
+82N
+98N
+68N
+84N
+70N
+86N
+78N
+94N
+100N
R +102N
Tableꢀ2.ꢀOffsetꢀTemperatureꢀMapping
ROW
(HEX)
BYTEꢀ0
BYTEꢀ1
BYTEꢀ2
BYTEꢀ3
BYTEꢀ4
BYTEꢀ5
BYTEꢀ6
BYTEꢀ7
F8h
< -8N
-8N
+8N
+24N
+40N
+56N
+72N
R +88N
���������������������������������������������������������������� ꢀMaxim Integrated Productsꢀ ꢀ 10
DS3911
Temperature-Controlled, Nonvolatile,
2
I C Quad DAC
memory locations by dropping TINDEX[7] and forcing
where the DAC[9:0] DAC control value is left-justified in
the 16-bit DAC VALUE register.
it high. When AEN = 0, any address between 80h and
FFh can be addressed. To get known results in the DAC
VALUE register, TINDEX should be kept between 80h
and AFh.
DAC VALUE[15:0] = DAC[9:0] x 64
ExampleꢀCalculationꢀforꢀDAC1:
Assumptions:
The device monitors the internal temperature by repeat-
edly polling the temperature sensor’s result at a rate of
1) Temperature is 43NC.
t
. Each cycle, for the DAC whose corresponding
FRAME
2) DAC1 OFFSET index associated with 43NC is memory
EN bit is set, the device reads the internal temperature
once, and, based on that temperature, calculates the
TINDEX register. The TINDEX value corresponds directly
to the LUT memory address for the given temperature
ranges. The DAC OFFSET address is calculated based
on the TINDEX value so only one pointer is necessary.
These two locations provide the values that eventually
become the 10-bit DAC input, DAC VALUE. This data
that gets loaded into the DAC VALUE register is a math
function of the temperature-indexed LUT value and the
temperature-indexed OFFSET value, as follows:
table location FCh and contains data = 2Ah.
3) DAC1 LUT index associated with 43NC is memory
table location 94h and contains data = 7Bh.
DAC1 = 7Bh + 4 x 2Ah = 123h = 291
DAC1 VALUE = 291 x 64
Note:ꢀLoss of information occurs if the result of the DAC
VALUE math function described above is greater than
10 bits. It is important to set the DAC VALUE and DAC
OFFSET values to ensure this overflow does not occur.
The eight DAC OFFSET registers can be independ-
ently set to achieve any desired temperature coefficient
(tempco) on its associated DAC. Figure 4 demonstrates
DAC[9:0] = LUT Setting + 4 x OFFSET Setting
DAC OFFSET LUTs
DAC OFFSET LUTs
EIGHT REGISTERS PER DAC
EIGHT REGISTERS PER DAC
EACH OFFSET REGISTER CAN BE INDEPENDENTLY
FFh
EACH OFFSET REGISTER CAN BE INDEPENDENTLY SET BETWEEN
0 AND 1020. 1020 = 4 x FFh. THIS EXAMPLE ILLUSTRATES POSITIVE
AND NEGATVE TEMPCO.
1023
767
511
255
0
1023
767
511
255
0
SET BETWEEN 0 AND 1020. 1020 = 4 x FFh. THIS
EXAMPLE ILLUSTRATES POSITIVE TEMPCO.
DAC
LUT
BITS
7:0
FEh
DAC
LUT
BITS
7:0
FDh
FDh
FCh
FEh
DAC
LUT
DAC
LUT
BITS
7:0
FFh
FBh
DAC
LUT
BITS
7:0
DAC
LUT
BITS
7:0
FCh
DAC
LUT
BITS
7:0
FAh
DAC
LUT
BITS
7:0
BITS
7:0
DAC
LUT
BITS
7:0
FBh
DAC
LUT
BITS
7:0
F9h
FAh
DAC
LUT
BITS
7:0
DAC
LUT
BITS
7:0
F9h
F8h
F8h
DAC
LUT
BITS
7:0
DAC
LUT
BITS
7:0
DAC
LUT
BITS
7:0
DAC
LUT
BITS
7:0
OFFSET MEMORY
LOCATIONS FOR
THE GIVEN
TEMPERATURE
-40°C -8°C +8°C +24°C +40°C +56°C +70°C +88°C +104°C
-40°C -8°C +8°C +24°C +40°C +56°C +70°C +88°C +104°C
Figure 4. DAC OFFSET LUT Examples
���������������������������������������������������������������� ꢀMaxim Integrated Productsꢀ ꢀ 11
DS3911
Temperature-Controlled, Nonvolatile,
2
I C Quad DAC
DONETEMP bit located in the CTRL register indicates
whether a temperature conversion has been completed
since the bit was last cleared.
9D
9C
9B
9A
99
98
Supply Voltage Monitoring
The device also features an internal 13-bit supply voltage
DECREASING
TEMPERATURE
(V ) monitor. A left-justified value of the supply voltage
CC
2
measurement can be read over I C at memory address-
es 06h–07h. To calculate the supply voltage, simply
convert the hexadecimal result into decimal and then
multiply it by the LSB as shown in the Analog Voltage
Monitoring Characteristics electrical specifications table.
The DONEVCC bit located in the CTRL register indicates
INCREASING
TEMPERATURE
1°C HYSTERESIS
WINDOW
whether a V
bit was last cleared.
conversion has been completed since the
CC
56
58
60
62
64
66
TEMPERATURE (°C)
Slave Address Byte and Address Pins
The slave address byte consists of a 7-bit slave address
plus a R/W bit, as shown in Figure 6. The device’s slave
address is determined by the state of the A0 and A1
address pins. These pins allow up to four devices to
reside on the same I C bus. Address pins connected to
GND result in a 0 in the corresponding bit position in the
slave address. Conversely, address pins connected to
Figure 5. LUT Hysteresis
LSB
R/W
MSB
2
1
0
1
1
0
A1
A0
SLAVE ADDRESS*
READ/WRITE BIT
V
result in a 1 in the corresponding bit positions. For
CC
example, the device’s slave address byte is B0h when
A0 and A1 are grounded. See the I C Serial Interface
*THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0 AND A1.
2
section for more information.
Figure 6. DS3911 Slave Address Byte
2
I C Serial Interface
how a positive and negative tempco can be achieved by
adjusting DAC OFFSET values. The DACs are updated
after each temperature conversion.
2
I C Definitions
The following terminology is commonly used to describe
I C data transfers. See the timing diagram (Figure 1) and
the I C AC Electrical Characteristics table for additional
2
The LUT features 1NC hysteresis to prevent chatter-
ing if the measured temperature falls on the boundary
between two windows (Figure 5). This 1NC hysteresis is
implemented in the TINDEX register value calculation by
adding 1NC to temperature changes of negative slope.
2
information.
MasterꢀDevice:ꢀThe master device controls the slave
devices on the bus. The master device generates SCL
clock pulses and START and STOP conditions.
Temperature Conversion and
Supply Voltage Monitoring
SlaveꢀDevices: Slave devices send and receive data
at the master’s request.
Temperature Conversion
The device features an internal 12-bit temperature sensor
that can drive the LUT and provide a measurement of the
Busꢀ Idleꢀ orꢀ Notꢀ Busy:ꢀ Time between STOP and
START conditions when both SDA and SCL are inac-
tive and in their logic-high states.
2
ambient temperature over I C by reading the value stored
in memory addresses 04h–05h. The sensor is functional
over the entire operating temperature range, and the results
are stored in signed two’s-complement format with a 1/16NC
resolution. See the Lower Memory, Register 04h–05h: TEMP
VALUE section for the temperature sensor’s bit weights. The
STARTꢀCondition:ꢀA START condition is generated by
the master to initiate a new data transfer with a slave.
Transitioning SDA from high to low while SCL remains
high generates a START condition.
���������������������������������������������������������������� ꢀMaxim Integrated Productsꢀ ꢀ 12
DS3911
Temperature-Controlled, Nonvolatile,
2
I C Quad DAC
STOPꢀ Condition:ꢀ A STOP condition is generated
that are transferred (most significant bit first) from the
slave to the master are read by the master using the bit
read definition, and the master transmits an ACK using
the bit write definition to receive additional data bytes.
The master must NACK the last byte read to terminate
communication so the slave returns control of SDA to
the master.
by the master to end a data transfer with a slave.
Transitioning SDA from low to high while SCL remains
high generates a STOP condition.
Repeatedꢀ STARTꢀ Condition:ꢀ The master can use a
repeated START condition at the end of one data trans-
fer to indicate that it will immediately initiate a new data
transfer following the current one. Repeated STARTs
are commonly used during read operations to identify
a specific memory address to begin a data transfer.
A repeated START condition is issued identically to a
normal START condition.
2
Slaveꢀ Addressꢀ Byte:ꢀ Each slave on the I C bus
responds to a slave address byte sent immediately
following a START condition. The slave address byte
contains the slave address in the most significant 7 bits
and the R/W bit in the least significant bit.
BitꢀWrite:ꢀTransitions of SDA must occur during the low
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL plus the
setup and hold time requirements. Data is shifted into
the device during the rising edge of the SCL.
The device’s slave address is determined by the state
of the A0 and A1 address pins as shown in Figure 6.
Address pins connected to GND result in a 0 in the corre-
sponding bit position in the slave address. Conversely,
address pins connected to V
result in a 1 in the
CC
corresponding bit positions. When the R/W bit is 0
(such as in B0h), the master is indicating it will write
data to the slave. If R/W is set to 1 (B1h in this case),
the master is indicating it wants to read from the slave.
If an incorrect (nonmatching) slave address is written,
the device assumes the master is communicating with
BitꢀRead:ꢀAt the end of a write operation, the master
must release the SDA bus line for the proper amount of
setup time before the next rising edge of SCL during a
bit read. The device shifts out each bit of data on SDA
at the falling edge of the previous SCL pulse and the
data bit is valid at the rising edge of the current SCL
pulse. Remember that the master generates all SCL
clock pulses including when it is reading bits from the
slave.
2
another I C device and ignores the communication
until the next START condition is sent.
2
MemoryꢀAddress:ꢀDuring an I C write operation to the
device, the master must transmit a memory address to
identify the memory location where the slave is to store
the data. The memory address is always the second
byte transmitted during a write operation following the
slave address byte.
Acknowledgeꢀ (ACKꢀ andꢀ NACK):ꢀ An acknowledge
(ACK) or not-acknowledge (NACK) is always the 9th bit
transmitted during a byte transfer. The device receiv-
ing data (the master during a read or the slave during
a write operation) performs an ACK by transmitting a
zero during the 9th bit. A device performs a NACK by
transmitting a one (done by releasing SDA) during the
9th bit. Timing for the ACK and NACK is identical to all
other bit writes. An ACK is the acknowledgment that
the device is properly receiving data (see Figure 7). A
NACK is used to terminate a read sequence, or used
as an indication that the device is not receiving data.
2
I C Communication
2
See Figure 7 for I C communication examples.
Writingꢀ aꢀ Singleꢀ Byteꢀ toꢀ aꢀ Slave:ꢀ The master must
generate a START condition, write the slave address
byte (R/W = 0), write the memory address, write the
byte of data, and generate a STOP condition. The mas-
ter must read the slave’s acknowledgement during all
byte write operations.
ByteꢀWrite: A byte write consists of 8 bits of informa-
tion transferred from the master to the slave (most sig-
nificant bit first) plus a 1-bit acknowledgment from the
slave to the master. The 8 bits transmitted by the mas-
ter are done according to the bit write definition and the
acknowledgment is read using the bit read definition.
When writing to the device, the DAC’s output adjusts
to the new setting once it has acknowledged the new
data that is being written, and writes to the EEPROM
are written following the STOP condition at the end of
the write command.
ByteꢀRead:ꢀA byte read is an 8-bit information transfer
from the slave to the master plus a 1-bit ACK or NACK
from the master to the slave. The 8 bits of information
2
Writingꢀ Multipleꢀ Bytesꢀ toꢀ aꢀ Slave: I C write opera-
tions of multiple bytes can also be performed. During
a single write sequence, up to 8 bytes in one page
���������������������������������������������������������������� ꢀMaxim Integrated Productsꢀ ꢀ 13
DS3911
Temperature-Controlled, Nonvolatile,
2
I C Quad DAC
can be written at one time. If more than 8 bytes are
with a NACK to indicate the end of the transfer, and
generates a STOP condition. However, since requiring
the master to keep track of the memory address coun-
ter is impractical, the next method should be used to
perform reads from a specified memory location.
transmitted in the sequence, only the last 8 transmit-
ted bytes are stored. After the last physical memory
location in a particular page (8-byte page write), the
address counter automatically wraps back to the first
location in the same page for subsequent byte write
operations.
Manipulatingꢀ theꢀ Addressꢀ Counterꢀ forꢀ Reads: A
dummy write cycle can be used to force the address
counter to a particular value. To do this, the master
generates a START condition, writes the slave address
byte (R/W = 0), writes the memory address where it
desires to read, generates a repeated START condi-
tion, writes the slave address byte (R/W = 1), reads
data with ACK or NACK as applicable, and generates
a STOP condition. Recall that the master must NACK
the last byte to inform the slave that no additional bytes
Acknowledgeꢀ Polling: Any time a EEPROM byte is
written, the device requires the EEPROM write time
(t ) after the STOP condition to write the contents of
W
the byte to EEPROM. During the EEPROM write time,
the device does not acknowledge its slave address
because it is busy. It is possible to take advantage
of this phenomenon by repeatedly addressing the
device, which allows communication to continue as
soon as the device is ready. The alternative to acknowl-
2
are to be read. See Figure 7 for I C communication
edge polling is to wait for a maximum period of t to
elapse before attempting to access the device.
examples.
W
Readingꢀ Multipleꢀ Bytesꢀ fromꢀ aꢀ Slave:ꢀ The read
operation can be used to read multiple bytes with a
single transfer. When reading bytes from the slave,
the master simply ACKs the data byte if it desires to
read another byte before terminating the transaction.
After the master reads the last byte, it must NACK to
indicate the end of the transfer and generates a STOP
condition. During a single read sequence of multiple
ReadingꢀaꢀSingleꢀByteꢀfromꢀaꢀSlave:ꢀUnlike the write
operation that uses the specified memory address
byte to define where the data is to be written, the read
operation occurs at the present value of the memory
address counter. To read a single byte from the slave,
the master generates a START condition, writes the
slave address byte with R/W = 1, reads the data byte
2
TYPICAL I C WRITE TRANSACTION
MSB
1
LSB
MSB
LSB
MSB
LSB
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
START
0
1
1
0
A1 A0 R/W
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
STOP
SLAVE
ADDRESS*
READ/
WRITE
REGISTER ADDRESS
DATA
*THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0 AND A1.
2
EXAMPLE I C TRANSACTIONS WITH B0h AS THE DEVICE ADDRESS (WHEN A0 AND A1 ARE CONNECTED TO GND)
B0h
00h
DATA
A) SINGLE-BYTE WRITE
-WRITE CONTROL REGISTER (00h)
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
START 1 0 1 1 0 0 0 0
0 0 0 0 0 0 0 0
DATA INTO 00h
STOP
B0h
01h
B1h
DATA
B) SINGLE-BYTE READ
-READ MODE REGISTER (01h)
SLAVE
ACK
SLAVE
ACK
REPEATED
START
SLAVE
ACK
MASTER
NACK
START 1 0 1 1 0 0 0 0
0 0 0 0 0 0 0 1
1 0 1 1 0 0 0 1
DATA IN 01h
STOP
B0h
80h
DATA
DATA
C) 2-BYTE WRITE
-WRITE LUT VALUES FOR REGISTERS
(80h−81h)
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
START 1 0 1 1 0 0 0 0
1 0 0 0 0 0 0 0
DATA INTO 80h
DATA INTO 81h
STOP
B0h
04h
B1h
DATA
DATA IN 04h
DATA
DATA IN 05h
D) 2-BYTE READ
-READ TEMPERATURE REGISTER
(04h−05h)
SLAVE
ACK
SLAVE
ACK
REPEATED
START
SLAVE
ACK
MASTER
ACK
MASTER
NACK
START 1 0 1 1 0 0 0 0
0 0 0 0 0 1 0 0
1 0 1 1 0 0 0 1
STOP
2
Figure 7. I C Communication Examples
���������������������������������������������������������������� ꢀMaxim Integrated Productsꢀ ꢀ 14
DS3911
Temperature-Controlled, Nonvolatile,
2
I C Quad DAC
bytes, after the last address counter position of FFh
The LowerꢀMemory is addressed from 00h–7Fh. Lower
Memory contains temperature reading, V reading,
status bits, control registers, table select bits, and all four
DAC VALUE and DAC POR registers.
is accessed, the address counter automatically wraps
back to the first location, 00h. Read operations can
continue indefinitely.
CC
The UpperꢀMemory consists of the following four memory
2
I C LUT Lockout
tables. The table select bits, TS[3:0], determine which
2
Both the I C port and the LUT controller have access to
the LUTs. To prevent bus/data contention, the LUT con-
troller goes into a wait state instead of accessing the LUT
2
table is currently accessible through I C at memory loca-
tion 80h–FFh.
2
if the I C port is active. Register updates and memory
ꢀ
ꢀ
ꢀ
ꢀ
Tableꢀ04h contains a nonvolatile temperature-indexed
DAC0 LUT and DAC0 OFFSET register designed to
hold the pulse-density modulation profile for DAC0.
access are briefly described below.
• After a voltage or temperature conversion completes
or the TINDEX register is calculated, the results are
loaded into a shadow SRAM for the associated regis-
Tableꢀ05h contains a nonvolatile temperature-indexed
DAC1 LUT and DAC1 OFFSET register designed to
hold the pulse-density modulation profile for DAC1.
2
ter by a backdoor that is not seen by the I C port. The
value is pushed forward to the SRAM cell seen by the
I C port at a later state. It is not pushed if the I C port
is active.
Tableꢀ06h contains a nonvolatile temperature-indexed
DAC2 LUT and DAC2 OFFSET registers designed to
hold the pulse-density modulation profile for DAC2.
2
2
• After TINDEX is calculated and loaded into the shad-
ow SRAM, the LUT controller goes into a round-robin
loop where it updates the VCC VALUE, TEMP VALUE,
and TINDEX registers, reads the DAC OFFSET and
DAC LUT, performs the calculation, and loads the
result into the DAC VALUE register. This process is
where contention could occur. As such, the state
Tableꢀ07h contains a nonvolatile temperature-indexed
DAC3 LUT and DAC3 OFFSET registers designed to
hold the pulse-density modulation profile for DAC3.
Shadowed EEPROM
The DAC POR memory locations are actually shadowed
EEPROM and are controlled by the shadowed EEPROM
bit, SEE. By default, SEE is not set and these locations
act as ordinary EEPROM. By setting SEE these loca-
tions function like SRAM cells, which allow an infinite
number of write cycles without concern of wearing out
the EEPROM. This also eliminates the requirement for
2
2
machine waits until I C is inactive before performing
this process. If the I C port were to become active
for a long time period, the temperature compensation
does not run.
Memory Description
the EEPROM write time, t . Because changes made with
W
SEE enabled do not affect the EEPROM, these changes
are not retained through power cycles. The power-on
value is the last value written with SEE disabled. This
function can be used to speed up calibration and mini-
mize the number of EEPROM write cycles.
The device’s internal memory consists of both volatile
and nonvolatile registers located in Lower Memory and
four separate memory tables (Upper Memory), as shown
in Figure 8.
���������������������������������������������������������������� ꢀMaxim Integrated Productsꢀ ꢀ 15
DS3911
Temperature-Controlled, Nonvolatile,
2
I C Quad DAC
TS[3:0] ARE THE TABLE SELECT BITS. THESE BITS
DETERMINE THE CURRENTLY SELECTED/ADDRESSABLE
UPPER MEMORY TABLE.
00h
02h
04h
06h
08h
10h
CTRL
SRAM
TEMP VALUE
VCC VALUE
EMPTY
MODE
TINDEX
NOTE: TABLES 00h–03h AND 08h–0Fh DO NOT EXIST.
LOWER
MEMORY
DAC VALUES
(8 BYTES)
17h
78h
EMPTY
TS[3:0] = 0100b
TABLE 04h
TS[3:0] = 0101b
TABLE 05h
TS[3:0] = 0110b
TABLE 06h
TS[3:0] = 0111b
TABLE 07h
DAC POR
(8 BYTES)
7Fh
80h
DAC0
LUT
DAC1
LUT
DAC2
LUT
DAC3
LUT
(48 BYTES)
(48 BYTES)
(48 BYTES)
(48 BYTES)
UPPER
MEMORY
(TABLES)
AFh
EMPTY
EMPTY
EMPTY
EMPTY
F8h
FFh
DAC0 OFFSET
(8 BYTES)
DAC1 OFFSET
(8 BYTES)
DAC2 OFFSET
(8 BYTES)
DAC3 OFFSET
(8 BYTES)
Figure 8. Memory Map
���������������������������������������������������������������� ꢀMaxim Integrated Productsꢀ ꢀ 16
DS3911
Temperature-Controlled, Nonvolatile,
2
I C Quad DAC
Register Description
This register map shows each byte/word (2-byte) in terms of its row and byte/word placement in the memory. The first
byte in the row is located in memory at the row address (hexadecimal) in the leftmost column. Each subsequent byte/
word on the row is one/two memory locations beyond the previous byte/word’s address. A total of 8 bytes are present
on each row. See the Lower Memory Register Descriptions section for more information about each of these bytes.
Lower Memory Register Map
LOWERꢀMEMORY
WORDꢀ0
WORDꢀ1
WORDꢀ2
BYTEꢀ4 BYTEꢀ5
WORDꢀ3
BYTEꢀ6 BYTEꢀ7
ADDR
(HEX)
BYTEꢀ0
CTRL
BYTEꢀ1
BYTEꢀ2
SRAM
BYTEꢀ3
00h
08h
10h
78h
MODE
TINDEX
TEMP VALUE
VCC VALUE
—
DAC3 VALUE
DAC3 POR
DAC2 VALUE
DAC2 POR
DAC1 VALUE
DAC1 POR
DAC0 VALUE
DAC0 POR
Lower Memory Register Descriptions
LowerꢀMemory,ꢀRegisterꢀ00h:ꢀCTRL
POWER-ON VALUE
ACCESS
00h
R/W
MEMORY TYPE
Volatile
00h
DONETEMP
BIT 7
DONEVCC
SRAM
SRAM
TS3
TS2
TS1
TS0
BIT 0
DONETEMP: Done Temp Status
0 = Temperature conversion in progress.
1 = Temperature conversion completed since this bit was last cleared.
BIT 7
DONEVCC: Done V Status
CC
BIT 6
0 = V
1 = V
conversion in progress.
conversion completed since this bit was last cleared.
CC
CC
BITS 5:4
SRAM: General-Purpose SRAM. These bits have no affect on device operation.
TS[3:0]: Table Select. The device’s memory tables are accessed by writing the desired table
value in this bit field. The device only contains four addressable memory tables, 04h–07h, and
therefore the values listed below are the only usable options.
TS[3:0]
0100b
0101b
0110b
0111b
TABLEꢀSELECTED
CORRESPONDINGꢀDACꢀLUT
BITS 3:0
04h
05h
06h
07h
0
1
2
3
���������������������������������������������������������������� ꢀMaxim Integrated Productsꢀ ꢀ 17
DS3911
Temperature-Controlled, Nonvolatile,
2
I C Quad DAC
LowerꢀMemory,ꢀRegisterꢀ01h:ꢀMODE
POWER-ON VALUE
40h
ACCESS
R/W
MEMORY TYPE
Volatile
01h
AEN
SRAM
SRAM
SRAM
SRAM
SRAM
SOFTTXD
BIT 0
SEE
BIT 7
SEE: Shadowed EEPROM Disable
0 = Enables EEPROM writes to the shadowed EEPROM bytes.
1 = Disables EEPROM writes to shadowed EPPROM bytes during configuration, so that the
configuration of the device is not delayed by the EEPROM cycle time. Once the values are known,
write this bit to a 0 and write the shadowed EEPROM locations again for data to be written to the
EEPROM.
BIT 7
AEN: Automatic Enable
0 = The temperature-calculated index value TINDEX is writable by the user and the automatic
updates of calculated indexes are disabled. This allows users to interactively test their modules by
controlling the indexing for the LUTs. The recalled values from the LUTs appear in the DAC VALUE
registers after the next completion of a temperature conversion.
BIT 6
BITS 5:1
BIT 0
1 = The internal temperature sensor determines the value of TINDEX.
SRAM: General-Purpose SRAM. These bits have no affect on device operation.
SOFTTXD:ꢀSoft Transmit Disable
0 = DACs operate normally.
1 = The DAC outputs are forced to the bit value of the POL bit, which is located in the DAC’s
associate DAC POR register.
For example, when SOFTTXD is set and POL = 1 in the DAC0 POR register, DAC0 is forced to full-
scale output, but if POL = 0, DAC0 is forced to a zero output. This applies to all four DACs.
LowerꢀMemory,ꢀRegisterꢀ02h:ꢀSRAM
POWER-ON VALUE
ACCESS
00h
R/W
MEMORY TYPE
Volatile
02h
SRAM
BIT 7
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
BIT 0
These general-purpose SRAM bits have no affect on device operation.
���������������������������������������������������������������� ꢀMaxim Integrated Productsꢀ ꢀ 18
DS3911
Temperature-Controlled, Nonvolatile,
2
I C Quad DAC
LowerꢀMemory,ꢀRegisterꢀ03h:ꢀTINDEX
POWER-ON VALUE
00h
ACCESS
When AEN = 1: R
When AEN = 0: R/W
Volatile
ACCESS
MEMORY TYPE
7
6
5
4
3
2
1
0
03h
2
2
2
2
2
2
2
2
BIT 7
BIT 0
The TINDEX register is the temperature indexed address pointer. The TINDEX value corresponds directly to the
LUT memory address for the given temperature ranges. The DAC OFFSET address is calculated based on the
TINDEX value, so only one pointer is necessary.
The pointer value is calculated based on the current temperature reading (see the below equation). The calculation
uses different math depending on which LUT range (2NC or 4NC) the current temperature measurement resides in.
Temperature + 40
Temperature − 8
TINDEX =
+128 =
+128
temp<56
temp≥56
4
2
A 1NC hysteresis is implemented in the TINDEX value calculation by adding 1NC to temperature changes of nega-
tive slope.
When the AEN bit is high, the TINDEX register is read-only and the pointer is updated after the temperature and
2
voltage conversions have completed. When the AEN bit is cleared, I C writes to the TINDEX register are enabled
and updates from the LUT controller are blocked. The register can be used to force DAC updates to be based
on the user-selected index. The TINDEX register directly addresses the LUT memory locations by dropping
TINDEX[7] and forcing it high. When AEN = 0, any address between 80h and FFh can be addressed. To obtain
known results in the DAC VALUE register, TINDEX should be kept between 80h and AFh.
TINDEX value is clamped for temperatures below -40NC and above 102NC.
LowerꢀMemory,ꢀRegisterꢀ04h–05h:ꢀTEMPꢀVALUE
POWER-ON VALUE
ACCESS
0000h
R
MEMORY TYPE
Volatile
6
5
4
3
2
1
0
04h
05h
S
2
2
2
2
2
2
2
-1
-2
-3
-4
2
2
2
2
0
0
0
0
BIT 7
BIT 0
Left-justified signed two’s complement direct-to-temperature measurement. The lower 4 bits always return zero.
The temperature reading is clamped to -128NC and +127.9375NC.
���������������������������������������������������������������� ꢀMaxim Integrated Productsꢀ ꢀ 19
DS3911
Temperature-Controlled, Nonvolatile,
2
I C Quad DAC
LowerꢀMemory,ꢀRegisterꢀ06h–07h:ꢀVCCꢀVALUE
POWER-ON VALUE
ACCESS
0000h
R
MEMORY TYPE
Volatile
12
2
11
3
10
2
9
1
8
0
7
6
5
06h
07h
2
2
2
2
2
2
2
2
2
4
2
2
2
0
0
0
BIT 7
BIT 0
Left-justified unsigned voltage measurement. To calculate the supply voltage, simply convert the hexadecimal
result into decimal and then multiply it by the LSB as shown in the Analog Voltage Monitoring Characteristics
electrical characteristics table. The lower 3 bits always return zero.
LowerꢀMemory,ꢀRegisterꢀ10h–11h:ꢀDAC3ꢀVALUE
LowerꢀMemory,ꢀRegisterꢀ12h–13h:ꢀDAC2ꢀVALUE
LowerꢀMemory,ꢀRegisterꢀ14h–15h:ꢀDAC1ꢀVALUE
LowerꢀMemory,ꢀRegisterꢀ16h–17h:ꢀDAC0ꢀVALUE
POWER-ON VALUE
ACCESS
0000h
When EN = 1: R
When EN = 0: R/W
Volatile
ACCESS
MEMORY TYPE
10h, 12h,
14h, 16h
9
8
0
7
6
5
4
3
2
2
2
2
2
2
2
2
2
2
11h, 13h,
15h, 17h
1
2
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
BIT 0
BIT 7
These registers are the left- justified digital 10-bit value used for their associated DAC output. The lower 6 bits
have no effect on device operation. At POR these registers are updated to the EEPROM value DAC POR. When
the EN bit in DAC POR is set, this register is updated at the end of each temperature conversion, with the calcu-
lated result of values recalled from LUT and OFFSET LUT pointed to by TINDEX.
V
REF
V
=
×DAC VALUE
DAC
1024
���������������������������������������������������������������� ꢀMaxim Integrated Productsꢀ ꢀ 20
DS3911
Temperature-Controlled, Nonvolatile,
2
I C Quad DAC
LowerꢀMemory,ꢀRegisterꢀ78h–79h:ꢀDAC3ꢀPOR
LowerꢀMemory,ꢀRegisterꢀ7Ah–7Bh:ꢀDAC2ꢀPOR
LowerꢀMemory,ꢀRegisterꢀ7Ch–7Dh:ꢀDAC1ꢀPOR
LowerꢀMemory,ꢀRegisterꢀ7Eh–7Fh:ꢀDAC0ꢀPOR
POWER-ON VALUE
ACCESS
Recalled from EEPROM
R/W
MEMORY TYPE
Nonvolatile (SEE)
78h, 7Ah,
7Ch, 7Eh
9
8
0
7
6
5
4
3
2
2
2
2
2
2
2
2
2
2
79h, 7Bh,
7Dh, 7Fh
1
2
SEE
SEE
SEE
SEE
POL
EN
BIT 7
BIT 0
A left-justified, digital, 10-bit initial DAC value. During a POR these 10 bits are used to fill the
corresponding DAC VALUE register.
BITS 15:6
BITS 5:2
SEE: These bits have no effect on device operation.
POL: Polarity Select
BIT 1
0 = Normal DAC mode, DAC VALUE = 3FFh results in full-scale output.
1 = Inverted DAC mode, DAC VALUE = 3FFh results in zero output.
EN:ꢀLUT Enable
0 = DAC mode: At power-on, the corresponding DAC VALUE register is loaded with the value
stored in the corresponding DAC POR register. Updates from the temperature-referenced LUT
and LUT OFFSET are disabled. The user can write to the DAC VALUE register to set the value for
the DAC. The DAC VALUE register is R/W.
BIT 0
1 = LUT mode: At power-on, the corresponding DAC VALUE register is loaded with the value
stored in the corresponding DAC POR register. After the first valid temperature conversion, the
DAC VALUE register is loaded with the value calculated from the LUT and LUT OFFSET that
correspond to the measured temperature. The DAC VALUE register is read-only.
���������������������������������������������������������������� ꢀMaxim Integrated Productsꢀ ꢀ 21
DS3911
Temperature-Controlled, Nonvolatile,
2
I C Quad DAC
Upper Memory Register Descriptions
Tableꢀ04h,ꢀRegisterꢀ80h–AFh:ꢀDAC0ꢀLUT
Tableꢀ05h,ꢀRegisterꢀ80h–AFh:ꢀDAC1ꢀLUT
Tableꢀ06h,ꢀRegisterꢀ80h–AFh:ꢀDAC2ꢀLUT
Tableꢀ07h,ꢀRegisterꢀ80h–AFh:ꢀDAC3ꢀLUT
FACTORY DEFAULT
ACCESS
00h
R/W
MEMORY TYPE
Nonvolatile
7
6
5
4
3
2
1
0
80h–AFh
2
2
2
2
2
2
2
2
BIT 7
BIT 0
The DAC LUT is a set of registers assigned to hold the pulse-density modulation profile for the associated DAC.
The values in this table are added to four times the corresponding value in the DAC OFFSET table to determine
the set point for the associated DAC. In all four DAC tables, the DAC LUT registers are formatted the same.
Beginning at -40NC, the LUT increments in 4NC steps per address until the temperature reaches 56NC, then it
increments in 2NC steps until it clamps at 102NC. See the LUT Temperature Mapping table for full register-to-
temperature mapping. Register 80h defines the -40NC to -36NC DAC LUT value, register 81h defines the -36NC to
-32NC DAC LUT value, and so on.
LUTꢀTEMPERATUREꢀMAPPING
ROW
(HEX)
BYTEꢀ0
BYTEꢀ1
BYTEꢀ2
BYTEꢀ3
BYTEꢀ4
BYTEꢀ5
BYTEꢀ6
BYTEꢀ7
4NCꢀLUTꢀ
-28N
80h
88h
90h
< -36N
-8N
-36N
-4N
-32N
0N
-24N
+8N
-20N
+12N
+44N
-16N
+16N
+48N
-12N
+20N
+52N
+4N
+24N
+28N
+32N
+36N
+40N
2NCꢀLUT
+62N
98h
A0h
A8h
+56N
+72N
+88N
+58N
+74N
+90N
+60N
+76N
+92N
+64N
+80N
+96N
+66N
+82N
+98N
+68N
+84N
+70N
+86N
+78N
+94N
+100N
R +102N
���������������������������������������������������������������� ꢀMaxim Integrated Productsꢀ ꢀ 22
DS3911
Temperature-Controlled, Nonvolatile,
2
I C Quad DAC
Tableꢀ04h,ꢀRegisterꢀF8h–FFh:ꢀDAC0ꢀOFFSET
Tableꢀ05h,ꢀRegisterꢀF8h–FFh:ꢀDAC1ꢀOFFSET
Tableꢀ06h,ꢀRegisterꢀF8h–FFh:ꢀDAC2ꢀOFFSET
Tableꢀ07h,ꢀRegisterꢀF8h–FFh:ꢀDAC3ꢀOFFSET
FACTORY DEFAULT
ACCESS
00h
R/W
MEMORY TYPE
Nonvolatile
7
6
5
4
3
2
1
0
F8h–FFh
2
2
2
2
2
2
2
2
BIT 7
BIT 0
The DAC OFFSET is a set of registers assigned to hold the pulse-density modulation profile for the associated DAC.
The values in this table are multiplied by four and added to the corresponding value in the LUT table to determine
the set point for the associated DAC. In all four DAC tables, the DAC OFFSET registers are formatted the same. The
OFFSET registers increase in 16NC steps from -8NC to +88NC. Below -8NC the DAC OFFSET is indexed at 0xF8. See
the Offset Temperature Mapping table for full register to temperature mapping. Register F8h defines the -40NC to
-8NC DAC OFFSET value, register F9h defines the -8NC to +8NC DAC OFFSET value, and so on.
OFFSETꢀTEMPERATUREꢀMAPPING
ROW
(HEX)
BYTEꢀ0
BYTEꢀ1
BYTEꢀ2
BYTEꢀ3
BYTEꢀ4
BYTEꢀ5
BYTEꢀ6
BYTEꢀ7
F8h
< -8N
-8N
+8N
+24N
+40N
+56N
+72N
R +88N
SDA and SCL Pullup Resistors
Applications Information
SDA is an I/O with an open-collector output that requires
a pullup resistor to realize high-logic levels. A master
using either an open-collector output with a pullup resis-
tor or a push-pull output driver can be used for SCL.
Pullup resistor values should be chosen to ensure that
Power-Supply Decoupling
To achieve the best results when using the DS3911,
decouple the power supply with a 0.01FF or 0.1FF capac-
itor. Use a high-quality ceramic surface-mount capacitor
if possible. Surface-mount components minimize lead
inductance, which improves performance, and ceram-
ic capacitors tend to have adequate high-frequency
response for decoupling applications. Likewise, a decou-
2
the rise and fall times listed in the I C AC Electrical
Characteristics table are within specification. A typical
value for the pullup resistors is 4.7kI.
pling capacitor should be placed from V
to GND.
REF
���������������������������������������������������������������� ꢀMaxim Integrated Productsꢀ ꢀ 23
DS3911
Temperature-Controlled, Nonvolatile,
2
I C Quad DAC
Ordering Information
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PART
DS3911T+
DS3911T+T
TEMPꢀRANGE
-40NC to +100NC
-40NC to +100NC
PIN-PACKAGE
14 TDFN-EP*
14 TDFN-EP*
Note: Contact the factory about CSBGA version availability.
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
PACKAGEꢀ
TYPE
PACKAGEꢀ
CODE
OUTLINEꢀ
NO.
LANDꢀ
PATTERNꢀNO.
*EP = Exposed pad.
14 TDFN-EP
T1435N+1
21-0253
90-0246
DS3911
Temperature-Controlled, Nonvolatile,
2
I C Quad DAC
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
0
6/11
Initial release
—
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical
Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
24
©
2011 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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