DS32503N [MAXIM]
PCM Transceiver, 1-Func, PBGA144, 13 X 13 MM, 1 MM PITCH, CSBGA-144;型号: | DS32503N |
厂家: | MAXIM INTEGRATED PRODUCTS |
描述: | PCM Transceiver, 1-Func, PBGA144, 13 X 13 MM, 1 MM PITCH, CSBGA-144 PC 电信 电信集成电路 |
文件: | 总124页 (文件大小:1238K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PRELIMINARY
a
DS32501/DS32502/DS32503/DS32504
Single-/Dual-/Triple-/Quad-Port
DS3/E3/STS-1 LIUs
www.maxim-ic.com
GENERAL DESCRIPTION
FEATURES
ꢀ
Pin-Compatible Family of Products
The DS32501 (single), DS32502 (dual), DS32503
(triple), and DS32504 (quad) line interface units ꢀ Each Port Independently Configurable
(LIUs) are highly integrated, low-power, feature-rich
ꢀ
Receive Clock and Data Recovery for Up to
457 meters (1500 feet) of 75Ω Coaxial Cable
Standards-Compliant Transmit Waveshaping
Uses 1:1 Transformers on Both Tx and Rx
LIUs for DS3, E3, and STS-1 applications. Each LIU
port in these devices has independent receive and
transmit paths, a jitter attenuator, a full-featured
pattern generator and detector, performance
ꢀ
ꢀ
ꢀ
Three Control Interface Options: 8/16-Bit
Parallel, SPI, and Hardware Mode
monitoring counters, and
a
complete set of
loopbacks. An on-chip clock adapter generates all
line-rate clocks from a single input clock. Ports are
independently software configurable for DS3, E3, and
STS-1 and can be individually powered down.
Control interface options include 8-bit parallel, SPI,
and hardware mode.
ꢀ
Jitter Attenuators (One Per Port) Can be
Placed in the Receive Path or the Transmit
Path
ꢀ
ꢀ
Jitter Attenuators Have Provisionable Buffer
Depth: 16, 32, 64, or 128 Bits
Built-In Clock Adapter Generates All Line-
Rate Clocks from a Single Input Clock (DS3,
E3, STS-1, 12.8MHz, 19.44MHz, 38.88MHz,
77.76MHz)
APPLICATIONS
SONET/SDH and PDH
Multiplexers
Digital Cross-Connects
Access Concentrators
PBXs
ATM and Frame Relay
Equipment
ꢀ
ꢀ
Per-Port Programmable Internal Line
Termination Requiring Only External
Transformers
DSLAMs
WAN Routers and
Switches
CSU/DSUs
High-Impedance Tx and Rx, Even When
VDD = 0, Enables Hot-Swappable, 1:1, and 1+1
Board Redundancy Without Relays
ORDERING INFORMATION
ꢀ
ꢀ
Per-Port BERT for PRBS and Repetitive
Pattern Generation and Detection
PART
LIUs TEMP RANGE PIN-PACKAGE
DS32501*
DS32501N*
DS32502*
DS32502N*
DS32503*
DS32503N*
DS32504*
DS32504N*
1
1
2
2
3
3
4
4
0°C to +70°C
-40°C to +85°C 144 TE-CSBGA
0°C to +70°C 144 TE-CSBGA
-40°C to +85°C 144 TE-CSBGA
0°C to +70°C 144 TE-CSBGA
-40°C to +85°C 144 TE-CSBGA
0°C to +70°C 144 TE-CSBGA
-40°C to +85°C 144 TE-CSBGA
144 TE-CSBGA
Tx and Rx Open- and Short-Detection
Circuitry
ꢀ
ꢀ
Transmit Driver Monitor Circuitry
Receive Loss-of-Signal (LOS) Monitoring
Compliant with ANSI T1.231 and ITU G.775
ꢀ
ꢀ
Automatic Data Squelching on Receive LOS
Large Line Code Performance Monitoring
Counters for Accumulation Intervals Up to 1s
Note: Add “+” for the lead-free package option.
*Future product—contact factory for availability.
ꢀ
ꢀ
ꢀ
ꢀ
Local and Remote Loopbacks
Transmit Common Clock Option
Power-Down Capability for Unused Ports
Functional Diagram appears in Section 3 (see
Figure 3-1).
Low-Power 1.8V/3.3V Operation (5V Tolerant
I/O)
ꢀ
ꢀ
ꢀ
Industrial Temperature Range: -40°C to +85°C
Small Package: (13mm)2 144-Pin TE-CSBGA
IEEE 1149.1 JTAG Support
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
1 of 124
REV: 042007
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
TABLE OF CONTENTS
1. ACRONYMS .........................................................................................................................6
2. STANDARDS COMPLIANCE...............................................................................................7
3. DETAILED DESCRIPTION...................................................................................................8
4. APPLICATION EXAMPLE..................................................................................................10
5. BLOCK DIAGRAM .............................................................................................................11
6. FEATURE DETAILS...........................................................................................................12
6.1 GLOBAL FEATURES .......................................................................................................................12
6.2 RECEIVER FEATURES....................................................................................................................12
6.3 TRANSMITTER FEATURES ..............................................................................................................12
6.4 JITTER ATTENUATOR FEATURES ....................................................................................................12
6.5 BIT ERROR RATE TESTER (BERT) FEATURES................................................................................13
6.6 CLOCK ADAPTER FEATURES..........................................................................................................13
6.7 PARALLEL MICROPROCESSOR INTERFACE FEATURES.....................................................................13
6.8 SPI SERIAL MICROPROCESSOR INTERFACE FEATURES ..................................................................13
6.9 MISCELLANEOUS FEATURES..........................................................................................................13
6.10 TEST FEATURES............................................................................................................................13
6.11 LOOPBACK FEATURES...................................................................................................................13
7. CONTROL INTERFACE MODES.......................................................................................14
8. PIN DESCRIPTIONS ..........................................................................................................15
8.1 SHORT PIN DESCRIPTIONS ............................................................................................................15
8.2 DETAILED PIN DESCRIPTIONS ........................................................................................................17
9. FUNCTIONAL DESCRIPTION............................................................................................23
9.1 LIU MODE ....................................................................................................................................23
9.2 TRANSMITTER ...............................................................................................................................23
9.2.1 Transmit Clock .................................................................................................................................... 23
9.2.2 Framer Interface Format and the B3ZS/HDB3 Encoder..................................................................... 23
9.2.3 Error Insertion ..................................................................................................................................... 24
9.2.4 AIS Generation.................................................................................................................................... 24
9.2.5 Waveshaping ...................................................................................................................................... 24
9.2.6 Line Build-Out ..................................................................................................................................... 27
9.2.7 Line Driver........................................................................................................................................... 28
9.2.8 Interfacing to the Line ......................................................................................................................... 28
9.2.9 Driver Monitor and Output Failure Detection ...................................................................................... 28
9.2.10 Power-Down........................................................................................................................................ 28
9.2.11 Jitter Generation (Intrinsic).................................................................................................................. 28
9.2.12 Jitter Transfer...................................................................................................................................... 29
9.3 RECEIVER.....................................................................................................................................29
9.3.1 Interfacing to the Line ......................................................................................................................... 29
9.3.2 Optional Preamp ................................................................................................................................. 29
9.3.3 Automatic Gain Control (AGC) and Adaptive Equalizer ..................................................................... 30
9.3.4 Clock and Data Recovery (CDR)........................................................................................................ 30
9.3.5 Loss-of-Signal (LOS) Detector............................................................................................................ 30
9.3.6 Framer Interface Format and the B3ZS/HDB3 Decoder .................................................................... 31
9.3.7 Power-Down........................................................................................................................................ 32
9.3.8 Input Failure Detection........................................................................................................................ 32
9.3.9 Jitter and Wander Tolerance............................................................................................................... 33
9.3.10 Jitter Transfer...................................................................................................................................... 34
9.4 JITTER ATTENUATOR.....................................................................................................................35
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PRELIMINARY
DS32501/DS32502/DS32503/DS32504
9.5 BERT...........................................................................................................................................36
9.5.1 Configuration and Monitoring.............................................................................................................. 36
9.5.2 Receive Pattern Detection .................................................................................................................. 37
9.5.3 Transmit Pattern Generation............................................................................................................... 39
9.6 LOOPBACKS..................................................................................................................................40
9.7 GLOBAL RESOURCES ....................................................................................................................40
9.7.1 Clock Rate Adapter (CLAD)................................................................................................................ 40
9.7.2 One-Second Reference Generator..................................................................................................... 42
9.7.3 General-Purpose I/O Pins................................................................................................................... 42
9.7.4 Performance Monitor Register Update ............................................................................................... 43
9.7.5 Transmit Manual Error Insertion ......................................................................................................... 43
9.8 8-/16-BIT PARALLEL MICROPROCESSOR INTERFACE ......................................................................44
9.8.1 8-Bit and 16-Bit Bus Widths................................................................................................................ 44
9.8.2 Byte Swap Mode................................................................................................................................. 44
9.8.3 Read-Write and Data Strobe Modes................................................................................................... 44
9.8.4 Multiplexed and Nonmultiplexed Operation........................................................................................ 44
9.8.5 Clear-On-Read and Clear-On-Write Modes ....................................................................................... 44
9.8.6 Global Write Mode .............................................................................................................................. 44
9.9 SPI SERIAL MICROPROCESSOR INTERFACE ...................................................................................45
9.10 INTERRUPT STRUCTURE ................................................................................................................47
9.11 RESET AND POWER-DOWN............................................................................................................48
10. REGISTER MAPS AND DESCRIPTIONS..........................................................................50
10.1 OVERVIEW ....................................................................................................................................50
10.1.1 Status Bits........................................................................................................................................... 50
10.1.2 Configuration Fields............................................................................................................................ 50
10.1.3 Counters.............................................................................................................................................. 50
10.2 OVERALL REGISTER MAP ..............................................................................................................51
10.3 GLOBAL REGISTERS......................................................................................................................52
10.4 PORT COMMON REGISTERS ..........................................................................................................60
10.5 LIU REGISTERS ............................................................................................................................68
10.6 B3ZS/HDB3 ENCODER REGISTERS ..............................................................................................77
10.7 B3ZS/HDB3 DECODER REGISTERS ..............................................................................................79
10.8 BERT REGISTERS ........................................................................................................................84
11. JTAG INFORMATION ........................................................................................................93
12. ELECTRICAL CHARACTERISTICS ..................................................................................94
13. PIN ASSIGNMENTS.........................................................................................................108
14. PACKAGE INFORMATION ..............................................................................................121
14.1 13MM X13MM 144-LEAD TE-CSBGA (56-G6016-001)................................................................121
15. THERMAL INFORMATION...............................................................................................122
16. TRADEMARK ACKNOWLEDGEMENTS.........................................................................123
17. DATA SHEET REVISION HISTORY ................................................................................124
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PRELIMINARY
DS32501/DS32502/DS32503/DS32504
LIST OF FIGURES
Figure 3-1. Functional Diagram ................................................................................................................................... 8
Figure 3-2. External Connections, Internal Termination Enabled................................................................................ 8
Figure 3-3. External Connections, Internal Termination Disabled............................................................................... 9
Figure 4-1. 3-Port Unchannelized DS3/E3 Card ....................................................................................................... 10
Figure 5-1. Block Diagram......................................................................................................................................... 11
Figure 9-1. DS3 Waveform Template........................................................................................................................ 25
Figure 9-2. STS-1 Waveform Template..................................................................................................................... 26
Figure 9-3. E3 Waveform Template........................................................................................................................... 27
Figure 9-4. STS-1 and E3 Jitter Tolerance................................................................................................................ 33
Figure 9-5. DS3 Jitter Tolerance................................................................................................................................ 34
Figure 9-6. DS3 and E3 Wander Tolerance .............................................................................................................. 34
Figure 9-7. Jitter Attenuation/Jitter Transfer.............................................................................................................. 35
Figure 9-8. PRBS Synchronization State Diagram.................................................................................................... 38
Figure 9-9. Repetitive Pattern Synchronization State Diagram................................................................................. 39
Figure 9-10. SPI Clock Polarity and Phase Options.................................................................................................. 46
Figure 9-11. SPI Bus Transactions............................................................................................................................ 46
Figure 9-12. Interrupt Signal Flow ............................................................................................................................. 47
Figure 12-1. Transmitter Framer Interface Timing Diagram...................................................................................... 97
Figure 12-2. Receiver Framer Interface Timing Diagram.......................................................................................... 97
Figure 12-3. Parallel CPU Interface Intel Read Timing Diagram (Nonmultiplexed) ................................................ 101
Figure 12-4. Parallel CPU Interface Intel Write Timing Diagram (Nonmultiplexed) ................................................ 101
Figure 12-5. Parallel CPU Interface Motorola Read Timing Diagram (Nonmultiplexed)......................................... 102
Figure 12-6. Parallel CPU Interface Motorola Write Timing Diagram (Nonmultiplexed) ......................................... 102
Figure 12-7. Parallel CPU Interface Intel Read Timing Diagram (Multiplexed)....................................................... 103
Figure 12-8. Parallel CPU Interface Intel Write Timing Diagram (Multiplexed)....................................................... 103
Figure 12-9. Parallel CPU Interface Motorola Read Timing Diagram (Multiplexed)................................................ 104
Figure 12-10. Parallel CPU Interface Motorola Write Timing Diagram (Multiplexed).............................................. 104
Figure 12-11. SPI Interface Timing Diagram........................................................................................................... 106
Figure 12-12. JTAG Timing Diagram....................................................................................................................... 107
Figure 13-1. DS32504 Pin Assignment—Microprocessor Interface Mode.............................................................. 109
Figure 13-2. DS32504 Pin Assignment—SPI Interface Mode................................................................................. 110
Figure 13-3. DS32504 Pin Assignment—Hardware Mode...................................................................................... 111
Figure 13-4. DS32503 Pin Assignment—Microprocessor Interface Mode.............................................................. 112
Figure 13-5. DS32503 Pin Assignment—SPI Interface Mode................................................................................. 113
Figure 13-6. DS32503 Pin Assignment—Hardware Mode...................................................................................... 114
Figure 13-7. DS32502 Pin Assignment—Microprocessor Interface Mode.............................................................. 115
Figure 13-8. DS32502 Pin Assignment—SPI Interface Mode................................................................................. 116
Figure 13-9. DS32502 Pin Assignment—Hardware Mode...................................................................................... 117
Figure 13-10. DS32501 Pin Assignment—Microprocessor Interface Mode............................................................ 118
Figure 13-11. DS32501 Pin Assignment—SPI Interface Mode............................................................................... 119
Figure 13-12. DS32501 Pin Assignment—Hardware Mode.................................................................................... 120
4 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
LIST OF TABLES
Table 2-1. Applicable Telecommunications Standards ............................................................................................... 7
Table 8-1. Short Pin Descriptions.............................................................................................................................. 15
Table 8-2. Analog Line Interface Pin Descriptions .................................................................................................... 17
Table 8-3. Digital Framer Interface Pin Descriptions................................................................................................. 17
Table 8-4. Global Pin Descriptions ............................................................................................................................ 18
Table 8-5. Hardware Interface Pin Descriptions........................................................................................................ 18
Table 8-6. Parallel Interface Pin Descriptions ........................................................................................................... 20
Table 8-7. SPI Serial Interface Pin Descriptions ....................................................................................................... 21
Table 8-8. CLAD Pin Descriptions............................................................................................................................. 21
Table 8-9. JTAG Pin Descriptions ............................................................................................................................. 22
Table 8-10. Power-Supply Pin Descriptions.............................................................................................................. 22
Table 8-11. Manufacturing Test Pin Descriptions...................................................................................................... 22
Table 9-1. DS3 Waveform Equations ........................................................................................................................ 25
Table 9-2. DS3 Waveform Test Parameters and Limits............................................................................................ 25
Table 9-3. STS-1 Waveform Equations..................................................................................................................... 26
Table 9-4. STS-1 Waveform Test Parameters and Limits......................................................................................... 26
Table 9-5. E3 Waveform Test Parameters and Limits............................................................................................... 27
Table 9-6. Jitter Generation....................................................................................................................................... 28
Table 9-7. Transformer Characteristics..................................................................................................................... 29
Table 9-8. Recommended Transformers................................................................................................................... 29
Table 9-9. Pseudorandom Pattern Generation.......................................................................................................... 36
Table 9-10. Repetitive Pattern Generation................................................................................................................ 36
Table 9-11. CLAD Clock Source Settings ................................................................................................................. 41
Table 9-12. CLAD Clock Pin Output Settings............................................................................................................ 41
Table 9-13. Global One-Second Reference Source.................................................................................................. 42
Table 9-14. GPIO Pin Global Signal Assignments .................................................................................................... 42
Table 9-15. GPIO Pin Control.................................................................................................................................... 43
Table 9-16. Reset and Power-Down Sources ........................................................................................................... 48
Table 10-1. Overall Register Map.............................................................................................................................. 51
Table 10-2. Port Registers......................................................................................................................................... 51
Table 10-3. Global Register Map............................................................................................................................... 52
Table 10-4. Port Common Register Map................................................................................................................... 60
Table 10-5. LIU Register Map.................................................................................................................................... 68
Table 10-6. B3ZS/HDB3 Encoder Register Map....................................................................................................... 77
Table 10-7. B3ZS/HDB3 Decoder Register Map....................................................................................................... 79
Table 10-8. BERT Register Map................................................................................................................................ 84
Table 11-1. JTAG ID Code ........................................................................................................................................ 93
Table 12-1. Recommended DC Operating Conditions.............................................................................................. 94
Table 12-2. DC Characteristics.................................................................................................................................. 95
Table 12-3. Framer Interface Timing ......................................................................................................................... 96
Table 12-4. Receiver Input Characteristics—DS3 and STS-1 Modes....................................................................... 98
Table 12-5. Receiver Input Characteristics—E3 Mode ............................................................................................. 98
Table 12-6. Transmitter Output Characteristics—DS3 and STS-1 Modes................................................................ 99
Table 12-7. Transmitter Output Characteristics—E3 Mode....................................................................................... 99
Table 12-8. Parallel CPU Interface Timing.............................................................................................................. 100
Table 12-9. SPI Interface Timing............................................................................................................................. 105
Table 12-10. JTAG Interface Timing........................................................................................................................ 107
Table 13-1. Pin Assignments Sorted by Signal Name for DS32504 (Microprocessor Interface Mode).................. 108
Table 15-1. Thermal Properties—Natural Convection............................................................................................. 122
Table 15-2. Theta-JA (θJA) vs. Airflow...................................................................................................................... 122
5 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
1. ACRONYMS
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
AIS
AMI
B3ZS
BER
BPV
CV
DS3
EXZ
HDB3
IO, I/O
JA
Alarm Indication Signal
Alternate Mark Inversion
Bipolar with Three-Zero Substitution
Bit Error Rate, Bit Error Ratio
Bipolar Violation
Code Violation
Digital Signal, Level 3
Excessive Zeros
High-Density Bipolar of Order 3
Input/Output
Jitter Attenuator
Line Interface Unit
Loss of Lock
LIU
LOL
LOS
LSB
Loss of Signal
Least Significant Bit
Most Significant Bit
MSB
PDH
PRBS
Rx, RX
SONET
SDH
STS
STS-1
Tx, TX
UI
Plesiochronous Digital Hierarchy
Pseudorandom Bit Sequence
Receive
Synchronous Optical Network
Synchronous Digital Hierarchy
Synchronous Transmission Signal
Synchronous Transmission Signal at Level 1
Transmit
Unit Interval
Unit Interval Peak-to-Peak
Unit Intervals Root Mean Squared
UIP-P
UIRMS
6 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
2. STANDARDS COMPLIANCE
Table 2-1. Applicable Telecommunications Standards
SPECIFICATION
SPECIFICATION TITLE
ANSI
T1.102-1993
T1.231-2003
T1.404-2002
Digital Hierarchy—Electrical Interfaces
Digital Hierarchy—Layer 1 In-Service Digital Transmission Performance Monitoring
Network-to-Customer Installation—DS3 Metallic Interface Specification
AT&T
TR54014
ACCUNET® T45 Service Description and Interface Specification, 05/92
ETSI
Business TeleCommunications; 34Mbps and 140Mbps Digital Leased Lines (D34U,
D34S, D140U, and D140S); Network Interface Presentation, v1.2.1 February 2001
Business TeleCommunications; 34Mbps Digital Leased Lines (D34U and D34S);
Connection Characteristics, v1.2.1 February 2001
Access and Terminals (AT); 34Mbps Digital Leased Lines (D34U and D34S); Terminal
equipment interface, v1.2.1July 2001
Business TeleCommunications; 34Mbps Digital Unstructured and Structured Lease Lines;
Attachment Requirements for Terminal Equipment Interface, July 1997
ITU
EN 300 686
EN 300 687
EN 300 689
TBR 24
G.703
G.751
Physical/Electrical Characteristics of Hierarchical Digital Interfaces, November 2001
Digital Multiplex Equipment Operating at the Third-Order Bit Rate of 34,368kbps and the
Fourth-Order Bit Rate of 139,264kbps and Using Positive Justification, November 1988
Digital Multiplex Equipment Operating at 139,264kbps and Multiplexing Three Tributaries
at 44,736kbps, November 1988
Loss of Signal (LOS) and Alarm Indication Signal (AIS) Defect Detection and Clearance
Criteria, November 1994
The Control of Jitter and Wander within Digital Networks that are Based on the 2048kbps
Hierarchy, March, 2000
G.755
G.775
G.823
G.824
The Control of Jitter and Wander within Digital Networks that are Based on the 1544kbps
Hierarchy, March, 2000
Error Performance Measuring Equipment Operating at the Primary Rate and Above,
October 1992
In-Service Code Violation Monitors for Digital Systems, November 1988
Equipment To Perform In-Service Monitoring on 2048, 8448, 34,368 and 139,264kbps
Signals, October 1992
O.151
O.161
O.152
TELCORDIA
GR-253-CORE
GR-499-CORE
GR-820-CORE
SONET Transport Systems: Common Generic Criteria, Issue 3, September 2000
Transport Systems Generic Requirements (TSGR): Common Requirements, Issue 2,
December 1998
Generic Digital Transmission Surveillance, Issue 2, December 1997
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PRELIMINARY
DS32501/DS32502/DS32503/DS32504
3. DETAILED DESCRIPTION
The DS32501 (single), DS32502 (dual), DS3203 (triple), and DS32504 (quad) LIUs perform the functions
necessary for interfacing at the physical layer to DS3, E3, or STS-1 lines. Each LIU has independent receive and
transmit paths and a built-in jitter attenuator. The receiver performs clock and data recovery from a B3ZS- or
HDB3-coded alternate mark inversion (AMI) signal and monitors for loss of the incoming signal. The receiver
optionally performs B3ZS/HDB3 decoding and outputs the recovered data in either binary (NRZ) or digital bipolar
format. The transmitter accepts data in either binary (NRZ) or digital bipolar format, optionally performs
B3ZS/HDB3 encoding, and drives standard pulse-shape waveforms onto 75Ω coaxial cable. Both transmitter and
receiver are high impedance when VDD is out of spec to enable hot-swappable 1:1 and 1+1 board redundancy
without relays. The jitter attenuator can be mapped into the receiver data path, mapped into the transmitter data
path, or can be disabled. An on-chip clock adapter generates all line-rate clocks from a single input clock. Control
interface options include 8- or 16-bit parallel, SPI, and hardware mode. The DS3250x LIUs conform to the
telecommunications standards listed in Table 2-1. The external components required for proper operation are
shown in Figure 3-2 and Figure 3-3.
Figure 3-1. Functional Diagram
EACH LIU
LINE IN
DS3, E3,
OR STS-1
RECEIVE
CLOCK
AND DATA
RXP
RXN
CLK
DATA
CONTROL
AND
STATUS
Dallas
Semiconductor
DS3250x
LINE OUT
DS3, E3,
OR STS-1
TRANSMIT
CLOCK
AND DATA
TXP
TXN
CLK
DATA
Figure 3-2. External Connections, Internal Termination Enabled
TXP
TVDD
RVDD
JVDD
0.1uF
0.1uF
0.01uF
0.01uF
1uF
1uF
1.8V
Power
Plane
TXN
RXP
0.1uF
0.01uF
1uF
1:1
TVSS
Ground
Plane
RVSS
JVSS
RXN
1:1
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PRELIMINARY
DS32501/DS32502/DS32503/DS32504
Figure 3-3. External Connections, Internal Termination Disabled
TXP
TVDD
RVDD
JVDD
0.1uF
0.1uF
0.01uF
0.01uF
1uF
1uF
42.2 W
(1%)
1.8V
0.05 uF
Power
Plane
42.2 W
(1%)
TXN
RXP
0.1uF
0.01uF
1uF
1:1
TVSS
38.3 W
(1%)
0.05 uF
Ground
Plane
RVSS
JVSS
38.3 W
(1%)
RXN
1:1
Shorthand Notations. The notation “DS3250x” throughout this data sheet refers to either the DS32501, DS32502,
DS3203, or DS32504. This data sheet is the specification for all four devices. The LIUs on the DS3250x devices
are identical. For brevity, this document uses the pin name and register name shorthand “NAMEn,” where “n”
stands in place of the LIU port number. For example, on the DS32504, TCLKn is shorthand notation for pins
TCLK1, TCLK2, TCLK3, and TCLK4 on LIU ports 1, 2, 3 and 4, respectively. This document also uses generic pin
and register names such as TCLK (without a number suffix) when describing LIU operation. When working with a
specific LIU on the DS3250x devices, generic names like TCLK should be converted to actual pin names, such as
TCLK1.
9 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
4. APPLICATION EXAMPLE
Figure 4-1. 3-Port Unchannelized DS3/E3 Card
DS32503
Three Port
DS3/E3/STS-1
LIU
DS3193
Three Port
DS3/E3/STS-1
Mapper
77.76/19.44 MHz
Telecom Bus
10 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
5. BLOCK DIAGRAM
Figure 5-1. Block Diagram
CLAD
JTAG
Port n (1 of 4)
AGC,
Equalizer,
and CDR
B3ZS/
HDB3
Decoder
RXPn
RXNn
Pre-Amp
RCLKn
RPOSn / RDATn
RNEGn / RLCVn
Pattern
Detector
ARES
Driver
Monitor
ALB
JA
LLB
DLB
RCLKI
TCLKI
TCC
Pattern
Generator
TDMn
B3ZS/
HDB3
Encoder
TXPn
TXNn
Line
Driver
Wave-
shaping
TCLKn
TPOSn / TDATn
TNEGn
AIS Generator
TAISn
AIST
Parallel and SPI Bus Interfaces
Dallas
Semiconductor
DS3250x
11 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
6. FEATURE DETAILS
6.1 Global Features
•
•
•
•
•
•
•
•
•
•
•
Three interface modes: hardware, 8-/16-bit parallel bus, and SPI serial bus
Independent per port operation (e.g., line rate, jitter attenuator placement, or loopback type)
Clock, data, and control signals can be inverted to allow a glueless interface to other devices
Manual or automatic one-second update of performance monitoring counters
Each port can be put into a low-power standby mode when not being used
Requires only a single reference clock for all three LIU data rates using internal clock rate adapter
Jitter attenuators can be used in either transmit or receive path
Detection of loss of transmit clock
Two programmable I/O pins per port
Optional global write mode configures all LIUs at the same time
Glueless interface to neighboring framer and mapper components
6.2 Receiver Features
•
•
•
•
•
•
•
AGC/equalizer block handles from 0 to 22dB of cable loss
Programmable internal termination resistor
Loss-of-lock (LOL) PLL status indication
Interfaces directly to a DSX monitor signal (~20dB flat loss) using built-in preamp
Digital and analog loss-of-signal (LOS) detectors (compliant with ANSI T1.231 and ITU-T G.775)
Software programmable B3ZS/HDB3 or AMI decoding
Detection and accumulation of bipolar violations (BPV), code violations (CV), and excessive zeroes
occurrences (EXZ)
•
•
•
•
Detection of receipt of B3ZS/HDB3 codewords
Binary or bipolar framer interface
On-board programmable PRBS detector
Per-channel power-down control
6.3 Transmitter Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Standards-compliant waveshaping
Programmable waveshaping
Programmable internal termination resistor
Binary or bipolar framer interface
Gapped clock capable up to 78MHz with jitter attenuator in transmit path
Wide 50 ±20% transmit clock duty cycle
Transmit common clock option
Software programmable B3ZS/HDB3 or AMI decoding
Programmable insertion of bipolar violations (BPV), code violations (CV), and excessive zeros (EXZ)
AIS generator: unframed all ones, framed DS3 AIS, and STS-1 AIS-L
Line build-out (LBO) control
High-impedance line driver output mode to support protection switching applications
Per-channel power-down control
Output driver monitor
6.4 Jitter Attenuator Features
•
•
•
•
•
•
One jitter attenuator per port
Fully integrated, requires no external components
Meets all applicable ANSI, ITU, ETSI, and Telcordia jitter transfer and output jitter requirements
Can be placed in the transmit path, receive path, or disabled
Programmable FIFO depth: 16, 32, 64, or 128 bits
Overflow and underflow status indications
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6.5 Bit Error Rate Tester (BERT) Features
•
•
•
One BERT per port
Software programmable for insertion toward the transmit line interface or the receive system interface
Generates and detects pseudorandom patterns of length 2n - 1 (n = 1-32) and repetitive patterns from 1 to 32
bits in length
•
•
•
Large 24-bit error counter and 32-bit bit counter allows testing to proceed for long periods without host
intervention
Errors can be inserted in the generated BERT patterns for diagnostic purposes (single bit errors or specific bit-
error rates)
Pattern synchronization even in the presence of 10-3 bit error rate
6.6 Clock Adapter Features
•
•
•
Creates DS3, E3, STS-1, and/or telecom bus clocks from single input reference clock
Input reference clock can be DS3, E3, STS-1, 12.8MHz, 19.44MHz, 38.88MHz, or 77.76MHz
Use of common system timing frequencies such as 19.44MHz eliminates the need for any local oscillators,
reduces cost and board space
•
•
•
Very small jitter gain and intrinsic jitter generation
Derived clocks can be output for external system use
Transmit signals using CLAD clocks meet Telcordia (DS3) and ITU (E3) jitter and wander requirements
6.7 Parallel Microprocessor Interface Features
•
•
Multiplexed or nonmultiplexed 8- or 16-bit interface
Configurable for Intel mode (CS, WR, RD) or Motorola mode (CS, DS, R/W)
6.8 SPI Serial Microprocessor Interface Features
•
•
•
•
Operation up to 10Mbps
Burst mode for multibyte read and write accesses
Programmable clock polarity and phase
Half-duplex operation gives option to tie SDI and SDO together externally to reduce wire count
6.9 Miscellaneous Features
•
•
•
Global reset input pin
Global interrupt output pin
Two programmable I/O pins per port
6.10 Test Features
•
•
•
•
•
5-pin JTAG port
All functional pins are in-out pins in JTAG mode
Standard JTAG instructions: SAMPLE/PRELOAD, BYPASS, EXTEST, CLAMP, HIGHZ, IDCODE
HIZ pin to force all digital output and I/O pins into a high-impedance state
TEST pin for manufacturing test modes
6.11 Loopback Features
•
•
•
•
Analog local loopback—ALB (transmit line output to receive line input)
Diagnostic local loopback—DLB (transmit framer interface to receive framer interface)
Line loopback—LLB (receive clock and data recover to transmit waveshaping)
Optional AIS generation on the line side of the loopback during diagnostic loopback
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7. CONTROL INTERFACE MODES
The DS3250x devices can be controlled by hardware interface or by microprocessor interface.
When the hardware interface is enabled (IFSEL = 00X), device configuration can be controlled by input pins, while
device status can be sensed on output pins. In this mode pins TOEn, RMON, TAIS, TLBO, TBIN, TCLKI, TPD,
RBIN, RCLKI, RPD, LMn[1:0], JAS[1:0], JAD[1:0], and LBn[1:0] are used to control the device and status can be
sensed on RLOSn pin.
The microprocessor interface (8-bit parallel, 16-bit parallel, or SPI) provides access to features, configuration
options, and device status information that the hardware interface does not support. The microprocessor interface
is enabled and configured by the IFSEL pins. When IFSEL = 01X, the SPI serial interface is enabled. When
IFSEL = 10X, the 8-bit parallel interface is enabled. When IFSEL = 11X, the 16-bit parallel interface is enabled. For
both the 8- and 16-bit parallel interfaces, IFSEL[0] = 0 specifies an Intel-style bus (CS, RD, and WR control signals)
while IFSEL[0] = 1 specifies a Motorola-style bus (CS, R/W, and DS control signals). Through the microprocessor
interface an external microprocessor can access a set of internal configuration and status registers inside the
device. Pins that are not used by the selected microprocessor interface type but are used in other microprocessor
interface modes are disabled (inputs are ignored and considered to be low and can be left floating or wired low or
high; outputs are placed in a high-impedance state and can be left unconnected or wired low or high). When no
microprocessor interface is selected (IFSEL = 00X) all microprocessor interface inputs are ignored, and all
microprocessor interface outputs are put in a high-impedance state.
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8. PIN DESCRIPTIONS
Note: All digital pins are I/O pins in JTAG mode. This feature is to increase the effectiveness of board level ATPG
patterns to isolate interconnect failures.
8.1 Short Pin Descriptions
n = port number (1–4 for DS32504, 1–3 for DS32503, 1–2 for DS32502, 1 for DS32501); I = input; Ipu = input with internal pullup resistor; Ipd =
input with internal pulldown resistor; Ia = analog input; I/O = bidirectional in/out; I/Opd = bidirectional in/out with internal pulldown resistor; O =
output; Oz = high-impedance output (needs an external pullup or pulldown resistor to keep the node from floating); Oa = analog output (high
impedance); P = power supply or ground. All unused input pins without pullup should be tied low.
Note: All internal pullup resistors are 50kΩ tied to approximately 2.2VDC. See Section 13 for pin assignments.
Table 8-1. Short Pin Descriptions
NAME
TYPE
ANALOG LINE INTERFACE
FUNCTION
TXPn
TXNn
RXPn
RXNn
Oa
Oa
Ia
Transmit Positive Analog (Port n)
Transmit Negative Analog (Port n)
Receive Positive Analog (Port n)
Receive Negative Analog (Port n)
Ia
DIGITAL FRAMER INTERFACE
I
I
TCLKn
TPOSn/
TDATn
Transmit Clock (Port n)
Transmit Positive AMI/Transmit NRZ Data (Port n)
TNEGn
RCLKn
RPOSn/
RDATn
I
Transmit Negative AMI (Port n)
Receive Clock (Port n)
Oz
Oz
Receive Positive AMI/Receive NRZ Data (Port n)
RNEGn/RLCVn
Oz
Receive Negative AMI/Receive Line Code Violation (Port n)
GLOBAL I/O
IFSEL[2:0]
TEST
HIZ
RST
RESREF
I
I
I
Microprocessor Interface Select
Factory Test enable (Active Low)
High impedance test enable (Active Low)
Reset (Active Low)
Ipu
Oa
Reference Resistor
HARDWARE INTERFACE
I
Microprocessor Interface Select
LIU Mode Control (DS3, E3 or STS-1) (Port n)
Transmit AIS Control (Port n)
IFSEL[2:0]
LMn[1:0]
TAISn
Ipd
I
I
I
I
Transmit Binary Interface Control (All Ports)
Transmit Clock Invert Control (All Ports)
Transmit Line Build-Out Control (Port n)
Transmit Output Enable Control (Port n)
Transmit Power-Down (All Ports)
Receive Binary Interface Control (All Ports)
Receive Clock Invert Control (All Ports)
Receive Loss of Signal Status (Port n)
Receive Monitor Preamp Control (Port n)
Receive Power-Down (All Ports)
TBIN
TCLKI
TLBOn
TOEn
TPD
Ipd
I
I
I
O
I
RBIN
RCLKI
RLOSn
RMONn
RPD
I
I
I
I
I
Jitter Attenuator Depth (All Ports)
Jitter Attenuator Select (Tx, Rx or Disabled) (All Ports)
Loopback Control (Port n)
JAD[1:0]
JAS[1:0]
LBn[1:0]
CLADBYP
CLAD Bypass
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NAME
TYPE
FUNCTION
8-/16-BIT PARALLEL INTERFACE
I
I
I
I
I
Chip Select (Active Low)
CS
RD/DS
WR/R/W
ALE
Read Enable (Active Low)/Data Strobe (Active Low)
Write Enable (Active Low)/Read/Write Select
Address Latch Enable
Address Bus (Excluding LSB)
Address Bus LSB/Byte Swap
Data Bus [15:0]
Interrupt (Active Low)
General-Purpose I/O A (Port n)
General-Purpose I/O B (Port n)
A[9:1]
A[0]/BSWAP
D[15:0]
INT
GPIOAn
GPIOBn
I
I/O
Oz
I/Opd
I/Opd
SPI SERIAL INTERFACE
I
I
I
Chip Select (Active Low)
Address Latch Enable
Serial Clock
CS
ALE
SCLK
SDI
I
Serial Data Input
SDO
O
I
I
Serial Data Output
Clock Phase
Clock Polarity
CPHA
CPOL
INT
Oz
Interrupt Output (Active Low)
GPIOAn
GPIOBn
I/Opd
I/Opd
General-Purpose I/O A (Port n)
General-Purpose I/O B (Port n)
CLAD
REFCLK
CLKA
CLKB
CLKC
CLKD
I
Reference Clock
Clock A DS3 44.736MHz
Clock B E3 34.368MHz
Clock C STS-1 51.84MHz
Clock D Telecom Bus 77.76MHz or 19.44MHz
I/O
I/O
I/O
O
JTAG
JTCLK
JTMS
JTDI
JTDO
JTRST
I
JTAG Clock
Ipu
Ipu
Oz
Ipu
JTAG Mode Select
JTAG Data Input
JTAG Data Output
JTAG Reset (Active Low)
POWER SUPPLY AND GROUND PINS
P
P
VDD18
VDD33
VSS
RVDDn
RVSSn
TPVSSn
TVDDn
TVSSn
CVDD
Digital Core 1.8V Power, 1.8V ±10%
I/O 3.3V Power, 3.3V ±5%
Ground for VDD18 and VDD33
Receive 1.8V Power, 1.8V ±10% (Port n)
Receive Ground (Port n)
Transmit 1.8V Power, 1.8V ±10% (Port n)
Transmit 1.8V Power, 1.8V ±10% (Port n)
Transmit Ground (Port n)
CLAD 1.8V ±10%
CLAD Ground
P
P
P
P
P
P
P
P
P
P
CVSS
JTVDDn
JTVSSn
Jitter Attenuator 1.8V Power, 1.8V ±10% (Port n)
Jitter Attenuator Ground (Port n)
MANUFACTURING TEST
MT
Test
Manufacturing Test Pins. Leave unconnected.
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8.2 Detailed Pin Descriptions
n = port number (1–4 for DS32504, 1–3 for DS32503, 1–2 for DS32502, 1 for DS32501); I = input; Ipu = input with internal pullup resistor; Ipd =
input with internal pulldown resistor; Ia = analog input; I/O = bidirectional in/out; I/Opd = bidirectional in/out with internal pulldown resistor; O =
output; Oz = high-impedance output (needs an external pullup or pulldown resistor to keep the node from floating); Oa = analog output (high
impedance); P= power supply or ground. All unused input pins without pullup should be tied low.
Note: All internal pullup resistors are 50kΩ tied to 2.2VDC.
Table 8-2. Analog Line Interface Pin Descriptions
PIN NAME TYPE
FUNCTION
Transmitter Analog Outputs. These differential AMI outputs are coupled to the
outbound 75Ω coaxial cable through a 1:1 transformer (Figure 3-2). These outputs can
be disabled (high impedance) using the TOEn pin or the TOE or TPD configuration bits.
See Section 9.2.8.
TXPn,
Oa
TXNn
RXPn,
Ia
Receiver Analog Inputs. These differential AMI inputs are coupled to the inbound 75Ω
coaxial cable through a 1:1 transformer (Figure 3-2). See Section 9.3.1.
RXNn
Table 8-3. Digital Framer Interface Pin Descriptions
PIN NAME TYPE
FUNCTION
Transmit Clock. A DS3 (44.736MHz ±20ppm), E3 (34.368MHz ±20ppm), or STS
(51.840MHz ±20ppm) clock should be applied at this pin. Data to be transmitted is
clocked into the device at TPOS/TDAT and TNEG either on the rising edge of TCLK
(TCLKI = 0) or the falling edge of TCLK (TCLKI = 1). When the PORT.CR2:TCC = 1, all
ports are clocked by TCLK1, and TCLKx (x ≠ 1) are ignored. See Section 9.2.1 for
additional details.
Transmit Positive AMI/Transmit NRZ Data. This pin is sampled either on the rising
edge of TCLK (TCLKI = 0) or on the falling edge of TCLK (TCLKI = 1). See Section 9.2.2.
TPOSn: When the transmitter is configured to have a bipolar interface (TBIN = 0), a
positive pulse is transmitted on the line when TPOS is high.
TCLKn
I
I
TPOSn/
TDATn
TDATn: When the transmitter is configured to have a binary interface (TBIN = 1), the
data on TDAT is transmitted after B3ZS or HDB3 encoding.
Transmit Negative AMI. When the transmitter is configured to have a bipolar interface
(TBIN = 0), a negative pulse is transmitted on the line when TNEG is high. When the
transmitter is configured to have a binary interface TBIN = 1), TNEG is ignored and
should be wired either high or low. TNEG is sampled either on the rising edge of TCLK
(TCLKI = 0) or the falling edge of TCLK (TCLKI = 1). See Section 9.2.2.
Receive Clock. The clock recovered from the receive signal is output on the RCLK pin.
Recovered data is output on the RPOS/RDAT and RNEG/RLCV pins on the falling edge
of RCLK (RCLKI = 0) or the rising edge of RCLK (RCLKI = 1). During an LOS condition
(RLOSn = 0), the RCLK output signal is derived from the LIU’s reference clock. See
Section 9.3.6.
TNEGn
RCLKn
I
Oz
Receive Positive AMI/Receive NRZ Data. This pin is updated either on the falling edge
of RCLK (RCLKI = 0) or the rising edge of RCLK (RCLKI = 1). See Section 9.3.6.
RPOSn: When the receiver is configured to have a bipolar interface (RBIN = 0), RPOS
pulses high for each positive AMI pulse received.
RDATn: When the receiver is configured to have a binary interface (RBIN = 1), RDAT
outputs decoded binary data.
Receive Negative AMI/Receive Line-Code Violation. This pin is updated either on the
falling edge of RCLK (RCLKI = 0) or the rising edge of RCLK (RCLKI = 1). See Section
9.3.6 for further details on code violations.
RNEGn: When the receiver is configured to have a bipolar interface (RBIN = 0), RNEG
pulses high for each negative AMI pulse received.
RPOSn/
RDATn
Oz
Oz
RNEGn/
RLCVn
RLCVn: When the receiver is configured to have a binary interface (RBIN = 1), RLCV
pulses high to flag code violations.
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Table 8-4. Global Pin Descriptions
PIN NAME TYPE
FUNCTION
Interface Select
000 = Hardware interface mode (external LIU termination)
001 = Hardware interface mode (internal LIU termination)
010 = SPI serial interface, address and data MSB first
011 = SPI serial interface, address and data LSB first
100 = 8-bit parallel interface, Intel style (CS, RD, WR control signals)
101 = 8-bit parallel interface, Motorola style (CS, R/W, DS control signals)
110 = 16-bit parallel interface, Intel style (CS, RD, WR control signals)
111 = 16- bit parallel interface, Motorola style (CS, R/W, DS control signals)
Note: The device should be reset (RST low) when the device is first placed in hardware
mode.
IFSEL[2:0]
I
Factory Test Enable (Active Low). This pin enables the internal scan test mode when
low. For normal operation tie high. This is an asynchronous input.
High-Impedance Test Enable (Active Low). This signal is used to enable testing. When
this signal is low while JTRST is low, all of the digital output and bi-directional pins are
placed in the high impedance state. For normal operation this signal is high. This is an
asynchronous input.
I
I
TEST
HIZ
Reset (Active Low, Open Drain, Internal 10kΩ Pullup to VDD33). When this global
asynchronous reset is pulled low, all internal circuitry is reset and all internal registers are
forced to their default values. The device is held in reset as long as RST is low. RST should
be held low for at least two reference clock cycles. See Section 9.11.
Reference Resistor. This pin is tied to VSS through a 10kΩ ±1% resistor. This accurate
resistor is used to calibrate on-chip resistor values including internal transmit and receive
termination resistors.
Ipu
Oa
RST
RESREF
Table 8-5. Hardware Interface Pin Descriptions
PIN NAME TYPE
Termination Select
FUNCTION
IFSEL[2:0]
I
000 = External LIU termination
001 = Internal LIU termination
LIU Mode Control (Port n). When the hardware interface is enabled (IFSEL = 00X), these
pins set the LIU mode for port n.
00 = DS3
01 = E3
LMn[1:0]
Ipd
10 = STS-1
11 = reserved
Transmit AIS Control (Port n). When the hardware interface is enabled (IFSEL = 00X),
these pins control the AIS insertion port n.
TAISn
I
0 = transmit normal data
1 = transmit AIS
The type of AIS signal is specified by the LMn[1:0] pins. See Section 9.2.4.
Transmit Binary Interface Control (All Ports). When the hardware interface is enabled
(IFSEL = 00X), this pin controls the TPOS/TNEG interface for all ports. See Section 9.2.2.
0 = Transmitter framer interface is bipolar on the TPOS and TNEG pins, and the
B3ZS/HDB3 encoder is disabled.
1 = Transmitter framer interface is binary on the TDAT pin, and the B3ZS/HDB3 encoder is
enabled.
Transmit Clock Invert Control (All Ports). When the hardware interface is enabled
(IFSEL = 00X), this pin controls the TCLK inversion for all ports. See Section 9.2.1.
0 = TPOS/TDAT and TNEG are sampled on the rising edge of TCLK.
1 = TPOS/TDAT and TNEG are sampled on the falling edge of TCLK.
TBIN
I
I
TCLKI
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PIN NAME TYPE
FUNCTION
Transmit Line Build-Out Control (Port n). When the hardware interface is enabled
(IFSEL = 00X), this pin specifies cable length for waveform shaping in DS3 and STS-1
modes. In E3 mode it is ignored and should be wired high or low. See Section 9.2.6.
0 = Cable length ≥ 225ft
TLBOn
I
1 = Cable length < 225ft
Transmitter Output Enable Control (Port n). This pin enables and disables the
transmitter outputs. The transmitter continues to operate internally when the outputs are
disabled; only the line driver and driver monitor are disabled. See Section 9.2.7. These
pins are available in both hardware and microprocessor interface modes.
0 = TXPn/TXNn output drivers disabled (high impedance)
1 = TXPn/TXNn output drivers enabled
Transmit Power-Down (All Ports). When the hardware interface is enabled
(IFSEL = 00X), this pin controls the power-down feature for all ports. See Section 9.2.10.
0 = Enable all transmitters
1 = Power down all transmitters (drivers become high impedance)
Receive Binary Interface Control (All Ports). When the hardware interface is enabled
(IFSEL = 00X), this pin controls the RPOS/RNEG interface for all ports. See Section 9.3.6.
0 = Receiver framer interface is bipolar on the RPOS and RNEG pins, and the
B3ZS/HDB3 encoder is disabled.
TOEn
TPD
Ipd
I
I
RBIN
1 = Receiver framer interface is binary on the RDAT pin, and the B3ZS/HDB3 encoder is
enabled.
Receive Clock Invert Control (All Ports). When the hardware interface is enabled
(IFSEL = 00X), this pin controls the RCLK inversion for all ports. See Section 9.3.6.3.
0 = RPOS/RDAT and RNEG/RLCV update on the falling edge of RCLK.
1 = RPOS/RDAT and RNEG/RLCV update on the rising edge of RCLK.
Receive Loss of Signal Status (Port n). This pin is asserted upon detection of 192
consecutive zeros in the receive data stream. It is deasserted when there are no excessive
zero occurrences over a span of 192 clock periods. An excessive zero occurrence is
defined as three or more consecutive zeros in DS3 and STS-1 modes or four or more
zeros in E3 mode. These pins are available in both hardware and microprocessor interface
modes. See Section 9.3.5.
RCLKI
RLOSn
I
O
Receive Monitor Preamp Control (Port n). When the hardware interface is enabled
(IFSEL = 00X), these pins control the LIU preamp for port n. This pin determines whether
the receiver preamp is enabled in port n to provide flat gain to the incoming signal before
the AGC/equalizer block processes it. This feature should be enabled when the device is
being used to monitor signals that have been resistively attenuated by a monitor jack. See
Section 9.3.2 for more information.
RMONn
I
0 = Disable the monitor preamp
1 = Enable the monitor preamp
Receive Power-Down (All Ports). When the hardware interface is enabled
(IFSEL = 00X), this pin controls the power-down feature for all ports. See Section 9.3.7.
0 = Enable all receivers
1 = Power down all receivers (RXPn/RXNn high impedance; RCLKn, RPOS/RDAT and
RNEGn/RLCVn high impedance)
Jitter Attenuator Depth (All Ports). When the hardware interface is enabled
(IFSEL = 00X), these pins control the jitter attenuator for all ports.
00 = 16 bits
RPD
I
I
I
JAD[1:0]
JAS[1:0]
01 = 32 bits
10 = 64 bits
11 = 128 bits
Jitter Attenuator Select (All Ports). These pins select the location of the jitter attenuator
when hardware interface is enabled (IFSEL = 00X). See Section 9.4.
00 = Disabled
01 = Receive path
1X = Transmit path
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PIN NAME TYPE
FUNCTION
Loopback Control (Port n). When the hardware interface is enabled (IFSEL = 00X),
these pins set the loopback mode for port n. See Section 9.6.
00 = No loopback
01 = Diagnostic Loopback (DLB)
10 = Line Loopback (LLB)
LBn[1:0]
I
I
11 = Analog Loopback (ALB)
CLAD Bypass Control. When the hardware interface is enabled (IFSEL = 00X), this pin
controls whether the CLAD is used or bypassed. See Section 9.7.1.
0 = Synthesize the DS3, E3, and STS-1 clocks from the clock on the REFCLK pin
1 = Source the DS3, E3, and STS-1 clocks from the CLKA, CLKB and CLKC pins
CLADBYP
Table 8-6. Parallel Interface Pin Descriptions
PIN NAME
TYPE
FUNCTION
Chip Select (Active Low). This pin must be asserted to read or write internal registers.
See Section 9.8.3.
I
CS
Read Enable (Active Low)/Data Strobe (Active Low)
RD: For the Intel-style bus (IFSEL = 1X0), RD is asserted to read internal registers.
DS: For the Motorola-style bus (IFSEL = 1X1), DS is asserted to access internal
registers while the R/W pin specifies whether the access is a read or a write. See
Section 9.8.3.
I
I
RD/DS
Write Enable (Active Low)/Read/Write Select
WR: For the Intel-style bus (IFSEL = 1X0), WR is asserted to write internal registers.
R/W: For the Motorola-style bus (IFSEL = 1X1), R/W determines the type of bus
transaction, with R/W = 1 indicating a read and R/W = 0 indicating a write. See
Section 9.8.3.
WR/R/W
Address Latch Enable. This pin controls a latch on the A[9:0] inputs. For a
nonmultiplexed parallel bus, ALE is wired high to make the latch transparent. For a
multiplexed parallel bus, the falling edge of ALE latches the address. See Section 9.8.3.
Address Bus (excluding LSB). These inputs specify the address of the internal 16-bit
register to be accessed. A[9] is not present on the DS32502 and DS32503; A[9:8] are
not present on the DS32501. See Section 9.8.
ALE
I
I
A[9:1]
Address Bus LSB/Byte Swap. See Section 9.8.2.
A[0]: This pin is connected to the lower address bit in 8-bit bus modes (IFSEL = 10X).
0 = Output register bits 7:0 on D[7:0]; D[15:8] high impedance
1 = Output register bits 15:8 on D[7:0]; D[15:8] high impedance
BSWAP: This pin is tied high or low in 16-bit bus modes ( = 11X).
0 = Output register bits 15:8 on D[15:8] and bits 7:0 on D[7:0]
A[0]/
BSWAP
I
1 = Output register bits 7:0 on D[15:8] and bits 15:8 on D[7:0]
Data Bus. A 8-bit or 16-bit bidirectional data bus. These pins are inputs during writes to
internal registers and outputs during reads. D[15:8] are disabled (high impedance) in
8-bit bus modes (IFSEL = 10X). D[15:0] are disabled (high impedance) when CS = 1 or
RST = 0. In 16-bit bus modes (IFSEL = 11X) the upper and lower bytes can be swapped
by pulling the BSWAP pin high. See Section 9.8.
Interrupt Output (Active Low, Open Drain or Push-Pull). This pin is driven low in
response to one or more unmasked, active interrupt sources within the device. INT
remains low until the interrupt is serviced or masked. When GLOBAL.CR2:INTM = 0,
INT is high impedance when inactive (default). When INTM = 1, INT is driven high when
inactive. INT is high impedance when RST = 0. See Section 9.10.
General-Purpose I/O A. When a microprocessor interface is enabled (IFSEL ≠ 00X),
this pin is the general-purpose I/O pin for port n. See Section 9.7.3.
General-Purpose I/O B. When a microprocessor interface is enabled (IFSEL ≠ 00X),
this pin is the general-purpose I/O pin for port n. See Section 9.7.3. Note: GPIOB1,
GPIOB2, and GPIOB3 can also be programmed as global control/status pins.
D[15:0]
I/O
Oz
INT
GPIOAn
GPIOBn
I/Opd
I/Opd
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Table 8-7. SPI Serial Interface Pin Descriptions
Note: Pins in the following table are muxed with pins in Table 8-6, and are valid only when the SPI serial interface
is enabled (IFSEL = 01X).
PIN NAME
TYPE
FUNCTION
Chip Select (Active Low). This pin must be asserted to read or write internal registers.
See Section 9.9.
I
CS
ALE
SCLK
I
I
Address Latch Enable. For SPI serial interface operation, ALE must be wired high.
Serial Clock. SCLK is always driven by the SPI bus master. See Section 9.9.
Serial Data Input. The SPI bus master transmits data to the device on this pin. See
Section 9.9.
SDI
I
Serial Data Output. The device transmits data to the SPI bus master on this pin. See
Section 9.9.
SDO
O
Clock Phase. See Section 9.9.
CPHA
CPOL
I
0 = Data is latched on the leading edge of the SCLK pulse.
1 = Data is latched on the trailing edge of the SCLK pulse.
Clock Polarity. See Section 9.9.
0 = SCLK is normally low and pulses high during bus transactions.
1 = SCLK is normally high and pulses low during bus transactions.
Interrupt Output (Active Low, Open Drain). See INT pin description in Table 8-6.
I
Oz
INT
GPIOAn
I/Opd General-Purpose I/O. See GPIOAn pin description in Table 8-6.
GPIOBn
I/Opd General-Purpose I/O. See GPIOBn pin description in Table 8-6.
Table 8-8. CLAD Pin Descriptions
PIN NAME
TYPE
FUNCTION
Reference Clock. The signal on this pin is the input reference clock to the CLAD and
must be transmission quality (±20ppm, low jitter). In hardware mode REFCLK must be
19.44MHz. In microprocessor interface modes REFCLK can be any of several
frequencies. See Section 9.7.1.
REFCLK
I
Clock A DS3 44.736MHz. When the CLAD is bypassed a transmission-quality DS3
clock (44.736MHz ±20ppm, low jitter) must be connected to this pin if any of the LIUs
are to operate in DS3 mode. When the CLAD is enabled this pin can be configured to
output the DS3 clock synthesized by PLL-A. See Section 9.7.1.
Clock B E3 34.368MHz. When the CLAD is bypassed a transmission-quality E3 clock
(34.368MHz ±20ppm, low jitter) must be connected to this pin if any of the LIUs are to
operate in E3 mode. When the CLAD is enabled this pin can be configured to output the
E3 clock synthesized by PLL-B. See Section 9.7.1.
CLKA
CLKB
I/O
I/O
Clock C STS-1 51.84MHz. When the CLAD is bypassed a transmission-quality STS-1
clock (51.84MHz ±20ppm, low jitter) must be connected to this pin if any of the LIUs are
to operate in STS-1 mode. When the CLAD is enabled this pin can be configured to
output the STS-1 clock synthesized by PLL-C. See Section 9.7.1.
Clock D Telecom Bus 77.76MHz or 19.44MHz. When the CLAD is bypassed this pin is
driven low. When the CLAD is enabled this pin can output a 77.76MHz or 19.44MHz
clock synthesized by PLL-D. See Section 9.7.1.
CLKC
CLKD
I/O
O
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Table 8-9. JTAG Pin Descriptions
PIN NAME
TYPE
FUNCTION
JTAG Clock. This pin shifts data into JTDI on the rising edge and out of JTDO on the
falling edge. JTCLK is typically a low frequency (less than 10MHz) 50% duty cycle clock
signal. If boundary scan is not used, JTCLK should be pulled high. See Section 11.
JTAG Mode Select (Internal 10kΩ Pullup to VDD33). This pin is used to control the
JTAG controller state machine. JTMS is sampled on the rising edge of JTCLK. If
boundary scan is not used, JTMS should be left unconnected or pulled high. See
Section 11.
JTAG Data Input (Internal 10kΩ Pullup to VDD33). This pin is used to input data into
the register that is enabled by the JTAG controller state machine. JTDI is sampled on
the rising edge of JTCLK. If boundary scan is not used, JTDI should be left unconnected
or pulled high. See Section 11.
JTCLK
I
JTMS
JTDI
Ipu
Ipu
JTAG Data Output. This pin is the output of an internal scan shift register enabled by
the JTAG controller state machine. JTDO is updated on the falling edge of JTCLK.
JTDO is in high impedance mode when a register is not selected or when the JTRST pin
is low. JTDO goes into and out of high*impedance mode after the falling edge of
JTCLK. See Section 11.
JTAG Reset (Internal 10kΩ Pullup to VDD33). When active this pin forces the JTAG
controller logic into the reset state and forces the JTDO pin into high impedance mode.
The JTAG controller is also reset when power is first applied via a power-on reset
circuit. JTRST can be driven high or low for normal operation, but must be high for JTAG
operation. See Section 11.
JTDO
Oz
Ipu
JTRST
Table 8-10. Power-Supply Pin Descriptions
PIN NAME
TYPE
FUNCTION
VDD18
VDD33
P
P
P
P
P
P
P
P
P
Digital Core 1.8V Power, 1.8V ±10%
I/O 3.3V Power, 3.3V ±5%
Ground for VDD18 and VDD33
Receive 1.8V Power, 1.8V ±10%
Receive Ground
VSS
RVDDn
RVSSn
TVDDn
TVSSn
CVDD
CVSS
Transmit 1.8V Power, 1.8V ±10%
Transmit Ground
CLAD 1.8V ±10%
CLAD Ground
Table 8-11. Manufacturing Test Pin Descriptions
PIN NAME
TYPE
FUNCTION
MT
Test Manufacturing Test Pin. Leave unconnected.
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9. FUNCTIONAL DESCRIPTION
9.1 LIU Mode
Each port is independently configurable for DS3, E3 or STS-1 operation. When the hardware interface is enabled
(IFSEL = 00X), the LMn[1:0] pins specify the LIU mode. When a microprocessor interface is enabled (IFSEL ≠ 00X)
the PORT.CR2:LM[1:0] control bits specify the LIU mode.
9.2 Transmitter
9.2.1 Transmit Clock
If the jitter attenuator is not enabled in the transmit path, the signal on TCLK is the transmit line clock and must be
transmission quality (i.e., ±20ppm frequency accuracy and low jitter). If the jitter attenuator is enabled in the
transmit path, the signal on TCLK can be jittery and/or periodically gapped, but must still have an average
frequency within ±20ppm of the nominal line rate. When enabled in the transmit path, the jitter attenuator generates
the transmit line clock. See Section 9.4 for more information about the jitter attenuator.
The polarity of TCLK can be inverted to support glueless interfacing to a variety of neighboring components.
Normally data is sampled on the TPOS/TDAT and TNEG pins on the rising edge of TCLK. To sample these pins on
the falling edge of TCLK, pull the TCLKI (hardware interface mode) pin high or set the PORT.INV:TCLKI
(microprocessor interface mode) configuration bit.
9.2.1.1 Transmit Common Clock Mode
In microprocessor interface mode the PORT.CR2:TCC register bit specifies whether the transmit clock for port n
comes from TCLKn or TCLK1. In designs where the transmit paths of all ports can be clocked synchronously with
one another, common transmit clocking reduces wiring complexity between the LIU and the neighboring framer or
mapper component.
9.2.2 Framer Interface Format and the B3ZS/HDB3 Encoder
Data to be transmitted can be input in either bipolar or binary format.
9.2.2.1 Bipolar Interface Format
To select the bipolar interface format, pull the TBIN (hardware interface mode) pin low or clear the
PORT.CR2:TBIN (microprocessor interface mode) configuration bit. In bipolar format, the B3ZS/HDB3 encoder is
disabled and the data to be transmitted is sampled on the TPOS and TNEG pins. Positive-polarity pulses are
indicated by TPOS = 1, while negative-polarity pulses are indicated by TNEG = 1. If TPOS and TNEG are high at
the same time the transmitter generates an AMI pulse that is the opposite state of the pulse previously transmitted.
9.2.2.2 Binary Interface Format
To select the binary interface format, pull the TBIN pin high (hardware interface mode for all ports) or set the
PORT.CR2:TBIN configuration bit (microprocessor interface mode for each port). In binary format, the B3ZS/HBD3
encoder is enabled, and the NRZ data to be transmitted is sampled on the TDAT pin. The TNEG pin is ignored in
binary interface mode and should be wired low. In DS3 and STS-1 modes, B3ZS encoding is performed. In these
modes whenever three consecutive zeros are found in the transmit data stream they are replaced with a B3ZS
codeword. In E3 mode HDB3 encoding is performed. In this mode, whenever four consecutive zeros are found in
the transmit data stream they are replaced with an HDB3 codeword. In all three modes, the B3ZS or HDB3
codeword is constructed such that the last bit is a BPV with the opposite polarity of the most recently transmitted
BPV.
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9.2.3 Error Insertion
Bipolar violation (BPV) errors and excessive zeros (EXZ) errors can be inserted into the transmit data stream using
the transmit manual error insert (TMEI) logic (see Section 9.7.5). Configuration bit LINE.TCR:BPVI enables the
insertion of bipolar violations, while LINE.TCR:EXZI enables the insertion of excessive zero events. Note: BPV
errors and EXZ errors can only be inserted in the binary interface format.
If the transmitter is configured for binary interface format (Section 9.2.2.2) and BPVI = 1 then when the configured
manual error insert control goes from 0 to 1 the transmitter waits for the next occurrence of two consecutive 1s
where the polarity of the first 1 is opposite the polarity of the BPV in the last B3ZS/HDB3 codeword. The first 1 is
transmitted according to the normal AMI rule, but the second 1 is transmitted with the same polarity as the first 1,
thus making the second 1 a bipolar violation.
If the transmitter is configured for binary interface format (Section 9.2.2.2) and EXZI = 1 then when the configured
manual error insert control goes from 0 to 1 the transmitter waits for the next occurrence of three (four) consecutive
zeros in the transmit data stream and inhibits the replacement of those zeros with a B3ZS (HDB3) codeword.
The transmitter ensures that there is at least one intervening 1 between consecutive BPV or EXZ errors. If a
second error insertion request of a given type (BPV or EXZ) is initiated before a previous request has been
completed, the second request is ignored.
9.2.4 AIS Generation
The transmitter can be configured to transmit an AIS signal by asserting the TAIS pin (hardware interface mode) or
the PORT.CR3:TAIS (microprocessor interface mode) configuration bit. In hardware mode, the type of AIS signal to
be generated is specified by the LMn[1:0] pins. In microprocessor interface mode the type of AIS signal to be
generated is specified by PORT.CR2:LM[1:0] configuration bits and the PORT.CR3:AIST configuration bit. When
AIST = 1, the AIS signal is the framed DS3 AIS signal in DS3 mode, unframed all ones in E3 mode, and the AIS-L
signal in STS-1 mode. The AIS-L signal is normally scrambled, but scrambling can be disabled by setting
PORT.CR3:SCRD = 1. When AIST = 0, the AIS signal is unframed all ones in all modes when AIS insertion is
requested (TAIS = 1).
9.2.5 Waveshaping
9.2.5.1 Standards-Compliant Waveshaping
Waveshaping converts the transmit clock, positive data, and negative data signals into a single analog AMI signal
with the waveshape required for interfacing to DS3/E3/STS-1 lines. Figure 9-1 and Table 9-1 show the DS3
waveform equations and template. Figure 9-2 and Table 9-3 show the STS-1 waveform equations and template.
Figure 9-3 shows the E3 waveform template.
9.2.5.2 Programmable Waveshaping
The transmit waveshape can be adjusted with the TWSC[19:0] bits in the LIU.TWSCR1 and LIU.TWSCR2
registers. These signals control the amplitude, slew rates and various other aspects of the waveform template. See
the register descriptions for further details.
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Figure 9-1. DS3 Waveform Template
2nd Rise
1st Fall
DS3250x WAVESHAPE SEGMENTS.
SEE THE LIU.TWSCR REGISTER
DESCRIPTIONS.
1.2
1.0
0.8
0.6
0.4
0.2
0
1st Rise
2nd Fall
-0.2
-1.0
0.25
-0.75
-0.5
0
0.5
0.75
1.0
1.25
1.5
-0.25
Time (UI)
Table 9-1. DS3 Waveform Equations
TIME (IN UNIT INTERVALS)
NORMALIZED AMPLITUDE EQUATION
UPPER CURVE
0.03
-0.85 ≤ T ≤ -0.68
-0.68 ≤ T ≤ +0.36
0.36 ≤ T ≤ 1.4
0.5 {1 + sin[(π / 2)(1 + T / 0.34)]} + 0.03
0.08 + 0.407e-1.84(T - 0.36)
LOWER CURVE
-0.03
0.5 {1 + sin[(π / 2)(1 + T / 0.18)]} - 0.03
-0.03
-0.85 ≤ T ≤ -0.36
-0.36 ≤ T ≤ +0.36
0.36 ≤ T ≤ 1.4
Table 9-2. DS3 Waveform Test Parameters and Limits
PARAMETER
SPECIFICATION
Rate
44.736Mbps (±20ppm)
Line Code
B3ZS
Transmission Medium
Test Measurement Point
Test Termination
Coaxial cable (AT&T 734A or equivalent)
At the end of 0 to 450ft of coaxial cable
75Ω (±1%) resistive
Pulse Amplitude
Between 0.36V and 0.85V
An isolated pulse (preceded by two zeros and
followed by one or more zeros) falls within the
curves listed in Table 9-1
Pulse Shape
Unframed All-Ones Power Level at 22.368MHz
Unframed All-Ones Power Level at 44.736MHz
Between -1.8dBm and +5.7dBm
At least 20dB less than the power at 22.368MHz
Ratio of positive and negative pulses must be
between 0.90 and 1.10
Pulse Imbalance of Isolated Pulses
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Figure 9-2. STS-1 Waveform Template
2nd Rise
1st Fall
DS3250x WAVESHAPE SEGMENTS.
SEE THE LIU.TWSCR REGISTER
DESCRIPTIONS.
1.2
1.0
0.8
0.6
0.4
0.2
0
1st Rise
2nd Fall
-0.2
-1.0
-0.75
-0.5
-0.25
0
0.5
1.0
1.25
1.5
0.25
0.75
Time (UI)
Table 9-3. STS-1 Waveform Equations
TIME (IN UNIT INTERVALS)
NORMALIZED AMPLITUDE EQUATIONS
UPPER CURVE
0.03
-0.85 ≤ T ≤ -0.68
-0.68 ≤ T ≤ +0.26
0.26 ≤ T ≤ 1.4
0.5 {1 + sin[(π / 2)(1 + T / 0.34)]} + 0.03
0.1 + 0.61e-2.4(T - 0.26)
LOWER CURVE
-0.03
0.5 {1 + sin[(π / 2)(1 + T / 0.18)]} - 0.03
-0.03
-0.85 ≤ T ≤ -0.36
-0.36 ≤ T ≤ +0.36
0.36 ≤ T ≤ 1.4
Table 9-4. STS-1 Waveform Test Parameters and Limits
PARAMETER
SPECIFICATION
Rate
51.840Mbps (±20ppm)
Line Code
B3ZS
Transmission Medium
Test Measurement Point
Test Termination
Coaxial cable (AT&T 734A or equivalent)
At the end of 0 to 450ft of coaxial cable
75Ω (±1%) resistive
Pulse Amplitude
0.800V nominal (not covered in specs)
An isolated pulse (preceded by two zeros and
followed by one or more zeros) falls within the
curved listed in Table 9-3
Pulse Shape
Unframed All-Ones Power Level at 25.92MHz
Unframed All-Ones Power Level at 51.84MHz
Between -1.8dBm and +5.7dBm
At least 20dB less than the power at 25.92MHz
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Figure 9-3. E3 Waveform Template
DS3250x WAVESHAPE
Zero Level
Overshoot
One Level
17.0 (14.55 + 2.45)
Undershoot
Zero Level
SEGMENTS. SEE THE
LIU.TWSCR REGISTER
DESCRIPTIONS.
1.2
1.0
0.8
0.6
0.4
0.2
0
1.1
0.9
8.65 (14.55 - 5.90)
12.1 (14.55 - 2.45)
Nominal Pulse
0.5
14.55
24.5 (14.55 + 9.95)
0.1
-0.1
-0.2
29.1 (14.55 +
14.55)
-15
-10
-5
0
5
10
15
Time (ns)
Table 9-5. E3 Waveform Test Parameters and Limits
PARAMETER
SPECIFICATION
34.368Mbps (±20ppm)
Rate
Line Code
HDB3
Transmission Medium
Test Measurement Point
Test Termination
Coaxial cable (AT&T 734A or equivalent)
At the transmitter
75Ω (±1%) resistive
Pulse Amplitude
1.0V (nominal)
An isolated pulse (preceded by two zeros and
Pulse Shape
followed by one or more zeros) falls within the
template shown in Figure 9-3
Ratio of the Amplitudes of Positive and Negative
Pulses at the Center of the Pulse Interval
Ratio of the Widths of Positive and Negative
Pulses at the Nominal Half Amplitude
0.95 to 1.05
0.95 to 1.05
9.2.6 Line Build-Out
Because DS3 and STS-1 signals must meet the waveform templates at the cross-connect through any cable length
from 0 to 450 feet, the waveshaping circuitry includes a selectable LBO feature. For cable lengths of 225 feet or
greater, both the TLBO pin (hardware interface mode) and the LIU.CR1:TLBO configuration bit (microprocessor
interface mode) should be low to disable the LBO circuitry. When the LBO circuitry is disabled, output pulses are
driven onto the coaxial cable without any preattenuation. For cable lengths less than 225 feet, either the TLBO pin
(hardware interface mode) or the LIU.CR1:TLBO configuration bit (microprocessor interface mode) should be high
to enable the LBO circuitry. When the LBO circuitry is enabled, pulses are preattenuated by the LBO circuitry
before being driven onto the coaxial cable to provide attenuation that mimics the attenuation of 225 feet of coaxial
cable.
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9.2.7 Line Driver
The transmit line driver can be disabled (TXP and TXN outputs high impedance) by deasserting the TOE pin
(hardware interface mode) and deasserting the LIU.CR1:TOE (microprocessor interface mode) configuration bit.
Powering down the transmitter through the TPD pin (hardware interface mode) or the PORT.CR1:TPD
(microprocessor interface mode) configuration bit also disables the transmit line driver.
9.2.8 Interfacing to the Line
The transmitter interfaces to the outgoing DS3/E3/STS-1 coaxial cable (75Ω) through a 1:1 isolation transformer
connected to the TXP and TXN pins. The transmit line termination can be internal to the device, external to the
device, or a combination of both. Figure 3-2 shows the arrangement of the transformer when the internal
termination is enabled (LIU.CR1:TTRE = 1) and no external termination resistors are used. Figure 3-3 shows the
arrangement of the transformer and external termination resistors when the internal termination is disabled
(LIU.CR1:TTRE = 0). Note that internal termination is only available when a microprocessor interface is enabled.
The internal termination resistor value for the transmitter is specified in LIU.CR1:TRESADJ. Table 9-7 and Table
9-8 specify the required characteristics of the transformer and provide a list of recommended transformers.
9.2.9 Driver Monitor and Output Failure Detection
The transmit driver monitor compares the amplitude of the transmit waveform to thresholds VTXMIN and VTXMAX. If
the amplitude is less than VTXMIN or greater than VTXMAX for approximately 32 reference clock cycles, then the
monitor sets the LIU.SR:TDM status bit. The setting of LIU.SR:TDM can cause an interrupt if enabled by
LIU.SRIE:TDMIE. When the transmitter is disabled, the transmit driver monitor is also disabled. The transmit driver
monitor is clocked by the LIU’s reference clock.
Note that the transmit driver monitor can be affected by reflections caused by shorts and opens on the line. A short
circuit at a distance less than a few inches (~11 inches for FR4 material) can introduce inverted reflections that
reduce the outgoing pulse amplitude below the VTXMIN threshold and thereby activate the TDM status bit. Similarly
an open circuit a similar distance away can introduce noninverted reflections that increase the outgoing amplitude
above the VTXMAX threshold and thereby activate the TDM status bit. Shorts and opens at larger distances away
from TXP/TXN can also activate the TDM status bit, but this effect is data-pattern dependent.
If either TXP or RXP is not connected (open), shorted to VDD, or shorted to VSS, then a transmit failure alarm is
declared by setting the LIU.SR:TFAIL status bit. A change of state of the TFAIL status bit can cause an interrupt if
enabled by LIU.SRIE:TFAILIE. TFAIL is cleared when activity is detected on both TXP and RXP.
9.2.10 Power-Down
To minimize power consumption when the transmitter is not being used, the TPD pin (hardware interface mode for
all ports) or the PORT.CR1:TPD configuration bit (microprocessor interface mode for each port) can be asserted.
When the transmitter is powered down, the TXP and TXN pins are put in a high-impedance state and the transmit
drivers are powered down.
9.2.11 Jitter Generation (Intrinsic)
The transmitter meets the jitter generation requirements of all applicable standards in Table 9-6, with or without the
jitter attenuator enabled. Generated jitter is measured with a jitter-free, 0ppm input clock.
Table 9-6. Jitter Generation
SIGNAL
STANDARD
REQUIREMENT
BANDWIDTH
DS3250x JITTER
DS3
DS3
DS3
DS3
DS3
E3
GR-499
T1.404
T1.404
PUB 54014
PUB 54014
G.751
GR-253
GR-253
0.3 UIRMS
0.5 UIP-P
10Hz to 400kHz
10Hz to 400kHz
30kHz to 400kHz
10Hz to 400kHz
30kHz to 400kHz
100Hz to 800kHz
12kHz to 400kHz
12kHz to 400kHz
< 0.1 UIRMS
< 0.2 UIP-P
< 0.02 UIP-P
< 0.025 UIP-P
< 0.02 UIP-P
< 0.1 UIP-P
0.05 UIP-P
0.05 UIP-P
0.025 UIP-P
0.05 UIP-P
0.01 UIRMS
0.10 UIP-P
STS-1
STS-1
< 0.005 UIRMS
< 0.05 UIP-P
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9.2.12 Jitter Transfer
Without the jitter attenuator on the transmit side, the transmitter passes jitter through unchanged. With the jitter
attenuator enabled on the transmit side, the transmitter meets the jitter transfer requirements of all applicable
telecommunication standards in Table 2-1. See Figure 9-7.
9.3 Receiver
9.3.1 Interfacing to the Line
The receiver can be transformer-coupled or capacitor-coupled to the line. Typically, the receiver interfaces to the
incoming coaxial cable (75Ω) through a 1:1 isolation transformer. The receive line termination can be internal to the
device, external to the device, or a combination of both. Figure 3-2 shows the arrangement of the transformer when
the internal termination is enabled (LIU.CR2:RTRE = 1) and no external termination resistors are used. Figure 3-3
shows the arrangement of the transformer and external termination resistors when the internal termination is
disabled (LIU.CR2:RTRE = 0). Note that internal termination is only available when a microprocessor interface is
enabled. The internal termination resistor value is specified in LIU.CR2:RRESADJ[3:0]. Table 9-7 and Table 9-8
specify the required characteristics of the transformer and provide a list of recommended transformers. The
receiver expects the incoming signal to be in B3ZS- or HDB3-coded AMI format.
Table 9-7. Transformer Characteristics
PARAMETER
Turns Ratio
VALUE
1:1 ±2%
0.200MHz to 340MHz (typ)
Bandwidth 75Ω
Primary Inductance
Leakage Inductance
Interwinding Capacitance
Isolation Voltage
40μH (min)
0.12μH (max)
10pF (max)
1500VRMS (min)
Table 9-8. Recommended Transformers
OCL
PRIMARY
(μH) (min)
40
LL
BANDWIDTH
75Ω (MHz)
PIN-PACKAGE/
SCHEMATIC
MANUFACTURER
PART
TEMP RANGE
(μH) (max)
Pulse Engineering
Pulse Engineering
Pulse Engineering
Pulse Engineering
Pulse Engineering
Pulse Engineering
Pulse Engineering
Halo Electronics
Halo Electronics
Halo Electronics
Halo Electronics
PE-65967
PE-65966
T3001
TX3025
TX3036
TX3047
TX3051
TG01-0406NS
TD01-0406NS
TG01-0456NS
TD01-0456NE
0°C to +70°C
0°C to +70°C
6 SMT LS-1/E
6 THT LC-1/E
6 SMT LS-2/E
16 SMT BH/3
24 SMT
32 SMT YB/1
48 SMT
6 SMT SMD/A
6 DIP DIP/A
6 SMT SMD/A
6 DIP DIP/A
0.10
0.10
0.11
0.120
0.110
0.150
0.120
0.10
1500
1500
1500
1500
1500
1500
1500
1500
1500
1500
1500
40
40
100
100
100
60
40
40
45
45
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
0.10
0.12
0.12
Note: Table subject to change. Multiport transformers are also available. Contact the manufacturer for details at www.pulseeng.com and
www.haloelectronics.com.
9.3.2 Optional Preamp
The receiver can be used in monitoring applications, which typically have series resistors with a resistive loss of
approximately 20dB. When the RMON pin (hardware interface mode) is high or the LIU.CR2:RMON
(microprocessor interface mode) configuration bit is set, the receiver can compensate for this resistive loss by
applying 14dB of additional flat gain to the incoming signal before sending the signal to the AGC/equalizer block
(an additional 6dB of flat gain is applied in the AGC circuitry for a total gain of 20dB). When the preamp is enabled
the receiver automatically determines whether or not to make use of the preamp’s additional gain. Status bit
LIU.SR:RPAS indicates whether or not the preamp is in use. A change of state of LIU.SR:RPAS can cause an
interrupt if enabled by LIU.SRIE:RPASIE.
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9.3.3 Automatic Gain Control (AGC) and Adaptive Equalizer
The AGC circuitry applies flat (frequency independent) gain to the incoming signal to compensate for flat losses in
the transmission channel and variations in transmission power. Since the incoming signal also experiences
frequency-dependent losses as it passes through the coaxial cable, the adaptive equalizer circuitry applies
frequency-dependent gain to offset line losses and restore the signal. The AGC/equalizer circuitry automatically
adapts to coaxial cable losses from 0 to 22dB, which translates into 0 to 457 meters (1500 feet) of coaxial cable
(AT&T 734A or equivalent). The AGC and the equalizer work simultaneously but independently to supply a signal
of nominal amplitude and pulse shape to the clock and data recovery block. The AGC/equalizer block automatically
handles direct (0 meters) monitoring of the transmitter output signal. The real-time receiver gain level can be read
from the LIU.RGLR register.
9.3.4 Clock and Data Recovery (CDR)
The CDR block takes the amplified, equalized signal from the AGC/equalizer block and produces separate clock,
positive data, and negative data signals. The CDR operates from the LIU’s reference clock. See Section 9.7.1 for
more information about reference clocks and clock selection.
The receiver locks onto the incoming signal using a clock recovery PLL. The PLL lock status is indicated in the
LIU.SR:RLOL status bit. The RLOL bit is set when the difference between recovered clock frequency and reference
clock frequency is greater than 7900ppm and cleared when the difference is less than 7700ppm. A change of state
of the RLOL status bit can cause an interrupt if enabled by LIU.SRIE:RLOLIE. Note that if the reference clock is not
present, RLOL is not set.
9.3.5 Loss-of-Signal (LOS) Detector
The receiver contains analog and digital LOS detectors. The analog LOS (ALOS) detector resides in the
AGC/equalizer block. At approximately 23dB below nominal pulse amplitude ALOS is declared by setting the
LIU.SR:ALOS status bit. A change of state of the ALOS status bit can cause an interrupt if enabled by
LIU.SRIE:ALOSIE. When ALOS is declared the CDR block forces all zeros out of the data recovery circuit, causing
digital LOS (DLOS), which is indicated by the RLOS pin and the LINE.RSR:RLOS status bit. During ALOS the
RCLK pin follows the LIU’s reference clock, since no clock information is being received on RXP/RXN. ALOS is
cleared at approximately 22dB below nominal pulse amplitude. When the preamp is enabled (section 9.3.2) ALOS
is declared at approximately 37dB below nominal and cleared at approximately 36dB below nominal.
The digital LOS detector declares DLOS when it detects 192 consecutive zeros in the recovered data stream.
When DLOS occurs, the receiver asserts the RLOS pin (if the hardware interface is enabled) and the
LINE.RSR:RLOS status bit. DLOS is cleared when there are no EXZ occurrences over a span of 192 clock periods.
An EXZ occurrence is defined as three or more consecutive zeros in DS3 and STS-1 modes and four or more
consecutive zeros in E3 mode. The RLOS pin and the RLOS status bit are deasserted when the DLOS condition is
cleared. A change of state of the LINE.RSR:RLOS status bit can cause an interrupt if enabled by
LINE.RSRIE:RLOSIE. DLOS is only declared when B3ZS/HDB3 decoding is enabled (LINE.RCR:RZSD = 0).
When B3ZS/HDB3 decoding is disabled in the LIU, decoding should be enabled in the neighboring DS3/E3 framer,
and DLOS should be detected and report by the framer.
The requirements of ANSI T1.231 and ITU-T G.775 for DS3 LOS defects are met by the DLOS detector, which
asserts RLOS when it counts 192 consecutive zeros coming out of the CDR block and clears RLOS when it counts
192 consecutive pulse intervals without excessive zero occurrences.
The requirements of ITU-T G.775 for E3 LOS defects are met by a combination of the ALOS detector and the
DLOS detector, as follows:
For E3 RLOS Assertion:
1) The ALOS detector in the AGC/equalizer block detects that the incoming signal is less than or equal to a signal
level approximately 23 dB below nominal, and mutes the data coming out of the clock and data recovery block.
(23 dB below nominal is in the “tolerance range” of G.775, where LOS may or may not be declared.)
2) The DLOS detector counts 192 consecutive zeros coming out of the CDR block and asserts RLOS. (192 meets
the 10 ≤ N ≤ 255 pulse-interval duration requirement of G.775.)
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For E3 RLOS Clear:
1) The ALOS detector in the AGC/equalizer block detects that the incoming signal is greater than or equal to a
signal level approximately 22 dB below nominal, and enables data to come out of the CDR block. (22 dB is in
the “tolerance range” of G.775, where LOS may or may not be declared.)
2) The DLOS detector counts 192 consecutive pulse intervals without EXZ occurrences and deasserts RLOS.
(192 meets the 10 ≤ N ≤ 255 pulse-interval duration requirement of G.775.)
The DLOS detector supports the requirements of ANSI T1.231 for STS-1 LOS defects. At the STS-1 rate, the time
required for the DLOS detector to count 192 consecutive zeros falls in the range of 2.3 ≤ T ≤ 100μs required by
ANSI T1.231 for declaring an LOS defect. Although the time required for the DLOS detector to count 192
consecutive pulse intervals with no excessive zeros is less than the 125 μs to 250 μs period required by ANSI
T1.231 for clearing an LOS defect, a period of this length where LOS is inactive can easily be timed in software.
During LOS, the RCLK output pin is derived from the LIU’s reference clock. The ALOS detector has a longer time
constant than the DLOS detector. Thus, when the incoming signal is lost, the DLOS detector activates first
(asserting the RLOS pin and RLOS status bit), followed by the ALOS detector. When a signal is restored, the
DLOS detector does not get a valid signal that it can qualify for no EXZ occurrences until the ALOS detector has
seen the signal rise above a signal level approximately 22dB below nominal.
9.3.6 Framer Interface Format and the B3ZS/HDB3 Decoder
The recovered data can be output in either bipolar or binary format. Reception of a B3ZS or HDB3 codeword is
flagged by the LINE.RSRL:ZSCDL latched status bit.
9.3.6.1 Bipolar Interface Format
To select the bipolar interface format, pull the RBIN pin (hardware interface mode) low and clear the
PORT.CR2:RBIN configuration bit (microprocessor interface mode). In bipolar format, the B3ZS/HDB3 decoder is
disabled and the recovered data is buffered and output on the RPOS and RNEG outputs for subsequent decoding
by a downstream framer or mapper. Received positive-polarity pulses are indicated by RPOS = 1, while negative-
polarity pulses are indicated by RNEG = 1.
In DS3 and STS-1 modes an excessive zeros error (EXZ) is declared whenever there is an occurrence of 3 or
more zeros in a row in the receive data stream. In E3 mode, an EXZ error is declared whenever there is an
occurrence of 4 or more zeros. EXZs are flagged by the LINE.RSRL:EXZL and EXZCL latched status bits and
accumulated in the LINE.REXZCR register.
In all three modes (DS3, E3, and STS-1) a bipolar violation is declared if two positive pulses are received without
an intervening negative pulse or if two negative pulses are received without an intervening positive pulse. Bipolar
violations (BPVs) are flagged by the LINE.RSRL:BPVL and BPVCL latched status bits and accumulated in the
LINE.RBPVCR register.
9.3.6.2 Binary Interface Format
To select the binary interface format, pull the RBIN pin high (hardware interface mode for all ports) or set the
PORT.CR2:RBIN configuration bit (microprocessor interface mode for each port). In binary format, the B3ZS/HBD3
decoder is enabled, and the recovered data is decoded and output as a binary (NRZ) value on the RDAT pin, while
bipolar violations, code violations, and excessive zero errors are detected and flagged on the RLCV pin.
In DS3 and STS-1 modes, B3ZS decoding is performed. In these modes, whenever a B3ZS codeword is found in
the receive data stream it is replaced with three zeros. In E3 mode HDB3 decoding is performed. In this mode,
whenever an HDB3 codeword is found in the receive data stream it is replaced with four zeros. The decoding
search criteria for a B3ZS/HDB3 codeword is programmable using the LINE.RCR:RDZSF control bit.
An excessive zeros error (EXZ) is declared in DS3 and STS-1 modes whenever there is an occurrence of 3 or
more zeros in a row in the receive data stream. In E3 mode, an EXZ error is declared whenever there is an
occurrence of 4 or more zeros in a row. EXZs are flagged by the LINE.RSRL:EXZL and EXZCL latched status bits
and accumulated in the LINE.REXZCR register.
A bipolar violation error (BPV error) is declared in DS3 and STS-1 modes if a BPV is detected that is not part of a
valid B3ZS codeword. In E3 mode, a bipolar violation error is declared whenever a BPV is detected that is not part
of a valid HDB3 codeword. In E3 mode if LINE.RCR:E3CVE = 1, code violations are detected rather than bipolar
violation errors. A code violation is declared whenever consecutive BPVs (not BPV errors) have the same polarity
(ITU O.161 definition). The error detection search criteria for a B3ZS/HDB3 codeword is programmable using the
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LINE.RCR:REZSF control bit. Bipolar violations (or code violations if LINE.RCR:E3CVE = 1) are flagged by the
LINE.RSRL:BPVL and BPVCL latched status bits and accumulated in the LINE.RBPVCR register.
In the discussion that follows, a valid pulse that conforms to the AMI rule is denoted as B. A BPV pulse that violates
the AMI rule is denoted as V.
In DS3 and STS-1 modes, B3ZS decoding is performed, and RLCV is asserted during any RCLK cycle where the
data on RDAT causes ones of the following code violations:
ꢀ
When LINE.RCR:E3CVE = 0:
–
–
–
A BPV immediately preceded by a valid pulse (B, V).
A BPV with the same polarity as the last BPV.
The third zero in an EXZ.
ꢀ
When LINE.RCR:E3CVE = 1:
–
–
A BPV immediately preceded by a valid pulse (B, V).
A BPV with the same polarity as the last BPV.
In E3 mode, HDB3 decoding is performed, and RLCV is asserted during any RCLK cycle where the data on RDAT
causes one of the following code violations:
ꢀ
When LINE.RCR:E3CVE = 0:
–
–
–
A BPV immediately preceded by a valid pulse (B, V) or by a valid pulse and a zero (B, 0, V).
A BPV with the same polarity as the last BPV.
The fourth zero in an EXZ.
ꢀ
When LINE.RCR:E3CVE = 1:
A BPV with the same polarity as the last BPV.
–
In any cycle where RLCV is asserted to flag a BPV, the RDAT pin outputs a one. In any cycle where RLCV is
asserted to flag an EXZ, the RDAT pin outputs a zero. The state bit that tracks the polarity of the last BPV is
toggled on every BPV, whether part of a valid B3ZS/HDB3 codeword or not.
9.3.6.3 RCLK Inversion
The polarity of RCLK can be inverted to support a glueless interface to a variety of neighboring components.
Normally, data is output on the RPOS/RDAT and RNEG/RLCV pins on the falling edge of RCLK. To output data on
these pins on the rising edge of RCLK, pull the RCLKI pin (hardware interface mode) high or set the
PORT.INV:RCLKI configuration bit (microprocessor interface mode).
9.3.6.4 Receiver Output Disable
The RCLK, RPOS/RDAT and RNEG/RLCV pins can be disabled (put in a high-impedance state) to support
protection switching and redundant-LIU applications. This capability supports system configurations where two or
more LIUs are wire-ORed together and a system processor selects one to be active. To disable these pins, set the
PORT.CR2:ROD configuration bit.
9.3.7 Power-Down
To minimize power consumption when the receiver is not being used, assert the RPD pin (hardware interface mode
for all ports) or the PORT.CR1:RPD configuration bit (microprocessor interface mode per port). When the receiver
is powered down, the RCLK, RPOS/RDAT and RNEG/RLCV pins are disabled (high impedance). In addition, the
RXP and RXN pins become high impedance.
9.3.8 Input Failure Detection
The LIU receiver can detect opens and shorts on the RXP and RXN differential inputs. By default, the receiver
detects the following problems, collectively labeled type 1 failures: open RXP connection, open RXN connection,
common-mode RXP/RXN short to VDD, and common-mode RXP/RXN short to VSS. Type 1 failures are reported
on LIU.SR:RFAIL1. RFAIL1 is cleared when activity is detected on both RXP and RXN.
If LIU.CR2:RFL2E = 1, the receiver also detects a type 2 failure, which is an open or high-impedance path between
RXP and RXN. On a board with the external components shown in Figure 3-2 or Figure 3-3, the receive
transformer normally presents a low-impedance path between RXP and RXN. To detect a type 2 failure, the
receiver connects an 40 µA DC current source to RXP and measures the impedance between RXP and RXN.
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When this impedance is greater than about 5 kΩ the receiver declares a type 2 failure on LIU.SR:RFAIL2. When
the type 2 failure-detection circuitry is enabled, internal termination must be disabled (LIU.CR2:RTRE = 0) and
external termination must not be present or a type 2 failure will not be detected because the impedance of the
termination is below the type 2 failure threshold.
9.3.9 Jitter and Wander Tolerance
The receiver exceeds the input jitter tolerance requirements of all applicable telecommunication standards in
Table 2-1. See Figure 9-4 for STS-1 and E3 jitter tolerance characteristics. See Figure 9-5 for DS3 jitter tolerance
characteristics. See Figure 9-6 for DS3 and E3 wander tolerance characteristics. Note: Only G.823 and G.824
have wander tolerance requirements.
Figure 9-4. STS-1 and E3 Jitter Tolerance
100
34.4
15
GR-253 (STS-1)
G.823 (E3)
10
DS3250x
Jitter Tolerance
1.5
1.0
0.15
0.1
30
1.675
4.4
300
2k
20k
10k
800k
1M
1
10
100
1k
100k
Frequency (Hz)
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Figure 9-5. DS3 Jitter Tolerance
100
G.824 (DS3)
GR-499 Cat I (DS3)
GR-499 Cat II (DS3)
67
10
5
DS3250x
Jitter Tolerance
1.0
0.3
0.1
1.675
21.9
600
669
2.3k
22.3k30k
60k
300k
400k
1
10
100
1k
10k
100k
1M
Frequency (Hz)
Figure 9-6. DS3 and E3 Wander Tolerance
1000
805
DS3250x
Wander Tolerance
G.824 (DS3)
G.823 (E3)
137.5
100
67
34.4
10
1.2
10-5
6.12
0.032
0.13
10-1
1.675
4.4
10-4
10-3
10-2
1
10
Frequency (Hz)
9.3.10 Jitter Transfer
Without the jitter attenuator on the receive side, the receiver attenuates jitter at frequencies above its corner
frequency (approximately 300kHz) and passes jitter at lower frequencies. With the jitter attenuator enabled on the
receive side, the receiver meets the jitter transfer requirements of all applicable telecommunication standards in
Table 2-1. See Figure 9-7.
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9.4 Jitter Attenuator
Each LIU contains an on-board jitter attenuator that can be placed in the receive path or the transmit path or can
be disabled. When the hardware interface is enabled (IFSEL = 00X), the JAS[1:0] and JAD[1:0] pins specify the
jitter attenuator location and buffer depth for all ports. When a microprocessor interface is enabled (IFSEL ≠ 00X),
the LIU.CR1:JAS[1:0] and JAD[1:0] configuration bits specify the JA location and buffer depth for each port
individually. The JA buffer depth can be set to 16, 32, 64 or 128 bits. Figure 9-7 shows the minimum jitter
attenuation for the device when the jitter attenuator is enabled. Figure 9-7 also shows the receive jitter transfer
when the jitter attenuator is disabled.
The jitter attenuator consists of a narrowband PLL to retime the selected clock, a FIFO to buffer the associated
data while the clock is being retimed, and logic to prevent FIFO over/underflow in the presence of very large jitter
amplitudes. The JA has a loop bandwidth of reference_clock ÷ 2,058,874 (see corner frequencies in Figure 9-7).
The JA attenuates jitter at frequencies higher than the loop bandwidth, while allowing jitter (and wander) at lower
frequencies to pass through relatively unaffected.
The jitter attenuator requires a transmission-quality reference clock (i.e., ±20ppm frequency accuracy and low
jitter). See Section 9.7.1 for more information about reference clocks and clock selection.
When the microprocessor interface is enabled, the jitter attenuator indicates the fill status of its FIFO buffer in the
LIU.SRL:JAFL (JA full) and LIU.SRL:JAEL (JA empty) status bits. When the buffer becomes full, the JA
momentarily increases the frequency of the read clock by 6250ppm to avoid buffer overflow and consequent data
errors. When the buffer becomes empty, the JA momentarily decreases the frequency of the read clock by 6250
ppm to avoid buffer underflow and consequent data errors. During these momentary frequency adjustments, jitter is
passed through the JA to avoid over/underflow. If the phase noise or frequency offset of the write clock is large
enough to cause the buffer to overflow or underflow, the JA sets both the JAFL bit and the JAEL bit to indicate that
data errors have occurred. JAFL and JAEL can cause an interrupt if enabled by the corresponding enable bits in
the LIU.SRIE register.
As shown in Figure 9-7, the jitter attenuator meets the jitter transfer requirements of all applicable standards listed
in Table 2-1.
Figure 9-7. Jitter Attenuation/Jitter Transfer
21.7 Hz (DS3)
16.7 Hz (E3)
25.2 Hz (STS-1)
27Hz
1k
>150k
40Hz
40k 59.6k
0
DS3 [GR - 499 (1995)]
CATEGORY I
DS3 [GR -253 (1999)]
CATEGORY I
DS3250x TYPICAL
RECEIVER JITTER
TRANSFER WITH
JITTER ATTENUATOR
DISABLED
STS-1 [GR-253 (1999)]
CATEGORY II
-10
-20
E3 [TBR24 (1997)]
DS3250x
DS3/E3/STS-1
MINIMUM
DS3 [GR- 499 (1999)]
CATEGORY II
JITTER
ATTENUATION
WITH JITTER
ATTENUATOR
ENABLED
-30
10k
10
100
1k
100k
1M
FREQUENCY (Hz)
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9.5 BERT
Each LIU port has a built-in bit error rate tester (BERT). The BERT is a software-programmable test-pattern
generator and monitor capable of meeting most error performance requirements for digital transmission equipment.
It can generate and synchronize to pseudo-random patterns with a generation polynomial of the form xn + xy + 1,
(where n and y can take on values from 1 to 32 with y < n) and to repetitive patterns of any length up to 32 bits.
The pattern generator generates the programmable test pattern, and inserts the test pattern into the data stream.
The pattern detector extracts the test pattern from the receive data stream and monitors it. Figure 5-1 shows the
location of the BERT Block within the DS3250x devices.
9.5.1 Configuration and Monitoring
The pattern detector is always enabled. The pattern generator is enabled by setting the PORT.CR3:BERTE
configuration bit. When the BERT is enabled and PORT.CR3:BERTD = 0, the pattern is transmitted and received in
the line direction, i.e., the pattern generator is the data source for the transmitter, and the receiver is the data
source for the pattern detector. When the BERT is enabled and PORT.CR3:BERTD = 1, the pattern is transmitted
and received in the system direction, i.e., the pattern generator is the data source for the RPOS/RDAT and
RNEG/RLCV pins, and the TPOS/TDAT and TNEG pins are the data source for the pattern detector. See Figure
5-1.
The I/O of the BERT are binary (NRZ) format. Thus while the BERT is enabled, both PORT.CR2:RBIN and
PORT.CR2:TBIN must be set to 1 for proper operation. In addition, while transmitting/receiving BERT patterns in
the system direction (PORT.CR3:BERTD = 1), the neighboring framer or mapper component must also be
configured for binary interface mode to match the LIU. If the LIU interface is normally bipolar, the interface can be
changed back to bipolar mode when the system is done using the BERT function (PORT.CR3:BERTE = 0).
The following tables show how to configure the BERT to send and receive common patterns.
Table 9-9. Pseudorandom Pattern Generation
BERT.PCR REGISTER
BERT.CR
PATTERN TYPE
BERT.SPR2
BERT.SPR1
PTF[4:0]
(hex)
PLF[4:0]
(hex)
TPIC,
RPIC
PTS QRSS
29-1 O.153 (511 type)
04
08
0
0
0
0
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0
211-1 O.152 and O.153
(2047 type)
08
0A
0
215-1 O.151
220-1 O.153
0D
10
02
11
0E
13
13
16
0
0
0
0
0
0
1
0
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
1
0
0
1
220-1 O.151 QRSS
223-1 O.151
Table 9-10. Repetitive Pattern Generation
BERT.PCR REGISTER
PATTERN TYPE
BERT.SPR2
BERT.SPR1
PTF[4:0]
(hex)
PLF[4:0]
(hex)
PTS QRSS
all 1s
NA
00
00
01
03
17
0F
07
03
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFF20
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFE
0xFFFE
0xFFFC
0x0022
0x0001
0xFF01
0xFFF1
all 0s
NA
NA
NA
NA
NA
NA
NA
alternating 1s and 0s
11001100...
3 in 24
1 in 16
1 in 8
1 in 4
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After configuring these bits, the pattern must be loaded into the BERT. This is accomplished via a zero-to-one
transition on BERT.CR.TNPL for the pattern generator and BERT.CR.RNPL for the pattern detector. The BERT
must be enabled (PORT.CR3:BERTE = 1) before the pattern is loaded for the pattern load operation to take effect.
Monitoring the BERT requires reading the BERT.SR register, which contains the Bit Error Count (BEC) bit and the
Out of Synchronization (OOS) bit. The BEC bit is set to one when the bit error counter is one or more. The OOS bit
is set to one when the pattern detector is not synchronized to the incoming pattern, which occurs when it receives 6
or more bit errors within a 64-bit window. The Receive BERT Bit Count Register (BERT.RBCR) and the Receive
BERT Bit Error Count Register (BERT.RBECR) are updated upon the reception of a Performance Monitor Update
signal (e.g., BERT.CR.LPMU). This signal updates the registers with the bit and bit-error counts since the last
update and then resets the counters. See Section 9.7.4 for more details about performance monitor updates.
9.5.2 Receive Pattern Detection
The pattern detector synchronizes the receive pattern generator to the incoming pattern. The receive pattern
generator is a 32-bit shift register that shifts data from the least significant bit (LSB) or bit 1 to the most significant
bit (MSB) or bit 32. The input to bit 1 is the feedback. For a PRBS pattern (generating polynomial xn + xy + 1), the
feedback is an XOR of bit n and bit y. For a repetitive pattern (length n), the feedback is bit n. The values for n and
y are individually programmable (1 to 32 with y < n) in the BERT.PCR:PLF and PTF fields. The output of the
receive pattern generator is the feedback. If QRSS is enabled (BERT.PCR:QRSS = 1), the feedback is forced to be
an XOR of bits 17 and 20, and the output is forced to one if the next 14 bits are all zeros. For PRBS and QRSS
patterns, the feedback is forced to one if bits 1 through 31 are all zeros. Depending on the type of pattern
programmed, pattern detection performs either PRBS synchronization or repetitive pattern synchronization.
9.5.2.1 Receive PRBS Synchronization
PRBS synchronization synchronizes the receive pattern generator to the incoming PRBS or QRSS pattern. The
receive pattern generator is synchronized by loading 32 data stream bits into the receive pattern generator, and
then checking the next 32 data stream bits. Synchronization is achieved if all 32 bits match the incoming pattern. If
at least six incoming bits in the current 64-bit window do not match the receive pattern generator, automatic pattern
resynchronization is initiated. Automatic pattern resynchronization can be disabled by setting BERT.CR:APRD = 1.
Pattern resynchronization can also be initiated manually by a zero-to-one transition of the Manual Pattern
Resynchronization bit (BERT.CR:MPR). The incoming data stream can be inverted before comparison with the
receive pattern generator by setting BERT.CR:RPIC. Refer to Figure 9-8 for the PRBS synchronization state
diagram.
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Figure 9-8. PRBS Synchronization State Diagram
Sync
1 bit error
Verify
Load
32 bits loaded
9.5.2.2 Receive Repetitive Pattern Synchronization
Repetitive pattern synchronization synchronizes the receive pattern generator to the incoming repetitive pattern.
The receive pattern generator is synchronized by searching each incoming data stream bit position for the
repetitive pattern, and then checking the next 32 data stream bits. Synchronization is achieved if all 32 bits match
the incoming pattern. If at least six incoming bits in the current 64-bit window do not match the receive PRBS
pattern generator, automatic pattern resynchronization is initiated. Automatic pattern resynchronization can be
disabled by setting BERT.CR:APRD = 1. Pattern resynchronization can also be initiated manually by a zero-to-one
transition of the Manual Pattern Resynchronization bit (BERT.CR:MPR). The incoming data stream can be inverted
before comparison with the receive pattern generator by setting BERT.CR:RPIC.
See Figure 9-9 for the repetitive pattern synchronization state diagram.
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Figure 9-9. Repetitive Pattern Synchronization State Diagram
Sync
1 bit error
Verify
Match
Pattern Matches
9.5.2.3 Receive Pattern Monitoring
Receive pattern monitoring monitors the incoming data stream for both an OOS condition and bit errors and counts
the incoming bits. An out-of-synchronization (BERT.SR:OOS = 1) condition is declared when the synchronization
state machine is not in the “Sync” state. An OOS condition is terminated when the synchronization state machine is
in the “Sync” state. A change of state of the OOS status bit sets the BERT.SRL:OOSL latched status bit and can
cause an interrupt if enabled by BERT.SRIE:OOSIE.
Bit errors are determined by comparing the incoming data stream bit to the receive pattern generator output. If the
two bits do not match, a bit error is declared (BERT.SRL:BEL = 1), and the bit error and bit counts are incremented
(BERT.RBECR and BERT.RBCR, respectively). If the two bits do match, only the bit count is incremented. The bit
count and bit error count are not incremented when an OOS condition exists. The setting of the BEL status bit can
cause an interrupt if enabled by BERT.SRIE:BEIE.
9.5.3 Transmit Pattern Generation
The pattern generator generates the outgoing test pattern. The transmit pattern generator is a 32-bit shift register
that shifts data from the least significant bit (LSB) or bit 1 to the most significant bit (MSB) or bit 32. The input to bit
1 is the feedback. For a PRBS pattern (generating polynomial xn + xy + 1), the feedback is an XOR of bit n and bit
y. For a repetitive pattern (length n), the feedback is bit n. The values for n and y are individually programmable (1
to 32 with y < n) in the BERT.PCR:PLF and PTF fields. The output of the receive pattern generator is the feedback.
If QRSS is enabled (BERT.PCR:QRSS = 1), the feedback is forced to be an XOR of bits 17 and 20, and the output
is forced to one if the next 14 bits are all zeros. For PRBS and QRSS patterns, the feedback is forced to one if bits
1 through 31 are all zeros. When a new pattern is loaded, the pattern generator is loaded with a seed/pattern value
before pattern generation starts. The seed/pattern value is programmable (0 – 2n - 1) in the BERT.SPR registers.
The generated pattern can be inverted by setting BERT.CR:TPIC.
9.5.3.1 Transmit Error Insertion
Errors can be inserted into the generated pattern one at a time or at a rate of one out of every 10n bits. The value of
n is programmable (1 to 7 or off) in the BERT.TEICR:TEIR[2:0] configuration field. Single bit error insertion is
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enabled by setting BERT.TEICR:BEI and can be initiated from the microprocessor interface or by the manual error
insertion pin (GPIOB2). See Section 9.7.5 for more information about manual error insertion.
9.6 Loopbacks
Each LIU has three internal loopbacks. See Figure 5-1. When the hardware interface is enabled (IFSEL = 00X),
loopbacks are controlled by the LBn[1:0]. When a microprocessor interface is enabled (IFSEL≠00X), loopbacks are
controlled by the LB[1:0] and LBS fields in the PORT.CR3 register.
Analog loopback (ALB) connects the outgoing transmit signal back to the receiver’s analog front end. During ALB
the transmit signal is output normally on TXP/TXN, but the received signal on RXP/RXN is ignored.
Line loopback (LLB) connects the output of the receiver to the input of the transmitter. The LLB path does not
include the B3ZS/HDB3 decoder and encoder so that the signal looped back is exactly the same as the signal
received, including bipolar violations and code violations. During LLB, recovered clock and data are output on
RCLK, RPOS/RDAT, and RNEG/RLCV, but the TPOS/TDAT and TNEG pins are ignored.
Diagnostic loopback (DLB) connects the TCLK, TPOS/TDAT and TNEG pins to the RCLK, RPOS/RDAT, and
RNEG/RLCV pins. During DLB (with LLB disabled), the signal on TXP/TXN can be the normal transmit signal or an
AIS signal from the AIS generator. In microprocessor interface mode DLB and LLB can be enabled simultaneously
to provide simultaneous remote and local loopbacks.
9.7 Global Resources
9.7.1 Clock Rate Adapter (CLAD)
The CLAD is used to create multiple transmission-quality reference clocks from a single transmission-quality
(±20ppm, low jitter) clock input on the REFCLK pin. The LIUs in the device need up to three different reference
clocks (DS3, E3, and STS-1) for use by the CDRs and jitter attenuators. Given one of these clock rates or any of
several other clock frequencies on the REFCLK pin, the CLAD can generate all three LIU reference clocks. The
internally generated reference clock signals can optionally be driven out on pins CLKA, CLKB, and CLKC for
external use. In addition a fourth frequency, either 77.76 MHz or 19.44 MHz, can be generated and driven out on
the CLKD pin for use in Telecom Bus applications.
When the hardware interface is enabled (IFSEL = 00X), the CLAD is controlled by the CLADBYP pin, and the
REFCLK frequency is fixed at 19.44 MHz. When the CLADBYP pin is high all PLLs in the CLAD are bypassed and
powered down, and the REFCLK pin is ignored. In this mode the CLKA, CLKB, and CLKC pins become inputs, and
the DS3, E3 and STS-1 reference clocks, respectively, are sourced from these pins. Transmission-quality clocks
(±20ppm, low jitter) must be provided to these pins for each line rate required by the LIUs. When CLADBYP is low,
all four PLLs in the CLAD are enabled, and the generated DS3, E3, STS-1, and 77.76/19.44MHz clocks are always
output on CLKA, CLKB, CLKC and CLKD, respectively.
When a microprocessor interface is enabled (IFSEL≠00X), the CLAD clock mode and the REFCLK frequency are
set by the GLOBAL.CR2:CLAD[6:4] bits, as shown in Table 9-11. When CLAD[6:4] = 000, all PLLs in the CLAD are
bypassed and powered down, and the REFCLK pin is ignored. In this mode the CLKA, CLKB, and CLKC pins
become inputs, and the DS3, E3 and STS-1 reference clocks, respectively, are sourced from these pins.
Transmission-quality clocks (±20ppm, low jitter) must be provided to these pins for each line rate required by the
LIUs. CLAD[6:4] = 000 is equivalent to pulling the CLADBYP pin high in hardware interface mode. When
CLAD[6:4] ≠ 000, the PLL circuits are enabled as needed to generate the required clocks, as determined by the
CLAD[6:0] bits and the LIU mode bits (PORT.CR2:LM[1:0]). If a clock rate is not required as a reference clock, then
the PLL used to generate that clock is automatically disabled and powered down. The CLAD[3:0] bits are output
enable controls for CLKA, CLKB, CLKC and CLKD, respectively. Configuration bit GLOBAL.CR2:CLKD19 specifies
the frequency to be output on the CLKD pin (77.76MHz or 19.44MHz). Status register GLOBAL.SRL provides
activity status for the REFCLK, CLKA, CLKB and CLKC pins and lock status for the CLAD.
Each LIU block indicates the absence of the reference clock it requires by setting its LIU.SR:LOMC bit.
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Table 9-11. CLAD Clock Source Settings
CLAD[6:4]*
REFCLK
CLKA
CLKB
E3 input
CLKC
STS-1 input
CLKD
Low output
000
001
010
011
100
101
110
111
Don't Care
DS3 input
E3 input
DS3 input
DS3 output
DS3 output
DS3 output
E3 output
E3 output
E3 output
E3 output
E3 output
E3 output
E3 output
STS-1 output 77.76 or 19.44MHz output
STS-1 output 77.76 or 19.44MHz output
STS-1 output 77.76 or 19.44MHz output
STS-1 output 77.76 or 19.44MHz output
STS-1 output 77.76 or 19.44MHz output
STS-1 output 77.76 or 19.44MHz output
STS-1 output 77.76 or 19.44MHz output
STS-1 input
77.76MHz input DS3 output
19.44MHz input DS3 output
38.88MHz input DS3 output
12.80MHz input DS3 output
Table 9-12. CLAD Clock Pin Output Settings
CLAD[3:0]*
CLKA PIN
Low output
PLL-A output
—
—
—
—
—
—
CLKB PIN
CLKC PIN
CLKD PIN
XXX0
XXX1
XX0X
XX1X
X0XX
X1XX
0XXX
1XXX
—
—
—
—
—
—
—
—
—
—
—
—
Low output
PLL-B output
—
—
—
—
Low output
PLL-C output
—
—
Low output
PLL-D output
*When CLAD[6:4] = 000, CLKA, CLKB, and CLKC are inputs and CLKD is held low.
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9.7.2 One-Second Reference Generator
The one-second reference signal can be used to update performance monitoring registers on a precise one-
second interval. The generated internal signal is a 50% duty cycle signal that is divided down from the indicated
reference signal. The low to high edge on this signal sets the GLOBAL.SRL:1SREFL latched one-second bit, which
can generate an interrupt if enabled. The low to high edge is used to initiate a performance monitor register update
when GLOBAL.CR1:GPM[1:0] = 1X. The internal one-second reference can be output on the GPIOB3 pin by
setting GLOBAL.CR1:G1SROE. The source for the one-second reference is set by GLOBAL.CR1:G1SRS[2:0].
The DS3, E3 and STS-1 reference clocks are sourced from the CLAD, if the CLAD is configured to generate them,
or from the CLKA, CLKB and CLKC pins, respectively.
Table 9-13. Global One-Second Reference Source
G1SRS[2:0]
SOURCE
000
001
010
011
100
101
110
111
Disabled
DS3 reference clock
E3 reference clock
STS-1 reference clock
Port 1 TCLK
Port 2 TCLK
Port 3 TCLK
Port 4 TCLK
9.7.3 General-Purpose I/O Pins
When a microprocessor interface is enabled (IFSEL ≠ 00X), there are two general-purpose I/O (GPIO) pins
available per port, each of which can be used as a general-purpose input, general-purpose output, or loss-of-signal
output. In addition, GPIOB1, GPIOB2, and GPIOB3 can be used as a global I/O signal. The GPIO pins are
independently configurable using the GPIOynS fields of the GLOBAL.GIOCR register. When a GPIO pin is
configured as an input, its value can be read from the GLOBAL.GIORR register. When a GPIO pin is configured as
a loss-of-signal (LOS) status output, its state mimics the state of the LINE.RSR:RLOS status bit. When a port is
powered down and a GPIO pin has been programmed as an associated loss-of-signal output, the pin is held low.
Programming a GPIO pin as a global signal as shown in Table 9-14 overrides the I/O settings specified by the
GPIOynS field for that pin and configures the pin as an input or an output as shown in the Function column of
Table 9-14.
Table 9-14. GPIO Pin Global Signal Assignments
GLOBAL SIGNAL
PIN
FUNCTION
None
Global PMU input
Global TMEI input
G1SREF output
None
CONTROL BIT
—
GLOBAL.CR1.GPM[1:0]
GLOBAL.CR1.MEIMS
GLOBAL.CR1.G1SROE
—
GPIOAn
GPIOB1
GPIOB2
GPIOB3
GPIOB4
Note: n = 1 to 4.
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Table 9-15. GPIO Pin Control
GPIOynS[1:0]
FUNCTION
00
01
10
11
Input
Output LOS status for port n
Output logic 0
Output logic 1
Note: n = 1 to 4, y = A or B.
9.7.4 Performance Monitor Register Update
Each performance monitor counter can count at least one second of events before saturating at the maximum
count. Each counter has an associated status bit that is set when the counter value is not zero, a latched status bit
that is set when the counter value changes from zero to one, and a latched status bit that is set each time the
counter is incremented.
There is a holding register for each performance monitor counter that is updated when a performance monitoring
update is performed. A performance monitoring update causes the counter value to be loaded into the holding
register and the counter to be cleared. If a counter increment occurs at the exact same time as the counter reset,
the counter is loaded with a value of one, and the “counter is non-zero” latched status bit is set.
The Performance Monitor Update (PMU) signal initiates a performance monitoring update. The PMU signal can be
sourced from a general-purpose I/O pin (GPIOB1), the internal one-second reference, a global register bit
(GLOBAL.CR1:GPMU), or a port register bit (PORT.CR1:PMU). Note: The BERT PMU can be sourced from a
block level register bit (BERT.CR:LPMU). To use GPIOB1, GLOBAL.CR1.GPM[1:0] is set to 01, the appropriate
PORT.CR1:PMUM bits are set to 1, and the appropriate BERT.CR:PMUM bits are set to 1. To use the internal one-
second reference, GLOBAL.CR1:GPM[1:0] is set to 1X, the appropriate PORT.CR1:PMUM bits are set to 1, and
the appropriate BERT.CR:PMUM bits are set to 1. To use the global PMU register bit, GLOBAL.CR1:GPM[1:0] is
set to 00, the appropriate PORT.CR1:PMUM bits are set to 1, and the appropriate BERT.CR:PMUM bits are set to
1. To use the port PMU register bit, the associated PORT.CR1:PMUM bit is set to 0, and the appropriate
BERT.CR:PMUM bits are set to 1. To use the BERT.CR:LPMU register bit, the appropriate BERT.CR:PMUM bit is
set to 0.
When using the global or port PMU register bits, the PMU bit should be set to initiate the process and cleared when
the associated PMS status bit (GLOBAL.SR:GPMS or PORT.SR:PMS) is set. When using the GPIO pin or internal
one-second reference, the PMS bit is set shortly after the signal goes high, and cleared shortly after the signal
goes low. The PMS has an associated latched status bit that can generate an interrupt if enabled. The port PMS
signal does not go high until an update of all the appropriately configured block-level performance monitoring
counters in the port has been completed. The global PMS signal does not go high until an update of all the
appropriately configured port-level performance monitoring counters in the entire chip has been completed.
9.7.5 Transmit Manual Error Insertion
Various types of errors can be inserted in the transmit data stream using the Transmit Manual Error Insertion
(TMEI) signal, which can be sourced from a block-level register bit, a port register bit (PORT.CR1:TMEI), a global
register bit (GLOBAL.CR1:TMEI), or a general-purpose I/O pin (GPIOB2). To use GPIOB2 as the TMEI signal,
GLOBAL.CR1.MEIMS is set to 1, the appropriate PORT.CR1.MEIMS bits are set to 1, and the appropriate block-
level MEIMS bits are set to 1. To use the global TMEI register bit, GLOBAL.CR1.MEIMS is set to 0, the appropriate
PORT.CR1.MEIMS bits are set to 1, and the appropriate block-level MEIMS bits are set to 1. To use the port TMEI
register bit, the associated PORT.CR1.MEIMS is set to 0 and the appropriate block-level MEIMS bits are set to 1.
To use the block-level TSEI register bit, the associated block-level MEIMS bit is set to 0.
In order for an error of a particular type to be inserted, the error type must be enabled by setting the associated
error insertion enable bit in the associated block's error insertion register. Once enabled, a single error is inserted
at the next opportunity when the TMEI signal transitions from zero to one. Note: If the TMEI signal has multiple
zero to one transitions between error insertion opportunities, only a single error is inserted.
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9.8 8-/16-Bit Parallel Microprocessor Interface
See Table 12-6 and Figure 12-3 through Figure 12-10 for parallel interface timing diagrams and parameters.
9.8.1 8-Bit and 16-Bit Bus Widths
When the IFSEL pins are set to 1XX the device presents a parallel microprocessor interface. In 8-bit modes (IFSEL
= 10X), the address is composed of all the address bits including A[0], the lower 8 data lines D[7:0] are used, and
the upper 8 data lines D[15:8] are disabled (high impedance). In 16-bit modes (IFSEL = 11X), the address does not
include A[0], and all 16 data lines D[15:0] are used.
9.8.2 Byte Swap Mode
In 16-bit modes (IFSEL = 11X) the microprocessor interface can operate in byte swap mode. The BSWAP pin is
used to determine whether byte swapping is enabled. This pin should be static and not change during operation.
When the BSWAP pin is low the upper register bits REG[15:8] are mapped to the upper external data bus lines
D[15:8], and the lower register bits REG[7:0] are mapped to the lower external data bus lines D[7:0]. When the
BSWAP pin is high the upper register bits REG[15:8] are mapped to the lower external data bus lines D[7:0], and
the lower register bits REG[7:0] are mapped to the upper external data bus lines D[15:8].
9.8.3 Read-Write and Data Strobe Modes
The processor interface can operate in either read-write strobe mode (also known as "Intel" mode) or data strobe
mode (also known as "Motorola" mode). When IFSEL = 1X0 the read-write strobe mode is enabled. In this mode a
negative pulse on RD performs a read cycle, and a negative pulse on WR performs a write cycle.
When IFSEL = 1X1 the data strobe mode is enabled. In this mode a negative pulse on DS when R/W is high
performs a read cycle, a negative pulse on DS when R/W is low performs a write cycle..
9.8.4 Multiplexed and Nonmultiplexed Operation
In all parallel interface modes the interface supports both multiplexed and nonmultiplexed operation. For
multiplexed operation in 8-bit modes, wire A[9:8] to the processor’s A[9:8] pins, wire A[7:0] to D[7:0] and to the
processor’s multiplexed address/data bus, and connect the ALE pin to the appropriate pin on the processor. For
nonmultiplexed 8-bit operation, wire ALE high and wire A[9:0] and D[7:0] to the appropriate pins on the processor.
For multiplexed operation in 16-bit modes, wire A[9:0] to D[9:0], wire D[15:0] to the CPU’s multiplexed address/data
bus, and connect the ALE pin to the appropriate pin on the processor. For nonmultiplexed 16-bit operation, wire
ALE high and wire A[9:0] and D[15:0] to the appropriate pins on the processor.
9.8.5 Clear-On-Read and Clear-On-Write Modes
The latched status register bits can be programmed to clear on a read access or clear on a write access. The
global control register bit GLOBAL.CR2.LSBCRE specifies the method used to clear all of the latched status
registers. When LSBCRE = 0, latched status register bits are cleared when written with a 1. When LSBCRE = 1,
latched status register bits are cleared when read.
The clear-on-write mode expects the user to use the following method: read the latched status register then write a
1 to the register bits to be cleared. This method is useful when multiple software tasks use the same latched status
register. Each task can clear the bits it uses without affecting any of the latched status bits used by other tasks.
The clear-on-read mode clears all latched status bits in a register automatically when the latched status register is
read. This method works well when no more than one software task uses any single latched status register. An
event that occurs while the associated latched status register is being read results in the associated latched status
bit being set after the read is completed.
9.8.6 Global Write Mode
When GLOBAL.CR2:GWRM = 1, a write to a register of any port, including a port not present on the device,
causes the data to be written to the same register in all the ports on the device. (On the DS32501 ports 2 through 4
are not present. On the DS32502 ports 3 through 4 are not present. On DS32503 port 4 is not present.) In this
mode register reads are not supported and result in undefined data.
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9.9 SPI Serial Microprocessor Interface
When the IFSEL pins are set to 01X the device presents an SPI interface on the CS, SCLK, SDI, and SDO pins.
SPI is a widely-used master/slave bus protocol that allows a master device and one or more slave devices to
communicate over a serial bus. The DS3250x is always a slave device. Masters are typically microprocessors,
ASICs or FPGAs. Data transfers are always initiated by the master device, which also generates the SCLK signal.
The DS3250x receives serial data on the SDI pin and transmits serial data on the SDO pin. SDO is high-
impedance except when the DS3250x is transmitting data to the bus master. Note that the ALE pin must be wired
high for proper operation of the SPI interface.
Bit Order. When IFSEL[2:0] = 010 the register address and all data bytes are transmitted MSB first on both SDI
and SDO. When IFSEL[2:0] = 011, the register address and all data bytes are transmitted LSB first on both SDI
and SDO. The Motorola SPI convention is MSB first.
Clock Polarity and Phase. The CPOL pin defines the polarity of SCLK. When CPOL = 0, SCLK is normally low
and pulses high during bus transactions. When CPOL = 1, SCLK is normally high and pulses low during bus
transactions. The CPHA pin sets the phase (active edge) of SCLK. When CPHA = 0, data is latched in on SDI on
the leading edge of the SCLK pulse and updated on SDO on the trailing edge. When CPHA = 1, data is latched in
on SDI on the trailing edge of the SCLK pulse and updated on SDO on the following leading edge. See Figure
9-10.
Device Selection. Each SPI device has its own chip-select line. To select the DS3250x, pull its CS pin low.
Control Word. After CS is pulled low, the bus master transmits the control word during the first 16 SCLK cycles. In
MSB-first mode the control word has the form:
R/W A13 A12 A11 A10 A9 A8 A7
A6 A5 A4 A3 A2 A1 A0 BURST
where A[13:0] is the register address, R/W is the data direction bit (1 = read, 0 = write), and BURST is the burst bit
(1 = burst access, 0 = single-byte access). In LSB-first mode the order of the 14 address bits is reversed. In the
discussion that follows, a control word with R/W = 1 is a read control word, while a control word with R/W = 0 is a
write control word. Note: The address range of the DS32504 is 000h–3FFh, therefore, A[13:10] are ignored.
Single-Byte Writes. See Figure 9-11. After CS goes low, the bus master transmits a write control word with
BURST = 0 followed by the data byte to be written. The bus master then terminates the transaction by pulling CS
high.
Single-Byte Reads. See Figure 9-11. After CS goes low, the bus master transmits a read control word with
BURST = 0. The DS3250x then responds with the requested data byte. The bus master then terminates the
transaction by pulling CS high.
Burst Writes. See Figure 9-11. After CS goes low, the bus master transmits a write control word with BURST = 1
followed by the first data byte to be written. The DS3250x receives the first data byte on SDI, writes it to the
specified register, increments its internal address register, and prepares to receive the next data byte. If the master
continues to transmit, the DS3250x continues to write the data received and increment its address counter. After
the address counter reaches 3FFh it rolls over to address 000h and continues to increment.
Burst Reads. See Figure 9-11. After CS goes low, the bus master transmits a read control word with BURST = 1.
The DS3250x then responds with the requested data byte on SDO, increments its address counter, and prefetches
the next data byte. If the bus master continues to demand data, the DS3250x continues to provide the data on
SDO, increment its address counter, and prefetch the following byte. After the address counter reaches 3FFh it
rolls over to address 000h and continues to increment.
Early Termination of Bus Transactions. The bus master can terminate SPI bus transactions at any time by
pulling CS high. In response to early terminations, the DS3250x resets its SPI interface logic and waits for the start
of the next transaction. If a write transaction is terminated prior to the SCLK edge that latches the LSB of a data
byte, the current data byte is not written.
Design Option: Wiring SDI and SDO Together. Because communication between the bus master and the
DS3250x is half-duplex, the SDI and SDO pins can be wired together externally to reduce wire count. To support
this option, the bus master must not drive the SDI/SDO line when the DS3250x is transmitting.
AC Timing. See Table 12-9 and Figure 12-11 for AC timing specifications for the SPI interface.
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Figure 9-10. SPI Clock Polarity and Phase Options
CS
SCK
CPOL = 0, CPHA = 0
SCK
CPOL = 0, CPHA = 1
SCK
CPOL = 1, CPHA = 0
SCK
CPOL = 1, CPHA = 1
SDI/SDO
MSB
6
5
4
3
2
1
LSB
CLOCK EDGE USED FOR DATA CAPTURE (ALL MODES)
Figure 9-11. SPI Bus Transactions
Single-Byte Write
CS
W
R/
Register Address Burst Data Byte
SDI
0 (Write)
0 (single-byte)
SDO
Single-Byte Read
CS
W
R/
Register Address Burst
SDI
1 (Read)
0 (single-byte)
SDO
Data Byte
Burst Write
CS
W
R/
Register Address Burst Data Byte 1
Data Byte N
SDI
0 (Write)
1 (burst)
SDO
Burst Read
CS
W
R/
Register Address Burst
SDI
1 (Read)
1 (burst)
Data Byte 1
Data Byte N
SDO
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9.10 Interrupt Structure
The interrupt structure is designed to efficiently guide the user to the source of an interrupt. The status bits in the
global interrupt status register (GLOBAL.ISR) are read to determine if the interrupt source comes from a global
event, such as a one-second timer interrupt, or one of the ports. If the interrupt source is a global event, the global
status register is read (GLOBAL.SRL) to determine the source. If the interrupt source is a port, the port interrupt
status register (PORT.ISR) is read to determine if the interrupt source comes from a port event, such as a
performance monitor update interrupt, or one of the functional blocks inside the port. If the interrupt source is a port
event, the port status register is read (PORT.SRL) to determine the source. If the interrupt source is from a
functional block inside the port, the associated block's status register is read to determine the source. The source
of an interrupt can be determined by reading no more than three 16-bit registers.
Once the interrupt source has been determined, the interrupt can be cleared by either reading or writing the latched
status register (see Section 9.8.5). An alternate method for clearing an interrupt is to disable the interrupt at the bit,
block, port, or global level by writing a zero to the associated interrupt enable bit. Note: Disabling the interrupt at
the block, port, or global level disables all interrupts sources at or below that level.
Figure 9-12. Interrupt Signal Flow
PORT LATCHED
STATUS REGISTER
AND INTERRUPT
ENABLE REGISTER
GLOBAL LATCHED
STATUS REGISTER
AND INTERRUPT
ENABLE REGISTER
PORT.SRL bit
PORT.SRIE bit
GLOBAL.SRL bit
GLOBAL.SRIE bit
GLOBAL INTERRUPT
STATUS REGISTER
AND INTERRUPT
ENABLE REGISTER
PORT.SRL bit
PORT.SRIE bit
GLOBAL.SRL bit
GLOBAL.SRIE bit
GLOBAL.ISR bit
GLOBAL.ISRIE bit
GLOBAL.ISRIE bit
GLOBAL.ISR bit
INT*
PORT.ISR bit
block SRL bit
block SRIE bit
PORT.ISRIE bit
PORT.ISRIE bit
PORT.ISR bit
block SRL bit
block SRIE bit
PORT INTERRUPT
STATUS REGISTER
AND INTERRUPT
BLOCK LATCHED
STATUS REGISTER
AND INTERRUPT
ENABLE REGISTER
ENABLE REGISTER
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9.11 Reset and Power-Down
When the hardware interface is enabled (IFSEL = 00X), the device can be reset via the RST pin. The transmitters
of all ports can be powered down using the TPD pin, while the receivers of all ports can be powered down using
the RPD pin.
When a microprocessor interface is enabled (IFSEL ≠ 00X), the device presents a number of reset and power-
down options. The device can be reset at a global level via the GLOBAL.CR1:RST bit or the RST pin, and at the
port level via the PORT.CR1:RST bit. Each port can be powered down via the PORT.CR1:TPD and RPD bits. The
JTAG logic is reset by the JTRST pin.
The external RST pin and the global reset bit (GLOBAL.CR1:RST) are combined to create an internal global reset
signal. The global reset signal resets all the status and control registers on the chip (except the GLOBAL.CR1:RST
bit), to their default values. It also resets all flip-flops in the global logic (including the CLAD block) and port logic to
their reset values. The GLOBAL.CR1:RST bit stays set after a one is written to it. It is reset to zero when a zero is
written to it or when the external RST pin is active.
At the port level, the global reset signal combines with the port reset bit (PORT.CR1:RST) to create a port reset
signal. The port reset signal resets all the status and control registers in the port (except PORT.CR1:RST bit) to
their default values. It also resets all flip-flops in the port logic to their reset values. The port reset bit
(PORT.CR1:RST) stays set after a one is written to it. It is reset to zero when a zero is written to it or when the
global reset signal is active.
The data path reset (RSTDP) resets all of the same registers and flip-flops as the “general” reset (RST), except for
the control registers. This allows the device to be programmed while the data path logic is in reset. It is
recommended that a port be placed in data path reset during configuration changes.
The global data path reset bit (GLOBAL.CR1:RSTDP) is set to one when the global reset signal is active. This bit is
cleared when a zero is written to it while the global reset signal is inactive. The global data path reset resets all of
the data path registers and flip-flops on the chip.
The port data path reset bit (PORT.CR1:RSTDP) is set to one when the port reset signal is active. It is cleared
when a zero is written to it while the port reset signal is inactive. The port data path reset resets all of the port logic
data path registers and flip-flops.
Table 9-16. Reset and Power-Down Sources
REGISTER BITS
PIN
INTERNAL SIGNALS
Tx
GLOBAL.CR1
PORT.CR1
GLOBAL
Rx
PORT
PORT
DATA
GLOBAL DATA
PORT
PORT
RST
RSTDP
RST
TPD RPD
RSTDP
RST
RESET
PATH
RESET POWER- POWER- PATH
DOWN DOWN RESET
RESET
0
1
1
1
1
1
1
1
1
F0
1
F1
F1
1
F0
F0
0
F1
F1
F1
F1
0
1
1
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
1
1
0
1
1
1
0
0
0
1
1
0
1
1
0
1
0
0
1
1
1
1
1
0
0
1
0
F1
0
F1
0
0
0
0
1
F1
1
F1
1
F1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
Register bit states: F0 = forced to 0, F1 = forced to 1, 0 = set to 0, 1 = set to 1.
The reset signals in the device are asserted asynchronously and do not require a clock to put the logic into the
reset state. The control registers do not require a clock to come out of the reset state, but all other logic does
require a clock to come out of the reset state.
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The port transmit power-down function (PORT.CR1:TPD) disables all of the transmit clocks and powers down the
transmit LIU to minimize power consumption. The port receive power-down function (PORT.CR1:RPD) disables all
of the receive clocks and powers down the receive LIU to minimize power consumption. The one-second timer
circuit can be powered down by disabling its reference clock. The CLAD can be powered down by disabling it
(setting GLOBAL.CR2:CLAD[6:0] = 0). The global logic cannot be powered down.
After a global reset, all of the control and status registers in all ports are set to their default values and all the other
flip-flops are reset to their reset values. The global data path reset (GLOBAL.CR1:RSTDP), all the port data path
resets (PORT.CR1:RSTDP), and all the port power-down (PORT.CR1:TPD and RPD) bits are set after the global
reset. A valid initialization sequence is to clear the port power-down bits in the ports that are to be active, write to all
of the configuration registers to set them in the desired modes, then clear the GLOBAL.CR1:RSTDP and
PORT.CR1:RSTDP bits. This causes all the logic to start up in a predictable manner. The device can also be
initialized by clearing the GLOBAL.CR1:RSTDP, PORT.CR1:RSTDP, and PORT.CR1:TPD and RPD bits, then
writing to all of the configuration registers to set them in the desired modes, and then clearing all of the latched
status bits. This second initialization scheme can cause the device to operate unpredictably for a brief period of
time.
Some of the I/O pins are put into a known state at reset. At the global level, the microprocessor interface output
and I/O pins (D[15:0]) are forced into the high impedance state when the RST pin is active, but not when the
GLOBAL.CR1:RST bit is active. The CLAD clock pins CLKA, CLKB, and CLKC are forced to be the LIU reference
clock inputs. The general-purpose I/O pins (GPIOAn & GPIOBn) are forced to be inputs until after the RST pin is
deasserted. At the port level, the LIU transmitter outputs TXP and TXN are forced into a high impedance state.
Note: Setting any of the reset (RST), data path reset (RSTDP), or power-down (TPD, RPD) bits for less than 100ns
can result in the associated circuits coming up in a random state. When a power-down bit is cleared, it takes
approximately 1ms for all the associated circuits to power-up.
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10. REGISTER MAPS AND DESCRIPTIONS
10.1 Overview
When a microprocessor interface is enabled (IFSEL[2:0] ≠ 00X), the registers described in this section are
accessible. The overall memory map is shown in Table 10-1. The DS32504 register map covers the address range
of 000 to 3FFh. Address line A[9] is not present on the DS32503 and DS32502. On the DS32502, writes into the
address space for LIU3 are ignored, and reads from these addresses return 00h. On the DS32501, address lines
A[9:8] are not present, and writes into the address space for LIU[2:4] are ignored, and reads from these addresses
return 00h. The address LSB A[0] is used to address the upper and lower bytes of a register in 8-bit mode, and to
swap the upper and lower bytes in 16-bit mode.
In each register, bit 15 is the MSB and bit 0 is the LSB. Register addresses not listed and bits marked “—“ are
reserved and must be written with 0 and ignored when read. Writing other values to these registers may put the
device in a factory test mode resulting in undefined operation. Bits labeled “0” or “1” must be written with that value
for proper operation. Register fields with underlined names are read-only fields; writes to these fields have no
effect. All other fields are read-write. Register fields are described in detail in the register descriptions in Sections
10.3 through 10.8.
10.1.1 Status Bits
The device has two types of status bits. Real-time status bits are read-only and indicate the state of a signal at the
time it is read. Latched status bit are set when the associated event occurs and remain set until cleared. Once
cleared, a latched status bit is not set again until the associated event recurs (goes away and comes back). A
latched-on-change bit is a latched status bit that is set when the event occurs and when it goes away. A latched
status bit can be cleared using either a clear-on-read or clear-on-write method (see Section 9.8.5). For clear-on-
read, all latched status bits in a latched status register are cleared when the register is read. In 16-bit mode, all 16
latched status bits are cleared. In 8-bit mode, only the eight bits read are cleared. For clear-on-write, a latched bit in
a latched status register is cleared when a logic 1 is written to that bit. For example, writing FFFFh to a 16-bit
latched status register clears all latched status bits in the register, whereas writing 0001h only clears bit 0 of the
register. When set, some latched status bits can cause an interrupt request if enabled to do so by corresponding
interrupt enable bits.
10.1.2 Configuration Fields
Configuration fields are read-write. During reset, each configuration field reverts to the default value shown in the
register definition. Configuration register bits marked “—“ are reserved and must be written with 0. Configuration
registers and bits can be written to and read from during a data path reset, however, all changes to these bits are
ignored during the data path reset. As a result, all bits requiring a 0 to 1 transition to initiate an action must have the
transition occur after the data path reset has been removed. See Section 9.11 for more information about resets
and data path resets.
10.1.3 Counters
All counters stop counting at their maximum count. A counter register is updated by asserting (low to high
transition) the performance monitoring update signal (PMU). During a counter register update, the performance
monitoring status signal (PMS) is deasserted. A counter register update consists of loading the counter register
with the current count, resetting the counter, resetting the zero count status indication, and then asserting PMS. No
events are missed during an update. See Section 9.7.4 for more information about performance monitor register
updates.
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10.2 Overall Register Map
Table 10-1. Overall Register Map
BASE
BLOCK
ADDRESS
000h
080h
100h
180h
200h
Global Registers
Port Registers for Port 1
Port Registers for Port 2
Port Registers for Port 3
Port Registers for Port 4
Table 10-2. Port Registers
ADDRESS
OFFSET
REGISTER
Port Common Registers
LIU Registers
BLOCK
00h–1Fh
20h–2Fh
30h–3Fh
40h–4Fh
50h–6Fh
70h–7Fh
PORT
LIU
B3ZS/HDB3 Encoder Registers
B3ZS/HDB3 Decoder Registers
BERT Registers
LINE Tx
LINE Rx
BERT
—
Reserved
Note: The address offsets given in this table are offsets from port base addresses shown in Table 10-1.
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10.3 Global Registers
Table 10-3. Global Register Map
ADDRESS
REGISTER
OFFSET
DESCRIPTION
000h
002h
004h
GLOBAL.IDR
GLOBAL.CR1
GLOBAL.CR2
—
GLOBAL.GIOCR
—
GLOBAL.ISR
GLOBAL.ISRIE
—
GLOBAL.SR
GLOBAL.SRL
GLOBAL.SRIE
—
ID Register
Global Control Register 1
Global Control Register 2
Unused
General-Purpose I/O Control Register
Unused
Global Interrupt Status Register
Global Interrupt Enable Register
Unused
Global Status Register
Global Status Register Latched
Global Status Register Interrupt Enable
Unused
006h–00Eh
010h
012h–01Eh
020h
022h
024h–026h
028h
02Ah
02Ch
02Eh–06h
038h
03Ah–07Eh
GLOBAL.GIORR
—
General-Purpose I/O Read Register
Unused
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Register Name:
Register Description:
Register Address:
GLOBAL.IDR
ID Register
000h
Bit #
15
14
13
12
11
10
9
8
Name
ID15
ID14
ID13
ID12
ID11
ID10
ID9
ID8
Bit #
7
6
5
4
3
2
1
0
Name
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
Bits 15 to 12: Device REV ID (ID[15:12]). These bits of the device ID register have the same information as the
four bits of the JTAG REV ID portion of the JTAG ID register, JTAG ID[31:28]. See Section 11.
Bits 11 to 0: Device CODE ID (ID[11:0]). These bits of the device ID register have the same information as the 12
bits of the JTAG CODE ID portion of the JTAG ID register, JTAG ID[23:12]. See Section 11.
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Register Name:
Register Description:
Register Address:
GLOBAL.CR1
Global Control Register 1
002h
Bit #
Name
Default
15
—
0
14
—
0
13
—
0
12
—
0
11
0
10
G1SRS[2:0]
0
9
0
8
G1SROE
0
Bit #
Name
Default
7
TMEI
0
6
MEIMS
0
5
0
4
0
3
GPMU
0
2
—
0
1
RSTDP
1
0
RST
0
GPM[1:0]
Bits 11 to 9: Global One-Second Reference Source (G1SRS[2:0]). These bits determine the source for the internally
generated one-second reference. The source is selected from one of the CLAD clocks or from one of the port transmit
clocks. See Section 9.7.2.
000 = Disabled
100 = Port 1 TCLK
101 = Port 2 TCLK
110 = Port 3 TCLK
111 = Port 4 TCLK
001 = DS3 reference clock
010 = E3 reference clock
011 = STS-1 reference clock
Bit 8: Global One-Second Reference Output Enable (G1SROE). This bit determines whether the GPIOB3 pin is used
to output the global one-second reference signal. See Section 9.7.2.
0 = GPIOB3 pin mode selected by GLOBAL.GIOCR:GIOB3S[1:0]
1 = GPIOB3 outputs the global one-second reference signal specified by GLOBAL.CR1:G1SRS[2:0]
Bit 7: Transmit Manual Error Insert (TMEI). When GLOBAL.CR1:MEIMS = 0, this bit is used to insert errors in all
blocks in all ports where block level MEIMS = 1 and PORT.CR1:MEIMS = 1. Error(s) are inserted at the next opportunity
after this bit transitions from low to high. See Section 9.7.5. Note: This bit should be set low immediately after each error
insertion.
Bit 6: Manual Error Insert Mode Select (MEIMS). This bit specifies the source of the manual error insertion signal for all
block-level error generators that have block-level MEIMS = 1 and PORT.CR1:MEIMS = 1. See Section 9.7.5.
0 = Global error insertion using GLOBAL.CR1:TMEI bit
1 = Global error insertion using the GPIOB2 pin
Bits 5 and 4: Global Performance Monitor Update Mode (GPM[1:0]). These bits specify the source of the
performance monitoring update signal for all blocks that have block-level PMUM = 1 and PORT.CR1:PMUM = 1. See
Section 9.7.4.
00 = Global PM update using the GLOBAL.CR1:GPMU bit
01 = Global PM update using the GPIOB1 pin
1X = One-second PM update using the internal one-second counter (see Section 9.7.2)
Bit 3: Global Performance Monitor Register Update (GPMU). When GLOBAL.CR1:GPM[1:0] = 00, this bit is used to
update all of the performance monitor registers where block-level PMUM = 1 and PORT.CR1:PMUM = 1. When this bit
transitions from low to high, all configured performance monitoring registers are updated with the latest counter value,
and all associated counters are reset. This bit should remain high until the performance monitor update status bit
(GLOBAL.SR:GPMS) goes high, and then it should be brought back low, which clears the GPMS status bit. If a counter
increment occurs at the exact same time as the counter reset, the counter is loaded with a value of one, and the “counter
is non-zero” latched status bit is set. See Section 9.7.4.
Bit 1: Reset Data Path (RSTDP). When this bit is set, it forces all of the internal data path and status registers in all ports
to their default state. This bit must be set high for a minimum of 100ns. See Section 9.11.
0 = Normal operation
1 = Force all data path registers to their default values
Bit 0: Reset (RST). When this bit is set, all of the internal data path and status and control registers (except this RST bit),
on all of the ports, are reset to their default state. This bit must be set high for a minimum of 100ns. This bit is logically
ORed with the inverted hardware signal RST. See Section 9.11.
0 = Normal operation
1 = Force all internal registers to their default values
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Register Name:
Register Description:
Register Address:
GLOBAL.CR2
Global Control Register 2
004h
Bit #
Name
Default
15
—
0
14
0
13
0
12
0
11
CLAD[6:0]
0
10
0
9
0
8
0
Bit #
Name
Default
7
—
0
6
—
0
5
CLKD19
0
4
INTM
0
3
—
0
2
—
0
1
LSBCRE
0
0
GWRM
0
Bits 14 to 8: CLAD I/O Mode (CLAD[6:0]). These bits control the CLAD clock I/O pins REFCLK, CLKA, CLKB, CLKC
and CLKD. See Table 9-11 and Table 9-12 in Section 9.7.1.
Bit 5: CLKD Frequency is 19.44MHz (CLKD19). This bit specifies the frequency to be output on CLKD when the
CLAD[3] configuration bit is high.
0 = 77.76MHz
1 = 19.44MHz
Bit 4: INT pin mode (INTM). This bit determines the inactive mode of the INT pin. The INT pin always drives low when
an enabled interrupt source is active. See Section 9.10.
0 = Pin is high impedance when no enabled interrupts are active
1 = Pin drives high when no enabled interrupts are active
Bit 1: Latched Status Bit Clear on Read Enable (LSBCRE). This bit determines when the latched status register bits
are cleared. See Section 9.8.5.
0 = Latched status register bits are cleared on a write
1 = Latched status register bits are cleared on a read
Bit 0: Global Write Mode (GWRM). This bit enables the global write mode. When this bit is set, a write to a register of
any port causes a write to the same register in all the ports. In this mode register reads are not supported and result in
undefined data. See Section 9.8.6.
0 = Normal write mode
1 = Global write mode
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Register Name:
GLOBAL.GIOCR
Register Description:
Register Address:
General-Purpose I/O Control Register
010h
Bit #
Name
Default
15
14
0
13
12
0
11
10
0
9
8
0
0
GIOA4S[1:0]
GIOA3S[1:0]
GIOA2S[1:0]
GIOA1S[1:0]
0
7
0
0
5
0
0
3
0
0
1
0
Bit #
Name
Default
6
4
2
GIOB4S[1:0]
GIOB3S[1:0]
GIOB2S[1:0]
GIOB1S[1:0]
0
0
0
0
Note: See Section 9.7.3 for more information.
Bits 15 and 14: General-Purpose I/O A4 Select (GIOA4S[1:0]). These bits specify the function of the GPIOA4 pin.
00 = Input
01 = Output LOS status from port 4
10 = Output logic 0
11 = Output logic 1
Bits 13 and 12: General-Purpose I/O A3 Select (GIOA3S[1:0]). These bits specify the function of the GPIOA3 pin.
00 = Input
01 = Output LOS status from port 3
10 = Output logic 0
11 = Output logic 1
Bits 11 and 10: General-Purpose I/O A2 Select (GIOA2S[1:0]). These bits specify the function of the GPIOA2 pin.
00 = Input
01 = Output LOS status from port 2
10 = Output logic 0
11 = Output logic 1
Bits 9 and 8: General-Purpose I/O A1 Select (GIOA1S[1:0]). These bits specify the function of the GPIOA1 pin.
00 = Input
01 = Output LOS status from port 1
10 = Output logic 0
11 = Output logic 1
Bits 7 and 6: General-Purpose I/O B4 Select (GIOB4S[1:0]). These bits specify the function of the GPIOB4 pin.
00 = Input
01 = Output LOS status from port 4
10 = Output logic 0
11 = Output logic 1
Bits 5 and 4: General-Purpose I/O B3 Select (GIOB3S[1:0]). These bits specify the function of the GPIOB3 pin.
Note: If GLOBAL.CR1:G1SROE is set to 1, GPIOB3 is the global one-second reference output signal.
00 = Input
01 = Output LOS status from port 3
10 = Output logic 0
11 = Output logic 1
Bits 3 and 2: General-Purpose I/O B2 Select (GIOB2S[1:0]). These bits specify the function of the GPIOB2 pin.
Note: If GLOBAL.CR1:MEIMS is set to 1, GPIOB2 is the global transmit manual error insertion (TMEI) input signal.
00 = Input
01 = Output LOS status from port 2
10 = Output logic 0
11 = Output logic 1
Bits 1 and 0: General-Purpose I/O B1 Select (GIOB1S[1:0]). These bits specify the function of the GPIOB1 pin.
Note: If GLOBAL.CR1:GPM[1:0] is set to 01, GPIOB1 is the global performance monitoring update input signal.
00 = Input
01 = Output LOS status from port 1
10 = Output logic 0
11 = Output logic 1
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Register Name:
GLOBAL.ISR
Register Description:
Register Address:
Global Interrupt Status Register
020h
Bit #
Name
15
—
14
—
13
—
12
—
11
—
10
—
9
—
8
—
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
P4ISR
P3ISR
P2ISR
P1ISR
GSR
Bits 4 to 1: Port n Interrupt Status Register (PnISR). This bit is set when any of the bits in the port n interrupt status
register (PORT.ISR) are set and enabled for interrupt. When set, this bit causes an interrupt if GLOBAL.ISRIE:PnISRIE is
set. See Section 9.10.
Bit 0: Global Status Register (GSR). This bit is set when any of the latched status register bits in the global latched
status register (GLOBAL.SRL) are set and enabled for interrupt. When set, this bit causes an interrupt if
GLOBAL.ISRIE:GSRIE is set. See Section 9.10.
Register Name:
GLOBAL.ISRIE
Register Description:
Register Address:
Global Interrupt Status Register Interrupt Enable
022h
Bit #
Name
Default
15
—
0
14
—
0
13
—
0
12
—
0
11
—
0
10
—
0
9
—
0
8
—
0
Bit #
Name
Default
7
—
0
6
—
0
5
—
0
4
P4ISRIE
0
3
P3ISRIE
0
2
P2ISRIE
0
1
P1ISRIE
0
0
GSRIE
0
Bits 4 to 1: Port n Interrupt Status Register Interrupt Enable (PnISRIE). This bit is the interrupt enable for the
GLOBAL.ISR:PnISR status bit. See Section 9.10.
0 = mask the interrupt
1 = enable the interrupt
Bit 0: Global Status Register Interrupt Enable (GSRIE). This bit is the interrupt enable for the GLOBAL.ISR:GSR
status bit. See Section 9.10.
0 = mask the interrupt
1 = enable the interrupt
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Register Name:
Register Description:
Register Address:
GLOBAL.SR
Global Status Register
028h
Bit #
Name
Default
15
—
—
14
—
—
13
—
—
12
—
—
11
—
—
10
—
—
9
—
—
8
—
—
Bit #
Name
Default
7
—
—
6
—
—
5
—
—
4
—
—
3
—
—
2
CLOL
0
1
—
—
0
GPMS
0
Bit 2: CLAD Loss of Lock (CLOL). This bit is set when the CLAD is not locked to the reference frequency.
Bit 0: Global Performance Monitoring Update Status (GPMS). This bit is set when the PORT.SR:PMS status bits are
set in all of the ports that are enabled for global update control (i.e., all ports that have PORT.CR1:PMUM = 1). Ports that
have PORT.CR1:PMUM = 0 have no effect on this bit. In global software update mode, the global update request bit
(GLOBAL.CR1:GPMU) should be held high until this status bit goes high. See Section 9.7.4.
0 = The associated update request signal is low or not all register updates are completed
1 = The requested performance register updates are all completed
Register Name:
GLOBAL.SRL
Register Description:
Register Address:
Global Status Register Latched
02Ah
Bit #
Name
Default
15
—
—
14
—
—
13
—
—
12
—
—
11
—
—
10
—
—
9
—
—
8
—
—
Bit #
Name
Default
7
—
—
6
CLKCL
—
5
CLKBL
—
4
CLKAL
—
3
CLADL
—
2
CLOLL
—
1
G1SREFL
—
0
GPMSL
—
Bit 6: CLAD C Clock Activity Latched (CLKCL). This bit is set when the signal on the CLKC pin is active. Note: This bit
should always be low when GLOBAL.CR2:CLAD[6:4] ≠ 000. See Section 9.7.1.
Bit 5: CLAD B Clock Activity Latched (CLKBL). This bit is set when the signal on the CLKB pin is active. Note: This bit
should always be low when GLOBAL.CR2:CLAD[6:4] ≠ 000. See Section 9.7.1.
Bit 4: CLAD A Clock Activity Latched (CLKAL). This bit is set when the signal on the CLKA pin is active. Note: This bit
should always be low when GLOBAL.CR2:CLAD[6:4] ≠ 000. See Section 9.7.1.
Bit 3: CLAD Reference Clock Activity Status Latched (CLADL). This bit is set when the CLAD PLL reference clock
signal on the REFCLK pin is active. Note: When GLOBAL.CR2:CLAD[6:4] = 000, the REFCLK pin is unused. See
Section 9.7.1.
Bit 2: CLAD Loss of Lock Latched (CLOLL). This bit is set when the GLOBAL.SR:CLOL status bit transitions from low
to high.
Bit 1: Global One-Second Reference Status Latched (G1SREFL). This bit is set once each second when the internal
global one-second timer signal transitions low to high. When set, this bit causes an interrupt if interrupt enables
GLOBAL.SRIE:G1SREFIE and GLOBAL.ISRIE:GSRIE are both set. See Section 9.7.1.
Bit 0: Global Performance Monitoring Update Status Latched (GPMSL). This bit is set when the GLOBAL.SR:GPMS
status bit changes from low to high. When set, this bit causes an interrupt if interrupt enables GLOBAL.SRIE:GPMSIE
and GLOBAL.ISRIE:GSRIE are both set. See Section 9.7.1.
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Register Name:
GLOBAL.SRIE
Register Description:
Register Address:
Global Status Register Interrupt Enable
02Ch
Bit #
Name
Default
15
—
0
14
—
0
13
—
0
12
—
0
11
—
0
10
—
0
9
—
0
8
—
0
Bit #
Name
Default
7
—
0
6
—
0
5
—
0
4
—
0
3
—
0
2
CLOLIE
0
1
0
G1SREFIE GPMSIE
0
0
Bit 2: CLAD Loss of Lock Interrupt Enable (CLOLIE). This bit is the interrupt enable for the GLOBAL.SRL:CLOLL bit.
0 = mask the interrupt
1 = enable the interrupt
Bit 1: Global One-Second Reference Interrupt Enable (G1SREFIE). This bit is the interrupt enable for the
GLOBAL.SRL:G1SREFL bit.
0 = mask the interrupt
1 = enable the interrupt
Bit 0: Global Performance Monitoring Update Status Interrupt Enable (GPMSIE). This bit is the interrupt enable for
the GLOBAL.SRL: GPMSL bit.
0 = mask the interrupt
1 = enable the interrupt
Register Name:
GLOBAL.GIORR
Register Description:
Register Address:
General-Purpose I/O Read Register
038h
Bit #
Name
Default
15
—
—
14
—
—
13
—
—
12
—
—
11
—
—
10
—
—
9
—
—
8
—
—
Bit #
Name
Default
7
GPIOA4
—
6
GPIOA3
—
5
GPIOA2
—
4
GPIOA1
—
3
GPIOB4
—
2
GPIOB3
—
1
GPIOB2
—
0
GPIOB1
—
Bits 7 to 4: General-Purpose I/O An Status (GPIOAn). Indicates the status of general-purpose I/O pin An (GPIOAn).
See Section 9.7.3.
Bits 3 to 0: General-Purpose I/O Bn Status (GPIOBn). Indicates the status of general-purpose I/O pin Bn (GPIOBn).
See Section 9.7.3.
59 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
10.4 Port Common Registers
Table 10-4. Port Common Register Map
ADDRESS
REGISTER
OFFSET
DESCRIPTION
Port Control Register 1
Port Control Register 2
Port Control Register 3
Unused
Unused
Port I/O Invert Control Register
Unused
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
1Eh
PORT.CR1
PORT.CR2
PORT.CR3
—
—
PORT.INV
—
—
Unused
Port Interrupt Status Register
Unused
PORT.ISR
—
PORT.ISRIE Port Interrupt Status Register Interrupt Enable
—
Unused
Port Status Register
Port Status Register Latched
PORT.SR
PORT.SRL
PORT.SRIE Port Status Register Interrupt Enable
Unused
—
60 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
Register Name:
PORT.CR1
Register Description:
Register Address:
Port Control Register 1
n x 80h + 00h
Bit #
Name
Default
15
—
0
14
—
0
13
—
0
12
—
0
11
—
0
10
—
0
9
—
0
8
—
0
Bit #
Name
Default
7
TMEI
0
6
MEIMS
0
5
PMUM
0
4
PMU
0
3
TPD
1
2
RPD
1
1
RSTDP
1
0
RST
0
Bit 7: Transmit Manual Error Insert (TMEI). When PORT.CR1:MEIMS = 0, this bit is used to insert errors in all blocks
where block-level MEIMS = 1. Error(s) are inserted at the next opportunity after this bit transitions from low to high. See
Section 9.7.5. Note: This bit should be set low immediately after each error insertion.
Bit 6: Transmit Manual Error Insert Mode Select (MEIMS). This bit specifies the source of the error insertion signal for
all block-level error generators that have block-level MEIMS = 1. See Section 9.7.5.
0 = Port-level error insertion via PORT.CR1:TMEI
1 = Global error insertion as specified by GLOBAL.CR1:MEIMS
Bit 5: Port Performance Monitor Update Mode (PMUM). This bit specifies the source of the performance monitoring
update signal for all blocks that have block-level PMUM = 1. See Section 9.7.4.
0 = Port-level PM update via PORT.CR1:PMU
1 = Global PM update as specified by GLOBAL.CR1:GPM[1:0]
Bit 4: Port Performance Monitor Register Update (PMU). When PORT.CR1:PMUM = 0, this bit is used to update all of
the performance monitor registers where block-level PMUM = 1. When this bit transitions from low to high, all configured
performance monitoring registers are updated with the latest counter values, and all associated counters are reset. This
bit should remain high until the performance monitor update status bit (PORT.SR:PMS) goes high, and then it should be
brought back low, which clears the PMS status bit. If a counter increment occurs at the exact same time as the counter
reset, the counter is loaded with a value of one, and the “counter is non-zero” latched status bit is set. See Section 9.7.4.
Bit 3: Transmit Power-Down (TPD). When this bit is set, the transmit path of the port is powered down and considered
“out of service”. The digital logic is powered down by stopping the clocks. See Section 9.11.
0 = Normal operation
1 = Power down the port transmit path (TXP and TXN become high impedance)
Bit 2: Receive Power-Down (RPD). When this bit is set, the receive path of the port is powered down and considered
“out of service”. The digital logic is powered down by stopping the clocks. See Section 9.11.
0 = Normal operation
1 = Power down the port receive path (RPOS/RDAT, RNEG/RLCV, and RCLK become high
impedance)
Bit 1: Reset Data Path (RSTDP). When this bit is set, it forces all of the port’s internal data path and status registers to
their default state. This bit must be set high for a minimum of 100ns and then set back low. See Section 9.11.
0 = Normal operation
1 = Force all data path registers to their default values
Bit 0: Reset (RST). When this bit is set, all of the internal data path and status and control registers (except this RST bit)
of this port are reset to their default state. This bit must be set high for a minimum of 100ns. This bit is logically ORed with
the inverted hardware signal RST and the GLOBAL.CR1:RST bit. See Section 9.11.
0 = Normal operation
1 = Force all internal registers to their default values
61 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
Register Name:
PORT.CR2
Register Description:
Register Address:
Port Control Register 2
n x 80h + 02h
Bit #
Name
Default
15
—
0
14
—
0
13
—
0
12
—
0
11
—
0
10
—
0
9
—
0
8
—
0
Bit #
Name
Default
7
0
6
0
5
—
0
4
ROD
0
3
TBIN
0
2
RBIN
0
1
TCC
0
0
—
0
LM[1:0]
Bits 7 and 6: LIU Mode (LM[1:0]). These bits select the operating mode of the port. See Section 9.1.
00 = DS3
01 = E3
10 = STS-1
11 = reserved
Bit 4: Receive Output Disable (ROD). See Section 9.3.6.4.
0 = enable the receiver outputs
1 = disable the receiver outputs (RCLK, RPOS/RDAT and RNEG/RLCV)
Bit 3: Transmit Binary Interface Enable (TBIN). See Section 9.2.2.
0 = Transmitter framer interface is bipolar on the TPOS and TNEG pins. The B3ZS/HDB3 encoder is
disabled.
1 = Transmitter framer interface is binary on the TDAT pin. The B3ZS/HDB3 encoder is enabled.
Bit 2: Receive Binary Interface Enable (RBIN). See Section 9.3.6.
0 = Receiver framer interface is bipolar on the RPOS and RNEG pins. The B3ZS/HDB3 decoder is disabled.
1 = Receiver framer interface is binary on the RDAT pin with the RLCV pin indicating line-code violations. The
B3ZS/HDB3 encoder is enabled.
Bit 1: Transmit Common Clock Mode (TCC). See Section 9.2.1.1.
0 = Source transmit clock for port n from TCLKn
1 = Source transmit clock for port n from TCLK1
62 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
Register Name:
PORT.CR3
Register Description:
Register Address:
Port Control Register 3
n x 80h + 04h
Bit #
Name
Default
15
—
0
14
—
0
13
—
0
12
—
0
11
—
0
10
—
0
9
BERTE
0
8
BERTD
0
Bit #
Name
Default
7
SCRD
0
6
—
0
5
—
0
4
AIST
0
3
TAIS
0
2
LBS
0
1
0
0
LB[1:0]
0
Bit 9: BERT Enable (BERTE). See Section 9.5.
0 = disable the BERT pattern generator (the pattern detector is always enabled)
1 = enable the BERT pattern generator (the pattern detector is always enabled)
Bit 8: BERT Direction (BERTD). See Section 9.5.
0 = line direction (transmit to receive)
1 = system direction (receive to transmit)
Bit 7: STS-1 Scrambling Disable (SCRD). This bit controls STS-1 scrambling when AIS-L is generated in STS-1 mode.
See Section 9.2.4.
0 = Perform scrambling
1 = Do not perform scrambling
Bit 4: AIS Type (AIST). See Section 9.2.4.
0 = Unframed all ones
1 = Framed DS3 AIS (DS3 mode), unframed all ones (E3 mode), or AIS-L (STS-1 mode)
Bit 3: Transmit AIS (TAIS). The type of AIS signal depends on the LIU mode (DS3, E3 or STS-1) and the configured
AIS type. See Section 9.2.4.
0 = transmit normal data
1 = transmit AIS signal
Bit 2: Loopback Select (LBS). This bit affects the function of the Loopback Mode (LBM[1:0]) bits below.
Bits 1 and 0: Loopback Mode (LB[1:0]). These bits enable loopbacks. The effect of the LB = 11 decode is controlled by
the LBS configuration bit. See Section 9.6.
00 = No loopback
01 = Diagnostic Loopback (DLB)
10 = Line Loopback (LLB)
11 (LBS = 0) = Line Loopback (LLB) and Diagnostic Loopback (DLB) simultaneously
11 (LBS = 1) = Analog Loopback (ALB)
63 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
Register Name:
PORT.INV
Register Description:
Register Address:
Port I/O Invert Control Register
n x 80h + 0Ah
Bit #
Name
Default
15
—
0
14
—
0
13
—
0
12
—
0
11
—
0
10
—
0
9
—
0
8
—
0
Bit #
Name
Default
7
—
0
6
TNEGI
0
5
TPOSI
0
4
TCLKI
0
3
—
0
2
RNEGI
0
1
RPOSI
0
0
RCLKI
0
Bit 6: TNEG Invert (TNEGI). This bit inverts the TNEG input pin when set.
0 = Noninverted
1 = Inverted
Bit 5: TPOS/TDAT Invert (TPOSI). This bit inverts the TPOS/TDAT input pin when set.
0 = Noninverted
1 = Inverted
Bit 4: TCLK Invert (TCLKI). This bit inverts the TCLK pin input pin when set. See Section 9.2.1.
0 = Noninverted; TPOS/TDAT and TNEG are sampled on the rising edge of TCLK.
1 = Inverted; TPOS/TDAT and TNEG are sampled on the falling edge of TCLK.
Bit 2: RNEG/RLCV Invert (RNEGI). This bit inverts the RNEG/RLCV output pin when set.
0 = Noninverted
1 = Inverted
Bit 1: RPOS/RDAT Invert (RPOSI). This bit inverts the RPOS/RDAT output pin when set.
0 = Noninverted
1 = Inverted
Bit 0: RCLK Invert (RCLKI). This bit inverts the RCLKn output pin when set. See Section 9.3.6.3.
0 = Noninverted; RPOS/RDAT and RNEG/RLCV are updated on the falling edge of RCLK.
1 = Inverted; RPOS/RDAT and RNEG/RLCV are updated on the rising edge of RCLK.
64 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
Register Name:
PORT.ISR
Register Description:
Register Address:
Port Interrupt Status Register
n x 80h + 10h
Bit #
Name
15
—
14
—
13
—
12
—
11
—
10
—
9
—
8
—
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
—
LDSR
LIUSR
BSR
PSR
Bit 3: Line Decoder Status Register Interrupt Status (LDSR). This bit is set when any of the latched status register
bits in the B3ZS/HDB3 Line Decoder block are set and enabled for interrupt. When set, this bit causes an interrupt if
PORT.ISRIE:LDSRIE and GLOBAL.ISRIE:PnISRIE are both set. See Section 9.10.
Bit 2: LIU Status Register Interrupt Status (LIUSR). This bit is set when any of the latched status register bits in the
LIU block are set and enabled for interrupt. When set, this bit causes an interrupt if PORT.ISRIE:LIUSRIE and
GLOBAL.ISRIE: PnISRIE are both set. See Section 9.10.
Bit 1: BERT Status Register Interrupt Status (BSR). This bit is set when any of the latched status register bits in the
BERT block are set and enabled for interrupt. When set, this bit causes an interrupt if PORT.ISRIE:BSRIE and
GLOBAL.ISRIE: PnISRIE are both set. See Section 9.10.
Bit 0: Port Status Register Interrupt Status (PSR). This bit is set when any of the latched status register bits in the port
latched status register (PORT.SRL) are set and enabled for interrupt. When set, this bit causes an interrupt if
PORT.ISRIE:PSRIE and GLOBAL.ISRIE: PnISRIE are both set. See Section 9.10.
Register Name:
PORT.ISRIE
Register Description:
Register Address:
Port Interrupt Status Register Interrupt Enable
n x 80h + 14h
Bit #
Name
Default
15
—
0
14
—
0
13
—
0
12
—
0
11
—
0
10
—
0
9
—
0
8
—
0
Bit #
Name
Default
7
—
0
6
—
0
5
—
0
4
—
0
3
LDSRIE
0
2
LIUSRIE
0
1
BSRIE
0
0
PSRIE
0
Bit 3: Line Decoder Status Register Interrupt Enable (LDSRIE). This bit is the interrupt enable for the
PORT.ISR:LDSR status bit.
0 = mask the interrupt
1 = enable the interrupt
Bit 2: LIU Status Register Interrupt Enable (LIUSRIE). This bit is the interrupt enable for the PORT.ISR:LIUSR status
bit.
0 = mask the interrupt
1 = enable the interrupt
Bit 1: BERT Status Register Interrupt Enable (BSRIE). This bit is the interrupt enable for the PORT.ISR:BSR status
bit.
0 = mask the interrupt
1 = enable the interrupt
Bit 0: Port Status Register Interrupt Enable (PSRIE). This bit is the interrupt enable for the PORT.ISR:PSR status bit.
0 = mask the interrupt
1 = enable the interrupt
65 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
Register Name:
PORT.SR
Register Description:
Register Address:
Port Status Register
n x 80h + 18h
Bit #
Name
Default
15
SPR1
0
14
—
0
13
—
0
12
—
0
11
—
0
10
—
0
9
—
0
8
—
0
Bit #
Name
Default
7
SPR2
0
6
—
0
5
—
0
4
—
0
3
—
0
2
—
0
1
—
0
0
PMS
0
Bit 15: Spare 1 Status Bit (SPR1). This bit is a spare status bit reserved for future use. It indicates the current value of
the PORT.CR1.SPARE1 bit. Note: The default value is the same as PORT.CR1.SPARE1.
Bit 7: Spare 2 Status Bit (SPR2). This bit is a spare status bit reserved for future use. It indicates the current value of
the PORT.CR2.SPARE2 bit. Note: The default value is the same as PORT.CR2.SPARE2.
Bit 0: Performance Monitoring Update Status (PMS). This bit is set when the PMS bits are set in all of the port
functional blocks that are configured for port-level update control (i.e., all blocks that have PMUM = 1). Blocks that have
PMUM = 0 have no effect on this bit. In port-level software update mode, the port update request bit (PORT.CR1:PMU)
should be held high until this status bit goes high. See Section 9.7.4.
0 = The associated update request signal is low or not all register updates are completed
1 = The requested performance register updates are all completed
Register Name:
PORT.SRL
Register Description:
Register Address:
Port Status Register Latched
n x 80h + 1Ah
Bit #
Name
Default
15
—
0
14
—
0
13
—
0
12
—
0
11
—
0
10
—
0
9
—
0
8
TCLKL
0
Bit #
Name
Default
7
—
0
6
—
0
5
—
0
4
—
0
3
—
0
2
—
0
1
—
0
0
PMSL
0
Bit 8: Transmit Clock Activity Status Latched (TCLKL). This bit is set when the signal on the TCLK pin for this port is
active. When set, this bit causes an interrupt if interrupt enables PORT.SRIE:TCLKIE, PORT.ISRIE:PSRIE and
GLOBAL.ISRIE: PnISRIE are all set.
Bit 0: Performance Monitoring Update Status Latched (PMSL). This bit is set when the PORT.SR:PMS status bit
changes from low to high. When set, this bit causes an interrupt if interrupt enables PORT.SRIE:PMSIE,
PORT.ISRIE:PSRIE and GLOBAL.ISRIE:PnISRIE are all set. See Section 9.7.4.
66 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
Register Name:
PORT.SRIE
Register Description:
Register Address:
Port Status Register Interrupt Enable
n x 80h + 1Ch
Bit #
Name
Default
15
—
0
14
—
0
13
—
0
12
—
0
11
—
0
10
—
0
9
—
0
8
TCLKIE
0
Bit #
Name
Default
7
SPR2IE
0
6
—
0
5
—
0
4
—
0
3
—
0
2
—
0
1
—
0
0
PMSIE
0
Bit 8: Transmit Clock Activity Latched Status Interrupt Enable (TCLKIE). This bit is the interrupt enable for the
PORT.SRL:TCLKL bit.
0 = mask the interrupt
1 = enable the interrupt
Bit 7: Spare 2 Latched Status Interrupt Enable (SPR2IE). This bit is the interrupt enable for the PORT.SRL:SPR2L bit.
0 = mask the interrupt
1 = enable the interrupt
Bit 0: Performance Monitoring Update Latched Status Interrupt Enable (PMSIE). This bit is the interrupt enable for
the PORT.SRL:PMSL bit.
0 = mask the interrupt
1 = enable the interrupt
67 of 124
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DS32501/DS32502/DS32503/DS32504
10.5 LIU Registers
Table 10-5. LIU Register Map
ADDRESS
REGISTER
OFFSET
DESCRIPTION
20h
22h
24h
26h
28h
2Ah
2Ch
2Eh
LIU.CR1
LIU.CR2
LIU Control Register 1
LIU Control Register 2
LIU.TWSCR1
LIU.TWSCR2
LIU.SR
LIU Transmit Waveshaping Control Register 1
LIU Transmit Waveshaping Control Register 2
LIU Status Register
LIU.SRL
LIU Status Register Latched
LIU.SRIE
LIU Status Register Interrupt Enable
LIU Receive Gain Level Register
LIU.RGLR
68 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
Register Name:
LIU.CR1
Register Description:
Register Address:
LIU Control Register 1
n x 80h + 20h
Bit #
Name
Default
15
—
0
14
—
0
13
—
0
12
—
0
11
0
10
0
9
0
1
8
0
0
0
JAD[1:0]
JAS[1:0]
Bit #
Name
Default
7
—
0
6
—
0
5
TLBO
0
4
TOE
0
3
2
TTRE
0
TRESADJ[2:0]
0
0
Bits 11 and 10: Jitter Attenuator Depth (JAD[1:0]). These bits select the jitter attenuator buffer depth. See Section 9.4.
00 = 16 bits
01 = 32 bits
10 = 64 bits
11 = 128 bits
Bits 9 and 8: Jitter Attenuator Select (JAS[1:0]). These bits select the location of the jitter attenuator. See Section 9.4.
00 = Disabled
01 = Receive Path
10 = Transmit Path
11 = Transmit Path
Bit 5: Transmit LIU LBO (TLBO). This bit is used to enable the transmit LBO circuit which causes the transmit signal to
be preattenuated to mimic the attenuation of approximately approximates about 225 feet of cable. This is used to reduce
near end cross talk when the cable lengths are short. This signal is only valid in DS3 and STS-1 modes. See Section
9.2.6.
0 = Disabled
1 = Enabled
Bit 4: Transmit Output Enable (TOE). This bit enables the transmitter outputs (TXP and TXN). The transmitter
continues to operate internally when the transmitter is tri-stated. Only the line driver and driver monitor are disabled. See
Section 9.2.7. Note: This bit is ORed with the associated TOE input pin.
0 = TXP and TXN are high impedance
1 = TXP and TXN are driven
Bit 3: Transmit Termination Resistor Enable (TTRE). This bit indicates when the transmitter internal termination is
enabled. See Section 9.2.8.
0 = Disabled, the transmitter is terminated externally
1 = Enabled, the transmitter is terminated internally
Bits 2 to 0: Transmit Resistor Adjustment (TRESADJ[2:0]). These bits are used to adjust the internal termination
resistance of the transmitter. See Section 9.2.8.
000 = 75Ω
001 = 82Ω
010 = 90Ω
011 = 100Ω
100 = 68Ω
101 = 62Ω
110 = 56Ω
111 = 50Ω
69 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
Register Name:
LIU.CR2
Register Description:
Register Address:
LIU Control Register 2
n x 80h + 22h
Bit #
Name
Default
15
—
0
14
—
0
13
—
0
12
—
0
11
—
0
10
—
0
9
—
0
8
—
0
Bit #
Name
Default
7
—
0
6
—
0
5
RFL2E
0
4
RMON
0
3
RTRE
0
2
0
1
0
0
RRESADJ[2:0]
0
Bit 5: Receive Fail 2 Enable (RFL2E). This bit is used to enable the receive failure type 2 detection. See Section 9.3.8.
0 = Disable receive failure type 2 detection
1 = Enable receive failure type 2 detection
Bit 4: Receive LIU Monitor Mode (RMON). This bit is used to enable the receive LIU monitor mode preamplifier.
Enabling the preamplifier adds about 14dB of linear amplification for use in monitor applications where the signal has
been reduced 20dB using resistive attenuator circuits. Note: When enabled, the preamp is turned on or off automatically
depending upon the input signal level. See Section 9.3.2.
0 = Disable the preamp
1 = Enable the preamp
Bit 3: Receive Termination Resistor Enable (RTRE). This bit indicates when the receiver internal termination is
enabled. See Section 9.3.1.
0 = Disabled, the receiver is terminated externally
1 = Enabled, the receiver is terminated internally
Bit 2-0: Receive Resistor Adjustment (RRESADJ[2:0]). These bits are used to adjust the internal termination
resistance of the receiver. See Section 9.3.1.
000 = 75Ω
001 = 82Ω
010 = 90Ω
011 = 100 Ω
100 = 68Ω
101 = 62Ω
110 = 56Ω
111 = 50Ω
70 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
Register Name:
LIU.TWSCR1
Register Description:
Register Address:
LIU Transmit Waveshaping Control Register 1
n x 80h + 24h
Bit #
Name
Default
15
0
14
0
13
0
12
11
0
10
0
9
0
1
0
8
0
0
0
TWSC[15:8]
0
4
0
Bit #
Name
Default
7
6
5
3
2
TWSC[7:0]
0
0
0
0
0
See Figure 9-1, Figure 9-2, and Figure 9-3 for illustrations of the first and second rise/fall time segments of the DS3 and
STS-1 waveforms and the overshoot, one level, undershoot, and zero level segments for the E3 waveform.
Bits 15 and 14: Transmit Waveshaping Control (TWSC[15:14]). In DS3 and STS-1 modes, this field adjusts the width
of the first of two rising-edge segments. In E3 mode this field adjusts the width of the leading edge overshoot.
DS3/STS-1 Behavior
E3 Behavior
00 - normal first rise time
normal overshoot width
increase overshoot width
decrease overshoot width
decrease overshoot width
01 - increase first rise time by 0.1ns
10 - decrease first rise time by 0.1ns
11 - decrease first rise time by 0.2ns
Bits 13 and 12: Transmit Waveshaping Control (TWSC[13:12]). In DS3 and STS-1 modes, this field adjusts the width
of the second of two rising-edge segments. In E3 mode this field adjusts the width of the pulse plateau.
DS3/STS-1 Behavior
E3 Behavior
00 - normal second rise time
normal “one level” time
01 - increase second rise time by 0.1ns
10 - decrease second rise time by 0.1ns
11 - decrease second rise time by 0.1ns
increase “one level” time by 0.15ns
decrease “one level” time by 0.15ns
decrease “one level” time by 0.3ns
Bits 11 and 10: Transmit Waveshaping Control (TWSC[11:10]). In DS3 and STS-1 modes, this field adjusts the width
of the first of two falling-edge segments. In E3 mode this field adjusts the width of the trailing edge undershoot.
DS3/STS-1 Behavior
E3 Behavior
00 - normal first fall time
normal undershoot width
01 - increase first fall time by 0.1ns
10 - decrease first fall time by 0.1ns
11 - decrease first fall time by 0.2ns
increase undershoot width by 0.15ns
decrease undershoot width by 0.15ns
decrease undershoot width by 0.3ns
Bits 9 and 8: Transmit Waveshaping Control (TWSC[9:8]). In DS3 and STS-1 modes, this field adjusts the width of
the second of two falling-edge segments. In E3 mode this field adjusts the width of the zero after the trailing edge.
DS3/STS-1 Behavior
E3 Behavior
00 - normal second fall time
normal “zero level” width
01 - increase second fall time by 0.1ns
10 - decrease second fall time by 0.1ns
11 - decrease second fall time by 0.2ns
increase “zero level” width by 0.15ns
decrease “zero level” width by 0.15ns
decrease “zero level” width by 0.3ns
Bits 7 and 6: Transmit Waveshaping Control (TWSC[7:6]). In DS3 and STS-1 modes, this field adjusts the amplitude
of the first of two rising-edge segments. In E3 mode this field adjusts the amplitude of the leading edge overshoot. The 11
value is a special case in which the entire pulse is made narrower.
DS3/STS-1 Behavior
E3 Behavior
00 - normal first rise amplitude
normal overshoot
01 - decrease first rise amplitude 15%
10 - increase first rise amplitude 15%
11 - decrease pulse width by 0.15ns
decrease overshoot amplitude 2%
increase overshoot amplitude 2%
decrease pulse width by 0.15ns
71 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
Bits 5 and 4: Transmit Waveshaping Control (TWSC[5:4]). In DS3 and STS-1 modes, this field adjusts the amplitude
of the second of two rising-edge segments. In E3 mode this field has no effect, except for the 11 value, which is a special
case in which the entire pulse is made wider.
DS3/STS-1 Behavior
E3 Behavior
00 - normal rise amplitude
normal pulse
01 - decrease second rise amplitude 15%
10 - increase second rise amplitude 15%
11 - increase pulse width by 0.15ns
normal pulse
normal pulse
increase pulse width by 0.15ns
Bits 3 and 2: Transmit Waveshaping Control (TWSC[3:2]). In DS3 and STS-1 modes, this field adjusts the amplitude
of the first of two falling-edge segments. In E3 mode this field adjusts the amplitude of the trailing edge overshoot. The 11
value is a special case in which the entire pulse is made wider.
DS3/STS-1 Behavior
E3 Behavior
00 - normal first fall time
normal undershoot
01 - decrease first fall amplitude 15%
10 - increase first fall amplitude 15%
11 - increase pulse width by 0.15ns
decrease undershoot 2%
increase undershoot 2%
increase pulse width by 0.15ns
Bits 1 and 0: Transmit Waveshaping Control (TWSC[1:0]). In DS3 and STS-1 modes, this field adjusts the fall time of
the second of two falling-edge segments. In E3 mode this field has no effect, except for the 11 value, which is a special
case in which the entire pulse is made narrower.
DS3/STS-1 Behavior
E3 Behavior
00 - normal second fall time
normal pulse
01 - decrease second fall amplitude 15%
10 - increase second fall amplitude 15%
11 - decrease pulse width by 0.15ns
normal pulse
normal pulse
decrease pulse width by 0.15ns
Register Name:
LIU.TWSCR2
Register Description:
Register Address:
LIU Transmit Waveshaping Control Register 2
n x 80h + 26h
Bit #
Name
Default
15
—
0
14
—
0
13
—
0
12
—
0
11
—
0
10
—
0
9
—
0
8
—
0
Bit #
Name
Default
7
—
0
6
—
0
5
—
0
4
—
0
3
0
2
1
0
0
0
TWSC[19:16]
0
Bits 3 to 0: Transmit Waveshaping Control (TWSC[19:16]). This field adjusts overall amplitude of the transmit output
pulse.
0000 - nominal amplitude (see Table 12-6 and Table 12-7)
0001 - increase amplitude by 3.75%
0010 - increase amplitude by 7.5%
0011 - increase amplitude by 11.25%
0100 - increase amplitude by 15%
0101 - increase amplitude by 20%
0110 - increase amplitude by 25%
0111 - increase amplitude by 30%
1000 - decrease amplitude by 12.5%
1001 - decrease amplitude by 9.375%
1010 - decrease amplitude by 6.25%
1011 - decrease amplitude by 3.125%
110X - increase amplitude to internal current limit
111X - increase amplitude to maximum, current limiting disabled
72 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
Register Name:
LIU.SR
Register Description:
Register Address:
LIU Status Register
n x 80h + 28h
Bit #
Name
Default
15
—
0
14
—
0
13
—
0
12
—
0
11
—
0
10
TDM
0
9
TFAIL
0
8
LOMC
0
Bit #
Name
Default
7
—
1
6
—
1
5
—
0
4
RPAS
0
3
RFAIL1
0
2
RFAIL2
0
1
RLOL
0
0
ALOS
0
Bit 10: Transmit Driver Monitor (TDM). This bit indicates when the transmit driver is faulty. See Section 9.2.9.
0 = the transmit line driver is operating properly
1 = the transmit line driver is faulty
Bit 9: Transmit Output Failure (TFAIL). This bit indicates when there is a failure on the transmit differential outputs
(TXP/TXN). See Section 9.2.9.
0 = an open or short has not been detected on TXP or TXN
1 = an open or short has been detected on TXP or TXN
Bit 8: Loss of Master Clock (LOMC). This bit indicates whether or not the appropriate reference clock (DS3, E3 or STS-
1, depending on PORT.CR2:LM[1:0] setting) is available from the CLAD block. See Section 9.7.1.
0 = the master reference clock is present
1 = that master reference clock is not present
Bit 4: Receive Preamp Status (RPAS). See Section 9.3.2.
0 = the receiver preamp is off
1 = the receiver preamp is on
Bit 3: Receive Failure Type 1 (RFAIL1). See Section 9.3.8.
0 = a receive failure type 1 has not been detected on RXP or RXN
1 = a receive failure type 1 has been detected on RXP or RXN
Bit 2: Receive Failure Type 2 (RFAIL2). See Section 9.3.8.
0 = a receive failure type 2 has not been detected on RXP or RXN
1 = a receive failure type 2 has been detected on RXP or RXN
Bit 1: Receive Loss of Lock (RLOL). See Section 9.3.4.
0 = the incoming clock frequency on RXP/RXN is within ±7700ppm of the master reference clock
(MCLK)
1 = the incoming clock frequency on RXP/RXN is more than ±7900ppm away from the master reference
clock (MCLK)
Bit 0: Analog Loss of Signal (ALOS). See Section 9.3.5.
0 = an analog LOS (ALOS) condition has not been detected
1 = an ALOS condition has been detected
73 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
Register Name:
LIU.SRL
Register Description:
Register Address:
LIU Status Register Latched
n x 80h + 2Ah
Bit #
Name
Default
15
—
0
14
—
0
13
—
0
12
JAFL
0
11
JAEL
0
10
TDML
0
9
TFAILL
0
8
LOMCL
0
Bit #
Name
Default
7
—
0
6
—
0
5
RGLCL
0
4
RPASL
0
3
RFAIL1L
0
2
RFAIL2L
0
1
RLOLL
0
0
ALOSL
0
Bit 12: Jitter Attenuator Full Latched (JAFL). This bit is set when the jitter attenuator buffer is full, or when data has
been lost due to a jitter attenuator buffer underflow or overflow. When set, this bit causes an interrupt if interrupt enables
LIU.SRIE:JAFIE, PORT.ISRIE:LDSRIE and GLOBAL.ISRIE:PnISRIE are all set. See Section 9.4.
Bit 11: Jitter Attenuator Empty Latched (JAEL). This bit is set when the jitter attenuator buffer is empty, or when data
has been lost due to a jitter attenuator buffer underflow or overflow. When set, this bit causes an interrupt if interrupt
enables LIU.SRIE:JAEIE, PORT.ISRIE:LDSRIE and GLOBAL.ISRIE:PnISRIE are all set. See Section 9.4.
Bit 10: Transmit Driver Monitor Change Latched (TDML). This bit is set when the LIU.SR:TDM bit changes state.
When set, this bit causes an interrupt if interrupt enables LIU.SRIE:TDMIE, PORT.ISRIE:LDSRIE and
GLOBAL.ISRIE:PnISRIE are all set.
Bit 9: Transmit Output Failure Change Latched (TFAILL). This bit is set when the LIU.SR:TFAIL bit changes state.
When set, this bit causes an interrupt if interrupt enables LIU.SRIE:TFAILIE, PORT.ISRIE:LDSRIE and
GLOBAL.ISRIE:PnISRIE are all set.
Bit 8: Loss of Master Clock Latched (LOMCL). This bit is set when the LIU.SR:LOMC bit is set. When set, this bit
causes an interrupt if interrupt enables LIU.SRIE:LOMCIE, PORT.ISRIE:LDSRIE and GLOBAL.ISRIE:PnISRIE are all
set.
Bit 5: Receive Gain Level Change Latched (RGLCL). This bit is set when the receive gain level (LIU.RGLR: RGL[7:0])
changes. When set, this bit causes an interrupt if interrupt enables LIU.SRIE:RGLCIE, PORT.ISRIE:LDSRIE and
GLOBAL.ISRIE:PnISRIE are all set.
Bit 4: Receive Preamp Status Change Latched (RPASL). This bit is set when the LIU.SR:RPAS bit changes state.
When set, this bit causes an interrupt if interrupt enables LIU.SRIE:RPASIE, PORT.ISRIE:LDSRIE and
GLOBAL.ISRIE:PnISRIE are all set.
Bit 3: Receive Failure Type 1 Change Latched (RFAIL1L). This bit is set when the LIU.SR:RFAIL1 bit changes state.
When set, this bit causes an interrupt if interrupt enables LIU.SRIE:RFAIL1IE, PORT.ISRIE:LDSRIE and
GLOBAL.ISRIE:PnISRIE are all set.
Bit 2: Receive Failure Type 2 Change Latched (RFAIL2L). This bit is set when the LIU.SR:RFAIL2 bit changes state.
When set, this bit causes an interrupt if interrupt enables LIU.SRIE:RFAIL2IE, PORT.ISRIE:LDSRIE and
GLOBAL.ISRIE:PnISRIE are all set.
Bit 1: Receive Loss of Lock Change Latched (RLOLL). This bit is set when the LIU.SR:RLOL bit changes state. When
set, this bit causes an interrupt if interrupt enables LIU.SRIE:RLOLIE, PORT.ISRIE:LDSRIE and
GLOBAL.ISRIE:PnISRIE are all set.
Bit 0: Analog Loss of Signal Change Latched (ALOSL). This bit is set when the LIU.SR:ALOS bit changes state.
When set, this bit causes an interrupt if interrupt enables LIU.SRIE:ALOSIE, PORT.ISRIE:LDSRIE and
GLOBAL.ISRIE:PnISRIE are all set.
74 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
Register Name:
LIU.SRIE
Register Description:
Register Address:
LIU Status Register Interrupt Enable
n x 80h + 2Ch
Bit #
Name
Default
15
—
0
14
—
0
13
—
0
12
JAFIE
0
11
JAEIE
0
10
TDMIE
0
9
TFAILIE
0
8
LOMCIE
0
Bit #
Name
Default
7
—
0
6
—
0
5
RGLCIE
0
4
RPASIE
0
3
2
1
RLOLIE
0
0
ALOSIE
0
RFAIL1IE RFAIL2IE
0
0
Bit 12: Jitter Attenuator Full Interrupt Enable (JAFIE). This bit is the interrupt enable for the LIU.SRL:JAFL bit.
0 = mask the interrupt
1 = enable the interrupt
Bit 11: Jitter Attenuator Empty Interrupt Enable (JAEIE). This bit is the interrupt enable for the LIU.SRL:JAEL bit.
0 = mask the interrupt
1 = enable the interrupt
Bit 10: Transmit Driver Monitor Interrupt Enable (TDMIE). This bit is the interrupt enable for the LIU.SRL:TDML bit.
0 = mask the interrupt
1 = enable the interrupt
Bit 9: Transmit Output Failure Interrupt Enable (TFAILIE). This bit is the interrupt enable for the LIU.SRL:TFAILL bit.
0 = mask the interrupt
1 = enable the interrupt
Bit 8: Loss of Master Clock Interrupt Enable (LOMCIE). This bit is the interrupt enable for the LIU.SRL:LOMCL bit.
0 = mask the interrupt
1 = enable the interrupt
Bit 5: Receive Gain Level Change Interrupt Enable (RGLCIE). This bit is the interrupt enable for the LIU.SRL:RGLCL
bit.
0 = mask the interrupt
1 = enable the interrupt
Bit 4: Receive Preamp Status Interrupt Enable (RPASIE). This bit is the interrupt enable for the LIU.SRL:RPASL bit.
0 = mask the interrupt
1 = enable the interrupt
Bit 3: Receive Failure Type 1 Interrupt Enable (RFAIL1IE). This bit is the interrupt enable for the LIU.SRL:RFAIL1L bit.
0 = mask the interrupt
1 = enable the interrupt
Bit 2: Receive Failure Type 2 Interrupt Enable (RFAIL2IE). This bit is the interrupt enable for the LIU.SRL:RFAIL2L bit.
0 = mask the interrupt
1 = enable the interrupt
Bit 1: Receive Loss of Lock Interrupt Enable (RLOLIE). This bit is the interrupt enable for the LIU.SRL:RLOLL bit.
0 = mask the interrupt
1 = enable the interrupt
Bit 0: Analog Loss of Signal Interrupt Enable (ALOSIE). This bit is the interrupt enable for the LIU.SRL:ALOSL bit.
0 = mask the interrupt
1 = enable the interrupt
75 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
Register Name:
LIU.RGLR
Register Description:
Register Address:
LIU Receive Gain Level Register
n x 80h + 2Eh
Bit #
Name
Default
15
—
0
14
—
0
13
—
0
12
—
0
11
—
0
10
—
0
9
—
0
8
—
0
Bit #
Name
Default
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
RGL[7:0]
Bits 7 to 0: Receive Gain Level (RGL[7:0]). This field reports the real-time receiver gain level in 0.25dB increments.
Values of 00–60h indicate receiver gain of 0dB to +24dB in 0.25dB increments. Values of F4–FFh indicate receiver gain
of -3dB to -0.25dB in 0.25dB increments. See Section 9.3.3.
76 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
10.6 B3ZS/HDB3 Encoder Registers
Table 10-6. B3ZS/HDB3 Encoder Register Map
ADDRESS
OFFSET
REGISTER
DESCRIPTION
30h
LINE.TCR
—
B3ZS/HDB3 Transmit Control Register
Unused
32h–3Eh
77 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
Register Name:
LINE.TCR
Register Description:
Register Address:
B3ZS/HDB3 Transmit Control Register
n x 80h + 30h
Bit #
Name
Default
15
—
0
14
—
0
13
—
0
12
—
0
11
—
0
10
—
0
9
—
0
8
—
0
Bit #
Name
Default
7
—
0
6
—
0
5
—
0
4
TZSD
0
3
EXZI
0
2
BPVI
0
1
TSEI
0
0
MEIMS
0
Bit 4: Transmit Zero Suppression Encoding Disable (TZSD)
0 = zero suppression (B3ZS or HDB3) encoding is enabled
1 = zero suppression (B3ZS or HDB3) encoding is disabled, and only AMI encoding is performed
Bit 3: Excessive Zero Insert Enable (EXZI). See Section 9.2.3.
0 = excessive zero event (EXZ) insertion is disabled
1 = excessive zero event insertion is enabled
Bit 2: BiPolar Violation Insert Enable (BPVI). See Section 9.2.3.
0 = bipolar violation (BPV) insertion is disabled
1 = bipolar violation insertion is enabled.
Bit 1: Transmit Single Error Insert (TSEI). When LINE.TCR:MEIMS = 0, this bit is used to insert errors of the type(s)
specified by EXZI and BPVI in the transmit data stream. A 0 to 1 transition causes a single error to be inserted. For a
second error to be inserted, this bit must be set to 0, and then back to 1. Note: If LINE.TCR:MEIMS is low, and this bit
transitions more than once between error insertion opportunities, only one error is inserted. See Section 9.7.5.
Bit 0: Manual Error Insert Mode Select (MEIMS). This bit specifies the source of the error insertion signal for the
transmit encoder/decoder block. Note: If TMEI or TSEI is one, changing the state of this bit may cause an error to be
inserted. See Section 9.7.5.
0 = Block-level error insertion using the LINE.TCR:TSEI control bit
1 = Port-level or global-level error insertion as specified by PORT.CR1:MEIMS
78 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
10.7 B3ZS/HDB3 Decoder Registers
Table 10-7. B3ZS/HDB3 Decoder Register Map
ADDRESS
REGISTER
OFFSET
DESCRIPTION
40h
42h
44h
46h
48h
4Ah
4Ch
4Eh
LINE.RCR
—
B3ZS/HDB3 Receive Control Register
Unused
LINE.RSR
LINE.RSRL
LINE.RSRIE
—
B3ZS/HDB3 Receive Status Register
B3ZS/HDB3 Receive Status Register Latched
B3ZS/HDB3 Receive Status Register Interrupt Enable
Unused
LINE.RBPVCR B3ZS/HDB3 Receive Bipolar Violation Count Register
LINE.REXZCR B3ZS/HDB3 Receive Excessive Zero Count Register
79 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
Register Name:
LINE.RCR
Register Description:
Register Address:
B3ZS/HDB3 Receive Control Register
n x 80h + 40h
Bit #
Name
Default
15
—
0
14
—
0
13
—
0
12
—
0
11
—
0
10
—
0
9
—
0
8
—
0
Bit #
Name
Default
7
—
0
6
—
0
5
—
0
4
—
0
3
E3CVE
0
2
REZSF
0
1
RDZSF
0
0
RZSD
0
Bit 3: E3 Code Violation Enable (E3CVE). In E3 mode (PORT.CR2:LM[1:0] = 01) this bit specifies whether the
LINE.RBPVCR register counts bipolar violations or E3 coding violations. Note: E3 line coding violations are defined in
ITU O.161 as consecutive bipolar violations of the same polarity. This bit is ignored in B3ZS mode. See Section 9.3.6.2.
0 = bipolar violations.
1 = E3 line coding violations
Bit 2: Receive BPV Error Detection Zero Suppression Code Format (REZSF). When REZSF = 0, BPV error detection
detects a B3ZS signature if a zero is followed by a bipolar violation (BPV), and an HDB3 signature if two zeros are
followed by a BPV. When REZSF = 1, BPV error detection detects a B3ZS signature if a zero is followed by a BPV that
has the opposite polarity of the BPV in the previous B3ZS signature, and an HDB3 signature if two zeros are followed by
a BPV that has the opposite polarity of the BPV in the previous HDB3 signature. Note: Immediately after a reset (RST or
DPRST bit high), this bit is ignored. The first B3ZS signature is defined as a zero followed by a BPV, and the first HDB3
signature is defined as two zeros followed by a BPV. All subsequent B3ZS/HDB3 signatures are determined by the
setting of this bit. Note: The default setting (REZSF = 0) conforms to ITU O.162. The default setting may falsely ignore
actual BPVs that are not codewords. It is recommended that REZSF be set to one for most applications. This setting is
more robust to accurately detect codewords. See Section 9.3.6.2.
Bit 1: Receive Zero Suppression Decoding Zero Suppression Code Format (RDZSF). When RDZSF = 0, zero
suppression decoding detects a B3ZS signature if a zero is followed by a bipolar violation (BPV), and an HDB3 signature
if two zeros are followed by a BPV. When RDZSF = 1, zero suppression decoding detects a B3ZS signature if a zero is
followed by a BPV that has the opposite polarity of the BPV in the previous B3ZS signature, and an HDB3 signature if
two zeros are followed by a BPV that has the opposite polarity of the BPV in the previous HDB3 signature. Note:
Immediately after a reset (RST or DPRST bit high), this bit is ignored. The first B3ZS signature is defined as a zero
followed by a BPV, and the first HDB3 signature is defined as two zeros followed by a BPV. All subsequent B3ZS/HDB3
signatures are determined by the setting of this bit. Note: The default setting (RDZSF = 0) may falsely decode actual
BPVs that are not codewords. It is recommended that RDZSF be set to one for most applications. This setting is more
robust to accurately detect codewords. See Section 9.3.6.2.
Bit 0: Receive Zero Suppression Decoding Disable (RZSD)
0 = zero suppression (B3ZS or HDB3) decoding is enabled
1 = zero suppression (B3ZS or HDB3) decoding is disabled, and only AMI decoding is performed
80 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
Register Name:
LINE.RSR
Register Description:
Register Address:
B3ZS/HDB3 Receive Status Register
n x 80h + 44h
Bit #
Name
Default
15
—
0
14
—
0
13
—
0
12
—
0
11
—
0
10
—
0
9
—
0
8
—
0
Bit #
Name
Default
7
—
0
6
—
0
5
—
0
4
—
0
3
EXZC
0
2
—
0
1
BPVC
0
0
LOS
0
Bit 3: Excessive Zero Count (EXZC). See Section 9.3.6.
0 = the excessive zero count is zero
1 = the excessive zero count is one or more
Bit 1: Bipolar Violation Count (BPVC). See Section 9.3.6.
0 = the bipolar violation count is zero
1 = the bipolar violation count is one or more
Bit 0: Loss of Signal (LOS). See Section 9.3.5.
0 = the receive line interface is not in an LOS condition
1 = the receive line interface is in an LOS condition
Register Name:
LINE.RSRL
Register Description:
Register Address:
B3ZS/HDB3 Receive Status Register Latched
n x 80h + 46h
Bit #
Name
Default
15
—
0
14
—
0
13
—
0
12
—
0
11
—
0
10
—
0
9
—
0
8
—
0
Bit #
Name
Default
7
—
0
6
—
0
5
ZSCDL
0
4
EXZL
0
3
EXZCL
0
2
BPVL
0
1
BPVCL
0
0
LOSL
0
Bit 5: Zero Suppression Code Detect Latched (ZSCDL). This bit is set when a B3ZS or HDB3 signature is detected.
When set, this bit causes an interrupt if interrupt enables LINE.RSRIE:ZSCDIE, PORT.ISRIE:LDSRIE and
GLOBAL.ISRIE:PnISRIE are all set. See Section 9.3.6.
Bit 4: Excessive Zero Latched (EXZL). This bit is set when an excessive zero event is detected on the incoming bipolar
data stream. When set, this bit causes an interrupt if interrupt enables LINE.RSRIE:EXZIE, PORT.ISRIE:LDSRIE and
GLOBAL.ISRIE:PnISRIE are all set. See Section 9.3.6.
Bit 3: Excessive Zero Count Latched (EXZCL). This bit is set when LINE.RSR:EXZC transitions from zero to one.
When set, this bit causes an interrupt if interrupt enables LINE.RSRIE:EXZCIE, PORT.ISRIE:LDSRIE and
GLOBAL.ISRIE:PnISRIE are all set. See Section 9.3.6.
Bit 2: Bipolar Violation Latched (BPVL). This bit is set when a bipolar violation (or E3 LCV if enabled) is detected on
the incoming bipolar data stream. When set, this bit causes an interrupt if interrupt enables LINE.RSRIE:BPVIE,
PORT.ISRIE:LDSRIE and GLOBAL.ISRIE:PnISRIE are all set. See Section 9.3.6.
Bit 1: Bipolar Violation Count Latched (BPVCL). This bit is set when LINE.RSR:BPVC transitions from zero to one.
When set, this bit causes an interrupt if interrupt enables LINE.RSRIE:BPVCIE, PORT.ISRIE:LDSRIE and
GLOBAL.ISRIE:PnISRIE are all set. See Section 9.3.6.
Bit 0: Loss of Signal Change Latched (LOSL). This bit is set when LINE.RSR:LOS changes state. When set, this bit
causes an interrupt if interrupt enables LINE.RSRIE:LOSIE, PORT.ISRIE:LDSRIE and GLOBAL.ISRIE:PnISRIE are all
set. See Section 9.3.5.
81 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
Register Name:
LINE.RSRIE
Register Description:
Register Address:
B3ZS/HDB3 Receive Status Register Interrupt Enable
n x 80h + 48h
Bit #
Name
Default
15
—
0
14
—
0
13
—
0
12
—
0
11
—
0
10
—
0
9
—
0
8
—
0
Bit #
Name
Default
7
—
0
6
—
0
5
ZSCDIE
0
4
EXZIE
0
3
EXZCIE
0
2
BPVIE
0
1
BPVCIE
0
0
LOSIE
0
Bit 5: Zero Suppression Code Detect Interrupt Enable (ZSCDIE). This bit is the interrupt enable for the
LINE.RSRL:ZSCDL status bit.
0 = mask the interrupt
1 = enable the interrupt
Bit 4: Excessive Zero Interrupt Enable (EXZIE). This bit is the interrupt enable for the LINE.RSRL:EXZL status bit.
0 = mask the interrupt
1 = enable the interrupt
Bit 3: Excessive Zero Count Interrupt Enable (EXZCIE). This bit is the interrupt enable for the LINE.RSRL:EXZCL
status bit.
0 = mask the interrupt
1 = enable the interrupt
Bit 2: Bipolar Violation Interrupt Enable (BPVIE). This bit is the interrupt enable for the LINE.RSRL:BPVL status bit.
0 = mask the interrupt
1 = enable the interrupt
Bit 1: Bipolar Violation Count Interrupt Enable (BPVCIE). This bit is the interrupt enable for the LINE.RSRL:BPVCL
status bit.
0 = mask the interrupt
1 = enable the interrupt
Bit 0: Loss of Signal Interrupt Enable (LOSIE). This bit is the interrupt enable for the LINE.RSRL:LOSL status bit.
0 = mask the interrupt
1 = enable the interrupt
82 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
Register Name:
LINE.RBPVCR
Register Description:
Register Address:
B3ZS/HDB3 Receive Bipolar Violation Count Register
n x 80h + 4Ch
Bit #
Name
Default
15
0
14
0
13
0
12
0
11
0
10
0
9
0
1
0
8
0
0
0
BPV[15:8]
BPV[7:0]
Bit #
Name
Default
7
6
5
4
3
2
0
0
0
0
0
0
Bits 15 to 0: Bipolar Violation Count (BPV[15:0]). These 16 bits indicate the number of bipolar violations detected on
the incoming bipolar data stream. See Section 9.3.6.
Register Name:
LINE.REXZCR
Register Description:
Register Address:
B3ZS/HDB3 Receive Excessive Zero Count Register
n x 80h + 4Eh
Bit #
Name
Default
15
0
14
0
13
0
12
0
11
0
10
0
9
0
1
0
8
0
0
0
EXZ[15:8]
EXZ[7:0]
Bit #
Name
Default
7
6
5
4
3
2
0
0
0
0
0
0
Bits 15 to 0: Excessive Zero Count (EXZ[15:0]). These 16 bits indicate the number of excessive zero conditions
detected on the incoming bipolar data stream. See Section 9.3.6.
83 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
10.8 BERT Registers
Table 10-8. BERT Register Map
ADDRESS
REGISTER
OFFSET
DESCRIPTION
50h
52h
54h
56h
58h
5Ah
5Ch
5Eh
60h
62h
64h
66h
68h
6Ah
6Ch
6Eh
BERT.CR
BERT.PCR
BERT.SPR1
BERT.SPR2
BERT.TEICR
—
BERT Control Register
BERT Pattern Configuration Register
BERT Seed/Pattern Register 1
BERT Seed/Pattern Register 2
BERT Transmit Error Insertion Control Register
Unused
BERT.SR
BERT.SRL
BERT.SRIE
—
BERT Status Register
BERT Status Register Latched
BERT Status Register Interrupt Enable
Unused
BERT.RBECR1 BERT Receive Bit Error Count Register 1
BERT.RBECR2 BERT Receive Bit Error Count Register 2
BERT.RBCR1
BERT Receive Bit Count Register 1
BERT Receive Bit Count Register 2
Unused
BERT.RBCR2
—
—
Unused
84 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
Register Name:
BERT.CR
Register Description:
Register Address:
BERT Control Register
n x 80h + 50h
Bit #
Name
Default
15
—
0
14
—
0
13
—
0
12
—
0
11
—
0
10
—
0
9
—
0
8
—
0
Bit #
Name
Default
7
PMUM
0
6
LPMU
0
5
RNPL
0
4
RPIC
0
3
MPR
0
2
APRD
0
1
TNPL
0
0
TPIC
0
Bit 7: Performance Monitoring Update Mode (PMUM). This bit specifies the source of the performance monitoring
update signal for the BERT block. See Section 9.7.4. Note: If RPMU or LPMU is one, changing the state of this bit may
cause a performance monitoring update to occur.
0 = Block-level update via BERT.CR:LPMU
1 = Port-level or global update as specified by PORT.CR1:PMUM
Bit 6: Local Performance Monitoring Update (LPMU). When BERT.CR:PMUM = 0, this bit updates the performance
monitoring registers in the BERT block. When this bit transitions from low to high, the BERT.RBECR and BERT.RBCR
registers are updated with the latest counter values and the counters are reset. This bit should remain high until the
performance monitor update status bit (BERT.SR:PMS) goes high, and then it should be brought back low, which clears
the PMS status bit. If a counter increment occurs at the exact same time as the counter reset, the counter is loaded with
a value of one, and the “counter is non-zero” latched status bit is set. See Section 9.7.4.
Bit 5: Receive New Pattern Load (RNPL). A zero to one transition of this bit causes the programmed test pattern
(QRSS, PTS, PLF[4:0], PTF[4:0] in the BERT.PCR register, and BSP[31:0] in the BERT.SPR registers) to be loaded into
the receive pattern generator. This bit must be changed to zero and back to one for another pattern to be loaded.
Loading a new pattern forces the receive pattern generator out of the “Sync” state which causes a resynchronization to
be initiated. Note: The test pattern fields mentioned above must not change for four RCLK cycles after this bit transitions
from 0 to 1. See Section 9.5.1.
Bit 4: Receive Pattern Inversion Control (RPIC). See Section 9.5.1.
0 = do not invert the incoming data stream
1 = invert the incoming data stream
Bit 3: Manual Pattern Resynchronization (MPR). A zero to one transition of this bit causes the receive pattern
generator to resynchronize to the incoming pattern. This bit must be changed to zero and back to one for another
resynchronization to be initiated. Note: A manual resynchronization forces the pattern detector out of the “Sync” state.
See Section 9.5.2.
Bit 2: Automatic Pattern Resynchronization Disable (APRD). When APRD = 0, the receive pattern generator
automatically resynchronizes to the incoming pattern if six or more times during the current 64-bit window the incoming
data stream bit and the receive pattern generator output bit did not match. When APRD = 1, the receive pattern
generator does not automatically resynchronize to the incoming pattern. Note: Automatic synchronization is prevented by
not allowing the receive pattern generator to automatically exit the “Sync” state. See Section 9.5.2.
Bit 1: Transmit New Pattern Load (TNPL). A zero to one transition of this bit causes the programmed test pattern
(QRSS, PTS, PLF[4:0], PTF[4:0] in the BERT.PCR register, and BSP[31:0] in the BERT.SPR registers) to be loaded into
the transmit pattern generator. This bit must be changed to zero and back to one for another pattern to be loaded. Note:
The test pattern fields mentioned above must not change for four TCLK cycles after this bit transitions from 0 to 1. See
Section 9.5.1.
Bit 0: Transmit Pattern Inversion Control (TPIC). See Section 9.5.1.
0 = do not invert the outgoing data stream
1 = invert the outgoing data stream
85 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
Register Name:
BERT.PCR
Register Description:
Register Address:
BERT Pattern Configuration Register
n x 80h + 52h
Bit #
Name
Default
15
—
0
14
—
0
13
—
0
12
0
11
0
10
PTF[4:0]
0
9
0
1
0
8
0
0
0
Bit #
Name
Default
7
—
0
6
QRSS
0
5
PTS
0
4
3
2
PLF[4:0]
0
0
0
Bits 12 to 8: Pattern Tap Feedback (PTF[4:0]). These five bits control the PRBS “tap” feedback of the pattern
generator. The “tap” feedback is from bit y of the pattern generator (y = PTF[4:0] +1). These bits are ignored when the
BERT block is programmed for a repetitive pattern (PTS = 1). For a PRBS signal, the feedback is an XOR of bit n and bit
y. See Section 9.5.1.
Bit 6: QRSS Enable (QRSS). See Section 9.5.1.
0 = Disabled: the pattern generator configuration is controlled by PTS, PLF[4:0], PTF[4:0], and
BSP[31:0]
1 = Enabled: the pattern generator configuration is forced to a PRBS pattern with a generating
polynomial of x20 + x17 + 1, and the output of the pattern generator is forced to one if the next 14
output bits are all zero.
Bit 5: Pattern Type Select (PTS). See Section 9.5.1.
0 = PRBS pattern
1 = repetitive pattern.
Bits 4 to 0: Pattern Length Feedback (PLF[4:0]). This field controls the “length” feedback of the pattern generator. The
“length” feedback is from bit n of the pattern generator (n = PLF[4:0] +1). For a PRBS signal, the feedback is an XOR of
bit n and bit y. For a repetitive pattern the feedback is bit n. See Section 9.5.1.
86 of 124
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DS32501/DS32502/DS32503/DS32504
Register Name:
BERT.SPR1
Register Description:
Register Address:
BERT Seed/Pattern Register 1
n x 80h + 54h
Bit #
Name
Default
15
0
14
0
13
0
12
0
11
0
10
0
9
0
1
0
8
0
0
0
BSP[15:8]
BSP[7:0]
Bit #
Name
Default
7
6
5
4
3
2
0
0
0
0
0
0
Register Name:
BERT.SPR2
Register Description:
Register Address:
BERT Seed/Pattern Register 2
n x 80h + 56h
Bit #
Name
Default
15
0
14
0
13
0
12
0
11
10
0
9
0
1
0
8
0
0
0
BSP[31:24]
0
3
0
Bit #
Name
Default
7
6
5
4
2
BSP[23:16]
0
0
0
0
0
BERT Seed/Pattern (BSP[31:0]). This 32-bit field is the programmable seed for a transmit PRBS pattern, or the
programmable pattern for a transmit or receive repetitive pattern. BSP[31] is the first bit output on the transmit side for a
32-bit repetitive pattern or 32-bit PRBS. BSP[31] is the first bit input on the receive side for a 32-bit repetitive pattern. See
Section 9.5.1.
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DS32501/DS32502/DS32503/DS32504
Register Name:
BERT.TEICR
Register Description:
Register Address:
BERT Transmit Error Insertion Control Register
n x 80h + 58h
Bit #
Name
Default
15
—
0
14
—
0
13
—
0
12
—
0
11
—
0
10
—
0
9
—
0
8
—
0
Bit #
Name
Default
7
—
0
6
—
0
5
0
4
TEIR[2:0]
0
3
0
2
BEI
0
1
TSEI
0
0
MEIMS
0
Bits 5 to 3: Transmit Error Insertion Rate (TEIR[2:0]). This field indicates the rate at which errors are automatically
inserted in the output data stream. One out of every 10n bits is inverted, where n = TEIR[2:0]. A value of 0 disables error
insertion. A value of 1 results in every 10th bit being inverted. A value of 2 result in every 100th bit being inverted. Error
insertion starts when this field is written with a non-zero value. If this field is written during an error insertion, the new
error rate is used after the next error is inserted. See Section 9.5.3.1.
Bit 2: Bit Error Insertion Enable (BEI). See Section 9.5.3.1.
0 = single-bit error insertion is disabled
1 = single-bit error insertion is enabled
Bit 1: Transmit Single Error Insert (TSEI). When BERT.TEICR:MEIMS = 0 and BEI = 1, this bit is used to insert single-
bit errors in the outgoing BERT data stream. A 0 to 1 transition causes a single bit error to be inserted. For a second bit
error to be inserted, this bit must be set to 0, and back to 1. Note: If MEIMS is low, and this bit transitions more than once
between error insertion opportunities, only one error is inserted. See Section 9.7.5.
Bit 0: Manual Error Insert Mode Select (MEIMS). This bit specifies the source of the error insertion signal for the BERT
block. Note: If TMEI or TSEI is one, changing the state of this bit may cause a bit error to be inserted. See Section 9.7.5.
0 = error insertion is initiated by the BERT.TEICR:TSEI register bit
1 = error insertion is initiated by the transmit manual error insertion signal (TMEI) specified by the
PORT.CR1:MEIMS register bit
88 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
Register Name:
BERT.SR
Register Description:
Register Address:
BERT Status Register
n x 80h + 5Ch
Bit #
Name
Default
15
—
0
14
—
0
13
—
0
12
—
0
11
—
0
10
—
0
9
—
0
8
—
0
Bit #
Name
Default
7
—
0
6
—
0
5
—
0
4
—
0
3
PMS
0
2
—
0
1
BEC
0
0
OOS
0
Bit 3: Performance Monitoring Update Status (PMS). This bit is set when the performance monitoring registers
(BERT.RBCR and BERT.RBECR) have been updated. PMS is asynchronously forced low when the BERT.CR:LPMU bit
(BERT.CR:PMUM = 0) or RPMU signal (BERT.CR:PMUM = 1) goes low. See Section 9.7.4.
0 = The associated update request signal is low or not all register updates are completed
1 = The requested performance register updates are all completed
Bit 1: Bit Error Count (BEC). See Section 9.5.1.
0 = the bit error count is zero
1 = the bit error count is one or more
Bit 0: Out Of Synchronization (OOS). See Section 9.5.1.
0 = the receive pattern generator is synchronized to the incoming pattern
1 = the receive pattern generator is not synchronized to the incoming pattern
Register Name:
BERT.SRL
Register Description:
Register Address:
BERT Status Register Latched
n x 80h + 5Eh
Bit #
Name
Default
15
—
0
14
—
0
13
—
0
12
—
0
11
—
0
10
—
0
9
—
0
8
—
0
Bit #
Name
Default
7
—
0
6
—
0
5
—
0
4
—
0
3
PMSL
0
2
BEL
0
1
BECL
0
0
OOSL
0
Bit 3: Performance Monitoring Update Status Latched (PMSL). This bit is set when the BERT.SR:PMS bit transitions
from 0 to 1. When set, this bit causes an interrupt if interrupt enables BERT.SRIE:PMSIE, PORT.ISRIE:BSRIE and
GLOBAL.ISRIE:PnISRIE are all set.
Bit 2: Bit Error Latched (BEL). This bit is set when a bit error is detected in the received pattern. When set, this bit
causes an interrupt if interrupt enables BERT.SRIE:BEIE, PORT.ISRIE:BSRIE and GLOBAL.ISRIE:PnISRIE are all set.
Bit 1: Bit Error Count Latched (BECL). This bit is set when the BERT.SR:BEC bit transitions from 0 to 1. When set, this
bit causes an interrupt if interrupt enables BERT.SRIE:BECIE, PORT.ISRIE:BSRIE and GLOBAL.ISRIE:PnISRIE are all
set.
Bit 0: Out Of Synchronization Latched (OOSL). This bit is set when the BERT.SR:OOS bit changes state. When set,
this bit causes an interrupt if interrupt enables BERT.SRIE:OOSIE, PORT.ISRIE:BSRIE and GLOBAL.ISRIE:PnISRIE are
all set.
89 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
Register Name:
BERT.SRIE
Register Description:
Register Address:
BERT Status Register Interrupt Enable
n x 80h + 60h
Bit #
Name
Default
15
—
0
14
—
0
13
—
0
12
—
0
11
—
0
10
—
0
9
—
0
8
—
0
Bit #
Name
Default
7
—
0
6
—
0
5
—
0
4
—
0
3
PMSIE
0
2
BEIE
0
1
BECIE
0
0
OOSIE
0
Bit 3: Performance Monitoring Update Status Interrupt Enable (PMSIE). This bit is the interrupt enable for the
BERT.SRL:PMSL status bit.
0 = mask the interrupt
1 = enable the interrupt
Bit 2: Bit Error Interrupt Enable (BEIE). This bit is the interrupt enable for the BERT.SRL:BEL status bit.
0 = mask the interrupt
1 = enable the interrupt
Bit 1: Bit Error Count Interrupt Enable (BECIE). This bit is the interrupt enable for the BERT.SRL:BECL status bit.
0 = mask the interrupt
1 = enable the interrupt
Bit 0: Out Of Synchronization Interrupt Enable (OOSIE). This bit is the interrupt enable for the BERT.SRL:OOSL
status bit.
0 = mask the interrupt
1 = enable the interrupt
90 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
Register Name:
BERT.RBECR1
Register Description:
Register Address:
BERT Receive Bit Error Count Register 1
n x 80h + 64h
Bit #
Name
Default
15
0
14
0
13
0
12
0
11
0
10
0
9
0
1
0
8
0
0
0
BEC[15:8]
BEC[7:0]
Bit #
Name
Default
7
6
5
4
3
2
0
0
0
0
0
0
Register Name:
BERT.RBECR2
Register Description:
Register Address:
BERT Receive Bit Error Count Register 2
n x 80h + 66h
Bit #
Name
Default
15
—
0
14
—
0
13
—
0
12
—
0
11
—
0
10
—
0
9
—
0
8
—
0
Bit #
Name
Default
7
0
6
0
5
0
4
3
0
2
0
1
0
0
0
BEC[23:16]
0
Bit Error Count (BEC[23:0]). This field is the holding register for an internal BERT bit error counter that tracks the
number of bit errors detected in the incoming data stream since the last performance monitoring update. The internal
counter stops incrementing when it reaches a count of FF FFFFh and does not increment when an OOS condition exists.
This register is updated when a performance monitoring update is performed. See Section 9.7.4. The source for the
performance monitoring update signal is specified by the BERT.CR:PMUM bit.
91 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
Register Name:
BERT.RBCR1
Register Description:
Register Address:
BERT Receive Bit Count Register 1
n x 80h + 68h
Bit #
Name
Default
15
0
14
0
13
0
12
0
11
0
10
0
9
0
1
0
8
0
0
0
BC[15:8]
BC[7:0]
Bit #
Name
Default
7
6
5
4
3
2
0
0
0
0
0
0
Register Name:
BERT.RBCR2
Register Description:
Register Address:
BERT Receive Bit Count Register 2
n x 80h + 6Ah
Bit #
Name
Default
15
0
14
0
13
0
12
0
11
0
10
0
9
0
1
0
8
0
0
0
BC[31:24]
BC[23:16]
Bit #
Name
Default
7
6
5
4
3
2
0
0
0
0
0
0
Bit Count (BC[31:0]). This field is the holding register for an internal BERT bit counter that tracks the total number of bit
received in the incoming data stream since the last performance monitoring update. The internal counter stops
incrementing when it reaches a count of FFFF FFFFh and does not increment when an OOS condition exists. This
register is updated when a performance monitoring update is performed. See Section 9.7.4. The source for the
performance monitoring update signal is specified by the BERT.CR:PMUM bit.
92 of 124
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DS32501/DS32502/DS32503/DS32504
11. JTAG INFORMATION
The DS3250x LIUs support the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional
public instructions included are HIGHZ, CLAMP, and IDCODE. The devices contain the following items, which
meet the requirements set by the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture:
Test Access Port (TAP)
TAP Controller
Instruction Register
Bypass Register
Boundary Scan Register
Device Identification Register
The TAP has the necessary interface pins, namely JTCLK, JTRST, JTDI, JTDO, and JTMS. Details on these pins
can be found in Table 8-9. Details about the boundary scan architecture and the TAP can be found in IEEE 1149.1-
1990, IEEE 1149.1a-1993, and IEEE 1149.1b-1994.
IEEE 1149.1 requires a minimum of two test registers—the bypass register and the boundary scan register. The
bypass register is a 1-bit shift register used with the BYPASS, CLAMP, and HIGHZ instructions to provide a short
path between JTDI and JTDO. The boundary scan register contains a shift register path and a latched parallel
output for control cells and digital I/O cells. DS3250x BSDL files are available at:
www.maxim-ic.com/TechSupport/telecom/bsdl.htm.
An optional test register, the identification register, has also been included in the device design. The identification
register contains a 32-bit shift register and a 32-bit latched parallel output. Table 11-1 shows the identification
register contents for the DS32501, DS32502, DS32503, and DS32504 devices.
Table 11-1. JTAG ID Code
PART
REVISION
DEVICE CODE
MANUFACTURER CODE
00010100001
REQUIRED
DS32501
DS32502
DS32503
DS32504
Consult factory
Consult factory
Consult factory
Consult factory
0000 0000 0111 1011
0000 0000 0111 1100
0000 0000 0111 1101
0000 0000 0111 1110
1
1
1
1
00010100001
00010100001
00010100001
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DS32501/DS32502/DS32503/DS32504
12. ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Input or Output Lead with Respect to VSS..................................................... -0.3V to +5.5V
Supply Voltage Range (VDD33) with Respect to VSS ........................................................................... -0.3V to +3.63V
Supply Voltage Range (VDD18) with Respect to VSS ........................................................................... -0.1V to +1.98V
Ambient Operating Temperature Range* .......................................................................................... -40°C to +85°C
Junction Operating Temperature Range ........................................................................................... -40°C to +125°C
Storage Temperature Range ............................................................................................................. -55°C to +125°C
Soldering Temperature ............................................................................... See IPC/JEDEC J-STD-020 Specification
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not
implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
*Ambient operating temperature range when device is mounted on a four-layer JEDEC test board with no airflow.
Note: The typical values listed in the following tables and operations at -40oC operation are not production tested, but are guaranteed by
design.
Table 12-1. Recommended DC Operating Conditions
(TA = -40°C to +85°C)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VDD18
VDD33
1.62
1.8
1.98
Digital Supply Voltage
V
3.135 3.300 3.465
CVDD, JVDD, RVDD, and
TVDD
Analog Supply Voltage
AVDD
1.71
1.80
1.89
V
Logic 1, All Other Input Pins
Logic 0, All Other Input Pins
VIH
VIL
2.0
3.6
V
V
-0.3
+0.8
94 of 124
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DS32501/DS32502/DS32503/DS32504
Table 12-2. DC Characteristics
(VDD18 = 1.8V ±10%, VDD33 = 3.3V ±5%, AVDD = 1.8V ±5%, TA = -40°C to +85°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DS32501
DS32502
DS32503
DS32504
DS32501
DS32502
DS32503
DS32504
DS32501
DS32502
DS32503
DS32504
DS32501
DS32502
DS32503
DS32504
DS32501,
DS32502,
DS32503,
DS32504
DS32501,
DS32502,
DS32503,
DS32504
58
96
134
172
15
30
45
60
45
70
95
120
15
30
70
120
170
220
32
55
80
110
50
80
110
140
32
55
80
Supply Current, VDD18 (Notes 1, 2)
IDD18
mA
Supply Current, VDD33 (Notes 1, 2)
IDD33
mA
mA
Supply Current, Transmitters Disabled
(All TOE = 0), VDD18 (Notes 2, 3)
IDDTTS18
Supply Current, Transmitters Disabled
(All TOE = 0), VDD33 (Notes 2, 3)
IDDTTS33
IDDPD18
IDDPD33
mA
mA
mA
45
60
110
Supply Current, Power-Down
(All TPD = RPD = 1), VDD18
(Notes 2, 3, 4)
16
20
10
Supply Current, Power-Down
(All TPD = RPD = 1), VDD33
(Notes 2, 3, 4)
5.3
7
Lead Capacitance
CIO
IIL
ILO
VOH
VOL
10
+10
+10
VDD33
0.4
pF
μA
μA
V
Input Leakage, All Other Input Pins
Output Leakage (when High-Z)
Output Voltage (IO = -4.0mA)
Output Voltage (IO = +4.0mA)
(Note 5)
(Note 5)
-300
-50
2.4
0
V
Note 1:
TCLKn = CLKC = 51.84MHz; LMn[1:0] = 10 (STS-1 mode); TXPn/TXNn driving all ones into 75Ω resistive loads; analog loopback
enabled; all other inputs at VDD33 or grounded; all other outputs open.
Note 2:
Note 3:
Note 4:
Design targets. Actual values will be listed after device characterization.
TCLKn = CLKC = 51.84MHz; other inputs at VDD33or grounded; digital outputs left open circuited.
IFSEL ≠ 0, CLAD[6:0] = 0000000 (disabled), G1SRS[3:0] = 0000 (disable), CS = 1 (inactive).
Note 5:
0V < VIN < VDD18 for all other digital inputs.
95 of 124
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DS32501/DS32502/DS32503/DS32504
Table 12-3. Framer Interface Timing
(VDD18 = 1.8V±10%, VDD33 = 3.3V ±5%, AVDD = 1.8V ±5%, TA = -40°C to +85°C.) (See Figure 12-1
and Figure 12-2.)
PARAMETER
SYMBOL
CONDITIONS
(Notes 1, 2)
MIN
TYP
MAX UNITS
22.4
29.1
19.3
50
RCLK/TCLK Clock Period
t1
ns
(Notes 2, 3)
(Notes 2, 4)
RCLK Duty Cycle
t2/t, t3/t1 (Notes 5, 6)
t2/t, t3/t1 (Note 6)
45
30
30
3
55
70
70
%
%
%
ns
ns
TCLK Duty Cycle
LIU Reference Clock Duty Cycle
TPOS/TDAT, TNEG to TCLK Setup Time
TPOS/TDAT, TNEG Hold Time
t2/t, t3/t1 (Notes 6, 7)
t4
t5
(Notes 6, 8)
(Notes 6, 8)
1
RCLK to RPOS/RDAT, RNEG/RLCV
Value Change
t6
(Notes 5, 6, 9)
1
7
ns
RCLK Rise and Fall Time
TCLK Rise and Fall Time
t7
t8
(Notes 6, 10 )
(Notes 5, 11)
1
2
2
ns
ns
Note 1:
Note 2:
DS3 mode.
78MHz is the maximum instantaneous frequency for a gapped clock. The maximum average frequency is 45.094MHz for DS3,
34.643MHz for E3, and 52.255MHz for STS-1.
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
E3 mode.
STS-1 mode.
Outputs loaded with 25pF, measured at 50% threshold.
Not tested during production test.
The LIU reference clock must be a ±20ppm low-jitter clock. See Section 9.7.1 for more information on reference clocks.
When TCLKI = 0, TPOS/TDAT and TNEG are sampled on the rising edge of TCLK. When TCLKI = 1, TPOS/TDAT and TNEG are
sampled on the falling edge of TCLK.
Note 9:
When RCLKI = 0, RPOS/RDAT and RNEG/RLCV are updated on the falling edge of RCLK. When RCLKI = 1, RPOS/RDAT and
RNEG/RLCV are updated on the rising edge of RCLK.
Note 10: Outputs loaded with 25pF, measured between VOL(MAX) and VOH(MIN)
.
Measured between VIL(MAX) and VIH(MIN)
.
Note 11:
96 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
Figure 12-1. Transmitter Framer Interface Timing Diagram
t1
t2
t3
TCLK (NORMAL)
TCLK (INVERTED)
t8
t4
t5
TPOS/TDAT
TNEG
Figure 12-2. Receiver Framer Interface Timing Diagram
t1
t2
t3
RCLK (NORMAL)
RCLK (INVERTED)
t6
t7
RPOS/RDAT
RNEG/RLCV
97 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
Table 12-4. Receiver Input Characteristics—DS3 and STS-1 Modes
(VDD18 = 1.8V ±10%, VDD33 = 3.3V ±5%, AVDD = 1.8V ±5%, TA = -40°C to +85°C.)
PARAMETER
MIN
TYP
MAX
UNITS
Receive Sensitivity (Length of Cable)
1500
10
ft
Signal-to-Noise Ratio, Interfering Signal Test (Notes 1, 2)
Input Pulse Amplitude, RMON = 0 (Notes 2, 3)
Input Pulse Amplitude, RMON = 1 (Note 2, 3)
Analog LOS Declare, RMON = 0 (Note 4)
Analog LOS Clear, RMON = 0 (Note 4)
1000
200
-25
mVpk
mVpk
dB
-23
-22
-20
-34
dB
Analog LOS Declare, RMON = 1 (Note 4)
Analog LOS Clear, RMON = 1 (Note 4)
-37
-39
dB
-36
dB
Intrinsic Jitter Generation (Note 2)
0.02
UIP-P
Note 1: An interfering signal (215 - 1 PRBS, B3ZS encoded, compliant waveshape, nominal bit rate) is added to the input signal. The combined
signal is passed through 0 to 900 feet of coaxial cable and presented to the DS3250x receiver. This spec indicates the lowest signal-
to-noise ratio that results in a bit error ratio ≤10-9.
Note 2: Not tested during production test.
Note 3: Measured on the line side (i.e., the BNC connector side) of the 1:1 receive transformer (see Figure 3-2). During measurement,
incoming data traffic is unframed 215 - 1 PRBS.
Note 4: With respect to nominal 800mVpk signal.
Table 12-5. Receiver Input Characteristics—E3 Mode
(VDD18 = 1.8V ±10%, VDD33 = 3.3V ±5%, AVDD = 1.8V ±5%, TA = -40°C to +85°C.)
PARAMETER
MIN
TYP
MAX
UNITS
Receive Sensitivity (Length of Cable)
2000
12
ft
Signal-to-Noise Ratio, Interfering Signal Test (Notes 1, 2)
Input Pulse Amplitude, RMON = 0 (Notes 2, 3)
Input Pulse Amplitude, RMON = 1 (Notes 2, 3)
Analog LOS Declare, RMON = 0 (Note 4)
Analog LOS Clear, RMON = 0 (Note 4)
1300
260
-25
mVpk
mVpk
dB
-20
-34
dB
Analog LOS Declare, RMON = 1 (Note 4)
Analog LOS Clear, RMON = 1 (Note 4)
-39
dB
dB
Intrinsic Jitter Generation (Note 2)
0.03
UIP-P
Note 1: An interfering signal (223 - 1 PRBS, B3ZS encoded, compliant waveshape, nominal bit rate) is added to the input signal. The combined
signal is passed through 0 to 900 feet of coaxial cable and presented to the DS3250x receiver. This spec indicates the lowest signal-
to-noise ratio that results in a bit error ratio ≤10-9.
Note 2: Not tested during production test.
Note 3: Measured on the line side (i.e., the BNC connector side) of the 1:1 receive transformer (see Figure 3-2). During measurement,
incoming data traffic is unframed 223 - 1 PRBS.
Note 4: With respect to nominal 1000mVpk signal.
98 of 124
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DS32501/DS32502/DS32503/DS32504
Table 12-6. Transmitter Output Characteristics—DS3 and STS-1 Modes
(VDD18 = 1.8V ±10%, VDD33 = 3.3V ±5%, AVDD = 1.8V ±5%, TA = -40°C to +85°C.)
PARAMETER
MIN
TYP
MAX
UNITS
DS3 Output Pulse Amplitude, TLBO = 0 (Note 1)
DS3 Output Pulse Amplitude, TLBO = 1 (Note 1)
STS-1 Output Pulse Amplitude, TLBO = 0 (Note 1)
STS-1 Output Pulse Amplitude, TLBO = 1 (Note 1)
Ratio of Positive and Negative Pulse-Peak Amplitudes
DS3 Power Level at 22.368MHz (Note 2)
700
500
700
500
0.9
800
600
800
600
1.0
900
700
900
700
1.1
mVpk
mVpk
mVpk
mVpk
-1.8
+5.7
-20
dBm
dB
DS3 Power Level at 44.736MHz vs. Power Level at 22.368 MHz (Note 2)
Note 1: Measured on the line side (i.e., the BNC connector side) of the 1:1 transmit transformer (Figure 3-2).
Note 2: Unframed all-ones output signal, 3kHz bandwidth.
Note 3: Measured with a jitter-free clock applied to TCLK and a bandpass jitter filter with 10Hz and 800kHz cutoff frequencies.
Note 4:
With ±5% power supply.
Table 12-7. Transmitter Output Characteristics—E3 Mode
(VDD18 = 1.8V ±10%, VDD33 = 3.3V ±5%, AVDD = 1.8V ±5%, TA = -40°C to +85°C.)
PARAMETER
MIN
TYP
MAX
UNITS
Output Pulse Amplitude (Note 1)
900
1000 1100
14.55
mVpk
ns
Pulse Width (Note 1)
Positive/Negative Pulse Amplitude Ratio (at Centers of Pulses) (Note 1)
Positive/Negative Pulse Width Ratio (at Nominal Half Amplitude)
0.95
0.95
1.00
1.00
880
1.05
1.05
Transmit Driver Monitor Minimum Threshold (VTXMIN
)
mVpk
mVpk
Transmit Driver Monitor Maximum Threshold (VTXMAX
)
1120
Note 1: Measured on the line side (i.e., the BNC connector side) of the 1:1 transmit transformer (Figure 3-2).
Note 2: Measured with a jitter-free clock applied to TCLK and a bandpass jitter filter with 10Hz and 800kHz cutoff frequencies.
Note 3:
With ±5% power supply.
99 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
Table 12-8. Parallel CPU Interface Timing
(VDD18 = 1.8V ±10%, VDD33 = 3.3V ±5%, AVDD = 1.8V ±5%, TA = -40°C to +85°C.) (See Figure 12-3,
Figure 12-4, Figure 12-5, Figure 12-6, Figure 12-7, Figure 12-8, Figure 12-9, and Figure 12-10.)
PARAMETER
SYMBOL MIN TYP MAX UNITS
t1
t2
0
0
ns
ns
Setup Time for A[9:1] Valid to RD, WR, or DS Active (Notes 1, 2)
Setup Time for CS Active to RD, WR, or DS Active
Delay Time from RD or DS Active to D[15:0] Valid Without ACK
Handshake
t3a
65
20
ns
Delay Time from ACK Active to D[15:0] Valid
t3b
t4
ns
ns
ns
0
2
Hold Time from RD, WR, or DS Inactive to CS Inactive
Delay from CS, RD, or DS Inactive to D[15:0] Invalid (Note 3)
t5
Wait Time from WR or DS Active to Latch D[15:0] Without ACK
Handshake
t6a
65
ns
Wait Time from ACK Active to Latch D[15:0]
D[15:0] Setup Time to WR or DS Inactive
D[15:0] Hold Time from WR or DS Inactive
A[9:1] Hold Time from WR, RD, or DS Inactive
Delay from WR, RD, or DS Inactive to ALE Active
RD, WR, or DS Inactive Time
Muxed Address Valid to ALE Inactive (Note 4)
Muxed Address Hold Time from ALE Inactive (Note 4)
ALE Pulse Width (Note 4)
t6b
t7
20
10
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
t8
t9a
t9b
t10
t11
t12
t13
5
20
75
10
10
20
Setup Time for ALE High or Muxed Address Valid to CS Active
(Notes 4, 5, 6)
t14
t15
0
ns
ns
15
Delay from CS Inactive to D[15:0] Disable
Note 1: D[15:0] loaded with 50pF when tested as outputs.
Note 2: If a gapped clock is applied on TCLK and local loopback is enabled, read cycle time must be extended by the length of the largest
TCLK gap.
Note 3: Not tested during production test.
Note 4: In nonmultiplexed bus applications (Figure 12-3 to Figure 12-6), ALE should be wired high. In multiplexed bus applications
(Figure 12-7 to Figure 12-10), A[9:1] should be wired to D[15:0] and the falling edge of ALE latches the address.
Note 5: t14 starts at the occurrence of the rising edge of ALE or A[9:1] valid whichever occurs later.
Note 6:
In order to avoid bus contention, during a read cycle A[9:1] should be disabled prior to RD or DS being active.
100 of 124
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DS32501/DS32502/DS32503/DS32504
Figure 12-3. Parallel CPU Interface Intel Read Timing Diagram (Nonmultiplexed)
t1
t9a
A[9:1]
WR
t2
t4
CS
RD
t10
t15
t3
t5
D[15:0]
Figure 12-4. Parallel CPU Interface Intel Write Timing Diagram (Nonmultiplexed)
t1
t9a
A[9:1]
RD
t2
t4
CS
t6
t10
WR
t7
t8
D[15:0]
101 of 124
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DS32501/DS32502/DS32503/DS32504
Figure 12-5. Parallel CPU Interface Motorola Read Timing Diagram (Nonmultiplexed)
t1
t9a
A[9:1]
R/W
CS
t2
t4
t10
t15
DS
t5
t3
D[15:0]
Figure 12-6. Parallel CPU Interface Motorola Write Timing Diagram (Nonmultiplexed)
t1
t9a
A[9:1]
R/W
CS
t2
t4
t6
t10
DS
t7
t8
D[15:0]
102 of 124
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DS32501/DS32502/DS32503/DS32504
Figure 12-7. Parallel CPU Interface Intel Read Timing Diagram (Multiplexed)
9b
t13
t11
ALE
t12
A[9:1]
t14
WR
CS
RD
t2
t4
t10
t15
t3
t5
D[15:0]
Figure 12-8. Parallel CPU Interface Intel Write Timing Diagram (Multiplexed)
9b
t13
t11
ALE
t12
A[9:1]
t14
RD
CS
t2
t4
t6
t10
WR
t7
t8
D[15:0]
103 of 124
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DS32501/DS32502/DS32503/DS32504
Figure 12-9. Parallel CPU Interface Motorola Read Timing Diagram (Multiplexed)
9b
t13
t11
ALE
t12
A[9:1]
t14
R/W
CS
t2
t4
t10
t15
DS
t3
t5
D[15:0]
Figure 12-10. Parallel CPU Interface Motorola Write Timing Diagram (Multiplexed)
9b
t13
t11
ALE
t12
A[9:1]
t14
R/W
CS
t2
t4
t6
t10
DS
t7
t8
D[15:0]
104 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
Table 12-9. SPI Interface Timing
(VDD18 = 1.8V ±10%, VDD33 = 3.3V ±5%, AVDD = 1.8V ±5%, TA = -40°C to +85°C.)
(See Figure 12-11.)
PARAMETER (Note 1)
SYMBOL
MIN
TYP
MAX
UNITS
SCLK Frequency
SCLK Cycle Time
fBUS
tCYC
tSUC
tHDC
tCLKH
tCLKL
tSUI
10
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100
15
15
50
50
5
CS Setup to First SCLK Edge
CS Hold Time After Last SCLK Edge
SCLK High Time
SCLK Low Time
SDI Data Setup Time
SDI Data Hold Time
tHDI
15
0
SDO Enable Time (High Impedance to Output Active)
SDO Disable Time (Output Active to High Impedance)
SDO Data Valid Time
tEN
tDIS
25
40
tDV
SDO Data Hold Time After Update SCLK Edge
tHDO
5
Note 1:
All timing is specified with 100pF load on all SPI pins.
105 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
Figure 12-11. SPI Interface Timing Diagram
CPHA = 0
CS
tHDC
tSUC
tCYC
tCLKL
SCLK,
CPOL=0
tCLKH
tCLKL
SCLK,
CPOL=1
tCLKH
tSUI tHDI
SDI
tDV
tDIS
SDO
tEN
tHDO
CPHA = 1
CS
tHDC
tSUC
tCYC
tCLKL
SCLK,
CPOL=0
tCLKH
tCLKL
SCLK,
CPOL=1
tCLKH
tSUI tHDI
SDI
tDV
tDIS
SDO
tEN
tHDO
106 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
Table 12-10. JTAG Interface Timing
(VDD18 = 1.8V ±10%, VDD33 = 3.3V ±5%, AVDD = 1.8V ±5%, TA = -40°C to +85°C.)
(See Figure 12-12.)
PARAMETER
JTCLK Clock Period
SYMBOL
MIN
TYP
1000
500
MAX
UNITS
ns
t1
t2/t3
t4
JTCLK Clock High/Low Time (Note 1)
JTCLK to JTDI, JTMS Setup Time
JTCLK to JTDI, JTMS Hold Time
JTCLK to JTDO Delay
50
50
50
2
ns
ns
t5
ns
t6
50
50
ns
JTCLK to JTDO High-Impedance Delay (Note 2)
JTRST Width Low Time
t7
2
ns
t8
100
ns
Note 1:
Note 2:
Clock can be stopped high or low.
Not tested during production test.
Figure 12-12. JTAG Timing Diagram
t1
t2
t3
JTCLK
t4
t5
JTDI
JTMS
JTRST
t6
t7
JTDO
t8
JTRST
107 of 124
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DS32501/DS32502/DS32503/DS32504
13. PIN ASSIGNMENTS
Table 13-1. Pin Assignments Sorted by Signal Name for DS32504 (Microprocessor
Interface Mode)
SIGNAL
BALL
SIGNAL
BALL
SIGNAL
BALL
SIGNAL
BALL
A0
A1
A2
A3
A4
A5
A6
A7
A8
A4
B4
C4
F5
A3
G5
B3
E4
C3
D4
F8
K6
K5
M5
L5
GPIOA2
GPIOA3
GPIOA4
GPIOB1
GPIOB2
GPIOB3
GPIOB4
HIZ
IFSEL0
IFSEL1
IFSEL2
INT
H3
C10
J5
G3
G4
D10
M4
J4
A2
A1
F4
G8
K3
RLOS4
RNEG1
RNEG2
RNEG3
RNEG4
RPOS1
RPOS2
RPOS3
RPOS4
RST
RVDD1
RVDD2
RVDD3
RVDD4
RVSS1
RVSS2
RVSS3
RVSS4
RXN1
RXN2
RXN3
RXN4
RXP1
RXP2
RXP3
RXP4
TCLK1
TCLK2
TCLK3
TCLK4
TEST
TNEG1
TNEG2
TNEG3
TNEG4
TOE1
J8
F10
H10
C11
K12
E11
G11
A12
J12
M2
E2
K2
B8
L10
F2
L2
B7
L11
F1
L1
A7
M11
E1
K1
A8
M10
F12
H12
D11
L12
M1
G10
J11
D12
M12
J7
TOE2
TOE3
TOE4
J9
H7
K10
F11
H11
C12
K11
C2
H2
B10
L8
D2
J2
B9
L9
D3
J3
TPOS1
TPOS2
TPOS3
TPOS4
TPVSS1
TPVSS2
TPVSS3
TPVSS4
TVDD1
TVDD2
TVDD3
TVDD4
TVSS1
TVSS2
TVSS3
TVSS4
TXN1
TXN2
TXN3
TXN4
TXP1
TXP2
TXP3
TXP4
A9
ALE
CLKA
CLKB
CLKC
CLKD
CS
CVDD
CVDD
CVSS
D0
D1
D2
D3
D4
D5
D6
D7
D8
JTCLK
JTDI
JTDO
L3
K4
L4
M3
B1
F9
L6
JTMS
JTRST
M6
K7
C8
D9
C7
D8
D6
D7
A6
E7
B6
A5
C6
B5
E9
C5
D5
E6
F3
JTVDD1
JTVDD2
JTVDD3
JTVDD4
JVSS1
JVSS2
JVSS3
JVSS4
MT
RCLK1
RCLK2
RCLK3
RCLK4
RD/DS
REFCLK
RESREF
RLOS1
RLOS2
RLOS3
C9
K9
D1
J1
G1
A11
M7
B2
G2
B11
L7
H4
E12
G12
B12
J10
G9
K8
A9
M9
C1
H1
A10
M8
E5
H8
E8
H5
F6
VDD18
VDD18
VDD33
VDD33
VSS
VSS
VSS
VSS
WR/R/W
D9
D10
D11
D12
D13
D14
D15
GPIOA1
E3
J6
H9
H6
F7
G6
G7
E10
Note: See Figure 13-1 for the pin assignment diagram.
108 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
Figure 13-1. DS32504 Pin Assignment—Microprocessor Interface Mode
1
2
3
4
5
6
7
8
9
10
11
12
IFSEL1
IFSEL0
A4
A0
D9
D6
RXN3
RXP3
TXN3
TXP3
JTVDD3 RPOS3
JVSS3 RCLK3
GPIOA3 RNEG3 TPOS3
A
B
C
D
E
F
A
B
C
D
E
F
JTVDD1 JVSS1
A6
A8
A1
A2
A9
A7
D11
D13
D8
D10
RVSS3
D2
RVDD3
D0
TVDD3 TPVSS3
TXP1
TXN1
RXP1
RXN1
TPVSS1
TVDD1
TVSS3
D1
TVSS1
D14
D4
D5
D3
GPIOB3
TCLK3
RPOS1
TPOS1
RPOS2
TPOS2
TNEG3
RCLK1
TCLK1
RCLK2
TCLK2
RVDD1 RESREF
VDD18
A3
D15
D7
VDD33
ALE
D12
WR/R/W
RNEG1
TNEG1
RNEG2
RCLK4
TOE4
RVSS1 GPIOA1 IFSEL2
VSS
VSS
RLOS3
VSS
CS
JTVDD2 JVSS2
GPIOB1 GPIOB2
MT
A5
VSS
INT
G
H
J
RD/DS
RLOS2
TOE2
G
H
J
TXP2
TXN2
RXP2
RXN2
TPVSS2 GPIOA2
VDD33
TOE3
TOE1
CVSS
JVSS4
VDD18
RLOS4
TVDD2
RVDD2
RVSS2
TVSS2
JTCLK
JTDI
GPIOA4 RLOS1
TNEG2 RPOS4
TPOS4 RNEG4
HIZ
JTDO
JTMS
CLKB
CLKD
CLKA
CVDD
REFCLK TVSS4
K
L
K
L
TVSS4
TVDD4
RVDD4
RVSS4
TCLK4
GPIOB4
CLKC
CVDD
JTVDD4
TXP4
TXN4
RXP4
RXN4
TNEG4
TEST
RST
JTRST
M
M
1
2
3
4
5
6
7
8
9
10
11
12
High-Speed Analog
Low-Speed Analog
High-Speed Digital
Low-Speed Digital
Digital I/O VDD, 3.3V
Digital Core VDD, 1.8V
Digital VSS
Analog VDD, 1.8V
Analog VSS
N.C. and Manufacturing Test. Not Connected.
109 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
Figure 13-2. DS32504 Pin Assignment—SPI Interface Mode
1
2
3
4
5
6
7
8
9
10
11
12
IFSEL1
IFSEL0
N.C.
N.C.
N.C.
CPHA
RXN3
RXP3
TXN3
TXP3
JTVDD3 RPOS3
JVSS3 RCLK3
A
B
C
D
E
F
A
B
C
D
E
F
JTVDD1 JVSS1
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
RVSS3
SCLK
N.C.
RVDD3
SDO
TVDD3
TVSS3
SDI
TVSS3
TXP1
TXN1
RXP1
RXN1
TVSS1
TVDD1
GPIOA3 RNEG3 TPOS3
TVSS1
N.C.
N.C.
N.C.
GPIOB3
N.C.
TCLK3
RPOS1
TPOS1
RPOS2
TPOS2
TNEG3
RCLK1
TCLK1
RCLK2
TCLK2
RVDD1 RESREF
VDD18
N.C.
N.C.
CPOL
VSS
VDD33
ALE
N.C.
RVSS1 GPIOA1 IFSEL2
VSS
RNEG1
TNEG1
RNEG2
RCLK4
TOE4
CS
JTVDD2 JVSS2
GPIOB1 GPIOB2
MT
N.C.
VSS
VSS
N.C.
INT
G
H
J
G
H
J
TXP2
TXN2
RXP2
RXN2
TVSS2 GPIOA2
VDD33
RLOS3
TOE3
TOE1
CVSS
JVSS4
VDD18
RLOS4
RLOS2
TOE2
TVDD2
RVDD2
RVSS2
TVSS2
JTCLK
JTDI
GPIOA4 RLOS1
TNEG2 RPOS4
TPOS4 RNEG4
HIZ
JTDO
JTMS
CLKB
CLKD
CLKA
CVDD
REFCLK TVSS4
K
L
K
L
TVSS4
TVDD4
RVDD4
RVSS4
TCLK4
GPIOB4
CLKC
CVDD
JTVDD4
TXP4
TXN4
RXP4
RXN4
TNEG4
TEST
RST
JTRST
M
M
1
2
3
4
5
6
7
8
9
10
11
12
High-Speed Analog
Low-Speed Analog
High-Speed Digital
Low-Speed Digital
Digital I/O VDD, 3.3V
Digital Core VDD, 1.8V
Digital VSS
Analog VDD, 1.8V
Analog VSS
N.C. and Manufacturing Test. Not Connected.
110 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
Figure 13-3. DS32504 Pin Assignment—Hardware Mode
1
2
3
4
5
6
7
8
9
10
11
12
IFSEL1
IFSEL0
TAIS1
TLBO1 RMON2
LB3[1]
RXN3
RXP3
TXN3
TXP3
JTVDD3 RPOS3
JVSS3 RCLK3
RNEG3 TPOS3
TCLK3 TNEG3
RPOS1 RCLK1
TPOS1 TCLK1
RPOS2 RCLK2
TPOS2 TCLK2
TNEG2 RPOS4
TPOS4 RNEG4
RVSS4 TCLK4
A
B
C
D
E
F
A
B
C
D
E
F
JTVDD1 JVSS1
TAIS3
RBIN
TLBO2 RMON4 RMON1 RVSS3
RVDD3
LB1[0]
TVDD3
TVSS3
LB2[0]
JAS0
TVSS3
LM3[1]
LM3[0]
TPD
TXP1
TXN1
RXP1
RXN1
TVSS1
TVDD1
TLBO3
TCLKI
JAS1
JAD0
RMON3
LB1[1]
JAD1
LB3[0]
LB2[1]
LB4[1]
VSS
TVSS1
LB4[0]
RVDD1 RESREF TAIS4
VDD18
TLBO4
TAIS2
VDD33
LM4[1]
CLKB
VDD33
TBIN
RVSS1
LM1[1]
LM1[0]
LM2[1]
TVSS2
JTCLK
JTDI
IFSEL2
LM2[0]
MT
VSS
RCLKI
RPD
RNEG1
TNEG1
RNEG2
RCLK4
TOE4
JTVDD2 JVSS2
VSS
VSS
CLADBYP
VDD18
RLOS4
REFCLK
TVSS4
G
H
J
G
H
J
TXP2
TXN2
RXP2
RXN2
TVSS2
TVDD2
RVDD2
RVSS2
RLOS3
RLOS1
CLKA
CVDD
TOE3
TOE1
CVSS
JVSS4
RLOS2
TOE2
HIZ
JTDO
JTMS
TVSS4
TVDD4
K
L
K
L
CLKD
RVDD4
LM4[0]
CLKC
CVDD
JTVDD4
TXP4
TXN4
RXP4
RXN4
TNEG4
TEST
RST
JTRST
M
M
1
2
3
4
5
6
7
8
9
10
11
12
High-Speed Analog
Low-Speed Analog
High-Speed Digital
Low-Speed Digital
Digital I/O VDD, 3.3V
Digital Core VDD, 1.8V
Digital VSS
Analog VDD, 1.8V
Analog VSS
N.C. and Manufacturing Test. Not Connected.
111 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
Figure 13-4. DS32503 Pin Assignment—Microprocessor Interface Mode
1
2
3
4
5
6
7
8
9
10
11
12
IFSEL1
IFSEL0
A4
A0
D9
D6
RXN3
RXP3
TXN3
TXP3
JTVDD3 RPOS3
JVSS3 RCLK3
A
B
C
D
E
F
A
B
C
D
E
F
JTVDD1
TXP1
JVSS1
TVSS1
TVDD1
A6
A8
A1
A2
D11
D13
D8
D10
RVSS3
D2
RVDD3
D0
TVDD3
TVSS3
D1
TVSS3
GPIOA3 RNEG3 TPOS3
TXN1
TVSS1
N.C.
A7
D14
D4
D5
D3
GPIOB3
TCLK3
RPOS1
TPOS1
RPOS2
TPOS2
TNEG2
N.C.
TNEG3
RCLK1
TCLK1
RCLK2
TCLK2
N.C.
RXP1
RXN1
JTVDD2
TXP2
RVDD1 RESREF
VDD18
A3
D15
D7
VDD33
ALE
D12
WR/R/W
RNEG1
TNEG1
RNEG2
N.C.
RVSS1 GPIOA1 IFSEL2
JVSS2 GPIOB1 GPIOB2
TVSS2 GPIOA2
VSS
VSS
VSS
TOE3
TOE1
CVSS
N.C.
CS
A5
VSS
INT
G
H
J
RD/DS
RLOS2
TOE2
N.C.
G
H
J
MT
HIZ
VDD33
N.C.
RLOS3
RLOS1
CLKA
CVDD
VDD18
N.C.
TXN2
TVDD2
RVDD2
RVSS2
TVSS2
JTCLK
JTDI
RXP2
RXN2
JTDO
JTMS
CLKB
CLKD
REFCLK
N.C.
N.C.
N.C.
K
L
K
L
N.C.
N.C.
N.C.
N.C.
N.C.
CLKC
CVDD
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
TEST
RST
JTRST
M
M
1
2
3
4
5
6
7
8
9
10
11
12
High-Speed Analog
Low-Speed Analog
High-Speed Digital
Low-Speed Digital
Digital I/O VDD, 3.3V
Digital Core VDD, 1.8V
Digital VSS
Analog VDD, 1.8V
Analog VSS
N.C. and Manufacturing Test. Not Connected.
112 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
Figure 13-5. DS32503 Pin Assignment—SPI Interface Mode
1
2
3
4
5
6
7
8
9
10
11
12
IFSEL1
IFSEL0
N.C.
N.C.
N.C.
CPHA
RXN3
RXP3
TXN3
TXP3
JTVDD3 RPOS3
JVSS3 RCLK3
A
B
C
D
E
F
A
B
C
D
E
F
JTVDD1 JVSS1
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
RVSS3
SCLK
N.C.
RVDD3
SDO
TVDD3
TVSS3
SDI
TVSS3
TXP1
TXN1
RXP1
RXN1
TVSS1
TVDD1
GPIOA3 RNEG3 TPOS3
TVSS1
N.C.
N.C.
N.C.
GPIOB3
N.C.
TCLK3
RPOS1
TPOS1
RPOS2
TPOS2
TNEG2
N.C.
TNEG3
RCLK1
TCLK1
RCLK2
TCLK2
N.C.
RVDD1 RESREF
VDD18
N.C.
N.C.
CPOL
VSS
VDD33
ALE
N.C.
RVSS1 GPIOA1 IFSEL2
VSS
RNEG1
TNEG1
RNEG2
N.C.
CS
JTVDD2 JVSS2
GPIOB1 GPIOB2
MT
N.C.
VSS
VSS
N.C.
INT
G
H
J
G
H
J
TXP2
TXN2
RXP2
RXN2
TVSS2 GPIOA2
VDD33
N.C.
RLOS3
RLOS1
CLKA
CVDD
TOE3
TOE1
CVSS
N.C.
VDD18
N.C.
RLOS2
TOE2
N.C.
TVDD2
RVDD2
RVSS2
TVSS2
JTCLK
JTDI
HIZ
JTDO
JTMS
CLKB
CLKD
REFCLK
N.C.
N.C.
N.C.
K
L
K
L
N.C.
N.C.
N.C.
N.C.
N.C.
CLKC
CVDD
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
TEST
RST
JTRST
M
M
1
2
3
4
5
6
7
8
9
10
11
12
High-Speed Analog
Low-Speed Analog
High-Speed Digital
Low-Speed Digital
Digital I/O VDD, 3.3V
Digital Core VDD, 1.8V
Digital VSS
Analog VDD, 1.8V
Analog VSS
N.C. and Manufacturing Test. Not Connected.
113 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
Figure 13-6. DS32503 Pin Assignment—Hardware Mode
1
2
3
4
5
6
7
8
9
10
11
12
IFSEL1
IFSEL0
TAIS1
TLBO1 RMON2
LB3[1]
RXN3
RXP3
TXN3
TXP3
JTVDD3 RPOS3
JVSS3 RCLK3
RNEG3 TPOS3
TCLK3 TNEG3
RPOS1 RCLK1
TPOS1 TCLK1
RPOS2 RCLK2
TPOS2 TCLK2
A
B
C
D
E
F
A
B
C
D
E
F
JTVDD1 JVSS1
TAIS3
RBIN
TLBO2
TLBO3
TCLKI
N.C.
N.C.
JAS1
JAD0
VDD18
N.C.
RMON1 RVSS3
RVDD3
LB1[0]
N.C.
TVDD3
TVSS3
LB2[0]
JAS0
TVSS3
LM3[1]
LM3[0]
TPD
TXP1
TXN1
RXP1
RXN1
TVSS1
TVDD1
RMON3
LB1[1]
JAD1
LB3[0]
LB2[1]
N.C.
TVSS1
RVDD1 RESREF
VDD33
TBIN
RVSS1
LM1[1]
LM1[0]
LM2[1]
TVSS2
JTCLK
JTDI
IFSEL2
LM2[0]
MT
VSS
VSS
RCLKI
RPD
RNEG1
TNEG1
RNEG2
N.C.
JTVDD2 JVSS2
TAIS2
VDD33
N.C.
VSS
VSS
CLADBYP
VDD18
N.C.
G
H
J
G
H
J
TXP2
TXN2
RXP2
RXN2
TVSS2
TVDD2
RVDD2
RVSS2
RLOS3
RLOS1
CLKA
CVDD
TOE3
TOE1
CVSS
N.C.
RLOS2
TOE2
N.C.
TNEG2
N.C.
N.C.
N.C.
N.C.
HIZ
JTDO
JTMS
CLKB
CLKD
REFCLK
N.C.
N.C.
K
L
K
L
N.C.
N.C.
N.C.
N.C.
CLKC
CVDD
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
TEST
RST
JTRST
M
M
1
2
3
4
5
6
7
8
9
10
11
12
High-Speed Analog
Low-Speed Analog
High-Speed Digital
Low-Speed Digital
Digital I/O VDD, 3.3V
Digital Core VDD, 1.8V
Digital VSS
Analog VDD, 1.8V
Analog VSS
N.C. and Manufacturing Test. Not Connected.
114 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
Figure 13-7. DS32502 Pin Assignment—Microprocessor Interface Mode
1
2
3
4
5
6
7
8
9
10
11
12
IFSEL1
IFSEL0
A4
A0
D9
D6
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
A
B
C
D
E
F
A
B
C
D
E
F
JTVDD1 JVSS1
A6
A8
A1
A2
D11
D13
D8
D10
N.C.
D2
N.C.
D0
N.C.
N.C.
D1
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
TXP1
TXN1
RXP1
RXN1
TVSS1
TVDD1
TVSS1
N.C.
A7
D14
D4
D5
D3
GPIOB3
N.C.
N.C.
RVDD1 RESREF
VDD18
A3
D15
D7
VDD33
ALE
D12
RPOS1
TPOS1
RPOS2
TPOS2
TNEG2
N.C.
RCLK1
TCLK1
RCLK2
TCLK2
N.C.
WR/R/W
RNEG1
TNEG1
RNEG2
N.C.
RVSS1 GPIOA1 IFSEL2
VSS
VSS
N.C.
RLOS1
CLKA
CVDD
VSS
VSS
N.C.
TOE1
CVSS
N.C.
CS
JTVDD2 JVSS2
GPIOB1 GPIOB2
MT
A5
INT
G
H
J
RD/DS
RLOS2
TOE2
N.C.
N.C.
G
H
J
TXP2
TXN2
RXP2
RXN2
TVSS2 GPIOA2
VDD33
N.C.
VDD18
N.C.
TVDD2
RVDD2
RVSS2
TVSS2
JTCLK
JTDI
HIZ
JTDO
JTMS
CLKB
CLKD
REFCLK
N.C.
N.C.
N.C.
K
L
K
L
N.C.
N.C.
N.C.
N.C.
CLKC
CVDD
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
TEST
RST
JTRST
M
M
1
2
3
4
5
6
7
8
9
10
11
12
High-Speed Analog
Low-Speed Analog
High-Speed Digital
Low-Speed Digital
Digital I/O VDD, 3.3V
Digital Core VDD, 1.8V
Digital VSS
Analog VDD, 1.8V
Analog VSS
N.C. and Manufacturing Test. Not Connected.
115 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
Figure 13-8. DS32502 Pin Assignment—SPI Interface Mode
1
2
3
4
5
6
7
8
9
10
11
12
IFSEL1
IFSEL0
N.C.
N.C.
N.C.
CPHA
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
A
B
C
D
E
F
A
B
C
D
E
F
JTVDD1 JVSS1
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
SCLK
N.C.
N.C.
SDO
N.C.
N.C.
SDI
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
TXP1
TXN1
RXP1
RXN1
TVSS1
TVDD1
TVSS1
N.C.
N.C.
N.C.
GPIOB3
N.C.
N.C.
N.C.
RVDD1 RESREF
VDD18
N.C.
N.C.
CPOL
VSS
VDD33
ALE
N.C.
CS
RPOS1
TPOS1
RPOS2
TPOS2
TNEG2
N.C.
RCLK1
TCLK1
RCLK2
TCLK2
N.C.
RVSS1 GPIOA1 IFSEL2
VSS
RNEG1
TNEG1
RNEG2
N.C.
JTVDD2 JVSS2
GPIOB1 GPIOB2
MT
N.C.
VSS
VSS
N.C.
RLOS2
TOE2
N.C.
N.C.
INT
G
H
J
G
H
J
TXP2
TXN2
RXP2
RXN2
TVSS2 GPIOA2
VDD33
N.C.
N.C.
N.C.
VDD18
N.C.
TVDD2
RVDD2
RVSS2
TVSS2
JTCLK
JTDI
RLOS1
CLKA
CVDD
TOE1
CVSS
N.C.
HIZ
JTDO
JTMS
CLKB
CLKD
REFCLK
N.C.
N.C.
N.C.
K
L
K
L
N.C.
N.C.
N.C.
N.C.
CLKC
CVDD
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
TEST
RST
JTRST
M
M
1
2
3
4
5
6
7
8
9
10
11
12
High-Speed Analog
Low-Speed Analog
High-Speed Digital
Low-Speed Digital
Digital I/O VDD, 3.3V
Digital Core VDD, 1.8V
Digital VSS
Analog VDD, 1.8V
Analog VSS
N.C. and Manufacturing Test. Not Connected.
116 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
Figure 13-9. DS32502 Pin Assignment—Hardware Mode
1
2
3
4
5
6
7
8
9
10
11
12
IFSEL1
IFSEL0
TAIS1
TLBO1 RMON2
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
A
B
C
D
E
F
A
B
C
D
E
F
JTVDD1 JVSS1
N.C.
RBIN
TLBO2
N.C.
N.C.
JAS1
JAD0
VDD18
N.C.
RMON1
N.C.
N.C.
N.C.
N.C.
LB1[0]
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
TXP1
TXN1
RXP1
RXN1
TVSS1
TVDD1
TVSS1
TCLKI
N.C.
LB1[1]
JAD1
VSS
LB2[1]
N.C.
LB2[0]
JAS0
RCLKI
RPD
N.C.
RVDD1 RESREF
VDD33
TBIN
TPD
RPOS1 RCLK1
TPOS1 TCLK1
RPOS2 RCLK2
TPOS2 TCLK2
RVSS1
LM1[1]
LM1[0]
LM2[1]
TVSS2
JTCLK
JTDI
IFSEL2
LM2[0]
MT
VSS
RNEG1
TNEG1
RNEG2
N.C.
JTVDD2 JVSS2
TAIS2
VDD33
N.C.
VSS
VSS
CLADBYP
VDD18
N.C.
G
H
J
G
H
J
TXP2
TXN2
RXP2
RXN2
TVSS2
TVDD2
RVDD2
RVSS2
N.C.
N.C.
RLOS2
TOE2
N.C.
RLOS1
CLKA
CVDD
TOE1
CVSS
N.C.
TNEG2
N.C.
N.C.
N.C.
N.C.
HIZ
JTDO
JTMS
CLKB
CLKD
REFCLK
N.C.
N.C.
K
L
K
L
N.C.
N.C.
N.C.
N.C.
CLKC
CVDD
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
TEST
RST
JTRST
M
M
1
2
3
4
5
6
7
8
9
10
11
12
High-Speed Analog
Low-Speed Analog
High-Speed Digital
Low-Speed Digital
Digital I/O VDD, 3.3V
Digital Core VDD, 1.8V
Digital VSS
Analog VDD, 1.8V
Analog VSS
N.C. and Manufacturing Test. Not Connected.
117 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
Figure 13-10. DS32501 Pin Assignment—Microprocessor Interface Mode
1
2
3
4
5
6
7
8
9
10
11
12
IFSEL1
IFSEL0
A4
A0
D9
D6
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
A
B
C
D
E
F
A
B
C
D
E
F
JTVDD1 JVSS1
A6
A1
A2
D11
D13
D8
D10
N.C.
D2
N.C.
D0
N.C.
N.C.
D1
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
TXP1
TXN1
RXP1
RXN1
N.C.
TVSS1
TVDD1
N.C.
TVSS1
N.C.
A7
D14
D4
D5
D3
GPIOB3
N.C.
N.C.
RVDD1 RESREF
VDD18
A3
D15
D7
VDD33
ALE
D12
CS
RPOS1
TPOS1
N.C.
RCLK1
TCLK1
N.C.
WR/R/W
RNEG1
TNEG1
N.C.
RVSS1 GPIOA1 IFSEL2
VSS
VSS
N.C.
RLOS1
CLKA
CVDD
VSS
VSS
N.C.
TOE1
CVSS
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
GPIOB1 GPIOB2
A5
INT
G
H
J
RD/DS
N.C.
N.C.
N.C.
N.C.
G
H
J
N.C.
N.C.
N.C.
MT
HIZ
VDD33
N.C.
VDD18
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
JTCLK
JTDI
JTDO
JTMS
CLKB
CLKD
REFCLK
N.C.
N.C.
N.C.
N.C.
K
L
K
L
N.C.
N.C.
N.C.
N.C.
N.C.
CLKC
CVDD
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
TEST
RST
JTRST
M
M
1
2
3
4
5
6
7
8
9
10
11
12
High-Speed Analog
Low-Speed Analog
High-Speed Digital
Low-Speed Digital
Digital I/O VDD, 3.3V
Digital Core VDD, 1.8V
Digital VSS
Analog VDD, 1.8V
Analog VSS
N.C. and Manufacturing Test. Not Connected.
118 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
Figure 13-11. DS32501 Pin Assignment—SPI Interface Mode
1
2
3
4
5
6
7
8
9
10
11
12
IFSEL1
IFSEL0
N.C.
N.C.
N.C.
CPHA
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
A
B
C
D
E
F
A
B
C
D
E
F
JTVDD1 JVSS1
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
SCLK
N.C.
N.C.
SDO
N.C.
N.C.
SDI
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
TXP1
TXN1
RXP1
RXN1
N.C.
TVSS1
TVDD1
TVSS1
N.C.
N.C.
N.C.
GPIOB3
N.C.
N.C.
N.C.
RVDD1 RESREF
VDD18
N.C.
N.C.
CPOL
VSS
VDD33
ALE
N.C.
CS
RPOS1
TPOS1
N.C.
RCLK1
TCLK1
N.C.
RVSS1 GPIOA1 IFSEL2
VSS
RNEG1
TNEG1
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
GPIOB1 GPIOB2
N.C.
VSS
VSS
N.C.
N.C.
N.C.
N.C.
N.C.
INT
G
H
J
G
H
J
N.C.
N.C.
N.C.
MT
HIZ
VDD33
N.C.
N.C.
N.C.
VDD18
N.C.
N.C.
N.C.
N.C.
RLOS1
CLKA
CVDD
TOE1
CVSS
N.C.
N.C.
N.C.
N.C.
N.C.
JTCLK
JTDI
JTDO
JTMS
CLKB
CLKD
REFCLK
N.C.
N.C.
N.C.
N.C.
K
L
K
L
N.C.
N.C.
N.C.
N.C.
N.C.
CLKC
CVDD
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
TEST
RST
JTRST
M
M
1
2
3
4
5
6
7
8
9
10
11
12
High-Speed Analog
Low-Speed Analog
High-Speed Digital
Low-Speed Digital
Digital I/O VDD, 3.3V
Digital Core VDD, 1.8V
Digital VSS
Analog VDD, 1.8V
Analog VSS
N.C. and Manufacturing Test. Not Connected.
119 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
Figure 13-12. DS32501 Pin Assignment—Hardware Mode
1
2
3
4
5
6
7
8
9
10
11
12
IFSEL1
IFSEL0
TAIS1
TLBO1
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
A
B
C
D
E
F
A
B
C
D
E
F
JTVDD1 JVSS1
N.C.
RBIN
N.C.
N.C.
N.C.
JAS1
JAD0
VDD18
N.C.
RMON1
N.C.
N.C.
N.C.
N.C.
N.C.
VSS
VSS
N.C.
TOE1
CVSS
N.C.
N.C.
LB1[0]
N.C.
N.C.
N.C.
N.C.
JAS0
RCLKI
RPD
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
TXP1
TXN1
RXP1
RXN1
N.C.
TVSS1
TVDD1
TVSS1
TCLKI
N.C.
LB1[1]
JAD1
VSS
N.C.
RVDD1 RESREF
VDD33
TBIN
TPD
RPOS1 RCLK1
TPOS1 TCLK1
RVSS1
N.C.
LM1[1]
LM1[0]
N.C.
IFSEL2
N.C.
RNEG1
TNEG1
N.C.
N.C.
VSS
CLADBYP
VDD18
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
G
H
J
G
H
J
N.C.
N.C.
MT
VDD33
N.C.
N.C.
N.C.
N.C.
N.C.
RLOS1
CLKA
CVDD
N.C.
HIZ
N.C.
N.C.
JTCLK
JTDI
JTDO
JTMS
CLKB
CLKD
REFCLK
N.C.
N.C.
K
L
K
L
N.C.
N.C.
N.C.
N.C.
CLKC
CVDD
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
TEST
RST
JTRST
M
M
1
2
3
4
5
6
7
8
9
10
11
12
High-Speed Analog
Low-Speed Analog
High-Speed Digital
Low-Speed Digital
Digital I/O VDD, 3.3V
Digital Core VDD, 1.8V
Digital VSS
Analog VDD, 1.8V
Analog VSS
N.C. and Manufacturing Test. Not Connected.
120 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
14. PACKAGE INFORMATION
(The package drawing(s) in this data sheet may not reflect the most current specifications. The package number provided for
each package is a link to the latest package outline information.)
14.1 13mm x13mm 144-Lead TE-CSBGA (56-G6016-001)
121 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
15. THERMAL INFORMATION
Table 15-1. Thermal Properties—Natural Convection
PARAMETER
Ambient Temperature (Note 1)
Junction Temperature
Theta-JA (θJA), Still Air (Note 2)
Psi-JB
MIN
-40°C
-40°C
TYP
MAX
+85°C
+125°C
22.4°C/W
9.2°C/W
1.6°C/W
Psi-JT
Note 1:
Note 2:
The package is mounted on a four-layer JEDEC standard test board with no airflow and dissipating maximum power.
Theta-JA (θJA) is the junction to ambient thermal resistance, when the package is mounted on a four-layer JEDEC standard test
board with no airflow and dissipating maximum power.
Table 15-2. Theta-JA (θJA) vs. Airflow
FORCED AIR
(METERS PER
THETA-JA (θJA)
SECOND)
0
1
2
22.4°C/W
19.0°C/W
17.2°C/W
122 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
16. TRADEMARK ACKNOWLEDGEMENTS
SPI is a trademark of Motorola, Inc.
ACCUNET is a registered trademark of AT&T.
Telcordia is a registered trademark of Telcordia Technologies.
123 of 124
PRELIMINARY
DS32501/DS32502/DS32503/DS32504
17. DATA SHEET REVISION HISTORY
REVISION
DATE
DESCRIPTION
042007
Initial data sheet release.
124 of 124
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.
No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2007 Maxim Integrated Products
The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation.
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