DS2182AQN [MAXIM]
Framer, CMOS, PQCC28, PLASTIC, LCC-28;
| 型号： | DS2182AQN |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Framer, CMOS, PQCC28, PLASTIC, LCC-28 电信 电信集成电路 |
| 文件： | 总26页 (文件大小：296K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS2182A
T1 Line Monitor Chip
www.maxim-ic.com
FEATURES
PIN ASSIGNMENT (Top View)
§ Performs framing and monitoring functions
§ Supports Superframe and extended
Superframe formats
INT
SDI
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
2
RLOS
§ Four on-board error counters
SDO
3
RFER
-
-
-
-
16-bit bipolar violation
8-bit CRC
8-bit OOF
CS
4
RBV
SCLK
NC
5
RCL
6
RNEG
RPOS
8-bit frame bit error
RYEL
RLINK
RLCLK
RCLK
RCHCLK
RSER
N.C.
7
§ Indication of the following
8
RST
-
-
-
-
-
-
Yellow and blue alarms
Incoming B8ZS code words
8 and 16 zero strings
Change-of-frame alignment
Loss-of-sync
9
TEST
10
11
12
13
14
RSIGSEL
RSIGFR
RABCD
RMSYNC
RFSYNC
Carrier loss
VSS
§ Simple serial interface used for
configuration, control, and status monitoring
§ Burst mode allows quick access to counters
for status updates
28-Pin DIP (600mil)
§ Automatic counter reset feature
§ Single 5V supply; low-power CMOS
technology
§ Available in 28-pin DIP and 28-pin PLCC
§ The DS2182A is upward-compatible from
the original DS2182
ORDERING INFORMATION
PIN-
PACKAGE
TEMP
RANGE
PART
DS2182A
28 DIP
28 DIP
0°C to +70°C
-40°C to +85°C
0°C to +70°C
DS2182AN
DS2182AQ
DS2182AQN
28 PLCC
28 PLCC
The DS2182A includes the following changes
from the original DS2182:
-40°C to +85°C
§ Ability to count excessive zeros
§ Severely errored-framing-event indication
§ Updated AIS detection
§ Updated RCL detection
§ AIS and RCL alarm clear indications
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: http://www.maxim-ic.com/errata.
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080802
DS2182A
DESCRIPTION
The DS2182A T1 line monitor chip is a monolithic CMOS device designed to monitor real-time
performance on T1 lines. The DS2182A frames to the data on the line, counts errors, and supplies
detailed information about the status and condition of the line. Large on-board counters allow the
accumulation of errors for extended periods, which permits a single CPU to monitor a number of T1
lines. Output clocks that are synchronized to the incoming data stream are provided for easy extraction of
S-Bits, FDL bits, signaling bits, and channel data. The DS2182A meets the requirements of ANSI
T1.231.
Figure 1. BLOCK DIAGRAM
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DS2182A
Table 1. PIN DESCRIPTION
PIN
SYMBOL TYPE
FUNCTION
Receive Alarm Interrupt. Flags host controller during alarm conditions.
1
O
I
INT
SDI
Active low; open-drain output.
2
3
Serial Data In. Data for on-board registers. Sampled on rising edge of SCLK.
Serial Data Out. Control and status information from on-board registers.
Updated on falling edge of SCLK; tri-stated during serial port write or when
CS is high.
SDO
O
4
5
I
I
Chip Select. Must be low to read or write the serial port.
CS
SCLK
Serial Data Clock. Used to read or write the serial port registers.
No Connect. No internal connection. This pin can be connected to either VSS
6, 13
N.C.
—
or VDD, or it can be floated.
Receive Yellow Alarm. Transitions high when a yellow alarm detected; goes
7
RYEL
O
low when the alarm clears.
Receive Link Data. Updated with extracted FDL data one RCLK before start
of odd frames (193E) and held until next update. Updated with extracted S-bit
data one RCLK before start of even frames (193S) and held until next update.
8
RLINK
O
9
RLCLK
RCLK
O
I
Receive Link Clock. 4kHz demand clock for RLINK
10
Receive Clock. 1.544MHz primary clock
Receive Channel Clock. 192kHz clock; identifies timeslot (channel)
11
12
15
16
RCHCLK
RSER
O
O
O
O
boundaries
Receive Serial Data. Received NRZ serial data; updated on rising edges of
RCLK
Receive Frame Sync. Extracted 8kHz clock, one RCLK wide; F-bit position
RFSYNC
RMSYNC
in each frame
Receive Multiframe Sync. Extracted multiframe sync; positive-going edge
indicates start of multiframe; 50% duty cycle
Receive ABCD Signaling. Extracted signaling data output; valid for each
channel in signaling frames. In non-signaling frames, RABCD outputs the
LSB of each channel word.
17
RABCD
O
Receive Signaling Frame. High during signaling frames; low during non-
18
19
21
RSIGFR
O
O
I
signaling frames (and during resync)
Receive Signaling Select. In 193E framing, a .667kHz clock that identifies
RSIGSEL
signaling frames A and C; a 1.33kHz clock in 193S
Reset. A high-low transition clears all internal registers and resets counters. A
RST
high-low-high transition initiates a resync.
22
23
RPOS
RNEG
Receive Bipolar Data Inputs. Sampled on falling of RCLK. Connect together
I
to receive NRZ data and disable bipolar violation monitoring circuitry.
Receive Carrier Loss. High if 192 consecutive 0’s appear at RPOS and
24
25
26
27
RCL
O
O
O
O
RNEG; goes low upon seeing 12.5% 1’s density.
Receive Bipolar Violation. High during accused bit time at RSER. If bipolar
RBV
violation detected, low otherwise.
Receive Frame Error. High during F-bit time when FT or FS errors occur
RFER
RLOS
(193S), or when FPS or CRC errors occur (193E). Low during resync.
Receive Loss-of-Sync. Indicates sync status; high when internal resync is in
progress, low otherwise.
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DS2182A
Table 2. POWER AND TEST PIN DESCRIPTION
PIN
SYMBOL
TYPE
FUNCTION
14
20
28
VSS
TEST
VDD
—
I
—
Signal Ground. 0V
Test Mode. Connect to VSS for normal operation.
Positive Supply. 5.0V
Table 3. REGISTER SUMMARY
REGISTER
ADDRESS
FUNCTION
Bipolar Violation Count Register 2. LSW of a 16-bit presettable
BVCR2
0000
counter that records individual bipolar violations.
Bipolar Violation Count Register 1. MSW of a 16-bit presettable
BVCR1
CRCCR
OOFCR
0001
0010
0011
counter that records individual bipolar violations.
CRC Error Count Register. 8-bit presettable counter that records
CRC6 errored words in the 193E frame mode.
OOF Count Register. 8-bit presettable counter that records OOF
events. OOF events are defined by RCR1.5 and RCR1.6.
Frame Error Count Register. 8-bit presettable counter that records
FECR
RSR1
0100
0101
0110
0111
1000
individual bit errors in the framing pattern.
Receive Status Register 1. Reports alarm conditions.
Receive Interrupt Mask Register 1. Allows masking of individual
RIMR1
RSR2
alarm-generated interrupts from RSR1.
Receive Status Register 2. Reports alarm conditions.
Receive Interrupt Mask Register 2. Allows masking of individual
RIMR2
alarm-generated interrupts from RSR2.
Receive Control Register 1. Programs device operating
RCR1
RCR2
1001
1010
characteristics.
Receive Control Register 2. Programs device operating
characteristics.
SERIAL PORT INTERFACE
The port pins of the DS2182A serve as a microprocessor/microcontroller-compatible serial port. Eleven
on-board registers allow the user to update operational characteristics and monitor device status through a
host controller, minimizing hardware interfaces. The port on the DS2182A can be read from or written to
at any time. Serial port reads and writes are independent of T1 line timing signals RCLK, RPOS, and
RNEG. However, RCLK is needed in order to clear RSR1 and RSR2 after reads.
ADDRESS/COMMAND
Reading or writing the control, configuration, or status registers requires writing one address/command
byte prior to transferring register data. The first bit written (LSB) of the address/command word specifies
register read or write. The following 4 bits identify the register address. The next 2 bits are reserved and
must be set to 0 for proper operation. The last bit of the address/ command word enables burst mode
when set; the burst mode causes all registers to be consecutively read or written to. Data is read and
written to the DS2182A LSB first.
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DS2182A
CHIP SELECT AND CLOCK CONTROL
All data transfers are initiated by driving the CS input low. Input data is latched on the rising edge of
SCLK and must be valid during the previous low period of SCLK to prevent momentary corruption of
register data during writes. Data is output on the falling edge of SCLK and held to the next falling edge.
All data transfers are terminated if the CS input transitions high. Port control logic is disabled and SDO is
tri-stated when CS is high.
DATA I/O
Following the eight SCLK cycles that input an address/command byte to write, a data byte is strobed into
the addressed register on the rising edge of the next eight SCLK cycles. Following an address/command
word to read, contents of the selected register are output on the falling edges of the next eight SCLK
cycles. The SDO pin is tri-stated during device write and can be connected to SDI in applications where
the host processor has a bidirectional I/O pin.
BURST MODE
The burst mode allows all on-board registers to be consecutively written to or read by the host processor.
A burst read is used to poll all registers; RSR1 and RSR2 contents are unaffected. This feature minimizes
device initialization time on system power-up or reset. Burst mode is initiated when ACB.7 is set and the
address is 0000. A burst is terminated by a low-high transition on CS .
ACB: ADDRESS COMMAND BYTE
MSB
BM
LSB
R/ W
—
—
ADD3
ADD2
ADD1
ADD0
SYMBOL
POSITION
FUNCTION
Burst Mode. If set (and register address is 0000), burst read or
BM
ACB.7
write is enabled.
—
ACB.6
ACB.5
Reserved; must be 0 for operation
-—
Reserved; must be 0 for operation
ADD3
ADD0
ACB.4
ACB.1
MSB of register address
LSB of register address
Read/Write Select
R/W
ACB.0
0 = write addressed register
1 = read addressed register
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DS2182A
Figure 2. SERIAL PORT READ/WRITE
NOTES:
1) SDI is sampled on rising edge of SCLK.
2) SDO is updated on falling edge of SCLK.
OPERATION OF THE COUNTERS
All four of the counters in the DS2182A can be preset by the user to establish an event-count interrupt
threshold. The counters count up from the preset value until they reach saturation. At saturation, each
additional event occurrence sets the appropriate bit in RSR2 and generates an interrupt if enabled by
RIMR2.
The DS2182A contains an auto-counter reset feature in the burst read mode. If RCR1.4 is set, then the
user can burst read the four counters (five registers), and all four counters are automatically reset to 0
after the read takes place. Since the burst mode can be terminated at any time by taking CS high, the user
has the option of reading all of the registers or only the counters. If RCR1.4 is set, then any read of the
registers, burst mode or not, clears the count in all four counters. If the user wishes to read the port and
not clear the counters, then RCR1.4 must be cleared first.
The counter registers can be read or written to at any time with the serial port, which operates totally
asynchronously with the monitoring of the T1 line. Reading a register does not affect the count as long as
RCR1.4 is cleared. The dual buffer architecture of the DS2182A ensures that no error events are missed
while the serial port is being accessed for reads.
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DS2182A
BVCR1: BIPOLAR VIOLATION COUNT REGISTER 1;
BVCR2: BIPOLAR VIOLATION COUNTER REGISTER 2
MSB
LSB
BV0
BV7
BV6
BV5
BV4
BV3
BV2
BV1
SYMBOL
BV7
POSITION
BVCR.7
BVCR.0
FUNCTION
MSB of bipolar violation count
LSB of bipolar violation count
BV0
Bipolar violation count register 1 (BVCR1) is the most significant word and BVCR2 is the least
significant word of a presettable 16-bit counter that records individual bipolar violations. If the B8ZS
mode is enabled (RCR2.2 = 1), then B8ZS code words are not counted. The BVCR can also be
programmed to count excessive 0’s by setting the RCR2.5 bit. In this mode, the BVCR counts
occurrences of eight consecutive 0’s when B8ZS is enabled or 16 consecutive 0’s when B8Z5 is disabled.
This counter increments at all times and is not disabled by a loss-of-sync condition (RLOS = 1). The
counter saturates at 65,535 and generates an interrupt for each occurrence after saturation if RIMR2.0 is
set.
Note: To properly preset the bipolar violation count register, BVCR2 must be written to before BVCR1
is written to.
CRCCR: CRC COUNT REGISTER 2
MSB
CRC7
LSB
CRC0
CRC6
CRC5
CRC4
CRC3
CRC2
CRC1
SYMBOL
CRC7
POSITION
CRCCR.7
CRCCR.0
FUNCTION
MSB of CRC6 word error count
LSB of CRC6 word error count
CRC0
The CRC count register (CRCCR) is an 8-bit presettable counter that records word errors in the cyclic
redundancy check (CRC). This 8-bit binary counter saturates at 255 and generates an interrupt for each
occurrence after saturation if RIMR2.1 is set. The count in this register is only valid in the 193E framing
mode (RCR2.4 = 1), and is reset and disabled in the 193S framing mode (RCR2.4 = 0). The count is
disabled during a loss-of-sync condition (RLOS = 1).
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DS2182A
OOFCR: OOF COUNT REGISTER
MSB
LSB
OOF0
OOF7
OOF6
OOF5
OOF4
OOF3
OOF2
OOF1
SYMBOL
OOF7
POSITION
OOFCR.7
OOFCR.0
FUNCTION
MSB of OOF event count
LSB of OOF of event count
OFF0
The OOF count register (OOFCR) is an 8-bit presettable counter that records out-of-frame (OOF) events.
OOF events are defined by RCR1.5 and RCR1.6. This 8-bit counter saturates at 255 and generates an
interrupt for each occurrence after saturation if RIMR2.2 is set. The count is disabled during a loss-of-
sync condition (RLOS = 1).
FECR: FRAME ERROR COUNT REGISTER
MSB
FE7
LSB
FE0
FE6
FE5
FE4
FE3
FE2
FE1
SYMBOL
FE7
POSITION
FECR.7
FECR.0
FUNCTION
MSB of frame error count
LSB of frame error count
FFE0
The frame error count register (FECR) is an 8-bit presettable counter that records individual frame-bit
errors. In the 193E mode (RCR2.4 = 1), the FECR records bit errors in the FPS framing pattern (001011).
In the 193S mode (RCR2.4 = 0), the FECR records bit errors in both the FT (101010) and FS (001110)
framing patterns if RCR1.3 is set. If RCR1.3 is cleared, then the FECR only records bit errors in the FT
pattern. This 8-bit counter saturates at 255 and generates an interrupt for each occurrence after saturation
if RIMR2.3 is set. The count is disabled during a loss-of-sync condition (RLOS = 1).
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DS2182A
RSR1: RECEIVE STATUS REGISTER 1
MSB
LSB
COFA
8ZD
16ZD
RCL
RYEL
RLOS
B8ZSD
RBL
SYMBOL
POSITION
FUNCTION
8 Zero Detect. Set when a string of eight consecutive 0’s has been
8ZD
RSR1.7
RSR1.6
received at RPOS and RNEG.
16 Zero Detect. Set when a string of 16 consecutive 0’s has been
received at RPOS and RNEG.
16ZD
RCL
Receive Carrier Loss. Set when a string of 192 consecutive 0’s
has been received at RPOS and RNEG. Cleared when 14 or more
1’s out of 112 possible bit positions are received.
RSR1.5
Receive Yellow Alarm. Set when yellow alarm is detected. The
RYEL
RLOS
RSR1.4
RSR1.3
format of yellow alarm is determined by RCR2.3 and RCR2.4.
Receive Loss-of-Sync. Set when resync is in progress.
B8ZS Code Word Detect. Set when a B8ZS code word is
received at RPOS and RNEG independent of whether the B8ZS
mode is enabled or not (RCR2.2).
B8ZSD
RSR1.2
Receive Blue Alarm. Set when over a 3ms window, five or fewer
0’s are received. Cleared when over a 3ms window, six or more 0’s
are received.
RBL
RSR1.1
RSR1.0
Change-of-Frame Alignment. Set when the last resync resulted in
a change-of-frame or multiframe alignment.
COFA
Note: Alarm 8ZD and 16ZD are cleared on the next occurrence of a 1 at RPOS and RNEG.
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DS2182A
RECEIVE STATUS REGISTERS
The receive status registers (RSR1 and RSR2) can be used in either a polled or an interrupt configuration.
In a polled configuration, the user reads the RSR at regular intervals to check for alarms. In an interrupt
configuration, the user monitors the INT pin. When the INT pin goes low, an alarm condition has
occurred and has been reported in one of the RSRs. The processor can then read the RSRs to find which
bits have been set. All of the bits in the RSRs operate in a latched fashion. That is, once set, they remain
set until read. The bits in the RSR are cleared when read unless the read was performed in the burst mode
or the alarm condition still exists.
YELLOW ALARM
193S BIT 2. If RCR2.4 = 0 and RCR2.3 = 0, then the DS2182A examines bit 2 of all incoming channels
for the presence of a yellow alarm. If bit 2 is set to 0 in 256 consecutive channels, then the reception of a
yellow alarm is declared. The alarm is considered cleared when the first channel with bit 2 set to a 1 is
received.
193S S-BIT. If RCR2.4 = 0 and RCR2.3 = 1, then the DS2182A examines the S-bit position of frame 12
for the presence of a yellow alarm. The DS2182A declares the presence of a yellow alarm on the first
occurrence of the S-bit in frame 12 being set to 1. The alarm is considered cleared when this S-bit returns
to 0.
193E FDL. If RCR2.4 = 1, then the DS2182A examines the FDL for a repeating 00FF pattern. If this
pattern is received in the FDL 16 consecutive times without error, then a yellow alarm is declared. The
alarm is considered cleared as soon as any pattern other than 00FF is received.
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DS2182A
RIMR1: RECEIVE INTERRUPT MASK REGISTER 1
MSB
LSB
COFA
8ZD
16ZD
RCL
RYEL
RLOS
B8ZSD
RBL
SYMBOL
8ZD
POSITION
FUNCTION
8 Zero Detect Mask
1 = interrupt enabled
0 = interrupt masked
16 Zero Detect Mask
1 = interrupt enabled
0 = interrupt masked
RIMR1.7
RIMR1.6
RIMR1.5
RIMR1.4
RIMR1.3
RIMR1.2
RIMR1.1
RIMR1.0
16ZD
RCL
Receive Carrier Loss Mask
1 = interrupt enabled
0 = interrupt masked
Receive Yellow Alarm Mask
1 = interrupt enabled
RYEL
RLOS
B8ZSD
RBL
0 = interrupt masked
Receive Loss-of-Sync Mask
1 = interrupt enabled
0 = interrupt masked
B8ZS Code Word Detect Mask
1 = interrupt enabled
0 = interrupt masked
Receive Blue Alarm Mask
1 = interrupt enabled
0 = interrupt masked
Change-of-Frame Alignment Mask
1 = interrupt enabled
COFA
0 = interrupt masked
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DS2182A
RSR2: RECEIVE STATUS REGISTER 2
MSB
LSB
BPVCS
SEFE
RCLC
RBLC
FERR
FECS
OOFS
CRCCS
SYMBOL
POSITION
FUNCTION
Severely Errored Framing Event. Set when two out of six framing
SEFE
RSR2.7
bits (Ft or FPS) are received in error.
Receive Carrier Loss Clear. Set when the carrier signal is restored;
remains set until read.
RCLC
RSR2.6
Receive Blue Alarm Clear. Set when the Blue Alarm (AIS) is no
RBLC
FERR
FECS
RSR2.5
RSR2.4
RSR2.3
longer detected; remains set until read.
Frame Bit Error. Set when FT (193S) or FPS (193E) bit errors occur.
Frame Error-Count Saturation. Set on the next frame error event
after the 8-bit frame error-count register (FECR) saturates at 255.
Out-of-Frame Count Saturation. Set on the next OOF event after the
8-bit OOF Count Register (OOFCR) saturates at 255.
CRC Count Saturation. Set on the next CRC error event after the 8-bit
CRC Count Register (CRCCR) saturates at 255.
Bipolar Violation Count Saturation. Set on the next BPV error event
after the 16-bit Bipolar Violation Count Register (BVCR) saturates at
65,535.
OOFCS
CRCCS
RSR2.2
RSR2.1
BPVCS
RSR2.0
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DS2182A
RIMR2: RECEIVE INTERRUPT MASK REGISTER 2
MSB
LSB
BPVCS
SEFE
RCLC
RBLC
FERR
FECS
OOFS
CRCCS
SYMBOL
SEFE
POSITION
FUNCTION
Severely Errored Framing-Event Mask
RIMR2.7
RIMR2.6
RIMR2.5
RIMR2.4
RIMR2.3
RIMR2.2
RIMR2.1
RIMR2.0
0 = interrupt masked
1 = interrupt enabled
Receive Carrier Loss Clear Mask
0 = interrupt masked
RCLC
RBLC
1 = interrupt enabled
Receive Blue Alarm Clear Mask
0 = interrupt masked
1 = interrupt enabled
Frame Bit Error Mask
1 = interrupt enabled
FERR
0 = interrupt masked
Frame Error-Count Saturation Mask
1 = interrupt enabled
FECS
0 = interrupt masked
Out-of-Frame Count Saturation Mask
1 = interrupt enabled
OOFCS
CRCCS
BPVCS
0 = interrupt masked
CRC Count Saturation Mask
1 = interrupt enabled
0 = interrupt masked
Bipolar Violation Count Saturation Mask
1 = interrupt enabled
0 = interrupt masked
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DS2182A
RCR1: RECEIVE CONTROL REGISTER 1
MSB
LSB
RESYNC
ARC
OOF1
OOF2
ACR
SYNCC
SYNCT
SYNCE
SYMBOL
ARC
POSITION
FUNCTION
Auto Resync Criteria
RCR1.7
RCR1.6
1 = resync on OOF event only
0 = resync on OOF event or Receive Carrier Loss (RCL)
Out-of-Frame 1. OOF event description. Valid when RCR1.5 is
cleared.
OOF1
1 = 2 out of 5 frame bits (FT or FPS) in error
0 = 2 out of 4 frame bits (FT or FPS) in error
Out-of-Frame 2. OOF event description.
1 = 2 out of 6 frame bits (FT or FPS) in error
0 = follow OOF event described in RCR1.6
Auto Counter Reset. When set, all four of the counters are reset to
0 when read.
OOF2
ACR
RCR1.5
RCR1.4
Sync Criteria. Determines the type of algorithm used by the
receive synchronizer; differs for each frame mode.
193S Framing (RCR2.4 = 0)
0 = synchronize to frame boundaries using FT pattern, then search
for multiframe by using FS
SYNCC
RCR1.3
1 = cross couple FT and FS patterns in sync algorithm
193E Framing (RCR2.4 = 1)
0 = normal sync (uses FPS only)
1 = validate new alignment with CRC before declaring sync
Sync Time
SYNCT
SYNCE
RCR1.2
RCR1.1
RCR1.0
1 = validate 24 consecutive F-bits before declaring sync
0 = validate 10 consecutive F-bits before declaring sync
Sync Enable. If clear, the DS2182A automatically begins a resync
if the conditions described in RCR1.7 are met. If set, no auto
resync occurs.
Resync. When toggled low to high, the DS2182A initiates a resync
immediately. The bit must be cleared and set again for subsequent
resyncs.
RESYNC
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DS2182A
SYNCHRONIZER
The heart of the monitor is the receive synchronizer. This circuit serves two purposes: 1) monitors the
incoming data stream for loss-of-frame or multiframe alignment, and 2) searches for new frame
alignment pattern when sync loss is detected. When sync loss is detected, the synchronizer begins an off-
line search for the new alignment; all output timing signals remain at the old alignment with the exception
of RSIGFR, which is forced low during resync. When one and only one candidate is qualified, the output
timing moves to the new alignment at the beginning of the next multiframe. One frame later, RLOS will
transition low, indicating valid sync and the resumption of the normal sync-monitoring mode. Several bits
in the RCR1 allow tailoring of the resync algorithm by the user. These bits are described below.
SYNC CRITERIA (RCR1.3)
193E. Bit RCR1.3 determines which sync algorithm is used when resync is in progress (RLOS = 1). In
193E framing, when RCR1.3 = 0, the synchronizer locks only to the FPS pattern and moves to the new
frame and multiframe alignment after the framing candidate is qualified. RLOS goes low one frame after
the move to the new alignment. When RCR1.3 = 1, the new alignment is further tested by a CRC6 code
match. RLOS transitions low after a CRC6 match occurs. If no CRC6 match occurs in three attempts
(three multiframes), the algorithm resets and a new search for the FPS pattern begins. It takes 9ms for the
synchronizer to check the first CRC6 code after the new FPS alignment has been loaded. Each additional
CRC6 test takes 3ms. Regardless of the state of RCR1.3, if more than one candidate exists after 24ms, the
synchronizer begins eliminating emulators by testing their CRC6 codes in order to find the true framing
candidate.
193S. In 193S framing, when RCR1.3 = 1, the synchronizer cross-checks the FT pattern with the FS
pattern to help eliminate false-framing candidates such as digital milliwatts. The FS patterns are
compared to the repeating pattern ...00111000111000...(00111x0 if RCR2.3 = 1). In this mode, FT and
FS must be correctly identified by the synchronizer before sync is declared. Clearing RCR1.3 causes the
synchronizer to search for the FT pattern (101010...) without cross-coupling the FS pattern. Frame sync is
established using the FT information, while multiframe sync is established only if valid FS information is
present. If no valid FS pattern is identified, the synchronizer moves to the FT alignment, RLOS goes low,
and a false multiframe position can be indicated by RMSYNC. RFER indicates when the received S-bit
pattern does not match the assumed internal multiframe alignment. This mode is used in applications
where nonstandard S-bit patterns exist. In such applications, multiframe alignment information can be
decoded externally by using the S-bits present at RLINK.
SYNC TIME (RCR1.2)
Bit RCR1.2 determines the number of consecutive framing pattern bits to be qualified before SYNC is
declared. If RCR1.2 =1, the algorithm validates 24 bits; if RCR1.2 = 0, 10 bits are validated. Validating
24 bits results in superior false-framing protection while 10-bit testing minimizes reframe time. In either
case, the synchronizer only establishes resync when one and only one candidate is found (Table 4).
Table 4. AVERAGE REFRAME TIME
FRAME
RCR1.2 = 0
AVG
RCR1.2 = 1
AVG
MODE
193S
193E
MIN
3.0ms
6.0ms
MAX
4.5ms
9.0ms
MIN
6.5ms
13.0ms
MAX
8.0ms
16.0ms
3.75ms
7.5ms
7.25ms
14.5ms
Note: Average reframe time is defined here as the average time it takes from the start of resync (rising edge of RLOS) to the actual loading of
the new alignment (on a multiframe edge) into the output receive timing.
15 of 26
DS2182A
SYNC ENABLE (RCR1.1)
When RCR1.1 is cleared, the receiver initiates automatic resync if an OOF event occurs or if carrier loss
(192 consecutive 0’s) occurs (depends on RCR1.7). When RCR1.1 is set, the automatic resync circuitry is
disabled. In this case, resync can only be initiated by setting RCR1.0 to 1 or externally transitioning RST
from low to high. Note that using RST to initiate a resync resets the output timing while RST is low; use
of RCR1.1 does not affect the output timing until the new alignment is located.
RESYNC (RCR1.0)
A 0-to-1 transition of RCR1.0 causes the synchronizer to search for the framing pattern sequence
immediately, regardless of the internal sync status. To initiate another resync command, this bit must be
cleared and then set again.
RCR2: RECEIVE CONTROL REGISTER 2
MSB
LSB
—
—
—
BVCRF
FM
SFYEL
B8ZS
—
SYMBOL
POSITION
FUNCTION
—
—
RCR2.7
RCR2.6
Reserved; must be 0 for proper operation
Reserved; must be 0 for proper operation
Bipolar Violation Count Register Function Select
0 = do not count excessive 0’s
1 = count excessive 0’s
BVCRF
FM
RCR2.5
RCR2.4
RCR2.3
RCR2.2
Frame Mode
1 = Extended Superframe (193E, 24 frames per Superframe)
0 = Superframe (193S or D4, 12 frames per Superframe)
SF Yellow Mode Select
SFYEL
B8ZS
1 = 1 in the S-bit position of frame 12
0 = 0 in bit 2 of all channels
Bipolar Eight-Zero Substitution
1 = B8ZS enabled
0 = B8ZS disabled
—
—
RCR2.1
RCR2.10
Reserved; must be 0 for proper operation
Reserved; must be 0 for proper operation
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DS2182A
Figure 3. 193S RECEIVE MULTIFRAME TIMING
NOTES:
1) Signaling data is updated during signaling frames on channel boundaries. Pin RABCD is the LSB of
each channel word in nonsignaling frames.
2) RLINK data (S-bit) is updated one bit-time prior to S-bit frames and held for two frames.
Figure 4. 193E RECEIVE MULTIFRAME TIMING
NOTES:
1) Signaling data is updated during signaling frames on channel boundaries. Pin RABCD is the LSB of
each channel word in nonsignaling frames.
2) RLINK data (FDL data) is updated one bit-time prior to odd frames and held for two frames.
17 of 26
DS2182A
Figure 5. RECEIVE MULTIFRAME BOUNDARY TIMING
NOTES:
1) RLINK timing is shown for 193E; in 193S, RLINK is updated on even frame boundaries and is held
across multiframe edges.
2) Total delay from RPOS and RNEG to RSER output is 13 RCLK periods.
ALARM OUTPUTS
The transceiver also provides direct alarm outputs for applications when additional decoding and
demuxing are required to supplement the on-board alarm logic.
RLOS OUTPUT
The receive loss-of-sync output indicates the status of the receiver synchronizer circuitry; when high, an
off-line resynchronization is in progress and a high-low transition indicates that resync is complete. The
RLOS bit (RSR1.3) is a latched version of the RLOS output. If the auto-resync mode is selected
(RCR1.1 = 0), RLOS is a real-time indication of a carrier loss or OOF event occurrence.
RYEL OUTPUT
The yellow alarm output transitions high when a yellow alarm is detected. A high-low transition indicates
the alarm condition has been cleared. The RYEL bit (RSR1.4) is a latched version of the RYEL output.
RBV OUTPUT
The bipolar violation output transitions high when the accused bit emerges at RSER. RBV goes low at the
next bit time if no additional violations are detected.
18 of 26
DS2182A
RFER OUTPUT
The receive frame-error output transitions high at the F-bit time and is held high for 2-bit periods when a
frame bit error occurs. In 193S, framing FT and FS patterns are tested. The FPS pattern is tested in 193E
framing. Additionally, in 193E framing, RFER reports CRC6 code word errors by a low-high-low
transition (1-bit period-wide) one-half RCLK period before a low-high transition on RMSYNC
(Figure 6).
RESET
A high-low transition on RST clears all registers and forces an immediate resync when RST returns high.
RST must be held low on system power-up to ensure proper initialization of the counters and registers.
Following reset, the host processor should restore all control modes by writing appropriate registers with
control data.
Figure 6. ALARM OUTPUT TIMING
NOTES:
1) RFER transitions high during F-bit time if received framing pattern bit is in error. (Frame 12 F-bits in
193S are ignored if RCR2.3 = 1.) Also, in 193E, RFER transitions high 1/2 bit-time before rising
edge of RMSYNC to indicate a CRC6 error for the previous multiframe.
2) RBV indicates received bipolar violation and transitions high when accused bit emerges from RSER.
If B8ZS is enabled, RBV does not report the zero replacement code.
3) RCL transitions high when 192 consecutive bits are 0; RCL transitions low upon reception of 12.5%
1’s density.
4) RLOS transitions high during F-bit time that caused an OOF event if auto-resync is enabled
(RCR1.1 = 0). Resync also occurs when loss-of-carrier is detected (RCL = 1) if RCR1.7 = 0. When
RCR1.1 = 1, RLOS remains low until resync occurs, regardless of OOF or carrier loss flags. In this
situation, resync is initiated only when RCR1.0 transitions low-to-high or the RST pin transitions
high-low-high.
19 of 26
DS2182A
ABSOLUTE MAXIMUM RATINGS*
Voltage Range on Any Pin Relative to Ground
Operating Temperature Range
-0.1V to +7.0V
0°C to +70°C
Storage Temperature Range
-55°C to +125°C
Soldering Temperature
See IPC/JEDEC J-STD-020A
*This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(TA = 0°C to +70°C)
PARAMETER
SYMBOL
MIN
TYP
MAX
VCC + 0.3
+0.8
UNITS NOTES
Input Logic 1
VIH
2.0
V
V
V
7
Input Logic 0
Supply
VIL
-0.3
4.50
VDD
5.50
DC ELECTRICAL CHARACTERISTICS
(VDD = 5V ±10%, TA = 0LC to +70LC)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS NOTES
Supply Current
IDD
IL
3
mA
µA
1, 2
3
Input Leakage
-1.0
-1.0
+4.0
-1.0
+1.0
Output Current (2.4V)
Output Current (0.4V)
Output Leakage
IOH
IOL
ILO
mA
mA
µA
4
5
+1.0
6
CAPACITANCE
PARAMETER
(TA = +25LC)
SYMBOL
CIN
MIN
TYP
MAX
UNITS NOTES
Input Capacitance
Output Capacitance
5
7
pF
pF
COUT
NOTES:
1) RCLK = 1.544MHz
2) Outputs open.
3) 0V < VIN < VDD
4) All outputs except INT , which is open-collector.
5) All outputs
6) Applies to SDO when tri-stated.
7) RCIL, SCIK, and RST VIH MIN = 2.4V.
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DS2182A
CHARACTERISTICS SERIAL PORT (Notes 1 and 2)
(VDD = 5V ±10%, TA = 0LC to +70LC)
PARAMETER
SDI to SCLK Setup
SCLK to SDI Hold
SYMBOL
tDC
MIN
50
TYP
MAX
UNITS NOTES
ns
ns
ns
ns
ns
ns
ns
tCHD
tCD
50
SDI to SCLK Falling Edge
SCLK Low Time
50
tCL
250
250
SCLK High Time
tCH
SCLK Rise and Fall Times
tR, tF
tCC
100
50
50
CS to SCLK Setup
SCLK to CS Hold
tCCH
tCWH
tCDV
tCDZ
ns
µs
ns
ns
2.5
CS Inactive Time
SCLK to SDO Valid
200
75
CS to SDO High-Z
NOTES:
1) Measured at VIH = 2.0 or VIL = 0.8 and 10ns maximum rise and fall time.
2) Output load capacitance = 100pF
21 of 26
DS2182A
AC ELECTRICAL CHARACTERISTICS, RECEIVE (Notes 1 and 2)
(VDD = 5.0V ±10%, TA = 0LC to +70LC)
PARAMETER
SYMBOL
MIN
TYP
MAX UNITS NOTES
Propagation Delay RCLK to
RMSYNC, RFSYNC, RSISEL,
RSIGFR, RLCLK, RCHCLK
tPRS
75
ns
Propagation Delay RCLK to RSER,
RABCD, RLINK
tPRD
75
20
ns
Transition Time, All Outputs
RCLK Period
tTTR
tP
ns
ns
ns
ns
648
324
20
RCLK Pulse Width
tR, tF
tCCH
RCLK Rise and Fall Times
RPOS, RNEG Setup to RCLK
Falling
tSRD
tHRD
tPRA
tRST
50
50
ns
ns
ns
µs
RPOS, RNEG Hold to RCLK Falling
Propagation Delay RCLK to RLOS,
RYEL, RBV, RCL, RFER
75
1
Minimum RST Pulse Width
NOTES:
1) Measured at VIH = 2.0 or VIL = 0.8 and 10ns maximum rise and fall time.
2) Output load capacitance = 100pF
22 of 26
DS2182A
Figure 7. SERIAL PORT WRITE AC TIMING DIAGRAM
Shaded regions indicate “don’t care” states of input.
NOTES:
1) Data byte bits must be valid across low clock periods to prevent transients in operating modes.
Figure 8. SERIAL PORT READAC TIMING DIAGRAM
NOTES:
1) Serial port write must precede a port read to provide address information.
23 of 26
DS2182A
Figure 9. RECEIVE AC TIMING DIAGRAM
24 of 26
DS2182A
DS2182A T1 LINE MONITOR 28-PIN DIP
INCHES
DIM
MIN
MAX
1.470
0.550
0.160
0.625
0.040
0.145
0.110
0.680
0.012
0.022
A
B
C
D
E
F
1.445
0.530
0.140
0.600
0.015
0.120
0.090
0.600
0.008
0.015
G
H
J
K
25 of 26
DS2182A
DS2182AQ T1 LINE MONITOR 28-PIN PLCC
INCHES
DIM
MIN
0.165
0.090
0.020
0.026
0.013
0.009
0.485
0.450
0.390
0.485
0.450
0.390
0.060
28
MAX
0.180
0.120
—
0.033
0.021
0.012
0.495
0.456
0.430
0.495
0.456
0.430
—
A
A1
A2
B
B1
C
D
D1
D2
E
E1
E2
L1
N
—
e1
CH1
0.050 BSC
0.042
0.048
26 of 26
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