DS2186S [MAXIM]
Digital SLIC, 1-Func, CMOS, PDSO20, 0.300 INCH, SOIC-20;
| 型号： | DS2186S |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Digital SLIC, 1-Func, CMOS, PDSO20, 0.300 INCH, SOIC-20 电信 光电二极管 电信集成电路 |
| 文件： | 总11页 (文件大小：138K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS2186
DS2186
Transmit Line Interface
FEATURES
PIN ASSIGNMENT
• Line interface for T1 (1.544 MHz) and CEPT (2.048
TAIS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
LCLK
LPOS
LNEG
TCLK
TPOS
TNEG
LB
MHz) primary rate networks
ZCSEN
TCLKSEL
LEN0
• On–chip transmit LBO (line build out) and line drivers
eliminate external components
• Programmable output pulse shape supports short–
and long–loop applications
LEN1
LEN2
• Supports bipolar and unipolar input data formats
V
DD
• Transparent B8ZS and HDB3 zero code suppression
modes
TTIP
MTIP
MRING
LF
TRING
• Compatible with DS2180A T1 and DS2181A CEPT
Transceivers DS2141A T1 and DS2143 E1 Control-
lers
V
SS
20–PIN DIP (300 MIL)
• Companion to the DS2187 Receive Line Interface
and DS2188 T1/CEPT Jitter Attenuator
TAIS
ZCSEN
TCLKSEL
LEN0
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
LCLK
LPOS
LNEG
TCLK
TPOS
TNEG
LB
• Single 5V supply; low–power CMOS technology
LEN1
LEN2
VDD
TTIP
MTIP
MRING
LF
TRING
VSS
20–PIN SOIC (300 Mil)
DESCRIPTION
The DS2186 T1/CEPT Transmit Line Interface Chip in-
terfaces user equipment to North American (T1–1.544
MHz) and European (CEPT–2.048 MHz) primary rate
communications networks. The device is compatible
with all types of twisted pair and coax cable found in
such networks.
Short loop (DSX–1, 0 to 655 feet) and long loop (CSU; 0
dB, –7.5 dB and –15 dB) pulse templates found in T1
applications are supported. Appropriate CCITT recom-
mendations are met in the CEPT mode.
Application areas include DACS, CSU, CPE, channel
banks, and PABX–to–computer interfaces such as DMI
and CPI. The DS2186 supports ISDN–PRI (Primary
Rate Interface) specifications.
Key on–chip components include: programmable wave
shaping circuitry, line drivers, remote loopback, and
zero suppression logic. A line–coupling transformer is
the only external component required.
022798 1/11
DS2186
DS2186 BLOCK DIAGRAM Figure 1
VSS
LNEG
LPOS
TTIP
LCLK
INPUT
ZERO CODE
SUPPRESSION
CIRCUITRY
LINE
DRIVERS
WAVESHAPPING
CIRCUITRY
DATA
TNEG
MUX
TPOS
TCLK
TRING
MTIP
LB
LINE DRIVER
MONITOR
ZCSEN
LEN0
LEN1 LEN2
MRING
LF
TAIS
TCLKSEL
VDD
SYSTEM LEVEL INTERCONNECT Figure 2
DS2187
AVDD
LCAP
DVDD
RAIS
AIS
10 µF
NC
ZCSEN
BPV
RCL
DS2180A/DS2181A
RCLKSEL
RTIP
RPOS
RNEG
RPOS
RNEG
RCLK
TSER
RSER
RRING
RECEIVE
PAIR
LOCK
AVSS
RCLK
DVSS
1:2
DS2186
RST
VDD
LCLK
LNEG
INT
CS
ZCSEN
LEN0
LPOS
TCLK
TCLK
TPOS
TNEG
SCLK
LEN1
SDO
SDI
TPOS
TNEG
LEN2
TCLKSEL
TAIS
LB
MTIP
MRING
LF
TRANSMIT
PAIR
TTIP
TRING
1.35:1
VSS
0.47 µF
NONPOLARIZED
SYSTEM CONTROLLER (DS5000)
022798 2/11
DS2186
PIN DESCRIPTION Table 1
PIN
SYMBOL
TYPE
DESCRIPTION
1
TAIS
I
Transmit Alarm Indication Signal. When high, output data is
forced to all ones at the TCLK (LB=0) or LCLK (LB=1) rate.
2
3
ZCSEN
I
I
I
Zero Code Suppression Enable. When high, B8ZS or HDB3
encoder enabled.
TCLKSEL
Transmit Clock Select. Tie to V for 1.544 MHz (T1) applica-
SS
tions, to V for 2.048 MHz (CEPT) applications.
DD
4
5
6
LEN0
LEN1
LEN2
Length Select 0, 1 and 2. State determines output T1 waveform
shape and characteristics.
7
V
DD
–
Positive Supply. 5.0 volts.
8
9
TTIP,
TRING
O
Transmit Tip and Ring. Line driver outputs; connect to transmit
line transformer.
10
11
V
–
Signal Ground. 0.0 volts.
SS
LF
O
Line Fault. Open collector active low output. Held low during an
output driver fault and/or failure; tri–stated otherwise.
12
13
MRING,
MTIP
I
I
Monitor Tip and Ring. Normally connected to TTIP and TRING.
Sense inputs for line fault detection circuitry.
14
LB
Loopback. When high, input data is sampled at LPOS and LNEG
on falling edges of LCLK; when low, input data is sampled at TPOS
and TNEG on falling TCLK.
15
16
TNEG,
TPOS
I
Transmit Data. Sampled on falling edges of TCLK when LB=0.
17
TCLK
I
I
Transmit Clock. 1.544 MHz or 2.048 MHz primary data clock.
Loopback Data. Sampled on falling edges of LCLK when LB=1.
18
19
LNEG,
LPOS
20
LCLK
I
Loopback Clock. 1.544 MHz or 2.048 MHz loopback data clock.
INPUT DATA MODES
ALARM INDICATION SIGNAL
Input data is sampled on the falling edge of TCLK or
LCLK and can be bipolar (dual rail) or unipolar (single
rail, NRZ). TPOS, TNEG and TCLK are the data and
clock inputs when LB=0, LPOS, LNEG and LCLK when
LB=1.TPOSandTNEG(LPOSandLNEG)mustbetied
together in NRZ applications.
When TAIS is set, an all ones code is continuously
transmitted at the TCLK rate (LB=0) or the LCLK rate
(LB=1).
WAVE SHAPING
The device supports T1 short loop (DSX–1; 0 to 655
feet), T1 long loop (CSU; 0 dB, –7.5 dB and –15 dB) and
CEPT (CCITT G.703) pulse template requirements.
On–chip laser trimmed delay lines clocked by either
TCLK or LCLK control a precision digital–to–analog
converter to build the desired waveforms, which are
buffered differentially by the line drivers.
ZERO CODE SUPPRESSION MODES
Transmitted data is treated transparently (no zero code
suppression) when ZCSEN=0. HDB3 code words re-
place any all–zero nibble when ZCSEN=1 and
TCLKSEL=1. B8ZS code words replace any incoming
all–zero byte when ZCSEN=1 and TCLKSEL=0.
022798 3/11
DS2186
The shape of the “pre–emphasized” T1 waveform is
controlled by inputs LEN0, LEN1, and LEN2
(TCLKSEL=0). These control inputs allow the user to
select the appropriate output pulse shape to meet
DSX–1 or CSU templates over a wide variety of cable
types and lengths. Those cable types include ABAM,
PIC, and PULP.
LINE DRIVERS
The on–chip differential line drivers interface directly to
the output transformer. To optimize device perform-
ance, length of the TTIP and TRING traces should be
minimized and isolated from neighboring interconnect.
FAULT PROTECTION
The line drivers are fault–protected and will withstand a
shorted transformer secondary (or primary) without
damage. Inputs MTIP and MRING are normally tied to
TTIP and TRING to provide fault monitoring capability.
Output LF will transition low if 192 TCLK cycles occur
without a one occurring at MTIP or MRING. LF will tri–
state on the next one occurrence or two TCLK periods
later, whichever is greater.
The CEPT mode is enabled when TCLKSEL=1. Only
one output pulse shape is available in the CEPT mode;
inputs LEN0, LEN1 and LEN2 can be any state except
all zeros.
The line coupling transformer also contributes to the
pulse shape seen at the cross–connect point. Trans-
formers for both T1 and CEPT applications must be
1:1.35.
The threshold of MTIP and MRING varies with the line
type selected at LEN0, LEN1 and LEN2. This insures
detection of the lowest level zero to one transition (–15
dB buildout) as it occurs on TTIP and TRING.
The wave shaping circuitry does not contribute signifi-
cantly to output jitter (less than 0.01 UIpp broadband).
Output jitter will be dominated by the jitter on TCLK or
LCLK. TCLK and LCLK need only be accurate in fre-
quency, not duty cycle.
T1 LINE LENGTH SELECTION Table 2
LEN2
LEN1
LEN0
OPTION SELECTED
Test mode
APPLICATION
Do not use
0
0
0
0
0
0
1
1
0
1
0
1
–7.5 dB buildout
–15 dB buildout
T1 CSU
T1 CSU
0 dB buildout,
0 – 133 feet
T1 CSU, DSX–1 Cross connect
1
1
1
1
0
0
1
1
0
1
0
1
133 – 266 feet
266 – 399 feet
399 – 533 feet
533 – 655 feet
DSX–1 Cross connect
DSX–1 Cross connect
DSX–1 Cross connect
DSX–1 Cross connect
NOTE:
1. TheLEN0, LEN1andLEN2inputscontrolT1outputwaveshapeswhenTCLKSEL=0.TheG.703(CEPT)template
is selected when TCLKSEL=1 and LEN0, LEN1, and LEN2 are at any state except all zeros.
022798 4/11
DS2186
DSX–1 ISOLATED PULSE TEMPLATE Figure 3
1.0
0.5
NORMALIZED
ALITITUDE
0.0
–0.5
0
250
500
750
1000
1250
NANOSECONDS
NOTES:
1. Template shown is measured at the cross–connect point.
2. Amplitude shown is normalized; the actual midpoint voltage measured may be between 2.4 and 3.6 volts.
3. The corner points shown below are joined by straight lines to form the template.
MAXIMUM CURVE
(0, 0.05)
MINIMUM CURVE
(0, –0.05)
(250, 0.05)
(325, 0.80)
(325, 1.15)
(425, 1.15)
(500, 1.05)
(675, 1.05)
(725, –0.07)
(875, 0.05)
(1250, 0.05)
(350, –0.05)
(350, 0.5)
(400, 0.95)
(500, 0.95)
(600, 0.9)
(650, 0.5)
(650, –0.45)
(800, –0.45)
(925, –0.2)
(1100, –0.05)
(1250, –0.05)
022798 5/11
DS2186
OUTPUT PULSE TEMPLATE AT 2.048 MHz Figure 4
1.2
1.0
NORMALIZED
AMPLITUDE
0.5
0.0
–0.2
250
NANOSECONDS
500
NOTES:
1. Unlikethe DSX–1 template, which is specified at the cross–connect point, the CEPT (2.048 MHz) template is spe-
cified at the transmit line output.
2. The template shown above is normalized. The actual pulse height is cable dependent and is specified in
Table 3.
3. The corner points shown below are joined by straight lines to form the template.
MAXIMUM CURVE
(0, 0.1)
MINIMUM CURVE
(0, –0.1)
(109.5, 0.5)
(109.5, 1.2)
(244, 1.1)
(134.5, –0.2)
(134.5, 0.5)
(147, 0.8)
(378.5, 1.2)
(378.5, 0.5)
(488, 0.1)
(244, 0.9)
(341, 0.8)
(353.5, 0.5)
(353.5, –0.2)
(488, –0.1)
022798 6/11
DS2186
CHARACTERISTICS OF T1 AND CEPT INTERFACES Table 3
CHARACTERISTIC
LINE RATE
T1
CEPT
1.544 MHz
2.048 MHz
1
LINE CODE
AMI or B8ZS
AMI or HDB3
TEST LOAD IMPEDANCE
100 ohm Resistive
120 ohm Resistive (wire pair)
75 ohm Resistive (coax)
2
NOMINAL PEAK
VOLTAGE
2.4V to 3.6 V
3.0V (wire pair)
2.37V (coax)
PULSE SHAPE
–Scaled to fit templates shown–
244 ns
NOMINAL PULSE WIDTH
PULSE IMBALANCE
324 ns
< 0.5 dB difference between
total power of positive and
negative pulses.
1) Negative peak = positive peak ±5%
2) Positive width at nominal half ampli-
tude = negative width at nominal half
amplitude ±5%.
NOTES:
1. With a ones density of at least 12.5% and no more than 15 consecutive zeros.
2. Measured at the cross–connect (DSX–1) point; CSU applications may be 7.5 to 15 dB below these levels.
022798 7/11
DS2186
ABSOLUTE MAXIMUM RATINGS*
Voltage on any Pin Relative to Ground
Operating Temperature
–1.0V to +7V
0°C to 70°C
Storage Temperature
Soldering Temperature
–55°C to +125°C
260°C for 10°C
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(0°C to 70°C)
PARAMETER
Logic 1
SYMBOL
MIN
2.0
TYP
MAX
UNITS
NOTES
V
IH
V
DD
+.3
V
V
V
1
1
Logic 0
V
IL
–0.3
4.75
+0.8
Supply
V
DD
5.25
DC ELECTRICAL CHARACTERISTICS
(0°C to 70° C; VDD = 5V ± 5%)
PARAMETER
SYMBOL
MIN
TYP
50
MAX
UNITS
mA
NOTES
Supply Current
Supply Current
Supply Current
Input Leakage
I
I
I
2,3
2,4
2,5
6
DD
DD
DD
35
mA
20
mA
I
IL
–1.0
+4.0
+1.0
µA
Output Current @ 0.4V
I
OL
mA
7
CAPACITANCE
PARAMETER
(tA = 25°C)
SYMBOL
MIN
TYP
MAX
UNITS
pF
NOTES
Input Capacitance
Output Capacitance
C
5
7
IN
C
pF
OUT
NOTES:
1. All inputs except MTIP and MRING.
2. V =5.25V; TCLK = LCLK = 1.544 MHz; output line transformer and load as shown in Figure 2.
DD
3. TAIS = 1
4. 50% ones density.
5. All zeros at data inputs.
6. 0.0V < V < 5.0V.
IN
7. Output LF (open collector).
022798 8/11
DS2186
AC ELECTRICAL CHARACTERISTICS
(0°C to 70°C; VDD = 5V ± 5%)
PARAMETER
SYMBOL
MIN
TYP
648
488
324
MAX
UNITS
ns
NOTES
TCLK, LCLK Period
TCLK, LCLK Period
TCLK, LCLK Pulse Width
t
t
1
2
1
CLK
CLK
ns
t
t
,
70
70
ns
RWH
t
RWL
TCLK, LCLK Pulse Width
,
244
ns
2
RWH
t
RWL
TCLK, LCLK Rise and Fall Times
t , t
20
ns
ns
R
F
TPOS, TNEG Setup to TCLK
Falling
t
50
50
50
50
STD
LPOS, LNEG Setup to LCLK
Falling
t
ns
ns
ns
STD
HTD
HTD
TPOS, TNEG Hold from TCLK
Falling
t
t
LPOS, LNEG Hold from LCLK
Falling
NOTES:
1. T1 applications.
2. CEPT applications.
AC TIMING DIAGRAM Figure 5
t
CLK
t
F
t
R
t
t
RWL
RWH
TCLK, LCLK
t
t
HTD
STD
TPOS, TNEG
LPOS, LNEG
022798 9/11
DS2186
DS2186 TRANSMIT LINE INTERFACE 20–PIN DIP
PKG
DIM
20–PIN
MIN
MAX
A IN.
MM
1.020
25.91
1.040
26.42
B
B IN.
MM
0.240
6.10
0.260
6.60
C IN.
MM
0.120
3.05
0.140
3.56
1
A
D IN.
MM
0.300
7.62
0.325
8.26
E IN.
MM
0.015
0.38
0.040
1.02
F IN.
MM
0.120
3.04
0.140
3.56
C
G IN.
MM
0.090
2.23
0.110
2.79
H IN.
MM
0.320
8.13
0.370
9.40
F
E
J IN.
MM
0.008
0.20
0.012
0.30
K
G
K IN.
MM
0.015
0.38
0.021
0.53
D
J
H
022798 10/11
DS2186
DS2186S TRANSMIT LINE INTERFACE 20–PIN SOIC
K
G
PKG
DIM
20–PIN
MIN
MAX
A IN.
MM
0.500
12.70
0.511
12.99
B IN.
MM
0.290
7.37
0.300
7.65
B
H
C IN.
MM
0.089
2.26
0.095
2.41
E IN.
MM
0.004
0.102
0.012
0.30
1
F IN.
MM
0.094
2.38
0.105
2.68
0.050 BSC
1.27 BSC
G IN.
MM
H IN.
MM
0.398
10.11
0.416
10.57
A
J IN.
MM
0.009
0.229
0.013
0.33
C
K IN.
MM
0.013
0.33
0.019
0.48
L IN.
MM
0.016
0.406
0.040
1.20
E
phi
0°
8°
F
phi
L
J
022798 11/11
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