DS1643+100 [MAXIM]
Real Time Clock, CMOS, ROHS COMPLIANT, EDIP MODULE-28;
| 型号： | DS1643+100 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Real Time Clock, CMOS, ROHS COMPLIANT, EDIP MODULE-28 时钟 双倍数据速率 外围集成电路 |
| 文件： | 总18页 (文件大小：372K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS1643/DS1643P
Nonvolatile Timekeeping RAMs
www.maxim-ic.com
FEATURES
PIN CONFIGURATIONS
CꢀIntegrated NV SRAM, Real-Time Clock,
Crystal, Power-Fail Control Circuit and
Lithium Energy Source
VCC
WE
CE2
A8
N.C.
A12
A7
1
28
TOP VIEW
27
2
3
4
5
6
7
8
DS1643
26
25
24
23
22
21
CꢀClock Registers are Accessed Identically to the
Static RAM. These Registers Reside in the
Eight Top RAM Locations.
A6
A5
A4
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
A3
CꢀTotally Nonvolatile with Over 10 Years of
Operation in the Absence of Power
CꢀAccess Times of 70ns and 100ns
CꢀBCD-Coded Year, Month, Date, Day, Hours,
Minutes, and Seconds with Leap Year
Compensation Valid Up to 2100
A2
A1
A0
9
10
20
19
DQ0
11
18
17
16
15
12
DQ1
DQ2
GND
13
14
CꢀPower-Fail Write Protection Allows for ±10%
Encapsulated DIP
(700-mil Extended)
VCC Power Supply Tolerance
CꢀLithium Energy Source is Electrically
Disconnected to Retain Freshness Until Power
is Applied for the First Time
N.C.
N.C.
N.C.
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
1
2
3
CꢀDS1643 Only (DIP Module)
Standard JEDEC Byte-Wide 8K x 8 RAM
Pinout
N.C.
N.C.
N.C.
DS1643P
N.C.
A12
A11
A10
A9
4
5
6
7
8
9
PFO
VCC
WE
OE
UL Recognized
CꢀDS1643P Only (PowerCap Module Board)
Surface Mountable Package for Direct
Connection to PowerCap Containing
Battery and Crystal
CE
A8
DQ7
A7
A6
A5
A4
A3
A2
A1
A0
10
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
11
12
13
14
15
16
17
Replaceable Battery (PowerCap)
Power-Fail Output
X1 GND VBAT
X2
Pin-for-Pin Compatible with Other Densities of
DS164XP Timekeeping RAM
PowerCap Module Board
(Uses DS9034PCX PowerCap)
ORDERING INFORMATION
VOLTAGE
PART
TEMP RANGE PIN-PACKAGE TOP MARK
RANGE (V)
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
DS1643-70+
DS1643-70
28 EDIP (0.740a) DS1643+70
28 EDIP (0.740a) DS1643-70
28 EDIP (0.740a) DS1643+100
28 EDIP (0.740a) DS1643-100
DS1643+100
DS1643-100
DS1643P-70+
DS1643P-70
DS1643P+100
DS1643P-100
34-PowerCap*
34-PowerCap*
34-PowerCap*
34-PowerCap*
DS1643P+70
DS1643P-70
DS1643P+100
DS1643P-100
*DS9034-PCX, DS9034I-PCX, DS9034-PCX+ required (must be ordered separately).
A “+” indicates a lead-free product. The top mark will include a “+” symbol on lead-free devices.
1 of 16
REV: 042705
DS1643/DS1643P
PIN DESCRIPTION
PIN
NAME
FUNCTION
PDIP
PowerCap
1, 2, 3,
31–34
30
25
24
23
22
21
20
19
18
28
29
27
26
16
15
14
13
12
11
10
9
1
N.C.
No Connection
Address Inputs
2
A12
A7
3
4
A6
5
A5
6
A4
7
A3
8
A2
9
A1
10
21
23
24
25
11
12
13
15
16
17
18
19
20
22
26
27
28
A0
A10
A11
A9
A8
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CE
Data Input/Output
8
Active-Low Chip-Enable Input
Active-Low Output-Enable Input
Chip-Enable 2 Input (Active High)
Active-Low Write-Enable Input
Power-Supply Input
7
OE
—
6
CE2
WE
VCC
5
Active-Low Power-Fail Output. This open-drain
—
4
PFO
pin requires a pullup resistor for proper operation.
14
—
17
GND
X1, X2,
VBAT
Ground
Crystal Connection, Battery Connection
2 of 16
DS1643/DS1643P
DESCRIPTION
The DS1643 is an 8K x 8 nonvolatile static RAM with a full function Real Time Clock (RTC) that are
both accessible in a byte-wide format. The nonvolatile timekeeping RAM is functionally equivalent to
any JEDEC standard 8K x 8 SRAM. The device can also be easily substituted in ROM, EPROM and
EEPROM sockets providing read/write nonvolatility and the addition of the real time clock function. The
real time clock information resides in the eight uppermost RAM locations. The RTC registers contain
year, month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for the day
of the month and leap year are made automatically. The RTC clock registers are double-buffered to
avoid access of incorrect data that can occur during clock update cycles. The double-buffered system also
prevents time loss as the timekeeping countdown continues unabated by access to time register data. The
DS1643 also contains its own power-fail circuitry, which deselects the device when the VCC supply is in
an out of tolerance condition. This feature prevents loss of data from unpredictable system operation
brought on by low VCC as errant access and update cycles are avoided.
PACKAGES
The DS1643 is available in two packages: 28-pin DIP module and 34-pin PowerCap® module. The 28-
pin DIP style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-
pin PowerCap Module Board is designed with contacts for connection to a separate PowerCap
(DS9034PCX) that contains the crystal and battery. This design allows the PowerCap to be mounted on
top of the DS1643P after the completion of the surface mount process. Mounting the PowerCap after the
surface mount process prevents damage to the crystal and battery due to high temperatures required for
solder reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and
PowerCap are ordered separately and shipped in separate containers. The part number for the PowerCap
is DS9034PCX.
CLOCK OPERATIONS—READING THE CLOCK
While the double-buffered register structure reduces the chance of reading incorrect data, internal updates
to the DS1643 clock registers should be halted before clock data is read to prevent reading of data in
transition. However, halting the internal clock register updating process does not affect clock accuracy.
Updating is halted when a one is written into the read bit, the seventh most significant bit in the control
register. As long as a 1 remains in that position, updating is halted. After a halt is issued, the registers
reflect the count, that is day, date, and time that was current at the moment the halt command was issued.
However, the internal clock registers of the double-buffered system continue to update so that the clock
accuracy is not affected by the access of data. All of the DS1643 registers are updated simultaneously
after the clock status is reset. Updating is within a second after the read bit is written to 0.
PowerCap is a registered trademark of Dallas Semiconductor.
3 of 16
DS1643/DS1643P
Figure 1. Block Diagram
DS1643P
Table 1. Truth Table
VCC
CE2
X
VIL
VIH
VIH
VIH
MODE
Deselect
Deselect
Write
DQ
POWER
Standby
Standby
Active
CE
VIH
X
OE
X
WE
X
High Z
High Z
Data In
Data Out
High-Z
X
X
VIL
VIL
VIL
X
VIL
VIH
VIL
VIH
VIH
5V M10%
Read
Active
Read
Active
<4.5V >
VBAT
<VBAT
X
X
X
X
X
X
X
X
Deselect
Deselect
High-Z
High-Z
CMOS Standby
Data Retention Mode
SETTING THE CLOCK
The 8-bit of the control register is the write bit. Setting the write bit to a 1, like the read bit, halts updates
to the DS1643 registers. The user can then load them with the correct day, date and time data in 24 hour
BCD format. Resetting the write bit to a 0 then transfers those values to the actual clock counters and
allows normal operation to resume.
STOPPING AND STARTING THE CLOCK OSCILLATOR
The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off
to minimize current drain from the battery. The OSC bit is the MSB for the seconds registers. Setting it to
a 1 stops the oscillator.
FREQUENCY TEST BIT
Bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to logic 1 and the
oscillator is running, the LSB of the seconds register will toggle at 512Hz. When the seconds register is
being read, the DQ0 line will toggle at the 512Hz frequency as long as conditions for access remain valid
(i.e., CE low, OE low, CE2 high, and address for seconds register remain valid and stable).
4 of 16
DS1643/DS1643P
CLOCK ACCURACY (DIP MODULE)
The DS1643 is guaranteed to keep time accuracy to within M1 minute per month at 25LC.
CLOCK ACCURACY (POWERCAP MODULE)
The DS1643P and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module is guaranteed to keep time accuracy to within M1.53 minutes per month (35ppm) at 25LC.
Table 2. Register Map—Bank1
DATA
ADDRESS
FUNCTION RANGE
B7
B6
B5
B4
B3
B2
B1
B0
1FFF
1FFE
—
—
—
—
—
—
—
—
Year
00-99
01-12
X
X
X
—
—
—
—
—
Month
1FFD
1FFC
1FFB
1FFA
1FF9
1FF8
X
X
X
X
X
Ft
X
—
—
X
—
X
—
—
—
—
—
X
—
—
—
—
—
X
—
—
—
—
—
X
Date
Day
01-31
01-07
00-23
00-59
00-59
A
X
—
—
—
X
—
—
—
X
—
—
—
X
Hour
—
—
R
Minutes
Seconds
Control
OSC
W
R = READ BIT
X = UNUSED
FT = FREQUENCY TEST
OSC = STOP BIT
W = WRITE BIT
Note: All indicated “X” bits are not used but must be set to “0” for proper clock operation.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1643 is in the read mode whenever WE (write enable) is high and CE (chip enable) is low. The
device architecture allows ripple-through access to any of the address locations in the NV SRAM. Valid
data will be available at the DQ pins within tAA after the last address input is stable, providing that the CE
and OE access times and states are satisfied. If CE or OE access times are not met, valid data will be
available at the latter of chip enable access (tCEA) or at output enable access time (tOEA). The state of the
data input/output pins (DQ) is controlled by CE and OE . If the outputs are activated before tAA , the data
lines are driven to an intermediate state until tAA. If the address inputs are changed while CE and OE
remain valid, output data will remain valid for output data hold time (tOH) but will then go indeterminate
until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1643 is in the write mode whenever WE and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE or CE . The addresses must be held valid throughout
the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of another read or
write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH afterward. In a
typical application, the OE signal will be high during a write cycle. However, OE can be active provided
that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low
the data bus can become active with read data defined by the address inputs. A low transition on WE will
then disable the outputs tWEZ after WE goes active.
5 of 16
DS1643/DS1643P
DATA RETENTION MODE
When VCC is within nominal limits (VCC > 4.5V) the DS1643 can be accessed as described above with
read or write cycles. However, when VCC is below the power-fail point VPF (point at which write
protection occurs) the internal clock registers and RAM are blocked from access. This is accomplished
internally by inhibiting access via the CE signal. At this time the power-on reset output signal (RST ) will
be driven active low and will remain active until VCC returns to nominal levels. When VCC falls below the
level of the internal battery supply, power input is switched from the VCC pin to the internal battery and
clock activity, RAM, and clock data are maintained from the battery until VCC is returned to nominal
level. The RST signal is an open drain output and requires a pull up. Except for the RST , all control, data,
and address signals must be powered down when VCC is powered down.
BATTERY LONGEVITY
The DS1643 has a lithium power source that is designed to provide energy for clock activity, and clock
and RAM data retention when the VCC supply is not present. The capability of this internal power supply
is sufficient to power the DS1643 continuously for the life of the equipment in which it is installed. For
specification purposes, the life expectancy is 10 years at 25LC with the internal clock oscillator running in
the absence of VCC power. Each DS1643 is shipped from Dallas Semiconductor with its lithium energy
source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than
VPF, the lithium energy source is enabled for battery backup operation. Actual life expectancy of the
Ds1643 will be much longer than 10 years since no lithium battery energy is consumed when VCC is
present.
6 of 16
DS1643/DS1643P
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground……………………………………………..-0.3V to +7.0V
Operating Temperature Range………………………………………………0°C to +70°C, Noncondensing
Storage Temperature Range………………………………………………-40°C to +85°C, Noncondensing
Soldering Temperature………………………………See IPC/JEDEC J-STD-020A Specification (Note 7)
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect
reliability.
RECOMMENDED DC OPERATING CONDITIONS
(TA = 0LC to +70LC)
PARAMETER
SYMBOL MIN
TYP
5.0
MAX
UNITS NOTES
Supply Voltage
Logic 1 Voltage All Inputs
Logic 0 Voltage All Inputs
VCC
VIH
VIL
4.5
2.2
-0.3
5.5
V
VCC + 0.3
+0.8
V
V
DC ELECTRICAL CHARACTERISTICS
(VCC = 5.0V M10%, TA = 0LC toꢀꢁ70LC.)
PARAMETER
SYMBOL MIN
TYP
MAX
UNITS NOTES
Active Supply Current
ICC
15
50
mA
2, 3
TTL Standby Current
(CE = VIH, CE2 = VIL)
CMOS Standby Current
(CE = VCC - 0.2V, CE2 = GND + 0.2V)
Input Leakage Current (Any Input)
Output Leakage Current (Any Output)
Output Logic 1 Voltage
(IOUT = -1.0mA)
ICC1
ICC2
1
1
3
3
mA
2, 3
mA
2, 3
1
IIL
IOL
-1
-1
+1
+1
ꢀA
ꢀA
VOH
2.4
Output Logic 0 Voltage
(IOUT = +2.1mA)
Write Protection Voltage
VOL
VPF
0.4
1
1
4.25
4.37
4.50
V
7 of 16
DS1643/DS1643P
AC CHARACTERISTICS—READ CYCLE
(VCC = 5.0V M10%, TA = 0LC to +70LC.)
70ns
100ns
PARAMETER
SYMBOL
ACCESS
ACCESS
UNITS NOTES
MIN MAX MIN MAX
Read Cycle Time
Address Access Time
tRC
tAA
70
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
4
4
4
4
4
4
4
4
4
70
100
tCEL
tCEA
tCE2A
tCEZ
tOEL
tOEA
tOEZ
tOH
5
5
CE and CE2 to DQ Low-Z
CE Access Time
70
80
25
100
105
35
CE2 Access Time
CE and CE2 Data Off Time
OE to DQ Low-Z
OE Access Time
OE Data Off Time
Output Hold from Address
5
5
5
5
35
25
55
35
READ CYCLE TIMING DIAGRAM
8 of 16
DS1643/DS1643P
AC CHARACTERISTICS—WRITE CYCLE
(VCC = 5.0V M10%, TA = 0LC to +70LC.)
70ns
ACCESS
100ns
PARAMETER
SYMBOL
ACCESS
UNITS NOTES
MIN MAX MIN MAX
Write Cycle Time
Address Setup Time
tWC
tAS
70
0
100
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
4
4
4
4
4
4
4
4
4
tWEW
tCEW
tCE2W
tDS
tDH
tAH
50
60
65
30
0
70
75
85
40
0
WE Pulse Width
CE Pulse Width
CE2 Pulse Width
Data Setup Time
Data Hold Time
Address Hold Time
5
5
tWEZ
tWR
25
35
WE Data Off Time
Write Recovery Time
5
5
9 of 16
DS1643/DS1643P
WRITE CYCLE TIMING DIAGRAM—WE CONTROLLED
WRITE CYCLE TIMING DIAGRAM—CE, CE2 CONTROLLED
10 of 16
DS1643/DS1643P
POWER-UP/DOWN AC CHARACTERISTICS
(VCC = 5.0V M10%, TA = 0LC to +70LC.)
PARAMETER
SYMBOL MIN
TYP
MAX
UNITS NOTES
CE or WE at VIH, CE2 at VIL, Before
tPD
0
ꢀs
Power-down
VCC Fall Time: VPF(MAX) to VPF(MIN)
VCC Fall Time: VPF(MIN) to VBAT
VCC Rise Time: VPF(MIN) to VPF(MAX)
Power-Up Recover Time
Expected Data Retention Time
(Oscillator On)
tF
tFB
tR
300
10
0
ꢀs
ꢀs
ꢀs
ms
tREC
35
tDR
10
years
5, 6
POWER-UP/POWER-DOWN TIMING
CAPACITANCE
(TA = +25LC)
PARAMETER
SYMBOL MIN
TYP
MAX
7
10
UNITS NOTES
Capacitance on All Pins
Capacitance on All Output Pins
CIN
CO
pF
pF
11 of 16
DS1643/DS1643P
AC TEST CONDITIONS
Output Load: 100pF + 1TTL Gate
Input Pulse Levels: 0 to 3.0V
Timing Measurement Reference Levels:
Input: 1.5V
Output: 1.5V
Input Pulse Rise and Fall Times: 5ns
NOTES:
1) Voltages are referenced to ground.
2) Typical values are at +25LC and nominal supplies.
3) Outputs are open.
4) The CE2 control signal functions exactly the same as the CE signal except that the logic levels for
active and inactive levels are opposite.
5) Data retention time is at 25LC.
6) Each DS1643 has a built-in switch that disconnects the lithium source until VCC is first applied by the
user. The expected tDR is defined for DIP modules as a cumulative time in the absence of VCC starting
from the time power is first applied by the user.
7) Real-Time Clock Modules (DIP) can be successfully processed through conventional wave-soldering
techniques as long as temperatures as long as temperature exposure to the lithium energy source
contained within does not exceed +85LC. Post-solder cleaning with water washing techniques is
acceptable, provided that ultrasonic vibration is not used.
In addition, for the PowerCap:
a. Dallas Semiconductor recommends that PowerCap Module bases experience one pass through
solder reflow oriented with the label side up (“live-bug”).
b. Hand soldering and touch-up: Do not touch or apply the soldering iron to leads for more than
3 seconds. To solder, apply flux to the pad, heat the lead frame pad and apply solder. To
remove the part, apply flux, heat the lead frame pad until the solder reflow and use a solder
wick to remove solder.
12 of 16
DS1643/DS1643P
PACKAGE INFORMATION
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information, go to www.maxim-ic.com/DallasPackInfo.)
DS1643 28-PIN PACKAGE
PKG
DIM
28-PIN
MIN
MAX
A IN.
MM
1.470
37.34
0.675
17.75
0.315
8.51
1.490
37.85
0.740
18.80
0.335
9.02
B IN.
MM
C IN.
MM
D IN.
MM
0.075
1.91
0.105
2.67
E IN.
MM
0.015
0.38
0.030
0.76
F IN.
MM
0.140
3.56
0.180
4.57
G IN.
MM
0.090
2.29
0.110
2.79
H IN.
MM
0.590
14.99
0.010
0.25
0.015
0.43
0.630
16.00
0.018
0.45
0.025
0.58
J IN.
MM
K IN.
MM
13 of 16
DS1643/DS1643P
DS1643P
PKG
DIM
A
INCHES
NOM
MIN
MAX
0.920
0.980
-
0.925
0.985
-
0.930
0.990
0.080
0.058
0.052
0.025
0.030
B
C
D
0.052
0.048
0.015
0.025
0.055
0.050
0.020
0.027
E
F
G
NOTE: DALLAS SEMICONDUCTOR RECOMMENDS THAT
POWERCAP MODULE BASES EXPERIENCE ONE PASS
THROUGH SOLDER REFLOW ORIENTED WITH THE LABEL
SIDE UP (“LIVE-BUG”).
HAND SOLDERING AND TOUCH-UP: DO NOT TOUCH OR
APPLY THE SOLDERING IRON TO LEADS FOR MORE THAN
3 SECONDS.
TO SOLDER, APPLY FLUX TO THE PAD, HEAT THE LEAD
FRAME PAD AND APPLY SOLDER. TO REMOVE THE PART,
APPLY FLUX, HEAT THE LEAD FRAME PAD UNTIL THE
SOLDER REFLOWS AND USE A SOLDER WICK TO
REMOVE SOLDER.
14 of 16
DS1643/DS1643P
DS1643P WITH DS9034PCX ATTACHED
PKG
DIM
A
INCHES
NOM
MIN
MAX
0.920
0.955
0.240
0.052
0.048
0.015
0.020
0.925
0.960
0.245
0.055
0.050
0.020
0.025
0.930
0.965
0.250
0.058
0.052
0.025
0.030
B
C
D
E
F
G
15 of 16
DS1643/DS1643P
RECOMMENDED POWERCAP MODULE LAND PATTERN
PKG
DIM
A
INCHES
MIN
NOM
MAX
-
-
-
-
-
1.050
0.826
0.050
0.030
0.112
-
-
-
-
-
B
C
D
E
16 of 16
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.
No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2005 Maxim Integrated Products S Printed USA
The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation.
EN GL ISH • ? ? ? ? • ? ? ? • ? ? ?
W HA T ' S N EW PR ODUC TS S OLU TI ONS D E SI G N AP P NOT ES SUPP ORT
BU Y C OM PA N Y M EM B ER S
DS 1 64 3
Pa r t Nu mb e r T ab l e
N o te s:
1 . S ee t he DS1 643 Quic kVie w D at a Sh ee t fo r fu r t h er i nf o rm a t i on on th i s p ro duc t f a mil y o r do wn lo a d t he
DS 16 43 fu ll d ata s heet (P DF , 3 20 k B) .
2. O th er o p ti on s an d l inks f or p urch asi ng p arts a re l is te d at : h t tp : / /w w w. m a xi m- ic. com /s al es .
3 . Did n' t F ind W ha t Y ou N e ed ? Ask ou r a pplic a tion s e ngine e r s. Expe r t a ssi sta nc e i n fi ndi ng p arts, usu al l y w i th in
o n e b u s i n e s s d ay .
4 . Pa r t n u mb e r suf f ix e s: T o r T &R = ta p e a n d r e e l; + = Ro HS/le ad - fr e e ; # = RoH S/ lea d - e xe m p t. Mo r e : S e e fu l l
da ta she e t o r P a r t Na m i n g C o n v en t i o n s .
5 . * So m e p ac ka ge s h a ve v ar i at i o n s , li s t e d o n t h e dr aw in g. " P kgC od e /Va ri a tion " t ells which va ri ation the
p r od u c t us e s .
P art Num ber
D S 1 6 4 3 - 8 5 +
F re e
Sa mp le
B uy
D i re c t
T em p
R oHS/L ead- Fr ee?
Ma t e ri a l s A n a ly s is
P a c ka g e : TY PE P INS S IZE
D R A WI N G C O D E / V A R *
MOD; 28 pi n;60 0
Dwg : 5 6 - G 0 0 0 2 - 0 0 1 A (P D F )
Use pkg code/ vari atio n: MDF 28+2 *
0 C t o + 7 0 C Ro H S / Le a d -F re e: Yes
Ma t e ri a l s A n a ly s is
D S 1 6 4 3 - 1 0 0
MOD; 28 pi n;60 0
Dwg : 5 6 - G 0 0 0 2 - 0 0 1 A (P D F )
Us e pkg cod e/ var iat io n: M DF 28 -2*
0 C t o + 7 0 C Ro H S / Le a d -F re e: N o
Ma t e ri a l s A n a ly s is
D S 1 6 4 3 - 1 0 0 +
MOD; 28 pi n;60 0
Dwg : 5 6 - G 0 0 0 2 - 0 0 1 A (P D F )
Use pkg code/ vari atio n: MDF 28+2 *
0 C t o + 7 0 C Ro H S / Le a d -F re e: Yes
Ma t e ri a l s A n a ly s is
Did n' t F ind W ha t You N e ed ?
CO NT ACT U S: SE ND US AN EMAI L
Co p y rig h t 2 00 7 b y M a x im I n te g r a te d Pr o d u c ts , D a lla s S em i co n d u c to r • Le ga l N ot i ce s • P ri va c y P o l ic y
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