DS1643-150 [DALLAS]
Nonvolatile Timekeeping RAM; 非易失时钟RAM
| 型号： | DS1643-150 |
| 厂家： | 
DALLAS SEMICONDUCTOR |
| 描述： | Nonvolatile Timekeeping RAM |
| 文件： | 总11页 (文件大小：83K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS1643
DS1643
Nonvolatile Timekeeping RAM
FEATURES
PIN ASSIGNMENT
• Form, fit, and function compatible with the MK48T08
Timekeeping RAM
NC
1
28
VCC
A12
A7
A6
A5
A4
A3
2
3
4
5
6
7
27
26
25
24
23
22
WE
• Integrated NV SRAM, real time clock, crystal, power–
CE2
fail control circuit and lithium energy source
A8
• Standard JEDEC bytewide 8K x 8 static RAM pinout
A9
• Clock registers are accessed identical to the static
RAM. These registers are resident in the eight top
RAM locations.
A11
OE
A2
A1
8
9
21
20
A10
CE
• Totally nonvolatile with over 10 years of operation in
the absence of power
A0
DQ0
DQ1
DQ2
GND
10
11
12
13
14
19
18
17
16
15
DQ7
DQ6
DQ5
DQ4
DQ3
• Access times of 120 ns and 150 ns
• Quartz accuracy ±1 minute a month @ 25°C, factory
calibrated
• BCD coded year, month, date, day, hours, minutes,
and seconds with leap year compensation valid up to
2100
28–PIN ENCAPSULATED PACKAGE
(700 MIL EXTENDED)
• Power–fail write protection allows for ±10% V
power supply tolerance
CC
ORDERING INFORMATION
DS1643–XXX 28–pin DIP module
–120 120 ns access
–150 150 ns access
DESCRIPTION
The DS1643 is an 8K x 8 nonvolatile static RAM with a
full function real time clock which are both accessible in
abytewideformat. ThenonvolatiletimekeepingRAMis
pin and function equivalent to any JEDEC standard
8K x 8 SRAM. The device can also be easily substituted
inROM, EPROMandEEPROMsocketsprovidingread/
write nonvolatility and the addition of the real time clock
function. The real time clock information resides in the
eight uppermost RAM locations. The RTC registers
contain year, month, date, day, hours, minutes, and se-
conds data in 24 hour BCD format. Corrections for the
day of the month and leap year are made automatically.
The RTC clock registers are double buffered to avoid
access of incorrect data that can occur during clock up-
date cycles. The double buffered system also prevents
time loss as the timekeeping countdown continues un-
abated by access to time register data. The DS1643
also contains its own power–fail circuitry which dese-
lectsthedevicewhentheV supplyisinanoutoftoler-
CC
ance condition. This feature prevents loss of data from
unpredictable system operation brought on by low V
as errant access and update cycles are avoided.
CC
ECopyright 1995 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.
041697 1/11
DS1643
DS1643 clock registers should be halted before clock
data is read to prevent reading of data in transition.
However, halting the internal clock register updating
process does not affect clock accuracy. Updating is
haltedwhenaoneiswrittenintothereadbit,theseventh
most significant bit in the control register. As long as a
one remains in that position, updating is halted. After a
halt is issued, the registers reflect the count, that is day,
date, and time that was current at the moment the halt
command was issued. However, the internal clock reg-
isters of the double buffered system continue to update
so that the clock accuracy is not affected by the access
of data. All of the DS1643 registers are updated simul-
taneously after the clock status is reset. Updating is
within a second after the read bit is written to zero.
PIN DESCRIPTION
A0–A12
CE
OE
WE
NC
–
–
–
–
–
–
–
–
Address Input
Chip Enable
Output Enable
Write Enable
No Connection
+5 Volts
V
CC
GND
DQ0-DQ7
Ground
Data Input/Output
CLOCK OPERATIONS–READING THE
CLOCK
Whilethedoublebufferedregisterstructurereducesthe
chance of reading incorrect data, internal updates to the
DS1643 BLOCK DIAGRAM Figure 1
CLOCK
REGISTERS
OSCILLATOR AND
CLOCK COUNTDOWN
32.768 KHz
CHAIN
CE
WE
8K X 8 NV SRAM
OE
POWER GOOD
A0–A12
POWER MONITOR,
SWITCHING, AND
WRITE PROTECTION
+
V
BAT
DQ0–DQ7
V
CC
041697 2/11
DS1643
DS1643 TRUTH TABLE Table 1
V
CE
CE2
OE
X
WE
X
MODE
DESELECT
DESELECT
WRITE
DQ
POWER
CC
V
IH
X
HIGH Z
HIGH Z
DATA IN
DATA OUT
HIGH Z
HIGH Z
STANDBY
STANDBY
ACTIVE
X
V
V
X
X
IL
V
IL
V
IL
V
IL
X
V
IL
5 VOLTS ± 10%
IH
IH
IH
V
V
V
IL
V
READ
ACTIVE
IH
IH
V
IH
V
READ
ACTIVE
<4.5 VOLTS
X
X
X
X
DESELECT
CMOS STANDBY
>V
BAT
<V
BAT
X
X
X
X
DESELECT
HIGH Z
DATA RETENTION
MODE
running, the LSB of the seconds register will toggle at
512 Hz. When the seconds register is being read, the
DQ0 line will toggle at the 512 Hz frequency as long as
conditions for access remain valid (i.e., CE low, OE low,
CE2high,andaddressforsecondsregisterremainvalid
and stable).
SETTING THE CLOCK
The 8–bit of the control register is the write bit. Setting
the write bit to a one, like the read bit, halts updates to
theDS1643registers. Theusercanthenloadthemwith
the correct day, date and time data in 24 hour BCD for-
mat. Resetting the write bit to a zero then transfers
those values to the actual clock counters and allows
normal operation to resume.
CLOCK ACCURACY
The DS1643 is guaranteed to keep time accuracy to
within ±1 minute per month at 25°C. The clock is cali-
brated at the factory by Dallas Semiconductor using
special calibration nonvolatile tuning elements. The
DS1643doesnotrequireadditionalcalibrationandtem-
perature deviations will have a negligible effect in most
applications. For this reason, methods of field clock cal-
ibration are not available and not necessary. Attempts
to calibrate the clock that may be used with similar de-
vice types (MK48T08 family) will not have any effect
even though the DS1643 appears to accept calibration
data.
STOPPING AND STARTING THE CLOCK
OSCILLATOR
The clock oscillator may be stopped at any time. To in-
crease the shelf life, the oscillator can be turned off to
minimize current drain from the battery. The OSC bit is
theMSBforthesecondsregisters. Settingittoa1stops
the oscillator.
FREQUENCY TEST BIT
Bit 6 of the day byte is the frequency test bit. When the
frequency test bit is set to logic “1” and the oscillator is
041697 3/11
DS1643
DS1643 REGISTER MAP – BANK1 Table 2
DATA
ADDRESS
FUNCTION
YEAR
B
B
B
B
B
B
B
B
0
7
6
5
4
3
2
1
1FFF
1FFE
1FFD
1FFC
1FFB
1FFA
1FF9
1FF8
–
–
–
–
–
–
–
–
00–99
01–12
01–31
01–07
00–23
00–59
X
X
X
X
X
–
X
–
–
–
X
–
–
X
–
–
–
X
–
–
X
–
–
–
X
–
–
–
–
–
–
X
–
–
–
–
–
–
X
–
–
–
–
–
–
X
MONTH
DATE
X
FT
X
DAY
X
HOUR
MINUTES
X
–
OSC
W
–
SECONDS 00–59
CONTROL
R
A
OSC = STOP BIT
= WRITE BIT
R
X
=
=
READ BIT
UNUSED
FT = FREQUENCY TEST
W
NOTE:
All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1643 is in the read mode whenever WE (write
enable) is high and CE (chip enable) is low. The device
architecture allows ripple-through access to any of the
address locations in the NV SRAM. Valid data will be
WRITING DATA TO RAM OR CLOCK
The DS1643 is in the write mode whenever WE and CE
areintheiractivestate. Thestartofawriteisreferenced
to the latter occurring transition of WE or CE. The ad-
dresses must be held valid throughout the cycle. CE or
available at the DQ pins within t after the last address
WE must return inactive for a minimum of t
prior to
WR
AA
input is stable, providing that the CE and OE access
times and states are satisfied. If CE or OE access times
are not met, valid data will be available at the latter of
the initiation of another read or write cycle. Data in must
be valid t prior to the end of write and remain valid for
DS
t
afterward. In a typical application, the OE signal will
DH
chip enable access (t
) or at output enable access
behighduringawritecycle. However, OEcanbeactive
providedthatcareistakenwiththedatabustoavoidbus
contention. If OE is low prior to WE transitioning low the
data bus can become active with read data defined by
the address inputs. A low transition on WE will then dis-
CEA
time (t
). The state of the data input/output pins (DQ)
OEA
is controlled by CE and OE. If the outputs are activated
before t , the data lines are driven to an intermediate
AA
state until t . If the address inputs are changed while
AA
CEandOEremainvalid, outputdatawillremainvalidfor
able the outputs t
after WE goes active.
WEZ
outputdataholdtime(t )butwillthengoindeterminate
OH
until the next address access.
041697 4/11
DS1643
clock and RAM data retention when the V supply is
DATA RETENTION MODE
CC
When V is within nominal limits (V > 4.5 volts) the
DS1643 can be accessed as described above by read
not present. The capability of this internal power supply
is sufficient to power the DS1643 continuously for the
life of the equipment in which it is installed. For specifi-
cation purposes, the life expectancy is 10 years at 25°C
with the internal clock oscillator running in the absence
CC
CC
or write cycles. However, when V is below the pow-
CC
er–fail point V (point at which write protection occurs)
PF
the internal clock registers and RAM is blocked from ac-
cess. This is accomplished internally by inhibiting ac-
of V
power. The DS1643 is shipped from Dallas
CC
cess via the CE and CE2 signals. When V falls below
the level of the internal battery supply, power input is
Semiconductor with the clock oscillator turned off, so
the expected life should be considered to start from the
time the clock oscillator is first turned on. Actual life ex-
pectancy of the DS1643 will be much longer than 10
years since no internal lithium battery energy is con-
CC
switched from the V
pin to the internal battery and
CC
clock activity, RAM, and clock data are maintained from
the battery until V is returned to nominal level.
CC
sumed when V is present. In fact, in most applica-
CC
tions, the life expectancy of the DS1643 will be approxi-
mately equal to the shelf life (expected useful life of the
lithium battery with no load attached) of the lithium bat-
tery which may prove to be as long as 20 years.
INTERNAL BATTERY LONGEVITY
The DS1643 has a self contained lithium power source
that is designed to provide energy for clock activity, and
041697 5/11
DS1643
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
–0.3V to +7.0V
0°C to 70°C
Storage Temperature
–20°C to +70°C
Soldering Temperature
260°C for 10 seconds (See Note 7)
* This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(0°C to 70°C)
PARAMETER
SYMBOL
MIN
4.5
TYP
MAX
UNITS
NOTES
Supply Voltage
V
CC
5.0
5.5
V
V
V
1
Logic 1 Voltage All Inputs
Logic 0 Voltage All Inputs
V
IH
2.2
V
+0.3
CC
V
IL
–0.3
0.8
DC ELECTRICAL CHARACTERISTICS
(0°C ≤ tA ≤ 70°C; VCC = 5.0V ± 10%)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Average V Power Supply
Current
I
I
I
65
mA
2, 3
CC
CC1
CC2
CC3
TTL Standby Current (CE = V
,
3
2
6
mA
mA
2, 3
2, 3
IH
CE2 = V )
IL
CMOS Standby Current
4.0
(CE=V –0.2V, CE2=GND+0.2V)
CC
µA
µA
V
Input Leakage Current (any input)
Output Leakage Current
I
–1
–1
+1
+1
IL
I
OL
Output Logic 1 Voltage
V
OH
2.4
(I
OUT
= –1.0 mA)
Output Logic 0 Voltage
(I = +2.1 mA)
V
OL
V
TP
0.4
4.5
V
V
OUT
Write Protection Voltage
4.0
4.25
041697 6/11
DS1643
AC ELECTRICAL CHARACTERISTICS
(0°C to 70°C; VCC = 5.0V ± 10%)
DS1643–120
DS1643–150
MIN
MAX
MIN
MAX
PARAMETER
SYMBOL
UNITS
ns
NOTES
Read Cycle Time
t
120
150
RC
Address Access Time
t
120
120
40
150
150
50
ns
AA
CE and CE2 Access Time
CE and CE2 Data Off Time
Output Enable Access Time
Output Enable Data Off Time
Output Enable to DQ Low–Z
CE and CE2 to DQ Low–Z
Output Hold from Address
Write Cycle Time
t
ns
CEA
t
ns
CEZ
OEA
t
100
35
120
45
ns
t
ns
OEZ
t
5
5
5
5
ns
OEL
t
ns
CEL
t
5
5
ns
OH
t
120
0
150
0
ns
WC
Address Setup Time
t
AS
ns
CE and CE2 Pulse Width
Address Hold from End of Write
t
100
120
ns
CEW
t
t
5
30
5
30
ns
ns
5
6
AH1
AH2
Write Pulse Width
WE Data Off Time
WE or CE Inactive Time
Data Setup Time
t
120
150
ns
ns
ns
ns
WEW
t
40
50
WEZ
t
10
85
10
WR
t
110
DS
Data Hold Time High
t
t
0
15
0
15
ns
ns
5
6
DH1
DH2
AC TEST CONDITIONS
Input Levels:
Transition Times:
0V to 3V
5 ns
CAPACITANCE
PARAMETER
(tA = 25°C)
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Capacitance on all pins
(except DQ)
C
7
pF
I
Capacitance on DQ pins
C
10
pF
DQ
041697 7/11
DS1643
AC ELECTRICAL CHARACTERISTICS (POWER–UP/DOWN TIMING)
(0°C to 70°C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
µs
CE2, CE or WE at V before
t
0
IH
PD
Power Down
V
V
(Max) to V (Min)
Fall Time
t
300
10
1
µs
µs
µs
µs
PF
CC
PF
F
V
V
(Min) to V
Fall Time
t
PF
CC
SO
FB
RB
V
SO
V
CC
to V (Min)
t
PF
Rise Time
V
V
(Min) to V (Max)
t
R
0
PF
CC
PF
Rise Time
Power–Up
t
15
10
25
35
ms
REC
Expected Data Retention Time
(Oscillator On)
t
years
4
DR
DS1643 READ CYCLE TIMING
READ
READ
WRITE
t
t
t
WC
RC
RC
A0–A12
t
t
AH
AA
t
AS
t
CEA
CE
OE
t
CEL
t
OEA
t
WR
t
WEW
WE
t
OEL
t
t
OEZ
OH
DQ0–DQ7
VALID OUT
VALID OUT
VALID IN
041697 8/11
DS1643
DS1643 WRITE CYCLE TIMING
WRITE
WRITE
READ
t
t
t
RC
WC
WC
A0–A12
t
t
AH2
AS
t
AA
t
WR
t
AH1
t
CEW
CE
t
OEA
OE
t
WR
t
WEW
WE
t
DH1
t
WEZ
t
t
DS
t
DH2
CEZ
t
DS
VALID
OUT
DQ0–
DQ7
VALID IN
VALID IN
VALID OUT
POWER–DOWN/POWER–UP TIMING
V
CC
V
(MAX)
PF
V
(MIN)
V
PF
PF
t
t
R
F
V
V
SO
SO
t
t
RB
FB
t
t
REC
PD
CE
I
BATT
DATA RETENTION
t
DR
041697 9/11
DS1643
NOTES:
1. All voltages are referenced to ground.
2. Typical values are at 25°C and nominal supplies.
3. Outputs are open.
4. Data retention time is at 25°C and is calculated from the date code on the device package. The date code XXYY
is the year followed by the week of the year in which the device was manufactured. For example, 9225, would
mean the 25th week of 1992.
5. t
6. t
, t
are measured from WE going high.
are measured from CE going high.
AH1 DH1
, t
AH2 DH2
7. Real–Time Clock Modules can be successfully processed through conventional wave–soldering techniques as
long as temperature exposure to the lithium energy source contained within does not exceed +85°C. Post solder
cleaning with water washing techniques is acceptable, provided that ultrasonic vibration is not used.
OUTPUT LOAD
+5 VOLTS
1.8KΩ
D.U.T.
1KΩ
100 pF
041697 10/11
DS1643
DS1643 28–PIN PACKAGE
PKG
DIM
28–PIN
MIN
MAX
A
IN.
MM
1.470
37.34
1.490
37.85
B
C
D
E
F
IN.
MM
0.675
17.75
0.740
18.80
1
IN.
MM
0.335
8.51
0.355
9.02
A
IN.
MM
0.075
1.91
0.105
2.67
IN.
MM
0.015
0.38
0.030
0.76
C
IN.
MM
0.140
3.56
0.180
4.57
G
H
J
IN.
MM
0.090
2.29
0.110
2.79
F
D
K
G
IN.
MM
0.590
14.99
0.630
16.00
IN.
MM
0.010
0.25
0.018
0.45
K
IN.
MM
0.015
0.43
0.025
0.58
J
E
H
B
041697 11/11
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