LTM4651IY#PBF_技术文档

LTM4651

EN55022B Compliant 58V, 24W

Inverting-Output DC/DC μModule Regulator

FEATURES

DESCRIPTION

The LTM^®4651 is an ultralow noise, 58V, 24W DC/DC

n

Complete Low EMI Switch Mode Power Supply

EN55022 Class B Compliant

μModule^®inverting topology regulator. It regulates a nega-

n

–

Wide Input Voltage Range: 3.6V to 58V

tive output voltage (V

) from a positive input supply

OUT

Up to 4A Output Current

voltage(V ),andisdesignedtomeettheradiatedemissions

IN

n

24W Output from 12V to –24V , P

A

= 5W,

requirements of EN55022. Conducted emission require-

ments can be met by adding standard filter components.

Included in the package are the switching controller, power

MOSFETs, inductor, filters and support components.

IN

OUT LOSS

T = 60°C, t

= 60°C, 200LFM

RISE

–

n

Output Voltage Range: –26.5V ≤ V

≤ –0.5V

OUT

–

n

Safe Operating Area: V + |V

| ≤ 58V

IN

OUT

1.6ꢀ7 Total DC Output Voltage Error Over Line,

Load and Temperature (–40°C to 125°C)

–

The LTM4651 can regulate V

to a value between

OUT

–0.5V and –26.5V, provided that its input and output

n

Parallel and Current Share with Multiple LTM4651s

Constant-Frequency Current Mode Control

Frequency Synchronization Range: 250kHz to 3MHz

Power Good Indicator and Programmable Soft-Start

Overcurrent/Overvoltage/Overtemperature Protection

15mm × 9mm × 5.01mm BGA Package

voltages adhere to the safe operating area criteria of the

–

LTM4651: V + |V

| ≤ 58V. A switching frequency

IN

OUT

range of 250kHz to 3MHz is supported (400kHz default)

and the module can synchronize to an external clock.

Despite being an inverting topology regulator, no level shift

circuitry is needed to interface to the LTM4651’s RUN,

PGOOD or CLKIN pins; those pins are referenced to GND.

APPLICATIONS

TheLTM4651isofferedina15mm×9mm×5.01mmBGA

package with SnPb or RoHS compliant terminal finish.

L, LT, LTC, LTM, Linear Technology , the Linear logo, LTpowerCAD and μModule are registered

trademarks of Analog Devices, Inc. All other trademarks are the property of their respective

owners. Protected by U.S. Patents, including 5481178, 5705919, 5847554, 6580258.

n

Avionics, Industrial Control and Test Equipment

n

Video, Imaging and Instrumentation

n

48V Telecom and Network Power Supplies

RF Systems

n

TYPICAL APPLICATION

–24V, 2.25A* Ultralow Noise** DC/DC μModule Regulator

Output Current Capability*

4.0

V

IN

V

PGND

IN

3.6V

3.5

4.7μF

TO 34V

SV

GND

IN

SNS

10µF

×2

3.0

LOAD

V

D

–

2.5

RUN

INTV

SV

V

OUT

4.7μF

–

–24V

UP TO 2.25A

,

–

OUT

CC

2.0

1.5

1.0

0.5

0

V

= –0.5V

= –3.3V

= –5V

OUT

LTM4651

–

VINREG

COMPa

COMPb

= –8V

= –12V

= –15V

= –20V

= –24V

PINS NOT USED IN

THIS CIRCUIT:

f

SET

CLKIN, PGOOD,

PGDFB, SW, EXTV

GND

ISETa ISETb

0

10

20

30

40

50

60

CC

4651 TA01a

+

–

INPUT VOLTAGE (V)

TEMP , TEMP , NC

90.9k

4651 TA01b

481k

*Current limit frequency-foldback activates at load currents higher than indicated

curves. Continuous output current capability subject to details of application

implementation. Switching frequency set per Table 1. See Notes 2 and 3.

**See Figures 5 – 8 for DC2328A Radiated Emission Performance against EN55022B limits.

4651f

1

For more information www.linear.com/LTM4651

LTM4651

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

(Note 1) (All Voltages Relative to V_OUT^–Unless Otherwise Indicated)

TOP VIEW

Terminal Voltages

1

2

3

4

5

6

7

V

V , V , SV , SW, PGND, GND , ISETa ..–0.3V to 60V

IN

D

IN

SNS

A

B

GND, EXTV ........................................ –0.3V to 28V

CC

V

CLKIN NC

V

D

–

RUN.................................GND – 0.3V to V

+ 60V

OUT

–

V

OUT

SV

IN

INTV , PGDFB, VINREG, COMPa .......... –0.3V to 4V

NC

OUT

CC

C

D

E

f

..................................................–0.3V to INTV

SET

CC

VINREG GND

PGOOD PGDFB

COMPb COMPa

COMPb ................................................... –0.3V to 5V

ISETb .................................................... –0.3V to 28V

CLKIN, PGOOD (Relative to GND) ........... –0.3V to 6V

Terminal Currents

–

f

NC

SV

SET

OUT

ISETb ISETa EXTV

RUN

CC

F

INTV Peak Output Current (Note 8)................30mA

INTV

CC

G

+

TEMP ..................................................–1mA to 10mA

–

GND

SV

SNS

OUT

SW

V

–

TEMP .................................................–10mA to 1mA

H

–

+

–

+

TEMP

Temperatures

TEMP

J

–

Internal Operating Temperature

OUT

K

Range (Notes 2, 7).......................... –40°C to 125°C

Storage Temperature Range .............. –55°C to 125°C

Peak Solder Reflow Package

PGND

NC

L

BGA PACKAGE

77-PIN (15mm × 9mm × 5.01mm)

= 125°C

Body Temperature ............................................ 245°C

T

JMAX

θ

JCtop

= 22.4°C/W, θ

= 7.9°C/W, θ = 9.6°C/W, θ = 20.8°C/W

JCbottom

JB

JA

θ VALUES DETERMINED PER JESD51-12

WEIGHT = 1.8 GRAMS

http://www.linear.com/product/LTM4651#orderinfo

ORDER INFORMATION

PART MARKING*

PACKAGE

MSL

TEMPERATURE RANGE

(SEE NOTE 2)

PART NUMBER

LTM4651EY#PBF

LTM4651IY#PBF

LTM4651IY

PAD OR BALL FINISH

SAC305 (RoHS)

SnPb (63/37)

DEVICE

FINISH CODE

TYPE

RATING

–40°C to 125°C

e1

LTM4651Y

BGA

3

e0

• Device temperature grade is indicated by a label on the shipping container. • Recommended BGA PCB Assembly and Manufacturing Procedures:

www.linear.com/BGA-assy

• Pad or ball finish code is per IPC/JEDEC J-STD-609.

• BGA Package and Tray Drawings: www.linear.com/packaging

• Terminal Finish Part Marking: www.linear.com/leadfree

• This product is moisture sensitive. For more information, go to:

• This product is not recommended for second side reflow. For more

www.linear.com/BGA-assy

information, go to www.linear.com/BGA-assy

4651f

2

For more information www.linear.com/LTM4651

LTM4651

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified internal

24V, EXTV_CC= PGND, CLKIN open circuit, R_fSET= 5ꢀ.6kΩ and R_ISET= 480kΩ and voltages referred to PGND unless otherwise noted.

–

operating temperature range (Note 2). T_A= 25°C, Test Circuit 1, V_IN= 24V and electrically connected to SV_INand RUN, ISETa – SV_OUT

=

SYMBOL

PARAMETER

CONDITIONS

MIN

3.6

TYP MAX UNITS

+

–

l

SV

, V

Input DC Voltage

V

|V | ≤ 58V

OUT

58

V

IN(DC) IN(DC)

IN

–

V

Range of Output Voltage Regulation

0.5V ≤ ISETa – SV

≤ 26.5V

OUT

–26.5

–0.5

V

OUT(RANGE)

–

Output Voltage Total Variation with

Line and Load at V

3.6V ≤ V ≤ 34V, 0A ≤ I

≤ 0.3A, CLKIN Driven per

–24.4 –24 –23.6

OUT(–24VDC)

IN

OUT

–

= –24V

Note 6, C = 4.7μF, C = 4.7μF × 2,

OUT

INH

= 47μF × 2

D

C

OUTH

–

l

V

Output Voltage Total Variation with

Measuring GND

– ISETa

–15

0

15

mV

OUT(–5VDC)

SNS

–

Line and Load at V

= –5V

12V ≤ V ≤ 53V, 0A ≤ I

≤ 3A, CLKIN Driven by

OUT

IN

550kHz Clock, C = 4.7μF, C = 4.7μF × 2, C

INH

D

OUTH

–

= 47μF × 2, ISETa – SV

= 5V

OUT

–

V

Output Voltage Total Variation with

Measuring GND

– ISETa

OUT(–0.5VDC)

SNS

–

Line and Load at V

= –0.5V

3.6V ≤ V ≤ 28V, 0A ≤ I

≤ 2A, C = 4.7μF,

OUT

IN

OUT INH

C = 4.7μF × 2, C

= 47μF × 2, R

= N/U,

D

OUTH

fSET

–

ISETa – SV

= 500mV, CLKIN Driven by 200kHz

OUT

Clock (Note 5)

Input Specifications

l

V

SV Undervoltage Lockout Threshold SV Rising

3.2

2.5

700

3.6

2.8

V

mV

IN(UVLO)

IN

SV Falling

2.1

400

IN

Hysteresis

V

SV Overvoltage Lockout Rising

(Note 4)

64

68

2

V

A

IN(OVLO)

IN

SV Overvoltage Lockout Hysteresis (Note 4)

IN

4

IN(HYS)

I

Input Inrush Current at Start-Up

C

= 4.7μF, C = 4.7μF × 2, C = 47μF × 2;

OUTH

1.1

INRUSH(VIN)

INH

D

–

I

= 0A, ISETa Electrically Connected to ISETb

OUT

I

Input Supply Bias Current

Shutdown, RUN = GND

RUN = V

16

450

30

μA

Q(SVIN)

IN

–

I

Input Supply Power Converter

CLKIN Open Circuit, I

= 2A

OUT

2.3

4

A

S(VIN)

Input Supply Current in Shutdown

Shutdown, RUN = GND

µA

S(VIN, SHUTDOWN)

Output Specifications

–

I

V

Output Continuous

From V = 24V, Regulating V

= –24V at f = 1.5MHz

0

2

3

A

OUT

IN

OUT

SW

Current Range

From V = 12V, Regulating V

= –5V at f = 550kHz

SW

IN

(See Note 3, Capable of Up to 4A Output Current for

–

Some Combinations of V , V

, and f )

SW

IN OUT

–

l

∆V

/V

Line Regulation Accuracy

Load Regulation Accuracy

I

= 0A, 3.6V ≤ V ≤ 34V, ISETa – SV

= 24V,

0.05 0.25

%

OUT(LINE) OUT

OUT

IN

OUT

CLKIN Driven by 1.8MHz Clock

–

/V

V

= 24V, 0A ≤ I

Clock, R

≤ 2A, CLKIN Driven by 1.5MHz

0.05

0.5

OUT(LOAD) OUT

IN

OUT

= 57.6kΩ, and R

= 480kΩ

fSET

ISET

–

V

Output Voltage Ripple, V

V

IN

V

IN

= 12V, ISETa – SV

= 5V

10

1.95

8

mV

P–P

OUT(AC)

OUT

–

l

f

s

V

OUT

Ripple Frequency

= 5V

1.7

2.2

9

MHz

mV

ms

–

∆V

Turn-On Overshoot

OUT(START)

t

Turn-On Start-Up Time

Delay Measured from V Toggling from 0V to 24V to

4

START

IN

PGOOD Exceeding 3V Above GND; PGOOD Having a

100kΩ Pull-Up to 3.3V with Respect to GND, VPGFB

Resistor-Divider Network as Shown in Test Circuit 1,

R

= 480kΩ, ISETa Electrically Connected to ISETb,

ISETa

and CLKIN Driven with 1.2MHz Clock

–

∆V

Peak Output Voltage Deviation for

Dynamic Load Step

I

: 0A to 1A and 1A to 0A Load Steps in 1μs,

400

50

mV

µs

OUT(LS)

OUT

C

= 47µF × 2 X5R

OUTH

–

t

Settling Time for Dynamic Load Step

I

C

: 0A to 0.5A and 0.5A to 0A Load Steps in 1μs,

= 47µF × 2 X5R

SETTLE

OUT

OUTH

4651f

3

For more information www.linear.com/LTM4651

LTM4651

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified internal

operating temperature range (Note 2). T_A= 25°C, Test Circuit 1, V_IN= 24V and electrically connected to SV_INand RUN, ISETa – SV_OUT

24V, EXTV_CC= PGND, CLKIN open circuit, R_fSET= 5ꢀ.6kΩ and R_ISET= 480kΩ and voltages referred to PGND unless otherwise noted.

–

=

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP MAX UNITS

–

I

Output Current Limit

2.45

A

OUT(OCL)

OUT

Control Section

–

l

I

t

Reference Current of ISETa Pin

GND Leakage Current

V

– SV

ISETa

= 0.5V, 3.6V ≤ V ≤ 28V

49.3

49

50

50.7

51

µA

ISETa

OUT

IN

–

0.1V ≤ V

– SV

≤ V – SV

≤ 58V

OUT

IN

–

V

– SV

= SV – SV

= RUN – GND =

600

μA

GNDSNS

ON(MIN)

SNS

IN

OUT

IN

= 58V

OUT

–

ISETa – SV

OUT

Minimum On-Time

(Note 4 )

60

ns

l

V

RUN Turn-On/-Off Thresholds

RUN Input Turn-On Threshold, RUN Rising

RUN Hysteresis

1.08

360

1.2

1.32

50

V

RUN

130

mV

(RUN Thresholds Measured with Respect to GND)

I

RUN Leakage Current

V

– 48V, RUN – GND = 3.3V

0.1

nA

RUN

IN

Oscillator and Phase-Locked Loop (PLL)

–

f

Oscillator Frequency Accuracy

V

= 12V, ISETa – SV

= 5V, and:

OSC

IN

OUT

f

Open Circuit

l

400

1.95

440

kHz

MHz

SET

R

= 57.6kΩ (See f Specification)

fSET

s

–

f

PLL Synchronization Capture Range

V

= 12V, ISETa – SV

= 5V, CLKIN Driven with a

SYNC

IN

OUT

GND-Referred Clock Toggling from 0.4V to 1.2V and

Having a Clock Duty Cycle:

From 10% to 90%; f Open Circuit

250

1.3

550

3

kHz

MHz

SET

From 40% to 60%; R

= 57.6kΩ

fSET

V

CLKIN Input Threshold

CLKIN Input Current

V

Rising, with Respect to GND

Falling, with Respect to GND

1.2

V

CLKIN

0.4

I

V

= 5V with Respect to GND

= 0V with Respect to GND

230

–5

500

μA

CLKIN

–20

Power Good Feedback Input and Power Good Output

l

OV

UV

∆V

Output Overvoltage PGOOD Upper

Threshold

PGDFB Rising, Differential Voltage from PGDFB

620

525

645

555

8

675

580

mV

PGDFB

–

to SV

OUT

Output Undervoltage PGOOD Lower

Threshold

PGDFB Falling, Differential Voltage from

PGDFB

–

PGDFB to SV

OUT

PGOOD Hysteresis

PGDFB Returning

mV

kΩ

Ω

PGDFB

–

R

Resistor Between PGDFB and SV

PGOOD Pull-Down Resistance

4.94 4.99 5.04

700 1500

OUT

–

V

= 0.1V with Respect to GND, V

SV

<

PGOOD

PGDFB

OUT

–

UV

or V

– SV

> OV

PGDFB

OUT

I

PGOOD Leakage Current

PGOOD Delay

V

= 3.3V with Respect to GND, UV

<

0.1

1

μA

PGOOD(LEAK)

PGOOD(DELAY)

PGOOD

PGDFB

–

– SV

< OV

PGDFB

OUT

t

PGOOD Low to High (Note 4)

PGOOD High to Low (Note 4)

16/f

s

SW(HZ)

64/f

4651f

4

For more information www.linear.com/LTM4651

LTM4651

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified internal

24V, EXTV_CC= PGND, CLKIN open circuit, R_fSET= 5ꢀ.6kΩ and R_ISET= 480kΩ and voltages referred to PGND unless otherwise noted.

–

operating temperature range (Note 2). T_A= 25°C, Test Circuit 1, V_IN= 24V and electrically connected to SV_INand RUN, ISETa – SV_OUT

=

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP MAX UNITS

Input Voltage Regulation Pin

l

V

VINREG Servo Voltage

VINREG Voltage During Output Current Regulation,

1.8

2.0

1

2.2

V

VINREG

–

Measured with Respect to SV

OUT

–

I

VINREG Leakage Current

VINREG – SV

= 2V

nA

VINREG

OUT

INTV Regulator

CC

–

V

Channel Internal V Voltage, No

3.6V ≤ SV – SV

≤ 58V, EXTV = Open Circuit

3.15

2.85

3.4

3.0

3.65

3.15

V

INTVCC

CC

IN

OUT

–

CC

–

INTV Loading (I

= 0mA)

5V ≤ SV – SV

≤ 58V, 3.2V ≤ EXTV – V

(INTV Measured with Respect to V

≤ 26.5V

CC

INTVCC

IN

OUT

CC

OUT

–

)

CC

OUT

V

EXTV Switchover Voltage

(Note 4)

3.15

0.5

V

EXTVCC(TH)

CC

∆V

/

INTV Load Regulation

0mA ≤ I ≤ 30mA

INTVCC

–2

2

%

INTVCC(LOAD)

INTVCC

CC

V

Temperature Sensor

+

–

∆V

TEMP

Temperature Sensor Forward Voltage,

TEMP

I

= 100µA and I

= –100μA at T = 25°C

0.6

V

TEMP

A

+

–

V

– V

TEMP

TC

∆V(TEMP)

∆V

TEMP

Temperature Coefficient

–2.0

mV/°C

–

Note 1: Stresses beyond those listing under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating conditions for extended periods may affect device

reliability and lifetime.

Note 5: V

low line regulation is tested at 3.6V , with f and

OUT(–0.5VDC)

IN

SET

CLKIN open circuit. High line regulation is tested at 28V , and with CLKIN

IN

driven at 200kHz—so as to ensure minimum on time criteria is met. The

LTM4651 is not recommended for applications where the minimum on-

time criteria (guardband to 90ns) is continuously violated. The LTM4651

Note 2: The LTM4651 is tested under pulsed load conditions such that

can ride through events (such as V surge) where the on-time criteria is

IN

T ≈ T . The LTM4651E is guaranteed to meet performance specifications

J

A

transiently violated. See the Applications Information section.

over the 0°C to 125°C internal operating temperature range. Specifications

over the full –40°C to 125°C internal operating temperature range are

assured by design, characterization and correlation with statistical process

controls. The LTM4651I is guaranteed to meet specifications over the full

internal operating temperature range. Note that the maximum ambient

temperature consistent with these specifications is determined by specific

operating conditions in conjunction with board layout, the rated package

thermal resistance and other environmental factors.

–

Note 6: V

is tested at 3.6V and 34V , with CLKIN driven

OUT(–24VDC)

IN IN

–

with a 1.8MHz clock, ISETa – SV

tested at 24V , with CLKIN driven with a 1.5MHz clock, R

= 24V, and R

= 57.6kΩ. It is also

OUT

fSET

= 57.6kΩ,

IN

fSET

and R

= 480kΩ.

ISET

Note ꢀ: This IC includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperature will exceed 125°C when overtemperature protection is active.

Continuous operation above the specified maximum operating junction

temperature may impair device reliability.

Note 3: See output current derating curves for different V , V , and T ,

IN OUT

A

located in the Applications Information section.

Note 4: Minimum on-time, V Overvoltage Lockout and Overvoltage

Note 8: The INTV Abs Max peak output current is specified as the sum

IN

CC

Lockout Hysteresis, PGOOD Delay, and EXTV Switchover Threshold are

of current drawn by circuits internal to the module biased off of INTV

CC

tested at wafer sort.

and current drawn by external circuits biased off of INTV . See the

Applications Information section.

CC

4651f

5

For more information www.linear.com/LTM4651

LTM4651

T_A= 25°C, unless otherwise noted.

–5V Efficiency vs Load Current

TYPICAL PERFORMANCE CHARACTERISTICS

–3.3V Efficiency vs Load Current

95

90

85

80

75

70

95

90

85

80

75

70

5V , 400kHz

IN

12V , 400kHz

IN

24V , 450kHz

IN

36V , 500kHz

IN

48V , 500kHz

IN

5V , 400kHz

IN

12V , 550kHz

IN

24V , 600kHz

IN

36V , 600kHz

IN

48V , 600kHz

IN

0

1

2

3

4

0

1

2

3

4

LOAD CURRENT (A)

4651 G01

4651 G02

–12V Efficiency vs Load Current

–15V Efficiency vs Load Current

95

90

85

80

75

70

95

90

85

80

75

70

5V , 475kHz

IN

5V , 500kHz

IN

12V , 825kHz

IN

12V , 875kHz

IN

24V , 1.1MHz

IN

24V , 1.2MHz

IN

36V , 1.2MHz

IN

36V , 1.4MHz

IN

0

0.5

1

1.5

2

2.5

3

3.5

0

0.5

1

1.5

2

2.5

3

LOAD CURRENT (A)

4651G03

4651 G04

–24V Efficiency vs Load Current

Rated Operating Output Voltage

95

90

85

80

75

70

0

–5

–10

–15

–20

–25

–30

SAFE OPERATING AREA

5V , 550kHz

IN

12V , 1MHz

IN

24V , 1.5MHz

IN

0

0.5

1

1.5

2

0

10

20

30

40

50

60

LOAD CURRENT (A)

INPUT VOLTAGE (V)

4651 G05

4651 G06

4651f

6

For more information www.linear.com/LTM4651

LTM4651

T_A= 25°C, unless otherwise noted.

TYPICAL PERFORMANCE CHARACTERISTICS

–5V Transient Response, 24V_IN

–24V Transient Response, 12V_IN

Start-Up, No Load

V

IN

–

V

OUT

5V/DIV

100mV/DIV

AC-COUPLED

100mV/DIV

AC-COUPLED

–

V

OUT

10V/DIV

I

OUT

RUN

2V/DIV

OUT

0.4A/DIV

1A/DIV

PGOOD

5V/DIV

4651 G09

4651 G08

4651 G07

20μs/DIV

FIGURE 32 CIRCUIT,

1ms/DIV

40μs/DIV

FIGURE 32 CIRCUIT, 24V

FIGURE 32 CIRCUIT, APPLICATION OF 12V

START-UP INTO NO LOAD

,

IN

0.625A TO 1.25A LOAD STEP AT 0.625A/μs

C

R

= C = C = C = 4.7μF,

DGND D

INOUT

OUT

ISET

IN

= 47μF ×2, R

= 665kΩ,

= 36.5kΩ,

PGDFB

fSET

= 100kΩ, R

= 20Ω, 1.8A TO 3.8A LOAD STEP AT 2A/μs

EXTVCC

Start-Up, 1.25A Load

Start-Up, Pre-Bias

–

V

OUT

IN

5V/DIV

–

10V/DIV

V

I

DIODE

100mA/DIV

OUT

10V/DIV

I

RUN

2V/DIV

OUT

500mA/DIV

PGOOD

5V/DIV

PGOOD

2V/DIV

4651 G10

4651 G11

1ms/DIV

–

FIGURE 32 CIRCUIT, APPLICATION OF 12V

START-UP INTO 19.2Ω LOAD

,

FIGURE 32 CIRCUIT, V

PRE-BIASED

IN

OUT

TO –5V THROUGH A 1N4148 DIODE PRIOR

TO RUN TOGGLING HIGH

Short Circuit, No Load

Short Circuit, 1.25A Load

–

V

OUT

10V/DIV

I

IN

10A/DIV

4651 G13

4651 G12

10μs/DIV

FIGURE 32 CIRCUIT,

10μs/DIV

FIGURE 32 CIRCUIT,

19.2Ω LOAD PRIOR TO APPLICATION OF

NO LOAD PRIOR TO APPLICATION OF

–

V

OUT

SHORT-CIRCUIT

V

OUT

SHORT-CIRCUIT

4651f

7

For more information www.linear.com/LTM4651

LTM4651

PIN FUNCTIONS

PACKAGE ROW AND COLUMN LABELING MAY VARY

RUN (F4): Run Control Pin. A voltage above 1.2V (with

respect to GND) commands the module to regulate its

output voltage. Undervoltage lockout (UVLO) can be

implemented by connecting RUN to the midpoint node

AMONG µModule PRODUCTS. REVIEW EACH PACKAGE

LAYOUT CAREFULLY.

V (A1 – A3, B3): Power Input Pins. Apply input voltage

IN

and input decoupling capacitance directly between V

IN

formed by a resistor-divider between V and GND. RUN

IN

and a power ground (PGND) plane.

features 130mV of hysteresis. See the Applications In-

formation section.

V (A4,B4,C4):DrainoftheConverter’sPrimarySwitching

D

MOSFET. Apply at least one 4.7μF high frequency ceramic

INTV (G3): Internal Regulator, 3.3V Output with Re-

CC

–

decoupling capacitor directly from V to V

. Give this

D

OUT

spect to V

. Internal control circuits and MOSFET-

OUT

capacitor higher layout priority (closer proximity to the

module) than any V decoupling capacitors.

drivers derive power from INTV bias. When operating

CC

IN

3.6V < SV ≤ 58V, an LDO generates INTV from SV

IN

CC

IN

whenRUNislogichigh(RUN>1.2V).Noexternaldecoupling

SV (C3): Input Voltage Supply for Small-Signal Circuits.

IN

is required. When RUN is logic low (RUN – GND < 1.2V),

SV is the input to the INTV LDO. Connect SV directly

IN

CC

IN

the INTV LDO is off, i.e., INTV is unregulated. (Also

CC

to V . No decoupling capacitor is needed on this pin.

IN

see EXTV .) It is not recommended to load INTV with

CC

–

V

(A5, B5, C2, C5, D5, E5, F5, G4 – 5, H3, H5,

OUT

external circuits exceeding ~10mA. See the Applications

J3 – 5, K4 – 5, L4 – 5): Negative Power Output of the

Information section and Note 8.

–

LTM4651. Connect all V

pins to the application’s

OUT

–

EXTV (F3): External Bias, Auxiliary Input to the INTV

CC

V

plane. Apply the output filter capacitor and the

OUT

–

Regulator. When EXTV – V

exceeds 3.2V and

CC

OUT

output load between these and the PGND pins.

–

SV – V

exceeds 5V, the INTV LDO derives power

IN

OUT

CC

IN

PGND(K1–3,L1–3):PowerGroundPinsoftheLTM4651.

Electricallyconnectallpinstotheapplication’sPGNDplane.

from EXTV bias instead of the SV path. This technique

CC

can reduce LDO losses considerably, resulting in a cor-

respondingreductioninmodulejunctiontemperature.For

GND(D4):GroundReferenceforRUN,CLKIN,andPGOOD

Signals. Connect GND directly to the PGND power ground

plane.

–

applications where |V

| > 4V, realize this benefit by

OUT

connecting EXTV to PGND through a resistor. (See the

CC

Application Information section for resistor value.) When

GND

(G1, H1): Voltage Sense, PGND Input and Feed-

SNS

taking advantage of this EXTV feature, locally decouple

CC

back Signal. Connect GND

to PGND at the point of

SNS

–

EXTV toV

witha1µFceramiccapacitor—otherwise,

CC

OUT

load (POL). Pins G1 and H1 are electronically connected

to each other internal to the module, and thus it is only

necessarytoconnectoneGND

leave EXTV open circuit.

CC

ISETb (F1): 1.5nF Soft-Start Capacitor. Connect ISETb

to ISETa to achieve default soft-start characteristics, if

desired—otherwise, leave ISETb open circuit. See ISETa.

pintoPGNDatthePOL.

SNS

TheremainingGND

pincanbeusedforredundantcon-

SNS

nectivity or routed to an ICT test point for design-for-test

considerations, as desired.

ISETa (F2): Accurate 50µA Current Source. Positive input

–

to the error amplifier. Connect a resistor (R ) from this

SV

(E4,G2,H2):VoltageSense,V

Input.Connect

SET

OUT

–

pintoSV

age, V

toprogramthedesiredLTM4651outputvolt-

Pin H2 to V

directly under the LTM4651. The SV

OUT

–

= –R • 50µA. A capacitor can be connected

pins at locations E4 and G2 are electrically connected

SET

OUT

–

from ISETa to SV

to soft-start the output voltage and

to each other internal to the module, and thus it is only

–

reduce start-up inrush current. Connect ISETa to ISETb in

order to achieve default soft-start, if desired. See ISETb.

necessary to connect one SV

the module. The remaining SV

redundant connectivity or routed to an ICT test point for

design-for-test considerations, as desired.

pin to V

under

OUT

pins can be used for

4651f

8

For more information www.linear.com/LTM4651

LTM4651

PIN FUNCTIONS

In addition, the output of the LTM4651 can track a voltage

applied between the ISETa pin and the SV

the Applications Information section.

COMPa (E2): Current Control Threshold and Error Ampli-

fier Compensation Node. The trip threshold of LTM4651’s

current comparator increases with a respective rise in

COMPa voltage. A small filter capacitor (10pF) internal

to the LTM4651 on this pin introduces a high-frequency

roll-offoftheerror-amplifierresponse,yieldinggoodnoise

rejection in the control-loop. COMPa is usually electrically

connected to COMPb in one’s application, thus applying

default loop compensation. Loop compensation (a series

resistor-capacitor) can be applied externally to COMPa if

desired or needed, instead. See COMPb.

–

pins. See

OUT

PGOOD (D1): Power Good Indicator, Open-Drain Output

–

Pin. PGOOD is high impedance when PGDFB – SV

is

OUT

within approximately 7.5% of 0.6V. PGOOD is pulled to

–

GND when PGDFB – SV

is outside this range.

OUT

PGDFB (D2): Power Good Feedback Programming Pin.

Connect PGDFB to GND

PGDFB

through a resistor, R

.

SNS

PGDFB

–

R

configures the voltage threshold of V

for

OUT

which PGOOD toggles its state. If the PGOOD feature is

COMPb (E1): Internal Loop Compensation Network.

For a majority of applications, the internal, default loop

compensation of the LTM4651 is suitable to apply “as is”

and yields very satisfactory results: apply the default loop

compensation to the control loop by simply connecting

COMPa to COMPb. When more specialized applications

requireapersonaltouchtotheoptimizationofcontrolloop

used, set R

to:

PGDFB

–





|V

|





OUT

R_PGDFB

=

–1 •4.99k











0.6V



otherwise, leave PGDFB open circuit.

response,thiscanbeaccomplishedbyconnectingaseries

A small filter capacitor (220pF) internal to the LTM4651

on this pin provides high frequency noise immunity for

the PGOOD output indicator.

–

resistor-capacitor network from COMPa to SV

leaving COMPb open circuit.

—and

OUT

VINREG(D3):InputVoltageRegulationProgrammingPin.

f

(E3): Oscillator Frequency Programming Pin. The

SET

Optionally connect this pin to the midpoint node formed

default switching frequency of the LTM4651 is 400kHz.

–

by a resistor-divider between V and SV

. When the

D

OUT

Often, it is necessary to increase the programmed fre-

quencybyconnectingaresistorbetweenf andSV

(See the Applications Information section.) Note that the

synchronization range of CLKIN is approximately 40%

of the oscillator frequency programmed by the f pin.

voltage on VINREG falls below approximately 2V with

–

.

SET

OUT

–

respect to SV

, a VINREG control loop servos COMPa

OUT

so as to decrease the power inductor current and thus

–

regulate VINREG at 2V with respect to SV

Applications Information section.

. See the

OUT

SET

CLKIN(B1):OscillatorSynchronizationInput.LeaveCLKIN

open circuit for forced continuous mode operation.

If this input voltage regulation feature is not desired, con-

nect VINREG to INTV .

CC

Alternatively,thispincanbedrivensoastosynchronizethe

switching frequency of the LTM4651 to a clock signal. In

thiscondition,theLTM4651operatesinforced-continuous

mode and the cycle-by-cycle turn-on of the Primary MOS-

FET is coincident with the rising edge of the clock applied

to CLKIN. Note the synchronization range of CLKIN is ap-

proximately 40%oftheoscillatorfrequencyprogrammed

+

TEMP (J1, J6): Temperature Sensor, Positive Input.

Emitterofa2N3906-genrePNPbipolarjunctiontransistor

(BJT). Optionally interface to temperature monitoring cir-

cuitrysuchasLTC^®2997, LTC2990, LTC2974orLTC2975.

Otherwise leave electrically open. Pins J1 and J6 are

electrically connected together internal to the LTM4651,

and thus it is only necessary to connect one TEMP pin

to monitoring circuitry. The remaining TEMP pin can be

+

by the f pin. See the Applications Information section.

SET

+

used for redundant connectivity or routed to an ICT test

point for design-for-test considerations, as desired.

4651f

9

For more information www.linear.com/LTM4651

LTM4651

PIN FUNCTIONS

–

TEMP (J2, J7): Temperature Sensor, Negative Input.

with a thin trace to a local test point to monitor switching

actionoftheconverter, ifdesired, butdonotroutenearany

sensitivesignals;otherwise,leaveelectricallyopencircuit.

Collector and base of a 2N3906-genre PNP bipolar junc-

tion transistor (BJT). Optionally interface to temperature

monitoringcircuitrysuchasLTC2997,LTC2990,LTC2974

or LTC2975. Otherwise leave electrically open. Pins J2

and J7 are electrically connected together internal to the

LTM4651, and thus it is only necessary to connect one

NC (A6 – 7, B2, B6 – 7, C1, C6 – 7, D6 – 7, E6 – 7, F6 – 7,

G6 – 7, H6 – 7, K6 – 7, L6 – 7): No Connect Pins, i.e., Pins

with No Internal Connection. The NC pins predominantly

serve to provide improved mounting of the module to the

board. In one’s layout, NC pins are permitted to remain

–

TEMP pin to monitoring circuitry. The remaining TEMP

pin can be used for redundant connectivity or routed to an

ICTtestpointfordesign-for-testconsiderations,asdesired.

electrically unconnected or can be connected as desired,

–

e.g., connected to a V

plane for heat-spreading pur-

OUT

SW (H4): Switching Node of Switching Converter Stage.

Used for test purposes. May be routed a short distance

poses and/or to facilitate routing.

SIMPLIFIED BLOCK DIAGRAM

1Ω

V

SV

IN

RUN:

NC

3.6V

>1.2V

= ON

TYP

+

TO 58V

400nH

0.1μF

–

<1.07V

= OFF

RUN

V

IN

C

INH

TYP

C

I

INL

SVIN

V

OUT

(REFERRED

TO GND)

C

*

INOUT

V

D

POWER CONTROL

AND ANALOG CIRCUITS

CLKIN

(REFERRED

TO GND)

C

*

D

DGND

–

V

OUT

4.7μF

×2

0.1μF

TO CURRENT COMPARATORS,

PWM AND FET DRIVERS

M

T

SW

EXTV

CC

4μH

PGND

50μA

ISETa

I

L

M

B

COMP

BUFFER

ISETb

COMPa

COMPb

0.1μF

+

–

GND

LOAD-LOCAL

MLCCs (HIGH-

FREQUENCY

DECOUPLING)

ERROR

AMPLIFIER

(CENTRALLY

LOCATED PNP

TEMP SENSOR)

C

LOAD

10nF

50Ω

1.5nF

10pF

OUTH

–

| V_OUT

|

–

R_ISET

=

V

OUT

50µA

–

V

OUT

UP TO 0A

DOWN TO (V –58V),

NO EXCEEDING 26V

BELOW PGND

R

ISET

IN

INTV

CC

–

I

SV

SVOUT

OUT

1µF

–

PGOOD

(REFERRED

TO GND)

V

OUT

VINREG

400kHz

HI-Z WHEN

– SV

IS WITHIN

+

–

V

PGDFB

OUT

0.6V 7.5ꢀ

DEFAULT

f

SET

R

PGDFB

+

2V

PGDFB

PGOOD

LOGIC

–

249k

+

100Ω

GND

TEMP

4.99k

220pF

–

SV

OUT

–

TEMP

*C

INOUT

and C

OPTIONAL, FOR REDUCED

DGND

RADIATED EMI. SEE FIGURES 5 THROUGH 8.

4651 BD

4651f

10

For more information www.linear.com/LTM4651

LTM4651

TEST CIRCUIT

V

IN

V

PGOOD

PGDFB

NC

SW

IN

3.6V

C

4.7μF

INH

TO 34V

SV

IN

R

PGDFB

RUN

196k

GND

SNS

GND

CLKIN

PGND

+

C

*

OUTL

LOAD

OUTH

LTM4651

V

D

27µF

68µF

–

C

4.7μF

2x

D

V

–

OUT

INTV

CC

–24V

–

SV

OUT

UP TO 2A

AT V = 24V

VINREG

COMPa

COMPb

+

IN

TEMP

EXTV

–

R

**

EXTVCC

0Ω

C

TH

f

ISETa ISETb

0.1μF

SET

CC

4651 TC01

R

499Ω

C

EXTVCC

1μF

TH

R

57.6k

fSET

R

480k

SET

*Polarized output capacitors C

, if used, must be rated to withstand ~0.3V typical reverse polarity prior to LTM4651 start-up,

OUTL

stemming from a weakly forward-biased body diode. In such cases, a Schottky diode should be connected between PGND and

–

V

to limit the voltage. See the Applications Information section and Figures 33a and 33b.

OUT

**Outside the ATE Test environment, R

, if used, should not be 0Ω. See the Applications Information section.

EXTVCC

T_A= 25°C. Refer to Test Circuit 1.

DECOUPLING REQUIREMENTS

APPLICATION SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Test Circuit 1

C , C

INH

External High Frequency Input Capacitor Requirement,

2A

9.4

µF

D

–

24V ≤ V ≤ 34V, V

= –24V

IN

OUT

C

External High Frequency Output Capacitor Requirement

2A

22

µF

OUTH

–

24V ≤ V ≤ 34V, V

= –24V

IN

OUT

4651f

11

For more information www.linear.com/LTM4651

LTM4651

OPERATION

Power Module Description

margins and good transient performance with a wide

range of output capacitors, even ceramic-only output

capacitors. For external loop compensation, see the Ap-

plications Information section. LTpowerCAD^®is available

for transient load step and stability analysis.

The LTM4651 is a non-isolated switch mode DC/DC

power supply. It can provide up to 4A output current

with a few external input and output capacitors. Set by a

single resistor, R , the LTM4651 regulates a negative

SET

–

output voltage, V

. V

can be set to as low as

Input filter and noise cancellation circuitry reduces noise-

coupling to the module’s inputs and outputs, ensuring the

module’s electromagnetic interference (EMI) meets the

limits of EN55022 Class B (see Figures 5 to 8).

OUT

–26.5V to as high as –0.5V. The LTM4651 operates from

a positive input supply rail, V , between 3.6V and 58V.

IN

The LTM4651’s safe operating area is defined by: V +

IN

–

|V

OUT

| ≤ 58V. The typical application schematic is shown

Pulling the RUN pin below 1.2V forces the LTM4651 into

in Figure 32. The output current capability of the LTM4651

is dependent on V and V , as indicated in the page 1

a shutdown state. A capacitor can be applied from ISETa

–

IN

OUT

to SV

to program the output voltage ramp-rate; or,

OUT

graph. Though the LTM4651 is a ground-referred buck

converter topology—also known as a two-switch buck-

boost converter—it contains built-in level-shift circuitry

sothattheRUN, CLKIN, andPGOODpinsareconveniently

referred to GND (not V

the default LTM4651 ramp-rate can be set by connecting

ISETa to ISETb; or, voltage tracking can be implemented

by interfacing rail voltages to the ISETa pin. See the Ap-

plication Information section.

–

).

OUT

Multiphase operation can be employed by applying an

external clock source to the LTM4651’s synchronization

input, the CLKIN pin. See the Typical Applications section.

The LTM4651 contains an integrated constant-frequency

current mode regulator, power MOSFETs, power inductor,

EMI filter and other supporting discrete components. The

nominal switching frequency range is from 400kHz to

3MHz, and the default operating frequency is 400kHz. It

can be externally synchronized to a clock, from 250kHz to

3MHz. See the Applications Information section.

LDO losses within the module are reduced by connecting

EXTV to PGND through an RC-filter or by connecting

CC

EXTV to a suitable voltage source.

CC

The LTM4651 also features a spare control pin called

VINREG which can be used to reduce the input current

draw during input line sag (“brownout”) conditions. Con-

The LTM4651 supports internal and external control loop

compensation. Internal loop compensation is selected by

connecting the COMPa and COMPb pins. Using internal

loop compensation, the LTM4651 has sufficient stability

nect VINREG to INTV when this feature is not needed.

CC

4651f

12

For more information www.linear.com/LTM4651

LTM4651

APPLICATIONS INFORMATION

The typical LTM4651 application circuit is shown in Test For completeness, ∆I

Circuit 1. External component selection is primarily deter-

mined by the maximum load current and output voltage.

Refer to Table 8 for recommended external component

values.

is given by:

PK-PK

Output Current Capability Varies as a Function of V

where:

L is 4μH, the LTM4651’s power inductor value, and f is

IN

–

to V

Conversion Ratios

OUT

SW

The output current capability of the LTM4651 has a strong the switching frequency of the LTM4651, in MHz.

–

dependencyontheoperatinginput(V )andoutput(V

)

IN

OUT

For a practical design, ∆I

is designed to be less than

PK-PK

voltages, as highlighted in the page 1 graph.

~2A

.

PK-PK

The reason for this is inherent in the two-switch buck-

boost topology employed by the LTM4651. To protect

For a practical design, the LTM4651’s on-time of M

T

each switching cycle should be designed to exceed the

the primary power MOSFET (M ) from overstress (see

T

LTM4651 control loop’s specified minimum on-time of

Simplified Block Diagram), its peak current (I ) is limited

PK

60ns, t , (guardband to 90ns) i.e.:

ON(MIN)

by control circuitry to 6A. When M is on, observe that no

T

D

f_SW

current flows to LTM4651’s output; furthermore, observe

> T_ON(MIN)

(3)

(4)

that only when M is off does current flow to the output

T

of the LTM4651. As a consequence of this arrangement:

for agiven outputvoltage, currentlimitinception activates

sooner at low line (higher, larger duty cycle) than at high

line (lower, smaller duty cycle). A further consequence is:

where D (unitless) is the duty-cycle of M , given by:

T

–

–V_OUT

D=

–

V – V

for a given input voltage, the output power capability of

IN

OUT

–

the LTM4651 is higher for lower-magnitude V

(lower,

OUT

Combining EQ. 4 with EQ. 1, it can be illustrative to see:

–

smaller duty cycle) than for higher-magnitude V









(higher,largerdutycycle).Thecombinationoftheseeffects

is shown the plots in the page 1 graph and described by

the following equation:

∆I_PK–PK



I_{OUT(CAPABILITY)}=(1–D)• I_PK

–

•η

(5)



2







∆I

In rare cases where the minimum on-time restriction is

violated, the frequency of the LTM4651 automatically and



^PK–PK

V • I_PK–

•η

IN





2





I_{OUT(CAPABILITY)}

=

(1)

–

gradually folds back down to one-fifth of its programmed

V – V

IN

OUT

–

switchingfrequencytoallowV

toremaininregulation.

OUT

Be reminded of Notes 2, 3 and 5 in the Electrical Char-

acteristics section regarding output current guidelines.

where:

∆I

is the inductor ripple current, in amps, and η (unit

PK-PK

less) is the efficiency of the LTM4651.

4651f

13

For more information www.linear.com/LTM4651

LTM4651

APPLICATIONS INFORMATION

Input Capacitors

A final precaution regarding ceramic capacitors concerns

the maximum input voltage rating of the LTM4651’s V ,

TheLTM4651achieveslowinputconductedEMInoisedue

to tight layout and high-frequency bypassing of MOSFETs

IN

SV ,andV pins.Aceramicinputcapacitorcombinedwith

IN

D

trace or cable inductance forms a high Q (underdamped)

tank circuit. If the LTM4651 circuit is plugged into a live

supply, the input voltage can ring to twice its nominal

value, possibly exceeding the device’s rating. This situa-

tioniseasilyavoided;seetheHot-PluggingSafelysection.

M and M within the module itself. A small filter induc-

T

B

tor (400nH) is integrated in the input line (from V to V )

IN

D

provides further noise attenuation—again, local to the

switching MOSFETs. The V and V pins are available

D

IN

for external input capacitors—V and V —to form a

D

INH

high-frequency � filter. As shown in the Simplified Block

Diagram, the ceramic capacitor C on the LTM4651’s V

pins handles the majority of the RMS current into the DC/

DC converter power stage and requires careful selection,

for that reason.

Output Capacitors

D

–

OutputcapacitorsC

theLTM4651:sufficientcapacitanceandlowESRarecalled

for, to meet the output voltage ripple, loop stability, and

transient requirements. C

or polymer capacitor. C

typical output capacitance is 22μF (type X5R material, or

better), if ceramic-only output capacitors are used.

andC

areappliedtoV

of

OUTH

OUTL

OUT

can be a low ESR tantalum

is a ceramic capacitor. The

OUTL

OUTH

TomeettheradiatedemissionsrequirementsofEN55022B,

anadditionalfiltercapacitor,C

,isneeded—connecting

INOUT

–

fromV toV

.SeeFigures5to 8forEMIperformance.

IN

OUT

The input capacitance, C , is needed to filter the pulsed

D

For highest reliability designs, polarized output capacitors

current drawn by M . To prevent excessive voltage sag

T

(V

) are not recommended, as there is a possibility of

OUTL

on V , a low-effective series resistance (low-ESR) input

D

a diode-drop of reverse voltage appearing transiently on

capacitor should be used, sized appropriately for the

–

V

during rapid application of input voltage or when

OUT

maximum C RMS ripple current:

D

RUNistoggledlogichigh(seeFigures33).Whenpolarized

–

I_CD(RMS)=I_PK• D•(1–D)

(6)

capacitorsareusedonV

,contactthecapacitorvendor

OUT

to understand what reverse voltage their polarized capaci-

tor can withstand. Be advised, polarized capacitor reverse

voltage rating is sometimes temperature-dependent.

I

is maximum for D = 1/2. For D = 1/2,

CD(RMS)

= 1/2 • I or 3A. This simplification of the worst-

PK

case condition is commonly used for design purposes

becauseevensignificantdeviationsinDdonotoffermuch

relief, in practice. Furthermore: note that ripple current

ratings from capacitor manufacturers are often based on

2000 hours of life; therefore, it is advisable to significantly

–

Output voltage ripple (∆V

) is governed by

OUT(PK-PK)

charge lost in C

and C

while M is on, in addition

OUTL T

OUTH

to the contribution of a resistive drop across the ESR of

the output capacitors. This is expressed by:

I_LOAD•D I_LOAD•ESR

over-designC ,and/orchooseacapacitorratedatahigher

D

∆V_OUT(PK–PK)

≈

+

(7)

temperature than required. Err on the side of caution and

contact the capacitor manufacturer to understand the

capacitor vendor’s derating methodology.

C_OUT•f_SW

D

Table 8 shows a matrix of suggested output capacitors

optimized for transient step-loads that are 50% of the full

Several capacitors may be paralleled to meet the applica-

–

loadcapabilityforthatcombinationofV , V

, andf

.

IN OUT

SW

tion’s targetsize,height,andC RMSripplecurrentrating.

D

The table optimizes total equivalent ESR and total bulk

capacitancetoyieldthestatedtransient-loadperformance.

Additional output filtering may be required by the system

designer, if further reduction of output ripple or dynamic

transient spike is required. The LTpowerCAD design tool

is available for transient and stability analysis.

For lower input voltage applications, sufficient bulk input

capacitance is needed for C to counteract line sag and

INL

transient effects during output load changes. Suggested

values for C and C

are found in Table 8. Take note

D

INH

–

that C is connected from V to V

, whereas C and

D

OUT

INH

C

are connected from V to PGND; this is deliberate.

INL

IN

4651f

14

For more information www.linear.com/LTM4651

LTM4651

APPLICATIONS INFORMATION

Forced Continuous Operation

equals V

—after which, the DC/DC converter com-

GNDSNS

–

mences switching action and V

is ramped according

OUT

LeavetheCLKINpinopencircuittocommandtheLTM4651

for forced continuous operation. In this mode, the control

loop is allowed to command the inductor peak current

to approximately –1A, allowing for significant negative

average current.

to the voltage commanded by ISETa.

Since the LTM4651 control loop servos its GND

SNS

voltage to match that of ISETa’s, the LTM4651’s output

can be configured to track any voltage applied to ISETa,

–

referenced to SV

.

OUT

Clocking the CLKIN pin at a frequency within 40% of

The LTM4651 can track the mirror-image of a positive rail

to generate the negative half of a split-supply, as seen in

Figure 37.

the target switching frequency commanded by the f

SET

pin synchronizes M ’s turn-on to the rising edge of the

T

CLKIN pin.

Optional Diodes to Guard Against Overstress

Output Voltage Programming, Tracking and Soft-Start

–

Just prior to output voltage start-up, a mechanism exists

TheLTM4651regulatesitsoutputvoltage,V

,according

OUT

–

whereby a diode-drop of reverse polarity can appear on

tothedifferentialvoltagepresentacrossISETaandSV

.

OUT

–

V

. See the simplified Block Diagram and observe: just

OUT

Inmostapplications,theoutputvoltageissetbysimplycon-

prior to output voltage start-up, SV bias current (I

)

IN

SVIN

–

nectingaresistor,R ,fromISETatoSV

,accordingto:

–

SET

OUT

flows through the module’s control IC, to SV

; from

OUT

–

–V_OUT

there, the bias current (now I

) flows into V

and

SVOUT

OUT

R_SET

=

(8)

50µA

through M ’s body diode, to SW. This current (now I )

B

L

continues to flow—though the 4μH power inductor—to

Since the LTM4651 control loop servos its output volt-

age according to the voltage between ISETa and SV

configures the

. In the time domain,

the output voltage ramp-up after the RUN pin is toggled

from low to high (t = 0s) is given by:

PGND and ground, closing the control IC bias circuit’s

–

:

OUT

path. It is this current through M ’s body diode that cre-

B

placing a capacitor, C , parallel to R

SS

SET

ates a diode-drop of reverse polarity (positive voltage) on

–

ramp-up rate of ISETa and thus V

–

OUT

V

, as shown in Figure 33. The voltage excursion is

OUT

highest when RUN toggles high because that is the instant

when INTV powers-up, with a corresponding increase

CC

–



t





in I

/I

/I current flow. With higher current flow,

L

SVIN SVOUT

–



R

_SET•C

V_OUT(t)^–=I_ISETa•R_SET• 1–e

(9)







^SET

the forward voltage drop (V ) of M ’s body diode—and

thus, the positive voltage excursion on V

F

B

–









—is higher.

OUT





If this transient voltage excursion is unwelcome for the

The soft-start time, t , is defined as the time it takes for

OUT

SS

load or polarized output capacitors, minimize it with a

–

V

to ramp from 0V to 90% of its final value:

–

lowV SchottkydiodethatstraddlesV

andPGND(see

F

OUT

T_SS= –R_SET•C_SET•In(1–0.9)

(10)

Figure 32 circuit and Figure 33 performance). Addition-

ally, the voltage excursion can be empirically reduced by

increasing output capacitance.

or

T_SS=2.3 •R_SET•C_SET

(11)

Lastly: in applications where it is anticipated that V may

IN

be rapidly applied (e.g., <10μs) and C

is used, the

INOUT

positive.Itisrecom-

INOUT

A default value of C

= 1.5nF can be implemented by

SET

resulting capacitor-divider network formed by C

and

connecting ISETa to ISETb. For other ramp-up rates, con-

–

C

||C maytransientlydragV

INL INH

OUT

nect an external C capacitor parallel to R

.

SET

–

mended to apply a low V Schottky diode from V

to

F

OUT

–

When starting up into a pre-biased V

, the LTM4651

OUT

PGND, in such applications. The reverse mechanism ap-

plies, as well: in applications where it is anticipated that

stays in a sleep mode, keeping M and M off until V

T

B

ISETa

4651f

15

For more information www.linear.com/LTM4651

LTM4651

APPLICATIONS INFORMATION

V

may be rapidly discharged and C

is used, the

current capability of the LTM4651 is reduced, according

to EQ. 5.

IN

INOUT

resulting capacitor-divider network formed by C

and

INOUT

–

C

||C maytransientlydragV

excessivelynegative.

andPGNDwithaTVS

INL INH

OUT

ToconfiguretheLTM4651forahigherswitchingfrequency

–

ItisrecommendedtostraddleV

OUT

than 400kHz default, apply a resistor, R , between the

fSET

diode, if output voltage excursions during V -discharge

–

IN

f

pin and SV

. R

is given (in MΩ) by:

SET

OUT

fSET

are anticipated.

1

R_fSET(MΩ)=

(14)

Frequency Adjustment

10pF •[f_SW(MHz)–0.4(MHz)]

The default switching frequency (f ) of the LTM4651 is

SW

The relationship of R

in Figure 2.

to programmed f is shown

SW

fSET

–

400kHz. This is suitable for mainly low-V or low-V

IN

OUT

–

applications (V < 5V or |V

| < 5V). For a practical

IN

OUT

See Table 1 and Table 8 for Recommended f and as-

design, the LTM4651’s inductor ripple current (∆

) is

PK-PK

SW

sociated R

values for various combinations of V

suggested to be less than ~2A

. From EQ. 2, it follows

fSET

IN

PK-PK

–

and V

.

that f should be chosen such that:

OUT

SW

1

(12)

10









1

V_OUT

L•∆I_PK-PK

•

–





^–

V

IN





In some cases, the value of f yielded by EQ. 12 violates

SW

Rf

NOT USED

1

SET

the supported minimum on time of the LTM4651 (see

EQ. 3). If this occurs, choose f instead according to:

SW

D

f_SW

<

(13)

T_ON(MIN)

0.1

10

100

1k

10k

Rf

(kΩ)

SET

The primary consequence of using a lower switching

frequency than that dictated by EQ. 12 is that the output

4651 F02

Figure 2. Relationship Between R_fSETand Target f_SW

–

Table 1. Recommended Switching Frequency (f_SW) and R_fSETValues for Common Combinations of V_INand V_OUT

–

V

OUT

(V)

–0.5

–3.3

–5

–8

–12

–15

–20

–24

3.6

5

400kHz,

425kHz,

4.3MΩ

450kHz,

2.2MΩ

No R

fSET

400kHz,

No R

fSET

400kHz,

No R

fSET

450kHz,

2.2MΩ

475kHz,

1.3MΩ

500kHz,

1MΩ

525kHz,

806kΩ

550kHz,

665kΩ

No R

fSET

12

24

550kHz,

665kΩ

700kHz,

332kΩ

825kHz,

237kΩ

875kHz,

210kΩ

900kHz,

200kΩ

1MHz,

165kΩ

Drive CLKIN

800kHz,

249kΩ

1.1MHz,

143kΩ

1.2MHz,

124kΩ

1.4MHz,

100kΩ

1.5MHz,

90.9kΩ

450kHz,

2.2MΩ

with a 200kHz

Clock, No R

fSET

600kHz,

499kΩ

36

48

Not

850kHz,

221kΩ

1.2MHz,

124kΩ

1.4MHz,

100kΩ

1.6MHz,

82.5kΩ

N/A

Recommended

Due to On-

Time Criteria

Violation

500kHz,

1MΩ

900kHz,

200kΩ

N/A Due to SOA Criteria Violation

4651f

16

For more information www.linear.com/LTM4651

LTM4651

APPLICATIONS INFORMATION

Power Module Protection

V

SUPPLY

R

A

TheLTM4651’scurrentmodecontrolarchitectureprovides

fast cycle-by-cycle current limit in an overcurrent condi-

tion, as shown in the Typical Performance Characteristics

section. If the output voltage collapses sufficiently due to

an overload or short-circuit condition, minimum on-time

will be violated (EQ. 3) and the internal oscillator will then

fold-back automatically to one-fifth of the LTM4651’s

programmed switching frequency—hereby reducing the

output current and affording the load a chance to recover.

RUN PIN

B

4651 F03

Figure 3. Undervoltage Lockout Resistive Divider

the user. The RUN pin hysteresis voltage prevents noise

from falsely tripping UVLO. Resistors are chosen by first

selecting R (refer to Figure 3). Then:

The LTM4651 features input overvoltage shutdown

B

–

protection: when V +|V

| > 68V, switching action

IN

OUT





V

ceases (with 4V of hysteresis)—however, be advised that

this protection is only active outside the LTM4651’s safe

operating area (see Note 1 and Note 4 of the Electrical

Characteristics table).

IN(ON)





R =R •

–1

(15)





A

B



1.2V





where V

is the input voltage at which the undervolt-

IN(ON)

age lockout is overcome and the supply turns on. R may

A

The LTM4651 ceases switching action if internal tempera-

tures exceed 165°C. The control IC resumes operation

after a 10°C cool-down hysteresis. Note that these typical

parameters are based on measurements in a lab oven and

arenotproductiontested.Thisovertemperatureprotection

is intended to protect the device during momentary over-

loadconditions.Themaximumratedjunctiontemperature

will be exceeded when this overtemperature protection is

active. Continuous operation above the specified absolute

maximum operating junction temperature may impair

device reliability or permanently damage the device.

be replaced with a hardwired connection from V to RUN.

D

The V turn-off voltage, V

is given by:

IN

IN(OFF)





R_A

R_B





V

=1.07V •

+1

(16)





IN(OFF)





IfUVLOisnotneeded,RUNcanbeconnectedtoLTM4651’s

V or V pins.

D

IN

When RUN is below its threshold, UVLO is engaged, M

T

and M are turned off, INTV ceases to be regulated,

B

CC

OUT

–

and ISETa is discharged to SV

by internal circuitry.

The LTM4651 does not feature any specialized output

overvoltage protection beyond what is inherent to the

control loop’s servo mechanism.

Loop Compensation

External loop compensation may be preferred for some

applications and can be implemented easily, as follows:

RUN Pin Enable

leave COMPb open circuit; connect a series-R network

C

The RUN pin is used to enable the power module or se-

quencethepowermodule. Thethresholdis1.2V. TheRUN

pincanbeusedtoprovideanundervoltagelockout(UVLO)

function by connecting a resistor divider from the input

supply to the RUN pin, as shown in Figure 3. Undervoltage

lockout keeps the LTM4651 in shutdown until the supply

input voltage is above a certain voltage programmed by

–

(R and C ) from COMPa to SV

; in some instances,

TH

OUT

–

connect a capacitor (C ) from COMPa to SV

(par-

THP

OUT

alleling the R

series-R network). See Table 8 for

TH-CTH

C

suggested input and output capacitances for a variety of

operatingconditions.Additionally,theLTpowerCADdesign

tool is available for transient and stability analysis.

4651f

17

For more information www.linear.com/LTM4651

LTM4651

APPLICATIONS INFORMATION

Hot-Plugging Safely

TherecommendedvalueoftheresistorbetweenPGNDand

–

EXTV is roughly |V

| • 4Ω/V. This resistor, R

,

.

CC

OUT

EXTVCC

The small size, robustness and low impedance of ceramic

capacitors make them an attractive option for the input

²

must be rated to continually dissipate (0.02A) • R

The primary purpose of this resistor is to prevent EXTV

bypasscapacitors(C andC )oftheLTM4651.However,

D

INH

overstress under a fault condition. For example, when an

these capacitors can cause problems if the LTM4651 is

plugged into a live supply (see Linear Technology Ap-

plication Note 88 for a complete discussion). The low

loss ceramic capacitor combined with stray inductance

in series with the power source forms an under damped

inductive short-circuit is applied to the module’s output,

–

V

OUT

may be briefly dragged above EXTV — forward-

CC

–

biasing the V

-to-EXTV body diode. This resistor

OUT

CC

limits the magnitude of current flow into EXTV . Bypass

CC

–

EXTV to V

with 1μF of X5R (or better) MLCC.

CC

OUT

tank circuit, and the voltage at the V pin of the LTM4651

IN

can ring to twice the nominal input voltage, possibly ex-

ceeding the LTM4651’s rating and damaging the part. If

the input supply is poorly controlled or the user will be

plugging the LTM4651 into an energized supply, the input

network should be designed to prevent this overshoot by

introducing a damping element into the path of current

flow. This is often done by adding an inexpensive elec-

Multiphase Operation

Multiple LTM4651 devices can be paralleled for higher

output current applications. For lowest input and output

voltage and current ripples, it is advisable to synchronize

paralleled LTM4651s to an external clock (within 40%

of the target switching frequency set by f —see Test

SET

Circuit 1). See Figure 34 for an example of a synchroniz-

trolytic bulk capacitor (C ) across the input terminals

INL

ing circuit.

of the LTM4651. The selection criteria for C calls for:

INL

an ESR high enough to damp the ringing; a capacitance

LTM4651modulescanbeparalleledwithoutsynchronizing

circuits:justbeawarethatsomebeat-frequencyripplewill

bepresentintheoutputvoltageandreflectedinputcurrent

by virtue of the fact that such modules are not operating

at identical, synchronized switching frequencies.

value several times larger than C . C does not need

INH INL

to be located physically close to the LTM4651; it should

be located close to the application board’s input connec-

tor, instead.

The LTM4651 device is an inherently current mode con-

trolled device, so parallel modules will have good current

sharing’s shown in Figure 35. This helps balance the

thermals on the design.

INTV and EXTV Connection

CC

When RUN is logic high, an internal low dropout regula-

tor regulates an internal supply, INTV , that powers the

CC

controlcircuitryfordrivingLTM4651’sinternalMOSFETs.

–

To parallel LTM4651s, connect the respective COMPa,

INTV is regulated at 3.3V above V

. In this manner,

CC

OUT

ISETa, and GND

pins of each LTM4651 together to

the LTM4651’s INTV is directly powered from SV , by

SNS

CC

IN

sharethecurrentevenly.Inaddition,tietherespectiveRUN

pins of paralleled LTM4651 devices together, to ensure

proper start-up and shutdown behavior. Figure 34 shows

a schematic of LTM4651 devices operating in parallel.

default. The gate driver current through the LDO is about

20mA for a typical 1MHz application. The internal LDO

power dissipation can be calculated as:

–

P

=20mA •(SV +|V

|–3.3V)

(17)

IN

LDO_LOSS(INTVCC)

OUT

Note that for parallel applications, EQ. 8 becomes:

TheLDOdrawscurrentoffofEXTV insteadofSV when

CC

IN

–

–V_OUT

–

EXTV istiedtoavoltagehigherthan3.2VaboveV

and

R_SET

=

(19)

CC

OUT

–

50µA •N

SV is 5V above V

. For output voltages at or below

IN

OUT

–4V, this pin can be connected to PGND through an RC-

filter. When the internal LDO derives power from EXTV

CC

instead of SV , the internal LDO power dissipation is:

IN

–

P

=20mA •(|V

|–3V)

(18)

LDO_LOSS(EXTVCC)

OUT

4651f

18

For more information www.linear.com/LTM4651

LTM4651

APPLICATIONS INFORMATION

where N is the number of LTM4651 modules in parallel

The motivation for providing these thermal coefficients is

found in JESD51-12 (“Guidelines for Reporting and Using

Electronic Package Thermal Information”).

configuration.

Depending on the duty cycle of operation (EQ. 4), the

outputvoltagerippleachievedbyparalleled, synchronized

LTM4651modulesmaybeconsiderablysmallerthanwhat

isyieldedbyEQ. 7. ApplicationNote77 provides a detailed

explanation of multiphase operation (relevant to parallel

LTM4651 applications) pertaining to noise reduction and

output and input ripple current cancellation. Regardless

of ripple current cancellation, it remains important for the

output capacitance of paralleled LTM4651 applications

to be designed for loop stability and transient response.

LTpowerCAD is available for such analysis.

Many designers may opt to use laboratory equipment

and a test vehicle such as the demo board to predict the

µModule regulator’s thermal performance in their appli-

cation at various electrical and environmental operating

conditions to compliment any FEA activities. Without FEA

software, the thermal resistances reported in the Pin Con-

figurationsectionare,inandofthemselves,notrelevantto

providing guidance of thermal performance; instead, the

derating curves provided in this data sheet can be used

in a manner that yields insight and guidance pertaining to

one’s application-usage, and can be adapted to correlate

thermal performance to one’s own application.

Figure 4 illustrates the RMS ripple current reduction as

a function of the number of interleaved (paralleled and

synchronized) LTM4651 modules—derived from Ap-

plication Note 77.

The Pin Configuration section gives four thermal coeffi-

cients explicitly defined in JESD51-12; these coefficients

are quoted or paraphrased below:

Radiated EMI Noise

1. θ , the thermal resistance from junction to ambient, is

JA

the natural convection junction-to-ambient air thermal

resistance measured in a one cubic foot sealed enclo-

sure. This environment is sometimes referred to as

“still air” although natural convection causes the air to

move. This value is determined with the part mounted

toaJESD51-9definedtestboard,whichdoesnotreflect

an actual application or viable operating condition.

The generation of radiated EMI noise is an inherent disad-

vantageofswitchingregulators.Fastswitchingturn-onand

turn-off of the power MOSFETs—necessary for achieving

high efficiency—create high-frequency (~30MHz+) ∆l/∆t

changes within DC/DC converters. This activity tends to

be the dominant source of high-frequency EMI radiation

in such systems. The high level of device integration

within LTM4651—including optimized gate-driver and

critical front-end � filter inductor—delivers low radiated

EMI noise performance. Figures 5 to 8 show typical ex-

amples of LTM4651 meeting the radiated emission limits

established by EN55022 Class B.

2. θ

, the thermal resistance from junction to the

JCbottom

bottom of the product case, is determined with all of

the component power dissipation flowing through the

bottomofthepackage.InthetypicalµModuleregulator,

the bulk of the heat flows out the bottom of the pack-

age, but there is always heat flow out into the ambient

environment. As a result, this thermal resistance value

may be useful for comparing packages but the test

conditionsdon’tgenerallymatchtheuser’sapplication.

Thermal Considerations and Output Current Derating

The thermal resistances reported in the Pin Configuration

section of this data sheet are consistent with those pa-

rameters defined by JESD51-12 and are intended for use

with finite element analysis (FEA) software modeling tools

that leverage the outcome of thermal modeling, simula-

tion, and correlation to hardware evaluation performed on

a µModule package mounted to a hardware test board.

3. θ

, the thermal resistance from junction to top of

JCtop

the product case, is determined with nearly all of the

4651f

19

For more information www.linear.com/LTM4651

LTM4651

APPLICATIONS INFORMATION

0.60

1-PHASE

2-PHASE

0.55

3-PHASE

4-PHASE

6-PHASE

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9

–

DUTY CYCLE (–V

/ V – V )

IN OUT

OUT

4651 F04

Figure 4. Normalized Input RMS Ripple Current vs Duty Cycle for One to Six LTM4651s (Phases)

70

60

50

40

30

20

10

0

70

MEAS DIST 10m

SPEC DIST 10m

MEAS DIST 10m

SPEC DIST 10m

60

50

40

30

20

10

0

[1] HORIZONTAL

[2] VERTICAL

QPK LIMIT

[1] HORIZONTAL

[2] VERTICAL

QPK LIMIT

+

FORMAL

–10

30

130 230 330 430 530 630 730 830 930 1000

30

130 230 330 430 530 630 730 830 930 1000

4651 F06

4651 F05

FREQUENCY (MHz)

Figure 5. Radiated Emissions Scan of the LTM4651. Producing

–24V_OUTat 1A, from 12V_IN. DC2328A Hardware. f_SW= 1.2MHz.

Measured in a 10m Chamber. Peak Detect Method

Figure 6. Radiated Emissions Scan of the LTM4651 Producing

–24V_OUTat 2A, from 25V_IN. DC2328 Hardware. f_SW= 1.2MHz.

Measured in a 10m Chamber. Peak Detect Method

70

MEAS DIST 10m

SPEC DIST 10m

60

50

40

30

20

10

0

60

SPEC DIST 10m

50

40

30

20

10

0

[1] HORIZONTAL

[2] VERTICAL

QPK LIMIT

[1] HORIZONTAL

[2] VERTICAL

QPK LIMIT

+

FORMAL

–10

30

130 230 330 430 530 630 730 830 930 1000

30

130 230 330 430 530 630 730 830 930 1000

4651 F07

4651 F08

FREQUENCY (MHz)

Figure 7. Radiated Emissions Scan of the LTM4651. Producing

–24V_OUTat 2A, from 34V_IN. DC2328A Hardware. f_SW= 1.2MHz.

Measured in a 10m Chamber. Peak Detect Method

Figure 8. Radiated Emissions Scan of the LTM4651. Producing

–12V_OUTat 2A, from 12V_IN. DC2328A Hardware. f_SW= 700kHz.

Measured in a 10m Chamber. Peak Detect Method

4651f

20

For more information www.linear.com/LTM4651

LTM4651

APPLICATIONS INFORMATION

componentpowerdissipationflowingthroughthetopof

the package. As the electrical connections of the typical

µModule regulator are on the bottom of the package, it

is rare for an application to operate such that most of

the heat flows from the junction to the top of the part.

exclusively through the top or exclusively through bot-

tom of the µModule package—as the standard defines

for θ

and θ

, respectively. In practice, power

JCtop

JCbottom

loss is thermally dissipated in both directions away from

the package—granted, in the absence of a heat sink and

airflow, a majority of the heat flow is into the board.

As in the case of θ

, this value may be useful

JCbottom

for comparing packages but the test conditions don’t

generally match the user’s application.

Within the LTM4651, be aware there are multiple power

devices and components dissipating power, with a con-

sequence that the thermal resistances relative to different

junctions of components or die are not exactly linear with

respect to total package power loss. To reconcile this

complicationwithoutsacrificingmodelingsimplicity—but

alsonotignoringpracticalrealities—anapproachhasbeen

taken using FEA software modeling along with laboratory

testing in a controlled-environment chamber to reason-

ably define and correlate the thermal resistance values

supplied in this data sheet: (1) Initially, FEA software is

used to accurately build the mechanical geometry of the

LTM4651 and the specified PCB with all of the correct

material coefficients along with accurate power loss

source definitions; (2) this model simulates a software-

definedJEDECenvironmentconsistentwithJESD51-9and

JESD51-12topredictpowerlossheatflowandtemperature

readings at different interfaces that enable the calculation

of the JEDEC-defined thermal resistance values; (3) the

model and FEA software is used to evaluate the LTM4651

with heat sink and airflow; (4) having solved for and

analyzed these thermal resistance values and simulated

various operating conditions in the software model, a

thorough laboratory evaluation replicates the simulated

4. θ , the thermal resistance from junction to the printed

JB

circuit board, is the junction-to-board thermal resis-

tance where almost all of the heat flows through the

bottom of the µModule regulator and into the board,

and is really the sum of the θ

and the thermal

JCbottom

resistance of the bottom of the part through the solder

joints and through a portion of the board. The board

temperature is measured a specified distance from the

package, using a two sided, two layer board. This board

is described in JESD51-9.

A graphical representation of the aforementioned ther-

mal resistances is given in Figure 9; blue resistances are

contained within the µModule regulator, whereas green

resistances are external to the µModule package.

As a practical matter, it should be clear to the reader that

no individual or sub-group of the four thermal resistance

parameters defined by JESD51-12 or provided in the

Pin Configuration section replicates or conveys normal

operating conditions of a µModule regulator. For example,

in normal board-mounted applications, never does 100%

of the device’s total power loss (heat) thermally conduct

JUNCTION-TO-AMBIENT THERMAL RESISTANCE COMPONENTS

JUNCTION-TO-CASE (TOP)

RESISTANCE

CASE (TOP)-TO-AMBIENT

RESISTANCE

JUNCTION-TO-BOARD RESISTANCE

JUNCTION

AMBIENT

JUNCTION-TO-CASE

(BOTTOM) RESISTANCE

CASE (BOTTOM)-TO-BOARD

RESISTANCE

BOARD-TO-AMBIENT

RESISTANCE

4651 F09

µModule DEVICE

Figure 9. Graphical Representation of JESD51-12 Thermal Coefficients

4651f

21

For more information www.linear.com/LTM4651

LTM4651

APPLICATIONS INFORMATION

conditions with thermocouples within a controlled envi-

ronment chamber while operating the device at the same

power loss as that which was simulated. The outcome of

this process and due diligence yields the set of derating

curves provided in later sections of this data sheet, along

withwell-correlatedJESD51-12-definedθvaluesprovided

in the Pin Configuration section of this data sheet.

temperaturerisecanbeallowed.AsanexampleinFigure26,

the load current is derated to 1A at 60°C ambient with

200LFMairflowandnoheatsinkandtheroomtemperature

(25°C) power loss for this 12V to –24V

at 1A out

IN

OUT

conditionis3.55W.A3.9Wlossiscalculatedbymultiplying

the 3.55W room temperature loss from the 12V to

IN

–24V

power loss curve at 1A (Figure 12), with the 1.1

OUT

multiplying factor at 60°C ambient (from Table 2). If the

60°C ambient temperature is subtracted from the 120°C

junction temperature, then the difference of 60°C divided

The –5V, –15V and –24V power loss curves in Figures 10,

11 and 12 respectively can be used in coordination with

the load current derating curves in Figures 13 to 30 for

by 3.9W yieldsathermalresistance, θ , of15.4°C/W—in

JA

calculating an approximate θ thermal resistance for the

JA

good agreement with Table 4. Tables 3, 4 and 5 provide

equivalent thermal resistances for –5V, –15V and –24V

outputs with and without air flow and heat sinking. The

derived thermal resistances in Tables 3, 4 and 5 for the

various conditions can be multiplied by the calculated

power loss as a function of ambient temperature to

derive temperature rise above ambient, thus maximum

junction temperature. Room temperature power loss

can be derived from the efficiency curves in the Typical

Performance Characteristics section and adjusted with

ambient temperature multiplicative factors from Table 2.

LTM4651 withvariousheatsinkingandairflowconditions.

These thermal resistances represent demonstrated

performance of the LTM4651 on DC2328A hardware; a

4-layerFR4PCBmeasuring99mm×133mm ×1.6mm using

outerandinnercopperweightsof2ozand1oz,respectively.

The power loss curves are taken at room temperature,

and are increased with multiplicative factors with ambient

temperature.TheseapproximatefactorsarelistedinTable2.

(Compute the factor by interpolation, for intermediate

temperatures.) The derating curves are plotted with the

LTM4651’s output initially sourcing its maximum output

capability(seeEq.5)andtheambienttemperatureat30°C.

The output voltages are –5V, –15V and –24V. These are

chosen to include the lower and higher output voltage

ranges for correlating the thermal resistance. In all derat-

ing curves, the switching frequency of operation follows

guidanceprovidedbyTable1. Thermalmodelsarederived

from several temperature measurements in a controlled

temperaturechamberalongwiththermalmodelinganalysis.

The junction temperatures are monitored while ambient

temperatureisincreasedwithandwithoutairflow,andwith

andwithoutaheatsinkattachedwiththermallyconductive

adhesive tape. The power loss increase with ambient

temperature change is factored into the derating curves.

The junctions are maintained at 120°C maximum while

loweringoutputcurrentorpowerwhileincreasingambient

temperature. The decreased output current decreases the

internal module loss as ambient temperature is increased.

The monitored junction temperature of 120°C minus the

ambientoperatingtemperaturespecifieshowmuchmodule

Table 2. Power Loss Multiplicative Factors vs Ambient

Temperature

POWER LOSS MULTIPLICATIVE

AMBIENT TEMPERATURE

FACTOR

1.00

1.05

1.10

1.15

1.20

1.25

1.30

1.35

1.40

Up to 40°C

50°C

60°C

70°C

80°C

90°C

100°C

110°C

120°C

4651f

22

For more information www.linear.com/LTM4651

LTM4651

APPLICATIONS INFORMATION

Table 3. –5V Output

DERATING CURVE

Figures 13, 14, 15

Figures 16, 17, 18

V

(V)

POWER LOSS CURVE

Figure 10

AIRFLOW (LFM)

HEAT SINK

None

θ

(°C/W)

JA

IN

5, 12, 24

0

20.8

17.0

16.3

18.7

16.1

14.2

Figure 10

200

400

0

None

Figure 10

None

Figure 10

BGA Heat Sink

Figure 10

200

400

Figure 10

Table 4. –15V Output

DERATING CURVE

Figures 19, 20, 21

Figures 22, 23, 24

V

(V)

POWER LOSS CURVE

Figure 11

AIRFLOW (LFM)

HEAT SINK

None

θ

(°C/W)

JA

IN

5, 12, 24

0

20.0

16.6

14.4

19.0

14.2

12.6

Figure 11

200

400

0

None

Figure 11

None

Figure 11

BGA Heat Sink

Figure 11

200

400

Figure 11

Table 5. –24V Output

DERATING CURVE

Figures 25, 26, 27

Figures 28, 29, 30

V

(V)

POWER LOSS CURVE

Figure 12

AIRFLOW (LFM)

HEAT SINK

None

θ

(°C/W)

JA

IN

5, 12, 24

0

18.3

15.2

14.4

17.6

14.7

13.9

Figure 12

200

400

0

None

Figure 12

None

Figure 12

BGA Heat Sink

Figure 12

200

400

Figure 12

Table 6. Heat Sink Manufacturer (Thermally Conductive Adhesive Tape Pre-Attached)

HEAT SINK MANUFACTURER

PART NUMBER

WEBSITE

Cool Innovations

3-0504035UT411

www.coolinnovations.com

Table 7. Thermally Conductive Adhesive Tape Vendor

THERMALLY CONDUCTIVE ADHESIVE

TAPE MANUFACTURER

PART NUMBER

WEBSITE

Chomerics

T411

www.chomerics.com

4651f

23

For more information www.linear.com/LTM4651

LTM4651

APPLICATIONS INFORMATION

Table 8. LTM4651 Output Voltage Response vs Component Matrix. Performance of Figure 32 Circuit with Values Here Indicated,

COMPa Connected to COMPb, C_EXTVCC= 1μF, and the Following Components Not Used: C_TH, R_THand C_OUTL. Load-Stepping from 50%

of Full Scale (F.S.) to 100% of F.S. Load Current, in 1μs. Typical Measured Values

C

OUTH

VENDORS

PART NUMBER

C

IN

/C VENDORS

PART NUMBER

D

AVX

12066D107MAT2A (100µF, 6.3V, 1206 Case Size)

GRM31CR60J107M (100µF, 6.3V, 1206 Case Size)

JMK316BBJ107MLHT (100µF, 6.3V, 1206 Case Size)

C3216X5R0J107M (100µF, 6.3V, 1206 Case Size)

1210YD476MAT2A (47µF, 16V, 1210 Case Size)

GRM32ER61C476M (47µF, 16V, 1210 Case Size)

EMK325BJ476MM (47µF, 16V, 1210 Case Size)

12103D226MAT2A (22µF, 25V, 1210 Case Size)

TMK325BJ226MM (22µF, 25V, 1210 Case Size)

C3225X5R1E226M (22µF, 25V, 1210 Case Size)

12105D106MAT2A (10µF, 50V, 1210 Case Size)

GRM32ER61H106M (10µF, 50V, 1210 Case Size)

UMK325BJ106M (10µF, 50V, 1210 Case Size)

C3225X5R1H106M (10µF, 50V, 1210 Case Size)

Murata

AVX

GRM32ER71K475M (4.7µF, 80V, 1210 Case Size)

12065C475MAT2A (4.7µF, 50V, 1206 Case Size)

GRM31CR71H475M (4.7µF, 50V, 1206 Case Size)

UMK316AB7475ML (4.7µF, 50V, 1206 Case Size)

C3216X5R1H475M (4.7µF, 50V, 1206 Case Size)

Murata

Taiyo Yuden

TDK

Murata

Taiyo Yuden

TDK

AVX

Murata

Taiyo Yuden

AVX

Taiyo Yuden

TDK

AVX

Murata

Taiyo Yuden

TDK

LOAD STEP LOAD STEP

F. S.

C

–

C

CDGND

–

C

TRANSIENT

DROOP

(mV)

PK-PK

DEVIATION

(mV)

RECOVERY

TIME

IN

INOUT

D

OUTH

(CERAMIC

–

V

OUT

(V)

V

LOAD (V TO GND

(V TO V

(V TO GND

D

R

f

R

IN

(V)

IN

OUT

D

OUT

ISET

PGDFB

(kΩ) (kHz) (kΩ)

SW

fSET

EXTVCC

(Ω)

(A)

3.2

4

BYPASS CAP)

4.7µF

BYPASS CAP)

4.7µF

BYPASS CAP) BYPASS CAP) OUTPUT CAP) (kΩ)

(μs)

–0.5

5

4.7µF

4.7µF × 2

4.7µF

4.7µF × 2

100µF × 4

100µF

10

N/A

400

N/A

2.2

75

150

190

130

330

355

310

300

235

340

380

360

330

235

340

330

400

370

270

290

325

400

170

380

400

415

220

275

280

55

60

25

50

40

35

45

60

55

45

38

30

27

25

32

25

32

28

45

30

27

12

90

–0.5* 24

4

10

200* N/A

2.2

90

–3.3

–5

5

2.2

3.5

4

66.5

100

160

240

301

481

22.6

36.5

61.9

95.3

121

400

N/A

15

65

12

24

36

48

5

100µF × 2

47µF × 2

47µF

15

165

175

160

152

125

175

185

180

165

125

185

180

205

185

140

157

170

200

90

450 2200

500 1000

15

4

15

4

15

1.75

3.2

3.85

4

400

550

600

N/A

665

499

20

–5

12

24

36

48

5

20

–5

20

–5

20

–5

4

20

–8

1.2

2.3

3.1

3.4

3.6

0.9

1.9

2.75

3.2

0.75

1.75

2.5

3

450 2200

32.4

49.9

60.4

100

–8

12

24

36

48

5

47µF

700

800

850

900

332

249

221

200

–8

47µF

–8

47µF

–8

47µF

–12

–15

–24

22µF

475 1300

825 237

12

24

36

5

22µF

1100 143

1200 124

500 1000

22µF

12

24

36

5

22µF

121

875

210

200

205

210

105

140

22µF

121

1200 124

1400 100

22µF

121

0.55

1.25

2

10µF × 2

196

550

665

12

24

196

1000 165

1500 90.9

196

*To avoid violating minimum on-time criteria, drive CLKIN with a 200kHz, 50% duty cycle clock. Consider using LTC6908-1, for example.

4651f

24

For more information www.linear.com/LTM4651

LTM4651

See Table 1 for f_SW.

APPLICATIONS INFORMATION—DERATING CURVES

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

5V , 400kHz

IN

5V , 500kHZ

IN

12V , 550kHz

IN

5V , 550kHz

IN

12V , 875HZ

IN

24V , 600kHz

IN

12V , 1MHz

IN

24V , 1.2MHZ

IN

36V , 1.4MHZ

IN

36V , 600kHz

IN

24V ,1.5MHz

IN

48V , 600kHz

IN

0

0.5

1

1.5

2

2.5

3

3.5

4

0

0.5

1

1.5

2

0

0.5

1

1.5

2

2.5

3

LOAD CURRENT (A)

4651 F10

4651 F12

4651 F11

Figure 10. –5V_OUTPower

Loss Curve

Figure 11. –15V_OUTPower Loss

Curve

Figure 12. –24V_OUTPower

Loss Curve

3.2

2.8

2.4

2.0

1.6

1.2

0.8

0.4

0

3.85

3.50

3.15

2.80

2.45

2.10

1.75

1.40

1.05

0.70

0.35

0

1.75

1.50

1.25

1.00

0.75

0.50

0.25

0

0LFM

200LFM

400LFM

0LFM

200LFM

400LFM

0LFM

200LFM

400LFM

20

40

60

80

100

120

20

40

60

80

100

120

20

40

60

80

100

120

AMBIENT TEMPERATURE (°C)

4651 F14

4651 F15

4651 G13

Figure 13. 5V to –5V Derating

Curve, No Heat Sink

Figure 14. 12V to –5V

Derating Curve, No Heat Sink

Figure 15. 24V to –5V

Derating Curve, No Heat Sink

3.85

3.50

3.15

2.80

2.45

2.10

1.75

1.40

1.05

0.70

0.35

0

3.2

2.8

2.4

2.0

1.6

1.2

0.8

0.4

0

1.75

1.53

1.31

1.09

0.88

0.66

0.44

0.22

0

0LFM

200LFM

400LFM

0LFM

200LFM

400LFM

0LFM

200LFM

400LFM

20

40

60

80

100

120

20

40

60

80

100

120

20

40

60

80

100

120

AMBIENT TEMPERATURE (°C)

4651 F18

4651 F17

4651 F16

Figure 17. 12V to –5V Derating

Curve, with BGA Heat Sink

Figure 16. 5V to –5V Derating

Curve, with BGA Heat Sink

Figure 18. 24V to –5V Derating

Curve, with BGA Heat Sink

4651f

25

For more information www.linear.com/LTM4651

LTM4651

See Table 1 for f_SW.

APPLICATIONS INFORMATION—DERATING CURVES

2.50

2.25

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

0

1.75

1.50

1.25

1.00

0.75

0.50

0.25

0

0.750

0.625

0.500

0.375

0.250

0.125

0

0LFM

200LFM

400LFM

0LFM

200LFM

400LFM

0LFM

200LFM

400LFM

20

40

60

80

100

120

20

40

60

80

100

120

20

40

60

80

100

120

AMBIENT TEMPERATURE (°C)

4651 F21

4651 F20

4651 F19

Figure 19. 5V to –15V

Derating Curve, No Heat Sink

Figure 20. 12V to –15V

Derating Curve, No Heat Sink

Figure 21. 24V to –15V Derating

Curve, No Heat Sink

1.75

1.50

1.25

1.00

0.75

0.50

0.25

0

2.50

2.25

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

0

0.750

0.625

0.500

0.375

0.250

0.125

0

0LFM

200LFM

400LFM

0LFM

200LFM

400LFM

0LFM

200LFM

400LFM

20

40

60

80

100

120

20

40

60

80

100

120

20

40

60

80

100

120

AMBIENT TEMPERATURE (°C)

4651 F23

4651 F24

4651 F22

Figure 24. 24V to –15V Derating

Curve, with BGA Heat Sink

Figure 22. 5V to –15V Derating

Curve, with BGA Heat Sink

Figure 23. 12V to –15V Derating

Curve, with BGA Heat Sink

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

0

0.55

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

1.250

1.125

1.000

0.875

0.750

0.625

0.500

0.375

0.250

0.125

0

0LFM

200LFM

400LFM

0LFM

200LFM

400LFM

0LFM

200LFM

400LFM

20

40

60

80

100

120

20

40

60

80

100

120

20

40

60

80

100

120

AMBIENT TEMPERATURE (oC)

AMBIENT TEMPERATURE (°C)

4651 F27

4651 F25

4651 F26

Figure 26. 12V to –24V Derating

Curve, No Heat Sink

Figure 27. 24V to –24V Derating

Curve, No Heat Sink

Figure 25. 5V to –24V Derating

Curve, No Heat Sink

4651f

26

For more information www.linear.com/LTM4651

LTM4651

APPLICATIONS INFORMATION—DERATING CURVES

1.250

1.125

1.000

0.875

0.750

0.625

0.500

0.375

0.250

0.125

0

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

0

0.55

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

0LFM

200LFM

400LFM

0LFM

200LFM

400LFM

0LFM

200LFM

400LFM

20

40

60

80

100

120

20

40

60

80

100

120

20

40

60

80

100

120

AMBIENT TEMPERATURE (°C)

4651 F29

4651 F30

4651 F28

Figure 29. 12V to –24V Derating

Curve, with BGA Heat Sink

Figure 30. 24V to –24V Derating

Curve, with BGA Heat Sink

Figure 28. 5V to –24V Derating

Curve, with BGA Heat Sink

APPLICATIONS INFORMATION

Safety Considerations

• Place high frequency ceramic input and output (and, if

used, input-to-output) capacitors next to the V , V ,

IN

D

TheLTM4651doesnotprovidegalvanicisolationfromV

IN

–

PGNDandV

pinstominimizehighfrequencynoise.

–

OUT

to V

. There is no internal fuse. If required, a slow blow

OUT

fuse with a rating twice the maximum input current needs

tobeprovidedtoprotecttheunitfromcatastrophicfailure.

• Place a dedicated power ground layer underneath the

LTM4651.

The fuse or circuit breaker, if used, should be selected to

• Tominimizetheviaconductionlossandreducemodule

thermal stress, use multiple vias for interconnection

between top layer and other power layers.

limit the current to the regulator in case of a M MOSFET

T

fault. If M fails, the system’s input supply will source

T

very large currents to PGND through M . This can cause

T

• Do not put vias directly on pads, unless they are capped

or plated over.

excessive heat and board damage depending on how

much power the input voltage can deliver to this system.

A fuse or circuit breaker can be used as a secondary fault

protector in this situation. The LTM4651 does feature

overcurrent and overtemperature protection.

–

• Use a separate SV

copper plane for components

OUT

–

connected to signal pins. Connect SV

directly under the module.

to V

OUT

–

• For parallel module applications, connect the V

,

OUT

Layout Checklist/Example

GND ,RUN,ISETa,COMPaandPGOODpinstogether

SNS

The high integration of LTM4651 makes the PCB board

layout straightforward. However, to optimize its electrical

and thermal performance, some layout considerations

are still necessary.

as shown in Figure 41.

• Bring out test points on the signal pins for monitoring.

Figure 31 gives a good example of the recommended

LTM4651 layout.

• Use large PCB copper areas for high current paths,

–

including V , PGND and V

. Doing so helps to

IN

OUT

minimize the PCB conduction loss and thermal stress.

4651f

27

For more information www.linear.com/LTM4651

LTM4651

APPLICATIONS INFORMATION

GND

–

V

OUT

V

D

V

IN

GND

4650 F31

Figure 31. Recommend PCB Layout, Package Top View

TYPICAL APPLICATIONS

R

100k

PGDFB

V

IN

3.3V

V

PGOOD

IN

12V

C

4.7μF

C

4.7μF

IN

INOUT

SV

GND

SNS

IN

GND

V

D

C

10µF

×2

PGND

OUT

D1*

RUN

LOAD

C

DGND

–

–24V

OUT

V

OUT

CLKIN

INTV

4.7μF

UP TO 1.25A

LTM4651

C

4.7μF

–

D

SV

CC

OUT

R

PGDFB

196k

VINREG

COMPa

COMPb

PGDFB

R

100Ω

EXTVCC

EXTV

CC

+

TEMP

f

SET

–

ISETa

ISETb

C

1µF

EXTVCC

4651 F32

R

165k

fSET

R

ISET

481k

*D1 optional (see effect in Figure 33): Central Semiconductor P/N CMMSH1-40L

Figure 32. 1.25A, –24V Output DC/DC μModule Regulator

4651f

28

For more information www.linear.com/LTM4651

LTM4651

TYPICAL APPLICATIONS

RUN, 5V/DIV

PGOOD, 5V/DIV

–

V

OUT

10V/DIV

–

V

OUT

200mV/DIV

4651 F33a

1ms/DIV

(a) Start-up Performance with D1 Not Installed.

–

V

Reverse-Polarity at Start-Up Transiently

OUT

Reaches 500mV

RUN, 5V/DIV

PGOOD, 5V/DIV

–

V

OUT

10V/DIV

–

V

OUT

200mV/DIV

4651 F33b

1ms/DIV

(b) Start-up Performance with D1 Installed.

–

V

Reverse-Polarity at Start-Up is Transiently

OUT

Limited to 360mV

Figure 33. Start-Up Waveforms at 12V_IN, Figure 32 Circuit

4651f

29

For more information www.linear.com/LTM4651

LTM4651

TYPICAL APPLICATIONS

R

PGDFB

100k

V

IN

24V

3.3V

V

PGOOD

IN

C

4.7μF

IN1

SV

GND

SNS

IN

C

INOUT1

4.7μF

GND

V

D

PGND

C

10µF

×4

C

OUT

DGND1

4.7μF

LTC6908-1

C

4.7μF

RUN

LOAD

D1

3.3V

–24V

OUT

UP TO 4A

–

+

V

OUT

V

OUT1

OUT2

MOD

CLKIN

INTV

R

SET

66.5k

U1

LTM4651

–

SV

OUT

CC

R

SET

PGDFB1

196k

VINREG

COMPa

COMPb

R

EXTVCC1

100Ω

PGDFB

GND

EXTV

CC

+

TEMP

C

EXTVCC1

1µF

f

–

SET

ISETa

ISETb

R

fSET1

90.9k

V

PGOOD

IN

C

4.7μF

IN2

SV

GND

SNS

IN

GND

C

INOUT2

4.7μF

V

D

PGND

C

DGND2

4.7μF

C

4.7μF

D2

RUN

–

V

CLKIN

INTV

OUT

U2

LTM4651

–

SV

CC

OUT

R

PGDFB2

196k

VINREG

COMPa

COMPb

R

100Ω

EXTVCC2

PGDFB

EXTV

CC

+

f

TEMP

SET

C

EXTVCC2

1µF

–

ISETa

ISETb

4651 F34

R

fSET2

90.9k

R

ISET2

240k

Figure 34. –24V Output at Up to 4A from 24V Input, 2-Phase Interleaved, Parallel Application at f_SW= 1.5MHz

4651f

30

For more information www.linear.com/LTM4651

LTM4651

TYPICAL APPLICATIONS

2.25

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

0

U1 OUTPUT CURRENT

U2 OUTPUT CURRENT

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

LOAD CURRENT (A)

4651 F35

Figure 35. Current Sharing Performance of LTM4651s in Figure 34 Circuit

RUN, 5V/DIV

PGOOD, 5V/DIV

+

V

OUT

5V/DIV

–

V

OUT

5V/DIV

4651 F36

10ms/DIV

Figure 36. Concurrent 12V Supply, Output Voltage Start-Up Waveforms. Figure 37 Circuit

4651f

31

For more information www.linear.com/LTM4651

LTM4651

PACKAGE PHOTOGRAPH

PACKAGE DESCRIPTION

Table 9. LTM4651 Component BGA Pinout

PIN ID

A1

FUNCTION

PIN ID

B1

FUNCTION

CLKIN

NC

PIN ID

C1

FUNCTION

PIN ID

D1

FUNCTION

PGOOD

PGDFB

PIN ID

E1

FUNCTION

COMPb

PIN ID

F1

FUNCTION

ISETb

V

IN

V

IN

V

IN

NC

–

A2

B2

C2

V

D2

E2

COMPa

F2

ISETa

OUT

A3

B3

V

C3

SV

D3

VINREG

E3

f

F3

EXTV

CC

IN

SET

–

A4

V

D

B4

V

D

C4

V

D

D4

GND

E4

SV

OUT

F4

RUN

–

A5

V

B5

V

C5

V

D5

V

OUT

E5

V

F5

V

OUT

A6

NC

B6

NC

C6

NC

D6

NC

E6

NC

F6

NC

A7

NC

B7

NC

C7

NC

D7

NC

E7

NC

F7

NC

PIN ID

G1

FUNCTION

PIN ID

H1

FUNCTION

PIN ID

J1

FUNCTION

PIN ID

K1

FUNCTION

PGND

PIN ID

L1

FUNCTION

PGND

+

GND

TEMP

SNS

–

SNS

–

G2

SV

H2

SV

OUT

J2

TEMP

K2

PGND

L2

PGND

OUT

–

G3

INTV

H3

V

J3

V

K3

PGND

L3

PGND

CC

–

OUT

–

G4

V

H4

SW

J4

K4

V

L4

V

OUT

–

G5

H5

V

OUT

J5

K5

L5

OUT

+

–

G6

NC

H6

NC

J6

TEMP

K6

NC

L6

NC

G7

NC

H7

NC

J7

K7

NC

L7

NC

4651f

32

For more information www.linear.com/LTM4651

LTM4651

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/product/LTM4651#packaging for the most recent package drawings.

Z

/ / b b b

Z

3 . 8 1 0

2 . 5 4 0

1 . 2 7 0

0 . 3 1 7 5

1 . 2 7 0

0 . 0 0 0

2 . 5 4 0

3 . 8 1 0

4651f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

33

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

For more information www.linear.com/LTM4651

LTM4651

TYPICAL APPLICATION

PULL-UP SUPPLY ≤ 5V

V

IN

22V TO 36V

C1 TO C3

10µF

50V

R4

51k

R3

51k

×3

V

PLLIN

D

IN

+

V

OUT

12V

V

OUT

PGOOD

RUN

COMP

INTV

DRV

C5

C

47µF

×4

OUT1

UP TO 8A

22pF

V

C

10µF

50V

FB

IN1

LTM4613

R

FB

5.23k

CC

FCB

MARG0

MARG1

MPGM

f

MARGIN

CONTROL

SET

TRACK/SS

C4

0.1µF

SGND

PGND

R1

392k

5% MARGIN

V

PGOOD

GND

IN

C

4.7μF

IN2

SV

IN

SNS

V

D

GND

C

DGND

4.7μF

C

D

4.7μF

INOUT

4.7μF

PGND

C

OUT2

22µF

LOAD

RUN

–

V

OUT

V

OUT

–12

CLKIN

LTM4651

–

UP TO 3.15A

SV

OUT

INTV

CC

R

PGDFB

95.3k

VINREG

COMPa

COMPb

PGDFB

R

EXTVCC

49.9Ω

TRACK

10k

EXTV

CC

+

TEMP

–

f

SET

ISETa

R

ISETb

4651 F37

R

fSET

124k

C

EXTVCC

1µF

ISET

240k||10k

Figure 37. Concurrent 1ꢀ2 ꢁupplꢂ. ꢁee Figure 36 for Output 2oltage ꢁtart-Up Waveforms

RELATED PARTS

PART NUMBER DEꢁCRIPTION

COMMENTꢁ

LTM8045

SEPIC or Inverting µModule DC/DC Converter

2.8V ≤ V ≤ 18V, 2.5V ≤ V

≤ 15V. I

≤ 24V. I

≤ 700mA. 6.25mm ×

≤ 1A/Channel. 9mm ×

IN

OUT

OUT(DC)

11.25mm × 4.92mm BGA

LTM8049

Dual, SEPIC and/or Inverting µModule DC/DC Converter 2.6V ≤ V ≤ 20V, 2.5V ≤ V

IN

OUT

OUT(DC)

15mm × 2.42mm BGA

LTM8073

LTM8064

LTM4613

60V, 3A Step-Down µModule Regulator

3.4V ≤ V ≤ 60V, 0.8V ≤ V

≤ 15V. 6.25mm × 9mm × 3.32mm BGA

IN

OUT

58V, 6A CVCC Step-Down µModule Regulator

EN55022B Compliant, 36V, 8A µModule Regulator

6V ≤ V ≤ 58V, 1.2V ≤ V

≤ 36V. 11.9mm x 16mm × 4.92mm BGA

≤ 15V. 15mm × 15mm × 4.32mm LGA, and

IN

OUT

5V ≤ V ≤ 36V, 3.3V ≤ V

IN

OUT

15mm × 15mm × 4.92mm BGA

4651f

LT 0817 • PRINTED IN USA

www.linear.com/LTM4651

34

For more information www.linear.com/LTM4651

 LINEAR TECHNOLOGY CORPORATION 2017


型号：	LTM4651IY#PBF
厂家：	Linear
描述：	LTM4651 - EN55022B Compliant 58V, 24W Inverting-Output DC/DC µModule Regulator; Package: BGA; Pins: 77; Temperature Range: -40°C to 85°C 开关
文件：	总34页 (文件大小：1301K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTM4651IY#PBF [Linear]

相关型号：

LTM4653

LTM4655

LTM4655IY

LTM4655MPY

LTM4656

LTM4656-1

LTM4656EY

LTM4656EY-1

LTM4656IY

LTM4656IY-1

LTM4657

LTM4657IY