LTM4653_技术文档

LTM4653

EN55022B Compliant 58V, 4A

Step-Down DC/DC μModule Regulator

FEATURES

DESCRIPTION

The LTM^®4653 is an ultralow noise 58V, 4A DC/DC step-

down μModule^®regulator designed to meet the radiated

emissions requirements of EN55022. Conducted emis-

sion requirements can be met by adding standard filter

components. Included in the package are the switching

controller, power MOSFETs, inductor, filters and support

components.

n

Complete Low EMI Switch Mode Power Supply

EN55022 Class B Compliant

Wide Input Voltage Range: 3.1V to 58V

Up to 4A Output Current

Output Voltage Range: 0.5V ≤ V

n

≤ 0.94 • V

OUT

IN

1.ꢀ67 Total DC Output Voltage Error Over Line,

Load and Temperature (–40°C to 125°C)

Parallel and Current Share with Multiple LTM4ꢀ53s

Analog Output Current Indicator

n

Operating over an input voltage range of 3.1V to 58V, the

LTM4653 supports an output voltage range of 0.5V to

Programmable Input Voltage Limiting

94% of V , and a switching frequency range of 250kHz

IN

Constant-Frequency Current Mode Control

Power Good Indicator and Programmable Soft-Start

Overcurrent/Overvoltage/Overtemperature Protection

15mm × 9mm × 5.01mm BGA Package

to 3MHz (400kHz default), each set by a single resistor.

For high load currents, the LTM4653 can be paralleled in

PolyPhase^®operation and synchronized to an external

clock. Only the bulk input and output filter capacitors are

needed to finish the design.

APPLICATIONS

The LTM4653 is offered in a 15mm × 9mm × 5.01mm

BGApackagewithSnPborRoHScompliantterminalfinish.

All registered trademarks and trademarks are the property of their respective owners. Protected

by U.S. Patents, including 5481178, 5705919, 5847554, 6580258.

n

Avionics, Industrial Control and Test Equipment

n

Video, Imaging and Instrumentation

n

48V Telecom and Network Power Supplies

RF Systems

n

TYPICAL APPLICATION

4A, 24V Output Low EMI DC/DC μModule Regulator

with Analog Output Current Indicator

Radiated Emission Scan in a 10m Chamber

LTM4ꢀ53 Delivering 24V_OUTat 3.5A, from 48V_IN

I

ꢓ0

OUT

V

24V

,

IN

ꢁꢈꢀꢨ ꢇꢄꢨꢅ ꢗ0ꢏ

ꢨꢂꢈꢜ ꢇꢄꢨꢅ ꢗ0ꢏ

OUT

V

OUT

IN

28V TO 58V

UP TO 4A

10µF

×2

ꢒ0

ꢑ0

ꢔ0

ꢕ0

ꢖ0

ꢗ0

0

4.7μF

V

OSNS

SV

IN

LOAD

V

D

SGND

PGND

RUN

INTV

CC

LTM4653

VINREG

COMPa

ANALOG OUTPUT

ꢣꢗꢤ ꢞꢥRꢄꢦꢥꢛꢅꢀꢃ

ꢣꢖꢤ ꢍꢈRꢅꢄꢜꢀꢃ

ꢚꢂꢧ ꢃꢄꢁꢄꢅ

IMONa

IMONb

CURRENT INDICATOR

10nF

V

= 0.25Ω • I

IMON

OUT

ꢩ

499Ω

ꢙꢥRꢁꢀꢃ

f

ꢘꢗ0

SET

PINS NOT USED IN

THIS CIRCUIT:

ꢕ0

ꢗꢕ0

ꢖꢕ0

ꢕꢕ0

ꢔꢕ0

ꢑꢕ0

ꢒꢕ0

ꢓꢕ0

ꢠꢕ0

ꢡꢕ0 ꢗ000

124k

GND

ISETa ISETb

ꢔꢒꢑꢕ ꢅꢀ0ꢗꢢ

ꢙRꢈꢚꢆꢈꢛꢜꢝ ꢉꢁꢞꢟꢐ

CLKIN, PGOOD, COMPb

PGDFB, SW, EXTV

4653 TA01a

CC

+

–

TEMP , TEMP , NC

481k

Rev 0

1

Document Feedback

For more information www.analog.com

LTM4653

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

(Note 1) (All Voltages Relative to V_OUT^–Unless Otherwise Indicated)

ꢏꢐꢑ ꢒꢓꢅꢔ

Terminal Voltages

ꢀ

ꢌ

ꢍ

ꢎ

ꢙ

ꢞ

ꢕ

V , V , SV , SW, V , V , ISETa....–0.3V to 60V

ꢒ

IN

D

IN

OUT OSNS

ꢓꢗ

ꢁ

ꢂ

GND, ISETb, EXTV ............................ –0.3V to 28V

CC

ꢒ

ꢃꢋꢊꢓꢗ

ꢗꢃ

ꢄ

RUN.................................... GND–0.3V to PGND+60V

ꢑꢇꢗꢄ

INTV , PGDFB, VINREG, COMPa, COMPb,

ꢓꢠꢐꢗꢦ ꢓꢠꢐꢗꢢ ꢣꢒ

CC

ꢓꢗ

ꢃ

ꢄ

ꢅ

IMONa, IMONb ........................................ –0.3V to 4V

ꢑꢇꢐꢐꢄ ꢑꢇꢄꢆꢂ ꢒꢓꢗRꢅꢇ ꢇꢗꢄ

f

...................................................–0.3V to INTV

SET

CC

CLKIN, PGOOD (Relative to GND) ........... –0.3V to 6V

ꢗꢃ

ꢃꢐꢠꢑꢦ ꢃꢐꢠꢑꢢ

ꢤ

ꢣꢇꢗꢄ

Rꢟꢗ

ꢣꢅꢏ

Terminal Currents

ꢓꢣꢅꢏꢦ ꢓꢣꢅꢏꢢ ꢅꢥꢏꢒ

ꢃꢃ

INTV Peak Output Current (Note 8)................30mA

CC

ꢆ

+

TEMP ..................................................–1mA to 10mA

ꢓꢗꢏꢒ

ꢃꢃ

–

ꢇ

TEMP .................................................–10mA to 1mA

ꢒ

ꢣꢇꢗꢄ

ꢐꢣꢗꢣ

ꢣꢔ

Temperatures

ꢈ

ꢡ

ꢧ

ꢡ

ꢧ

Internal Operating Temperature Range

(Note 2) ............................................. –40°C to 125°C

Storage Temperature Range .............. –55°C to 125°C

Peak Solder Reflow Package

ꢏꢅꢠꢑ

ꢉ

ꢑꢇꢗꢄ

ꢊ

ꢒ

ꢗꢃ

ꢐꢟꢏ

ꢋ

Body Temperature ............................................ 245°C

ꢂꢇꢁ ꢑꢁꢃꢊꢁꢇꢅ

ꢕꢕꢖꢑꢓꢗ ꢘꢀꢙꢚꢚ × ꢛꢚꢚ × ꢙꢜ0ꢀꢚꢚꢝ

= 125°C

T

JMAX

θ

= 20.6°C/W, θ

= 5.1°C/W, θ = 6.0°C/W, θ = 15.5°C/W

JCtop

JCbottom

JB

JA

θ VALUES DETERMINED PER JESD51-12

WEIGHT = 1.8 GRAMS

http://www.linear.com/product/LTM4ꢀ53#orderinfo

ORDER INFORMATION

PART MARKING*

PACKAGE

MSL

TEMPERATURE RANGE

(SEE NOTE 2)

PART NUMBER

LTM4653EY#PBF

LTM4653IY#PBF

LTM4653IY

PAD OR BALL FINISH

SAC305 (RoHS)

SnPb (63/37)

DEVICE

FINISH CODE

TYPE

RATING

e1

e0

–40°C to 125°C

LTM4653Y

BGA

3

• Device temperature grade is indicated by a label on the shipping container. • Recommended BGA PCB Assembly and Manufacturing Procedures:

www.linear.com/BGA-assy

• Pad or ball finish code is per IPC/JEDEC J-STD-609.

• BGA Package and Tray Drawings: www.linear.com/packaging

• Terminal Finish Part Marking: www.linear.com/leadfree

• This product is moisture sensitive. For more information, go to:

• This product is not recommended for second side reflow. For more

www.linear.com/BGA-assy

information, go to www.linear.com/BGA-assy

Rev 0

2

For more information www.analog.com

LTM4653

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified internal

operating temperature range (Note 2). T_A= 25°C, Test Circuit, V_IN= SV_IN= 48V, EXTV_CC= 24V, RUN = 3.3V, R_ISET= 480k,

R_fSET= 56.ꢀkΩ, f_SW= 1.5MHz (CLKIN driven with 1.2MHz clock signal) unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

3.1

TYP MAX UNITS

l

SV

, V

Input DC Voltage

58

0.94V

V

IN(DC) IN(DC)

V

Range of Output Voltage Regulation

0.5V ≤ ISETa - SGND ≤ 0.94V , I

= 0A (See Note 6)

0.5

OUT(RANGE)

OUT(24VDC)

IN OUT

IN

Output Voltage Total Variation with

Line and Load at V

28V ≤ V ≤ 58V, 0A ≤ I

≤ 4A, C = 4.7μF,

23.6

24

0

24.4

IN

OUT

INH

= 24V

C = 4.7μF, C = 2 × 47μF, CLKIN driven with

OUTH

OUT

D

1.5MHz Clock

l

V

Output Voltage Total Variation with

Line and Load at V = 0.5V

Measuring V

- ISETa

OSNS

–15

15

mV

OUT(0.5VDC)

3.1V ≤ V ≤ 13.2V, 0A ≤ I

≤ 4A, C = 4.7μF,

INH

= 2 × 47μF, ISETa = 500mV,

OUT

IN

OUT

C = 4.7μF, C

D

fSET

OUTH

R

= N/U (Note 5)

Input Specifications

l

V

SV Undervoltage Lockout Threshold SV Rising

2.85

2.6

250

3.1

2.9

V

mV

IN(UVLO)

IN

SV Falling

2.4

150

IN

Hysteresis

V

SV Overvoltage Lockout Rising

(Note 4)

64

68

2

V

IN(OVLO)

IN(HYS)

IN

SV Overvoltage Lockout Hysteresis (Note 4)

IN

4

I

Input Inrush Current at Start-Up

C

= 4.7μF, C = 4.7μF, C

= 2 × 47μF; I = 0A,

OUT

300

mA

INRUSH(VIN)

INH

D

OUTH

ISETa Electrically Connected to ISETb

I

Input Supply Bias Current

Shutdown, RUN = GND

16

450

30

μA

Q(SVIN)

RUN = V

IN

I

Input Supply Current

CLKIN Open Circuit, I

= 4A

OUT

2.1

4

A

S(VIN, FCM)

Input Supply Current in Shutdown

Shutdown, RUN = GND

µA

S(VIN, SHUTDOWN)

Output Specifications

I

V

Output Continuous Current

OUT

(Note 3)

0

4

A

OUT

Range

l

∆V

/V

Line Regulation Accuracy

Load Regulation Accuracy

I

= 0A, 28V ≤ V ≤58V

0.05

0.1

%

OUT(LINE) OUT

OUT

IN

/V

V

= 48V, 0A ≤ I

≤ 4A

0.05 0.75

2

OUT(LOAD) OUT

IN

OUT

V

Output Voltage Ripple, V

= 12V, ISETa = 5V

= 57.6k, CLKIN Open Circuit

mV

P–P

OUT(AC)

OUT

IN

l

f

V

Ripple Frequency

ISETa = 5V, R

fSET

1.7

1.95

8

2.2

MHz

mV

ms

s

OUT

∆V

Turn-On Overshoot

OUT(START)

t

Turn-On Start-Up Time

Delay Measured from V Toggling from 0V to 48V to

4

9

START

IN

PGOOD Exceeding 3V; PGOOD Having a 100k Pull-Up

to 3.3V, VPGFB Resistor-Divider Network as Shown in

Test Circuit, R

to ISETb and CLKIN Driven with 1.5MHz Clock

= 480k, ISETa Electrically Connected

ISETa

∆V

Peak Output Voltage Deviation for

Dynamic Load Step

I

: 0A to 2A and 2A to 0A Load Steps in 1μs,

OUTH

400

50

mV

µs

A

OUT(LS)

OUT

C

= 47µF × 2

t

I

Settling Time for Dynamic Load Step

I

C

: 0A to 2A and 2A to 0A Load Steps in 1μs,

OUTH

SETTLE

OUT

= 47µF × 2

–

I

Output Current Limit

5.5

OUT(OCL)

OUT

Control Section

l

I

Reference Current of ISETa Pin

Leakage Current

V

= 0.5V, 3.1V ≤ V ≤ 13.2V

49.3

49

50

50.7

51

µA

ISETa

IN

= 24V, 28V ≤ V ≤ 58V

IN

I

t

V

= SV = RUN = ISETa = 58V

600

60

µA

ns

VOSNS

OSNS

IN

Minimum On-Time

(Note 4 )

ON(MIN)

Rev 0

3

For more information www.analog.com

LTM4653

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified internal

operating temperature range (Note 2). T_A= 25°C, Test Circuit, V_IN= SV_IN= 48V, EXTV_CC= 24V, RUN = 3.3V, R_ISET= 480k,

R_fSET= 56.ꢀkΩ, f_SW= 1.5MHz (CLKIN driven with 1.2MHz clock signal) unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP MAX UNITS

l

V

RUN Turn-On/-Off Thresholds

RUN Input Turn-On Threshold, RUN Rising

RUN Hysteresis

1.08

1.2

1.32

V

RUN

130

mV

I

RUN Leakage Current

RUN = 3.3V

0.1

50

nA

RUN

Oscillator and Phase-Locked Loop (PLL)

f

Oscillator Frequency Accuracy

V

= 12V, ISETa = 5V, and:

OSC

IN

f

Open Circuit

l

360

400

1.95

440

kHz

MHz

SET

R

= 57.6kΩ (See f Specification)

fSET

s

f

PLL Synchronization Capture Range

V

= 12V, ISETa = 5V, CLKIN Driven with a GND-

SYNC

IN

Referred Clock Toggling from 0.4V to 1.2V and Having

a Clock Duty Cycle:

From 10% to 90%; f Open Circuit

250

1.3

550

3

kHz

MHz

SET

fSET

From 40% to 60%; R

= 57.6kΩ

V

CLKIN Input Threshold

CLKIN Input Current

V

Rising

Falling

1.2

V

CLKIN

0.4

I

V

= 5V

= 0V

230

–5

500

μA

CLKIN

–20

Power Good Feedback Input and Power Good Output

l

OV

UV

∆V

Output Overvoltage PGOOD Upper

Threshold

PGDFB Rising

PGDFB Falling

PGDFB Returning

620

525

645

555

8

675

580

mV

PGDFB

Output Undervoltage PGOOD Lower

Threshold

PGDFB

PGOOD Hysteresis

mV

kΩ

Ω

PGDFB

R

Resistor Between PGDFB and SGND

PGOOD Pull-Down Resistance

4.94 4.99 5.04

700 1500

V

= 0.1V, V

< UV

or

PGOOD

PGDFB

> OV

I

t

PGOOD Leakage Current

PGOOD Delay

V

= 3.3V, UV

< V

< OV

PGDFB

0.1

1

μA

PGOOD(LEAK)

PGOOD(DELAY)

PGOOD

PGDFB

PGOOD Low to High (Note 4)

PGOOD High to Low (Note 4)

16/f

s

SW(HZ)

64/f

Current Monitor and Input Voltage Regulation Pins

l

h

I

/I

Ratio of V

Output Current to I

= 0A

Current, I = 4A

OUT

36

–5

40

10

44

5

k

µA

kΩ

V

IMONa

OUT IMONa

OUT

IMONa

I

Offset Current

I

at I

IMONa OUT

OS(IMON)

MONa

Resistor

Resistor Between I

and SGND

9.8

1.9

1.8

10.2

2.1

2.2

MONb

l

V

I

Servo Voltage

MONa

IMONa Voltage During Output Current Regulation

VINREG Voltage During Output Current Regulation

VINREG = 2V

2.0

1

IMONa

VINREG

VINREG Servo Voltage

V

I

VINREG Leakage Current

nA

INTV Regulator

CC

V

Channel Internal V Voltage, No

3.6V ≤ SV ≤ 58V, EXTV = Open Circuit

3.15

2.85

3.4

3.0

3.65

3.15

V

INTVCC

CC

IN

CC

INTV Loading (I

= 0mA)

5V ≤ SV ≤ 58V, 3.2V ≤ EXTV ≤ 26.5V

CC

INTVCC

IN CC

V

EXTV Switchover Voltage

(Note 4)

0mA ≤ I ≤ 30mA

INTVCC

3.15

0.5

V

EXTVCC(TH)

CC

∆V

V

/

INTV Load Regulation

–2

2

%

INTVCC(LOAD)

INTVCC

CC

Rev 0

4

For more information www.analog.com

LTM4653

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified internal

operating temperature range (Note 2). T_A= 25°C, Test Circuit, V_IN= SV_IN= 48V, EXTV_CC= 24V, RUN = 3.3V, R_ISET= 480k,

R_fSET= 56.ꢀkΩ, f_SW= 1.5MHz (CLKIN driven with 1.2MHz clock signal) unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP MAX UNITS

Temperature Sensor

+

–

∆V

Temperature Sensor Forward Voltage,

TEMP

I

= 100µA and I

= –100μA at T = 25°C

0.6

V

TEMP

A

+

–

V

– V

TEMP

TC

∆V(TEMP)

∆V

TEMP

Temperature Coefficient

–2.0

mV/°C

Note 1: Stresses beyond those listing under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating conditions for extended periods may affect device

reliability and lifetime.

Note 5: To ensure minimum on time criteria is met, V

high-line

OUT(0.5VDC)

regulation is tested at 13.2V , with f and CLKIN open circuit. See the

IN

SET

Applications Information section.

Note ꢀ. See Applications Information Section for Dropout Criteria.

Note 2: The LTM4653 is tested under pulsed load conditions such that

Note 6. This IC includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperature will exceed 125°C when overtemperature protection is active.

Continuous operation above the specified maximum operating junction

temperature may impair device reliability.

T ≈ T . The LTM4653E is guaranteed to meet performance specifications

J

A

over the 0°C to 125°C internal operating temperature range. Specifications

over the full –40°C to 125°C internal operating temperature range are

assured by design, characterization and correlation with statistical process

controls.The LTM4653I is guaranteed to meet specifications over the full

internal operating temperature range. Note that the maximum ambient

temperature consistent with these specifications is determined by specific

operating conditions in conjunction with board layout, the rated package

thermal resistance and other environmental factors.

Note 8. The INTV Abs Max peak output current is specified as the sum

CC

of current drawn by circuits internal to the module biased off of INTV

CC

and current drawn by external circuits biased off of INTV . See the

CC

Applications Information section.

Note 3: See output current derating curves for different V , V , and T ,

IN OUT

A

located in the Applications Information section.

Note 4: Minimum on-time, V Overvoltage Lockout and Overvoltage

IN

Lockout Hysteresis, and EXTV Switchover Threshold are tested at wafer

CC

sort.

Rev 0

5

For more information www.analog.com

LTM4653

T_A= 25°C, unless otherwise noted.

TYPICAL PERFORMANCE CHARACTERISTICS

Efficiency vs Load Current at

5V_IN, Forced Continuous Mode

Efficiency vs Load Current at

12V_IN, Forced Continuous Mode

Efficiency vs Load Current at

15V_IN, Forced Continuous Mode

ꢑꢌ

ꢑ0

ꢍꢌ

ꢍ0

ꢐꢌ

ꢐ0

ꢏꢌ

ꢑꢂ

ꢑ0

ꢌꢂ

ꢌ0

ꢐꢂ

ꢐ0

ꢏꢂ

ꢀ00

ꢑꢍ

ꢑ0

ꢂꢍ

ꢂ0

ꢐꢍ

ꢐ0

ꢏꢍ

ꢏ0

ꢎꢁꢎꢃ ꢇ ꢈ00ꢉꢊꢋ

ꢄꢅꢆ

ꢀꢌꢃ ꢇ ꢍ00ꢉꢊꢋ

ꢄꢅꢆ

ꢂꢁꢌꢃ ꢇ ꢈ00ꢉꢊꢋ

ꢄꢅꢆ

ꢍꢁ0ꢃ ꢇ ꢈꢍ0ꢉꢊꢋ

ꢄꢅꢆ

ꢂꢁ0ꢃ ꢇ ꢈ00ꢉꢊꢋ

ꢄꢅꢆ

ꢀꢁꢍꢃ ꢇ ꢈ00ꢉꢊꢋ

ꢄꢅꢆ

ꢎꢁꢎꢃ ꢇ ꢈ00ꢉꢊꢋ

ꢄꢅꢆ

ꢎꢁꢎꢃ ꢇ ꢈ00ꢉꢊꢋ

ꢄꢅꢆ

ꢀꢁꢌꢃ ꢇ ꢈ00ꢉꢊꢋ

ꢄꢅꢆ

ꢌꢁꢍꢃ ꢇ ꢈ00ꢉꢊꢋ

ꢄꢅꢆ

ꢍꢁꢂꢃ ꢇ ꢈ00ꢉꢊꢋ

ꢄꢅꢆ

ꢀꢁꢌꢃ ꢇ ꢈ00ꢉꢊꢋ

ꢄꢅꢆ

ꢀꢁ0ꢃ ꢇ ꢈ00ꢉꢊꢋ

ꢄꢅꢆ

ꢀꢁꢂꢃ ꢇ ꢈ00ꢉꢊꢋ

ꢄꢅꢆ

ꢀꢁꢂꢃ ꢇ ꢈ00ꢉꢊꢋ

ꢄꢅꢆ

ꢀꢁꢍꢃ ꢇ ꢈ00ꢉꢊꢋ

ꢄꢅꢆ

ꢀꢁ0ꢃ ꢇ ꢈ00ꢉꢊꢋ

ꢄꢅꢆ

ꢀꢁꢌꢃ ꢇ ꢈ00ꢉꢊꢋ

ꢄꢅꢆ

ꢀꢁꢍꢃ ꢇ ꢈ00ꢉꢊꢋ

ꢄꢅꢆ

ꢀꢁ0ꢃ ꢇ ꢈ00ꢉꢊꢋ

ꢄꢅꢆ

ꢀꢁꢂꢃ ꢇ ꢈ00ꢉꢊꢋ

ꢄꢅꢆ

0ꢁꢌ ꢀꢁ0 ꢀꢁꢌ ꢂꢁ0 ꢂꢁꢌ ꢎꢁ0 ꢎꢁꢌ ꢈꢁ0

0ꢁꢂ ꢀꢁ0 ꢀꢁꢂ ꢍꢁ0 ꢍꢁꢂ ꢎꢁ0 ꢎꢁꢂ ꢈꢁ0

0ꢁꢍ ꢀꢁ0 ꢀꢁꢍ ꢌꢁ0 ꢌꢁꢍ ꢎꢁ0 ꢎꢁꢍ ꢈꢁ0

ꢛꢄꢜꢝ ꢕꢅRRꢒꢖꢆ ꢘꢜꢚ

ꢈꢏꢌꢎ ꢞ0ꢀ

ꢈꢏꢍꢎ ꢞ0ꢎ

ꢈꢏꢂꢎ ꢞ0ꢍ

Efficiency vs Load Current at

24V_IN, Forced Continuous Mode

Efficiency vs Load Current at

3ꢀV_IN, Forced Continuous Mode

Efficiency vs Load Current at

48V_IN, Forced Continuous Mode

ꢒꢋ

ꢒ0

ꢑꢋ

ꢑ0

ꢐꢋ

ꢐ0

ꢌꢋ

ꢌ0

ꢍ00

ꢑꢂ

ꢑ0

ꢎꢂ

ꢎ0

ꢏꢂ

ꢏ0

ꢐꢂ

ꢐ0

ꢂꢂ

ꢊ00

ꢑꢀ

ꢑ0

ꢏꢀ

ꢏ0

ꢆꢀ

ꢆ0

ꢐꢀ

ꢐ0

ꢀꢀ

ꢎꢇꢂ ꢆ ꢍꢁꢋꢏꢉꢊ

ꢃꢄꢅ

ꢍꢂꢃ ꢇ ꢏꢂ0ꢉꢊꢋ

ꢄꢅꢆ

ꢍꢋꢂ ꢆ ꢍꢁꢇꢏꢉꢊ

ꢃꢄꢅ

ꢋꢎꢁ ꢅ ꢊꢌꢋꢍꢈꢉ

ꢂꢃꢄ

ꢒꢌꢒꢁ ꢅ ꢎ00ꢇꢈꢉ

ꢂꢃꢄ

ꢍꢀꢃ ꢇ ꢎ00ꢉꢊꢋ

ꢄꢅꢆ

ꢍꢁꢎꢃ ꢇ ꢈ00ꢉꢊꢋ

ꢄꢅꢆ

ꢍꢎꢂ ꢆ ꢍꢁꢎꢏꢉꢊ

ꢃꢄꢅ

ꢊꢀꢁ ꢅ ꢊꢌꢋꢍꢈꢉ

ꢂꢃꢄ

ꢋꢌꢀꢁ ꢅ ꢎ00ꢇꢈꢉ

ꢂꢃꢄ

ꢂꢁ0ꢃ ꢇ ꢂꢂ0ꢉꢊꢋ

ꢄꢅꢆ

ꢍꢁꢂꢃ ꢇ ꢈ00ꢉꢊꢋ

ꢄꢅꢆ

ꢋꢁ0ꢂ ꢆ ꢌ00ꢈꢉꢊ

ꢃꢄꢅ

ꢊꢋꢁ ꢅ ꢊꢌꢊꢍꢈꢉ

ꢂꢃꢄ

ꢀꢁ ꢅ ꢀꢆꢀꢇꢈꢉ

ꢂꢃꢄ

ꢊꢌꢏꢁ ꢅ ꢎ00ꢇꢈꢉ

ꢂꢃꢄ

ꢊꢌꢀꢁ ꢅ ꢎ00ꢇꢈꢉ

ꢂꢃꢄ

ꢌꢁꢌꢃ ꢇ ꢈ00ꢉꢊꢋ

ꢄꢅꢆ

ꢍꢁꢀꢃ ꢇ ꢈ00ꢉꢊꢋ

ꢄꢅꢆ

ꢍꢁ0ꢃ ꢇ ꢈ00ꢉꢊꢋ

ꢄꢅꢆ

ꢀꢁꢀꢂ ꢆ ꢇ00ꢈꢉꢊ

ꢃꢄꢅ

ꢀꢁꢂꢃ ꢇ ꢈ00ꢉꢊꢋ

ꢄꢅꢆ

ꢎꢁꢋꢂ ꢆ ꢇ00ꢈꢉꢊ

ꢃꢄꢅ

0ꢁꢂ ꢍꢁ0 ꢍꢁꢂ ꢀꢁ0 ꢀꢁꢂ ꢌꢁ0 ꢌꢁꢂ ꢈꢁ0

0ꢌꢀ ꢊꢌ0 ꢊꢌꢀ ꢋꢌ0 ꢋꢌꢀ ꢒꢌ0 ꢒꢌꢀ ꢎꢌ0

0ꢁꢋ ꢍꢁ0 ꢍꢁꢋ ꢎꢁ0 ꢎꢁꢋ ꢀꢁ0 ꢀꢁꢋ ꢇꢁ0

ꢛꢄꢜꢝ ꢕꢅRRꢒꢖꢆ ꢘꢜꢚ

ꢜꢂꢝꢞ ꢖꢃRRꢓꢗꢄ ꢙꢝꢛ

ꢜꢃꢝꢞ ꢖꢄRRꢓꢗꢅ ꢙꢝꢛ

ꢇꢌꢋꢀ ꢟ0ꢌ

ꢈꢐꢂꢌ ꢞ0ꢈ

ꢎꢐꢀꢒ ꢟ0ꢀ

3.3V Transient Response, 48V_IN

12V Transient Response, 48V_IN

1V Transient Response, 24V_IN

V

OUT

50mV/DIV

100mV/DIV

50mV/DIV

AC-COUPLED

I

OUT

2A/DIV

OUT

2A/DIV

4653 G07

4653 G08

4653 G09

40µs/DIV

FIGURE 30 CIRCUIT, 48V

40µs/DIV

FIGURE 30 CIRCUIT, 48V

40µs/DIV

FIGURE 30 CIRCUIT, 24V

,

IN

C

= C = 4.7µF, C

= 2 x 100µF,

C

= C = 4.7µF, C

= 2 x 22µF,

C

= C = 4.7µF, C

= 3 x 100µF,

INH

fSET

D

OUT

INH

fSET

D

OUT

INH

fSET

D

OUT

R

C

= N/A, R

= 66.5kΩ,

R

C

= 124k, R

= 240kΩ,

R

C

= N/A, R

= 20kΩ,

ISET

= 10nF, R = 604Ω,

= 10nF, R = 562Ω,

= 6.8nF, R = 681Ω,

TH TH

TH

R

TH

R

TH

= N/A, C

= N/A,

= 49.9Ω, C

= 1µF,

R

= N/A, C

= N/A,

EXTVCC

2A to 4A LOAD STEP AT 2A/µs

Rev 0

6

For more information www.analog.com

LTM4653

T_A= 25°C, unless otherwise noted.

TYPICAL PERFORMANCE CHARACTERISTICS

Start-Up, No Load

Start-Up, 4A Load

Start-Up, Pre-Bias

RUN

2V/DIV

RUN

2V/DIV

RUN

2V/DIV

V

OUT

5V/DIV

V

OUT

5V/DIV

OUT

5V/DIV

I

DIODE

1mA/DIV

PGOOD

2V/DIV

PGOOD

2V/DIV

PGOOD

2V/DIV

4653 G10

4653 G11

4653 G12

2ms/DIV

FIGURE 30 CIRCUIT, 48V

,

FIGURE 30 CIRCUIT, 48V ,

IN

FIGURE 30 CIRCUIT, 48V

,

IN

C

= C = 4.7µF, C

= 2 x 22µF,

C

= C = 4.7µF, C

= 2 x 22µF,

OUT

C

= C = 4.7µF, C

= 2 x 22µF,

OUT

INH

D

OUT

INH

D

INH

D

R

C

= 124k, R

= 240kΩ,

R

C

= 124k, R

= 240kΩ,

R

C

= 124k, R

= 240kΩ,

fSET

PGDFB

= 10nF, R = 562Ω,

ISET

fSET

ISET

fSET

PGDFB

ISET

= 95.3kΩ,

PGDFB

= 95.3kΩ,

= 10nF, R = 562Ω,

TH TH

= 10nF, R = 562Ω,

TH

R

TH

= 49.9Ω, C

= 1µF,

R

= 49.9Ω, C

= 1µF,

EXTVCC

R

= 49.9Ω, C

PRE-BIASED TO 5V

= 1µF,

EXTVCC

NO LOAD

EXTVCC

3Ω RESISTIVE LOAD

V

OUT

THROUGH 1N4148 DIODE

Short Circuit, No Load

Short Circuit, 4A Load

V

OUT

V

OUT

5V/DIV

I

IN

I

IN

1A/DIV

4653 G13

4653 G14

10µs/DIV

FIGURE 30 CIRCUIT, 48V

,

FIGURE 30 CIRCUIT, 48V ,

IN

C

= C = 4.7µF, C

= 2 x 22µF,

C

= C = 4.7µF, C

= 2 x 22µF,

INH

fSET

D

OUT

INH

fSET

D

OUT

R

= 124k, R

= 240kΩ,

R

= 124k, R

= 240kΩ,

ISET

= 95.3kΩ,

PGDFB

TH

EXTVCC

PGDFB

TH TH

EXTVCC

C

R

= 10nF, R = 562Ω,

C

R

= 10nF, R = 562Ω,

TH

= 49.9Ω, C

= 1µF,

= 49.9Ω, C

= 1µF,

EXTVCC

NO LOAD PRIOR TO APPLICATION

OF OUTPUT SHORT-CIRCUIT

3Ω RESISTIVE LOAD PRIOR TO

APPLICATION OF OUTPUT

SHORT-CIRCUIT

Rev 0

7

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LTM4653

PIN FUNCTIONS

PACKAGE ROW AND COLUMN LABELING MAY VARY

RUN (F4): Run Control Pin. A voltage above 1.2V com-

mands the Module to regulate its output voltage. Under-

voltagelockout(UVLO)canbeimplementedbyconnecting

RUN to the midpoint node formed by a resistor-divider

AMONG µModule PRODUCTS. REVIEW EACH PACKAGE

LAYOUT CAREFULLY.

V

(A1-A3, B3): Power Input Pins. Apply input voltage

IN

and input decoupling capacitance directly between VIN

betweenV andGND. RUNfeatures130mVofhysteresis.

IN

and a ground (PGND) plane.

See the Applications Information section.

V (A4, B4, C4): Drain of the Converter’s Primary Switch-

D

INTV (G3): Internal Regulator, 3.3V Nominal Output.

CC

ing MOSFET. Apply at minimum one 4.7µF high frequency

Internal control circuits and MOSFET-drivers derive pow-

ceramic decoupling capacitor directly from V to PGND.

D

er from INTV bias. When operating 3.1V < SV ≤ 58V,

CC

IN

Give this capacitor higher layout priority (closer proximity

an LDO generates INTV from SV when RUN is logic

CC

IN

to the module) than any V decoupling capacitors.

IN

high (RUN > 1.2V). No external decoupling is required.

When RUN is logic low (RUN - GND < 1.2V), the INTV

CC

SV (C3): Input Voltage Supply for Small-Signal Circuits.

IN

LDO is off, i.e., INTV is unregulated. (Also see EXTV .)

CC

SV is the input to the INTV LDO. Connect SV directly

IN

CC

IN

to V . No decoupling capacitor is needed on this pin.

IN

EXTV (F3): External Bias, Auxiliary Input to the INTV

CC

Regulator. When EXTV exceeds 3.2V and SV exceeds

CC

IN

PGND (A5, B5, C5, D5, E5, F5, G4-5, H3, H5, J3-5, K4-

5, L4-5): Power Ground Pins of the LTM4653. Connect

all pins to the application’s PGND plane.

5V, the INTV LDO derives power from EXTV bias

CC

instead of the SV path. This technique can reduce LDO

IN

losses considerably, resulting in a corresponding reduc-

V

(K1-3, L1-3): Power Output Pins of the LTM4653.

OUT

tion in module junction temperature. For applications in

Connectallpinstotheapplication’spowerV plane.Apply

OUT

which4V≤V ≤26.5V,connectEXTV toV through

OUT

CC

the output filter capacitors and the output load between

a power V

a resistor. (See the Applications Information section for

plane and the application’s PGND plane.

OUT

resistor value.) When taking advantage of this EXTV

CC

feature, locally decouple EXTV to PGND with a 1µF ce-

GND (D4): Ground Pin of the LTM4653. Electrically con-

nect to the application’s PGND plane.

CC

ramic—otherwise, leave EXTV open circuit.

CC

ISETb (F1): 1.5nF Soft-Start Capacitor. Connect ISETb

to ISETa to achieve default soft-start characteristics, if

desired. See ISETa.

V

(G1,H1):OutputVoltageSenseandFeedbackSignal.

OSNS

Connect V

to V

at the point of load (POL). Pins G1

OSNS

OUT

and H1 are electrically connected to each other internal to

the module, and thus it is only necessary to connect one

V

can be used for redundant connectivity or routed to an ICT

test point for design-for-test considerations, as desired.

ISETa (F2): Accurate 50μA Current Source. Positive input

pin to V

at the POL. The remaining V

OSNS

OUT

OSNS

to the error amplifier. Connect a resistor (R ) from this

ISET

pintoSGNDtoprogramthedesiredLTM4653outputvolt-

age, V

= R

• 50μA. A capacitor can be connected

OUT

ISET

from ISETa to SGND to soft-start the output voltage and

reduce start-up inrush current. Connect ISETa to ISETb in

order to achieve default soft-start, if desired. (See ISETb.)

SGND (E4, G2, H2): Signal Ground Pins of the LTM4653.

Connect Pin H2 to PGND directly under the LTM4653. The

SGND pins at locations E4 and G2 are electrically con-

nected to each other internal to the module, and thus it is

only necessary to connect one SGND pin to PGND under

the module. The remaining SGND pins can be used for

redundant connectivity or routed to an ICT test point for

design-for-test considerations, as desired.

In addition, the output of the LTM4653 can track a voltage

applied between the ISETa pin and the SGND pins. (See

the Applications Information section.)

Rev 0

8

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LTM4653

PIN FUNCTIONS

PGOOD (D1): Power Good Indicator, Open-Drain Output

Pin. PGOOD is high impedance when PGDFB is within

approximately 7.5% of 0.6V. PGOOD is pulled to GND

when PGDFB is outside this range.

default loop compensation. Loop compensation (a series

resistor-capacitor) can be applied externally to COMPa if

desired or needed, instead. (See COMPb.)

COMPb (E1): Internal Loop Compensation Network. For

mostapplications,theinternal,defaultloopcompensation

of the LTM4653 is suitable to apply “as is”, and yields very

satisfactoryresults:applythedefaultloopcompensationto

the control loop by simply connecting COMPa to COMPb.

When more specialized applications require a personal

touch to the optimization of control loop response, this

can be accomplished by connecting a series resistor-

capacitor network from COMPa to SGND—and leaving

COMPb open circuit.

PGDFB (D2): Power Good Feedback Programming Pin.

Connect PGDFB to V

PGDFB

through a resistor, R

.

OSNS

PGDFB

forwhich

R

configuresthevoltagethresholdofV

OUT

PGOOD toggles its state. If the PGOOD feature is used,

set R

to:

PGDFB

⎛

⎞

V

OUT

R

=

– 1 • 4.99k

⎟

⎜

PGDFB

⎝

⎠

0.6V

otherwise, leave PGDFB open circuit.

A small filter capacitor (220pF) internal to the LTM4653

on this pin provides high frequency noise immunity for

the PGOOD output indicator.

VINREG (D3): Input Voltage Regulation Programming

Pin. Optionally connect this pin to the midpoint node

formed by a resistor-divider between V and SGND. When

D

the voltage on VINREG falls below approximately 2V, a

f

(E3): Oscillator Frequency Programming Pin. The

SET

VINREG control loop servos V

to decrease the power

OUT

default switching frequency of the LTM4653 is 400kHz.

inductor current and thus regulate VINREG at 2V. (See

the Applications Information section.)

Often, it is necessary to increase the programmed fre-

quency by connecting a resistor between f and SGND.

SET

(See the Applications Information section.) Note that the

If this input voltage regulation feature is not desired, con-

synchronization range of CLKIN is approximately 40%

nect VINREG to INTV .

CC

of the oscillator frequency programmed by the f pin.

SET

IMONa (C2): Power InductorCurrentAnalog IndicatorPin

and Current Limit Programming Pin. The current flowing

out of this pin is equal to 1/40,000 of the average power

CLKIN (B1): Mode Select and Oscillator Synchronization

Input. Leave CLKIN open circuit for forced continuous

mode operation. Alternatively, this pin can be driven to

synchronize the switching frequency of the LTM4653 to

a clock signal. In this condition, the LTM4653 operates

in forced continuous mode and the cycle-by-cycle turn-

inductor current. To construct a voltage (V

) that is

IMONa

proportional to the power inductor current, optionally

apply a parallel resistor-capacitor network to this pin and

terminate it to SGND.

on of the primary power MOSFET M is coincident with

T

IMONa can be connected to IMONb if the default resis-

tor-capacitor termination network provided by IMONb is

desired: 1V at full scale (4A) load current. (See IMONb.)

If this analog indicator feature is not desired, connect

IMONa to SGND.

the rising edge of the clock applied to CLKIN. Note the

synchronization range of CLKIN is approximately 40%

of the oscillator frequency programmed by the f

(See the Applications Information section.)

pin.

SET

COMPa (E2): Current Control Threshold and Error Ampli-

fier Compensation Node. The trip threshold of LTM4653’s

current comparator increases with a corresponding rise

in COMPa voltage. A small filter cap (10pF) internal to the

LTM4653 on this pin introduces a high-frequency roll-

off of the error-amplifier response, yielding good noise

rejection in the control-loop. COMPa is often electrically

connected to COMPb in one’s application, thus applying

If IMONa ever exceeds a trip threshold of approximately

2V, an IMON control loop servos V

to decrease power

OUT

inductor current and thus regulate IMONa at 2V. In this

manner, the average current limit inception threshold of

the LTM4653 can be configured. (See the Applications

Information section.)

Rev 0

9

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LTM4653

PIN FUNCTIONS

IMONb(C1):PowerInductorAnalogIndicatorCurrentDe-

fault Termination R-C Network. A 10kΩ resistor in parallel

with a 10nF capacitor and terminating to SGND connect

to this pin. Connect IMONb to IMONa to achieve default

power inductor analog indicator current characteristics:

1V at full scale (4A) load current. (See IMONa.)

TEMP– (J2, J6): Temperature Sensor, Negative Input.

Collector and base of a 2N3906-genre PNP bipolar junc-

tion transistor (BJT). Optionally interface to temperature

monitoringcircuitrysuchasLTC2997,LTC2990,LTC2974

or LTC2975. Otherwise leave electrically open. Pins J2

and J7 are electrically connected together internal to the

LTM4653, and thus it is only necessary to connect one

TEMP– pin to monitoring circuitry. The remaining TEMP–

pin can be used for redundant connectivity or routed to an

ICTtestpointfordesign-for-testconsiderations,asdesired.

TEMP+ (J1, Jꢀ): Temperature Sensor, Positive Input.

Emitter of a 2N3906-genre PNP bipolar junction transis-

tor (BJT). Optionally interface to temperature monitor-

ing circuitry such as LTC^®2997, LTC2990, LTC2974 or

LTC2975.Otherwiseleaveelectricallyopen.PinsJ1andJ6

areelectricallyconnectedtogetherinternaltotheLTM4653,

and thus it is only necessary to connect one TEMP+ pin

to monitoring circuitry. The remaining TEMP+ pin can be

used for redundant connectivity or routed to an ICT test

point for design-for-test considerations, as desired.

SW (H4): Switching Node of Switching Converter Stage.

Used for test purposes. May be routed a short distance

with a thin trace to a local test point to monitor switching

actionoftheconverter, ifdesired, butdonotroutenearany

sensitivesignals;otherwise,leaveelectricallyopencircuit.

NC (Aꢀ-6, B2, Bꢀ-6, Cꢀ-6, Dꢀ-6, Eꢀ-6, Fꢀ-6, Gꢀ-6, Hꢀ-6,

Kꢀ-6, Lꢀ-6): No connect pins, i.e., pins with no internal

connection. The NC pins predominantly serve to provide

improved mounting of the module to the board. In one’s

layout, NC pinsare permitted to remain electricallyuncon-

nected or can be connected as desired, e.g., connected

to a GND plane for heat-spreading purposes and/or to

facilitate routing.

Rev 0

10

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LTM4653

SIMPLIFIED BLOCK DIAGRAM

Rev 0

11

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LTM4653

TEST CIRCUIT

V

24V

UP TO 4A

,

IN

OUT

NC

SW

V

OSNS

IN

OUT

28V TO 58V

C

4.7μF

INH

V

SV

+

IN

C

68µF

C

27µF

OUTL

OUTH

LOAD

RUN

GND

SGND

PGND

CLKIN

LTM4653

V

R

PGDFB

196k

D

C

D

4.7μF

x2

INTV

CC

PGDFB

PGOOD

CC

TEMP+

TEMP–

IMONa

IMONb

VINREG

COMPa

EXTV

C

TH

0.1μF

COMPb

R

TH

f

SET

499Ω

ISETa ISETb

4653 TC01

R

57.6k

R

ISET

480k

fSET

T_A= 25°C. Refer to Test Circuit

CONDITIONS

DECOUPLING REQUIREMENTS

APPLICATION SYMBOL PARAMETER

MIN

TYP

MAX

UNITS

Test Circuit

C , C

INH

External High Frequency Input Capacitor Requirement,

28V ≤ V ≤ 58V, V = 24V

I

= 4A

9.4

µF

D

OUT

IN

OUT

C

External High Frequency Output Capacitor Requirement

28V ≤ V ≤ 58V, V = 24V

I

= 4A

22

µF

OUTH

OUT

IN

OUT

Rev 0

12

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LTM4653

OPERATION

Power Module Description

IMONaisananalogoutputcurrentindicatorpin.Itsources

a current proportional to the LTM4653’s load current.

When IMONa is electrically connected to IMONb, the

voltage on the IMONa/IMONb node is proportional to load

current—with 1V corresponding to 4A load. IMONa can

be interfaced to an external parallel-RC network instead

of the one provided by IMONb. If IMONa ever exceeds 2V,

a servo loop reduces the LTM4653’s output current in

order to keep IMONa at or below 2V. Through this servo

mechanism, a parallel RC network can be connected to

IMONa to implement an average current limit function—if

desired. When the feature is not needed, connect IMONa

to SGND.

The LTM4653 is a non-isolated switch mode DC/DC step-

down power supply. It can provide up to 4A output current

with a few external input and output capacitors. Set by a

single resistor, R , the LTM4653 regulates a positive

ISET

output voltage, V . V

can be set to as low as 0.5V to

OUT OUT

ashighas0.94V . TheLTM4653operatesfromapositive

IN

input supply rail, V , between 3.1V and 58V. The typical

IN

application schematic is shown in Figure 30.

The LTM4653 contains an integrated constant-frequency

current mode regulator, power MOSFETs, power inductor,

EMI filter and other supporting discrete components. The

nominal switching frequency range is from 400kHz to

3MHz, and the default operating frequency is 400kHz. It

can be externally synchronized to a clock, from 250kHz

to 3MHz. See the Applications Information section. The

LTM4653 supports internal and external control loop

compensation. Internal loop compensation is selected by

connecting the COMPa and COMPb pins. Using internal

loop compensation, the LTM4653 has sufficient stability

margins and good transient performance with a wide

range of output capacitors—even ceramic-only output

capacitors. For external loop compensation, see the

ApplicationsInformationsection.LTpowerCAD^®isavailable

for transient load step and stability analysis. Input filter

and noise cancellation circuitry reduces noise-coupling to

the module’s inputs and outputs, ensuring the module’s

electromagnetic interference (EMI) meets the limits of

EN55022 Class B (see Figures 4 to 6).

The LTM4653 also features a spare control pin called

VINREG, with a 2V servo threshold, which can be used

to reduce the input current draw during input line sag

(“brownout”)conditions.ConnectVINREGtoINTV when

CC

this feature is not needed.

TEMP+ and TEMP– pins give access to a diode-con-

nected PNP transistor, making it possible to monitor the

LTM4653’s internal temperature—if desired.

External component selection is primarily determined by

the maximum load current and output voltage. Refer to

Table 7 and the Test Circuit for recommended external

component values.

V to V

Step-Down Ratios

IN

OUT

There are restrictions on the V to V

step-down ratio

IN

OUT

that the LTM4653 can achieve. The maximum duty cycle

of the LTM4653 is 96% typical. The V to V mini-

Pulling the RUN pin below 1.2V forces the LTM4653 into

a shutdown state. A capacitor can be applied from ISETa

to SGND to program the output voltage ramp-rate; or,

the default LTM4653 ramp-rate can be set by connecting

ISETa to ISETb; or, voltage tracking can be implemented

by interfacing rail voltages to the ISETa pin. See the

Applications Information section.

IN

OUT

mum dropout voltage is a function of load current when

operating in high duty cycle applications. As an example,

V

from the Electrical Characteristics table high-

OUT(24VDC)

lights the LTM4653’s ability to regulate 24V

at up to

OUT

4A from 28V , when running at a switching frequency,

IN

f

SW

, of 1.5MHz.

Multiphase operation can be employed by applying an

external clock source to the LTM4653’s synchronization

input, the CLKIN pin. See the Typical Applications section.

At very low duty cycles, the LTM4653’s on-time of M

T

each switching cycle should be designed to exceed the

LTM4653 control loop’s specified minimum on-time of

60ns, t

D

, (guardband to 90ns), i.e.:

LDO losses within the module are reduced by connecting

ON(MIN)

EXTV to V

through an RC-filter or by connecting

CC

OUT

> T

ON(MIN)

EXTV to a suitable voltage source.

CC

f

SW

Rev 0

13

For more information www.analog.com

LTM4653

OPERATION

where D (unitless) is the duty-cycle of M , given by:

effectsduringoutputloadchanges.Thebulkcapacitorcan

be a switcher-rated aluminum electrolytic capacitor or a

T

V

OUT

D =

Polymer capacitor. Suggested values for C and C are

D

INH

V

IN

found in Table 7.

A final precaution regarding ceramic capacitors concerns

the maximum input voltage rating of the LTM4653’s V ,

In rare cases where the minimum on-time restriction is

violated, the frequency of the LTM4653 automatically and

graduallyfoldsbackdowntoapproximatelyone-fifthofits

IN

SV ,andV pins.Aceramicinputcapacitorcombinedwith

IN

D

programmed switching frequency to allow V

to remain

OUT

trace or cable inductance forms a high Q (underdamped)

tank circuit. If the LTM4653 circuit is plugged into a live

supply, the input voltage can ring to twice its nominal

value, possibly exceeding the device’s rating. This situa-

tioniseasilyavoided;seetheHot-PluggingSafelysection.

in regulation. See the Frequency Adjustment section. Be

remindedofNotes2,3and5intheElectricalCharacteristics

section regarding output current guidelines.

Input Capacitors

TheLTM4653achieveslowinputconductedEMInoisedue

to tight layout and high-frequency bypassing of MOSFETs

Output Capacitors

Output capacitors C

theLTM4653.SufficientcapacitanceandlowESRarecalled

for, to meet the output voltage ripple, loop stability, and

transient requirements. C

or polymer capacitor. C

typical output capacitance is 22μF (type X5R material, or

better), if ceramic-only output capacitors are used.

and C

are applied to V

of

OUTH

OUTL

OUT

M and M within the module itself. A small filter inductor

T

B

(400nH) is integrated in the input line (from V to V ),

IN

D

providing further noise attenuation—again, local to the

switching MOSFETs. The V and V pins are available

can be a low ESR tantalum

OUTL

D

IN

is a ceramic capacitor. The

OUTH

for external input capacitors—C and C —to form a

D

INH

high-frequency π filter. As shown in the Simplified Block

Diagram, the ceramic capacitor C on the LTM4653’s V

D

pins handles the majority of the RMS current into the DC/

DC converter power stage and requires careful selection,

for that reason.

Table 7 shows a matrix of suggested output capacitors

optimized for 2A transient step-loads applied at 2A/μs.

Additional output filtering may be required by the system

designer, if further reduction of output ripple or dynamic

transientspikeisrequired. TheLTpowerCADdesigntoolis

availablefortransientandstabilityanalysis.Stabilitycriteria

are considered in the Table 7 matrix, and LTpowerCAD is

available for stability analysis. Multiphase operation will

reduce effective output ripple as a function of the num-

ber of phases. Application Note 77 discusses this noise

reduction versus output ripple current cancellation, but

the output capacitance should be considered carefully as

afunctionofstabilityandtransientresponse.LTpowerCAD

can be used to calculate the output ripple reduction as the

number of implemented phases increases by N times.

External loop compensation can be applied to COMPa if

needed, for transient response optimization.

See Figures 4 to 6 for demonstration of LTM4653’s EMI

performance,meetingtheradiatedemissionsrequirements

of EN55022B.

The input capacitance, C , is needed to filter the pulsed

D

current drawn by M . To prevent excessive voltage sag

T

on V , a low-effective series resistance (low-ESR, such

D

as an X7R ceramic) input capacitor should be used, sized

appropriately for the maximum C RMS ripple current:

D

I

OUT(MAX)

I

=

• D • (1–D)

CD(RMS)

η%

whereη%istheestimatedefficiencyofthepowermodule.

(See Typical Performance Characteristics graphs.)

Forced Continuous Operation

Several capacitors may be paralleled to meet the applica-

LeavetheCLKINpinopencircuittocommandtheLTM4653

for forced continuous operation. In this mode, the control

loop is allowed to command the inductor peak current to

Rev 0

tion’stargetsize,height,andC RMSripplecurrentrating.

D

For lower input voltage applications, sufficient bulk input

capacitance is needed to counteract line sag and transient

14

For more information www.analog.com

LTM4653

OPERATION

approximately –1A, allowing for significant negative aver-

age current. Clocking the CLKIN pin at a frequency within

40% of the target switching frequency commanded by

Frequency Adjustment

The default switching frequency (f ) of the LTM4653

SW

is 400kHz. This is suitable for low-V (V ≤ 5V) ap-

IN

the f pin synchronizes M ’s turn-on to the rising edge

SET

T

plications and low-V

(V ≤3.3V) applications. For a

OUT OUT

of the CLKIN pin.

practical design, the LTM4653’s inductor ripple current

(∆I ) is suggested to be less than ~2A . Choose

PK-PK

Output Voltage Programming, Tracking and Soft-Start

f

according to:

SW

The LTM4653 regulates its output voltage, V , accord-

OUT

V

• 1− D

(

)

OUT

ing to the differential voltage present across ISETa and

f

=

SW

L • ∆I

PK-PK

SGND. In most applications, the output voltage is set by

simply connecting a resistor, R , from ISETa to SGND,

ISET

where the value of LTM4653’s power inductor, L, is 4μH.

according to:

To avoid cycle-skipping, impose restrictions on f , to

SW

V

OUT

R

=

ensure minimum on time criteria is met:

ISET

50µA

D

f

<

SW

Since the LTM4653 control loop servos its output volt-

age according to the voltage between ISETa and SGND:

T

ON(MIN)

placing a capacitor, C , parallel to R

configures the

SS

SET

The LTM4653’s minimum on-time, t

, is specified

ON(MIN)

ramp-up rate of ISETa and thus V . In the time domain,

OUT

as 60ns. For a practical design, it is recommended to

guardband to 90ns.

the output voltage ramp-up after the RUN pin is toggled

from low to high (t = 0s) is given by:

ToconfiguretheLTM4653forahigherswitchingfrequency

t

⎛

⎞

⎟

–

than its default of 400kHz, apply a resistor, R , between

fSET

⎜

R_ISET• C_SS

V

(t)=I

•R

• 1– e

the f pin and SGND. R

is given (in MΩ) by:

OUT

ISETa

ISET

⎜

⎟

SET

fSET

⎟

⎝

⎠

1

R

(MΩ)=

fSET

10pF •[f (MHz)– 0.4(MHz)]

The soft-start time, t , is defined as the time it takes for

SS

SW

V

to ramp from 0V to 90% of its final value:

OUT

The relationship of R

to programmed f is shown

SW

fSET

t

= –R

•C •In (1– 0.9)

SS

ISET

SS

in Figure 1. See Table 7 for recommended f and cor-

SW

or

responding R

values for various combinations of V

fSET

IN

= 2.3 • R

•C

SS

ISET

SS

and V

.

OUT

ꢀ0

A default value of C = 1.5nF can be implemented by

SS

connecting ISETa to ISETb. For other ramp-up rates,

connect an external C capacitor parallel to R . When

SS

ISET

starting up into a pre-biased V , the LTM4653 stays in

OUT

a sleep mode, keeping M and M off until V equals

T

B

ISETa

Rꢀ

ꢄꢅꢃ ꢆꢁꢂꢇ

ꢀ

ꢁꢂꢃ

V

—after which, the DC/DC converter commences

OSNS

switching action and V

is ramped according to the

OUT

voltage commanded by ISETa.

Since the LTM4653 control loop servos its V

voltage

OSNS

0ꢀꢁ

to match that of ISETa’s, the LTM4653’s output can be

configured to track any voltage applied to ISETa, refer-

enced to SGND.

ꢀ0

ꢀ00

ꢀꢁ

(kΩ)

ꢀ0ꢁ

Rf

SET

ꢀꢁꢂꢃ ꢄ0ꢅ

Figure 1. Relationship Between R_fSETand Target f_SW

Rev 0

15

For more information www.analog.com

LTM4653

APPLICATIONS INFORMATION

Power Module Protection

ꢆ

ꢇꢀꢂꢂꢈꢉ

R

ꢄ

TheLTM4653’scurrentmodecontrolarchitectureprovides

fastcycle-by-cyclecurrentlimitinanovercurrentcondition,

as shown in the Typical Performance Characteristics sec-

tion. If the output voltage collapses sufficiently due to an

overload or short-circuit condition, minimum on-time will

be violated and the internal oscillator will then fold-back

automatically to one-fifth of the LTM4653’s programmed

switchingfrequency—therebyreducingtheoutputcurrent

and affording the load a chance to recover.

Rꢀꢁ ꢂꢃꢁ

ꢅ

ꢊꢋꢌꢍ ꢎ0ꢏ

Figure 2. Undervoltage Lockout Resistive Divider

from falsely tripping UVLO. Resistors are chosen by first

selecting R (refer to Figure 2). Then:

B

TheLTM4653featuresinputovervoltageshutdownprotec-

tion: when V > 68V, switching action ceases (with 4V of

IN

⎛

⎜

⎝

⎞

V

IN(ON)

hysteresis)—however, be advised that this protection is

onlyactiveoutsidetheLTM4653’ssafeoperatingarea(see

Note 1 and Note 4 of the Electrical Characteristics table).

R =R •

– 1

⎟

⎠

A

B

1.2V

where V

is the input voltage at which the undervolt-

IN(ON)

The LTM4653 ceases switching action if internal tempera-

tures exceed 165°C. The control IC resumes operation

after a 10°C cool-down hysteresis. Note that these typical

parameters are based on measurements in a lab oven and

arenotproductiontested.Thisovertemperatureprotection

is intended to protect the device during momentary over-

loadconditions.Themaximumratedjunctiontemperature

will be exceeded when this overtemperature protection is

active. Continuous operation above the specified absolute

maximum operating junction temperature may impair

device reliability or permanently damage the device.

age lockout is overcome and the supply turns on. R may

A

be replaced with a hardwired connection from V to RUN.

D

The V turn-off voltage, V

is given by:

IN

IN(OFF)

⎛

⎜

⎝

⎞

R

A

B

V

= 1.07V •

+1

⎟

IN(OFF)

⎠

IfUVLOisnotneeded,RUNcanbeconnectedtoLTM4653’s

V or V pins.

D

IN

When RUN is below its threshold, UVLO is engaged, M

T

and M are turned off, INTV ceases to be regulated, and

B

CC

ISETa is discharged to SGND by internal circuitry.

The LTM4653 does not feature any specialized output

overvoltage protection beyond what is inherent to the

control loop’s servo mechanism.

Loop Compensation

External loop compensation may be preferred for some

applications and can be implemented easily, as follows:

RUN Pin Enable

leave COMPb open circuit; connect a series-R network

C

The RUN pin is used to enable the power module or se-

quencethepowermodule. Thethresholdis1.2V. TheRUN

pincanbeusedtoprovideanundervoltagelockout(UVLO)

function by connecting a resistor divider from the input

supply to the RUN pin, as shown in Figure 2. Undervoltage

lockout keeps the LTM4653 in shutdown until the supply

input voltage is above a certain voltage programmed by

the user. The RUN pin hysteresis voltage prevents noise

(R and C ) from COMPa to SGND; in some instances,

TH

connect a capacitor (C ) from COMPa to SGND (paral-

THP

leling the R

series-RC network). See Table 7 for

TH-CTH

suggested input and output capacitances for a variety of

operatingconditions.Additionally,theLTpowerCADdesign

tool is available for transient and stability analysis.

Rev 0

16

For more information www.analog.com

LTM4653

APPLICATIONS INFORMATION

Hot-Plugging Safely

The recommended value of the resistor between V

and

OUT

EXTV is roughly V

• 4Ω/V. This resistor, R

,

.

The small size, robustness and low impedance of ceramic

capacitors make them an attractive option for the input

CC

OUT

EXTVCC

²

must be rated to continually dissipate (0.02A) • R

The primary purpose of this resistor is to prevent EXTV

bypasscapacitors(C andC )oftheLTM4653.However,

CC

D

INH

overstress under a fault condition. For example, when an

these capacitors can cause problems if the LTM4653 is

plugged into a live supply (see Linear Technology Ap-

plication Note 88 for a complete discussion). The low

loss ceramic capacitor combined with stray inductance

in series with the power source forms an under damped

inductive short-circuit is applied to the module’s output,

V

OUT

may be briefly dragged below PGND—forward bias-

ing the PGND-to-EXTV body diode. This resistor limits

CC

the magnitude of current flow in EXTV . Bypass EXTV

CC

with 1μF of X5R (or better) MLCC.

tank circuit, and the voltage at the V pin of the LTM4653

IN

can ring to twice the nominal input voltage, possibly ex-

ceeding the LTM4653’s rating and damaging the part. If

the input supply is poorly controlled or the user will be

plugging the LTM4653 into an energized supply, the input

network should be designed to prevent this overshoot by

introducing a damping element into the path of current

flow. This is often done by adding an inexpensive elec-

Multiphase Operation

Multiple LTM4653 devices can be paralleled for higher

output current applications. For lowest input and output

voltage and current ripples, it is advisable to synchronize

paralleled LTM4653s to an external clock (within 40%

of the target switching frequency set by f —see Test

SET

trolytic bulk capacitor (C ) across the input terminals

Circuit 1). See Figure 32 for an example of a synchroniz-

INL

of the LTM4653. The selection criteria for C calls for:

ing circuit.

INL

an ESR high enough to damp the ringing; a capacitance

LTM4653modulescanbeparalleledwithoutsynchronizing

circuits:justbeawarethatsomebeat-frequencyripplewill

bepresentintheoutputvoltageandreflectedinputcurrent

by virtue of the fact that such modules are not operating

at identical, synchronized switching frequencies.

value several times larger than C . C does not need

INH INL

to be located physically close to the LTM4653; it should

be located close to the application board’s input connec-

tor, instead.

INTV and EXTV Connection

The LTM4653 device is an inherently current mode con-

trolled device, so parallel modules will have good current

sharing’s shown in Figure 33. This helps balance the

thermals on the design.

CC

When RUN is logic high, an internal low dropout regula-

tor regulates an internal supply, INTV , that powers the

CC

controlcircuitryfordrivingLTM4653’sinternalMOSFETs.

INTV isregulatedat3.3V.Inthismanner,theLTM4653’s

To parallel LTM4653s, connect the respective COMPa,

CC

INTV is directly powered from SV , by default. The gate

ISETa, and V

pins of each LTM4653 together to share

CC

IN

OSNS

driver current through the LDO is about 20mA for a typical

1MHz application. The internal LDO power dissipation can

be calculated as:

the current evenly. In addition, tie the respective RUN

pins of paralleled LTM4653 devices together, to ensure

proper start-up and shutdown behavior. Figure 32 shows

a schematic of LTM4653 devices operating in parallel.

P_{LDO _ LOSS(INTVCC)}= 20mA •(SV_IN– 3V)

Note that for parallel applications, V

can be set by a

OUT

The LDO draws current off of EXTV instead of SV

CC

IN

single, common resistor on the ISETa net:

when EXTV is higher than 3.2V and SV is above 5V.

CC

IN

For output voltages of 4V and higher, EXTV can be con-

CC

V

OUT

R

=

ISET

nectedtoV

throughanRC-filter.WhentheinternalLDO

OUT

50µA •N

derives power from EXTV instead of SV , the internal

CC

IN

where N is the number of LTM4653 modules in parallel

configuration.

LDO power dissipation is:

P_{LDO _ LOSS(EXTVCC)}= 20mA •(V_OUT−3V)

Rev 0

17

For more information www.analog.com

LTM4653

APPLICATIONS INFORMATION

Manydesignersmayopttouselaboratoryequipmentanda

testvehiclesuchasthedemoboardtopredicttheµModule

regulator’s thermal performance in their application at

various electrical and environmental operating conditions

to compliment any FEA activities. Without FEA software,

the thermal resistances reported in the Pin Configuration

sectionare, inandofthemselves, notrelevanttoproviding

guidance of thermal performance; instead, the derating

curves provided in this data sheet can be used in a man-

ner that yields insight and guidance pertaining to one’s

application-usage,andcanbeadaptedtocorrelatethermal

performance to one’s own application.

Depending on the duty cycle of operation, the output volt-

age ripple achieved by paralleled, synchronized LTM4653

modulesmaybeconsiderablysmallerthanwhatisyielded

by a single-phase solution. Application Note 77 provides

a detailed explanation of multiphase operation (relevant

to parallel LTM4653 applications) pertaining to noise

reduction and output and input ripple current cancella-

tion. Regardless of ripple current cancellation, it remains

importantfortheoutputcapacitanceofparalleledLTM4653

applications to be designed for loop stability and transient

response. LTpowerCAD is available for such analysis.

Figure 3 illustrates the RMS ripple current reduction as

a function of the number of interleaved (paralleled and

synchronized) LTM4653 modules—derived from Ap-

plication Note 77.

The Pin Configuration section gives four thermal coeffi-

cients explicitly defined in JESD51-12; these coefficients

are quoted or paraphrased below:

1. θ , the thermal resistance from junction to ambient, is

JA

Radiated EMI Noise

the natural convection junction-to-ambient air thermal

resistance measured in a one cubic foot sealed enclo-

sure. This environment is sometimes referred to as

“still air” although natural convection causes the air to

move. This value is determined with the part mounted

toaJESD51-9definedtestboard,whichdoesnotreflect

an actual application or viable operating condition.

The generation of radiated EMI noise is an inherent disad-

vantageofswitchingregulators.Fastswitchingturn-onand

turn-off of the power MOSFETs—necessary for achieving

high efficiency—create high-frequency (~30MHz+) ∆l/∆t

changes within DC/DC converters. This activity tends to

be the dominant source of high-frequency EMI radiation

in such systems. The high level of device integration

within LTM4653—including optimized gate-driver and

critical front-end � filter inductor—delivers low radiated

EMI noise performance. Figures 4 to 6 show typical ex-

amples of LTM4653 meeting the radiated emission limits

established by EN55022 Class B.

2. θ

, the thermal resistance from junction to the

JCbottom

bottom of the product case, is determined with all of

the component power dissipation flowing through the

bottomofthepackage.InthetypicalµModuleregulator,

the bulk of the heat flows out the bottom of the pack-

age, but there is always heat flow out into the ambient

environment. As a result, this thermal resistance value

may be useful for comparing packages but the test

conditionsdon’tgenerallymatchtheuser’sapplication.

Thermal Considerations and Output Current Derating

The thermal resistances reported in the Pin Configuration

section of this data sheet are consistent with those pa-

rameters defined by JESD51-12 and are intended for use

with finite element analysis (FEA) software modeling tools

that leverage the outcome of thermal modeling, simula-

tion, and correlation to hardware evaluation performed on

a µModule package mounted to a hardware test board.

The motivation for providing these thermal coefficients is

found in JESD51-12 (“Guidelines for Reporting and Using

Electronic Package Thermal Information”).

3. θ

, the thermal resistance from junction to top of

JCtop

the product case, is determined with nearly all of the

componentpowerdissipationflowingthroughthetopof

the package. As the electrical connections of the typical

µModule regulator are on the bottom of the package, it

is rare for an application to operate such that most of

the heat flows from the junction to the top of the part.

As in the case of θ

, this value may be useful

JCbottom

for comparing packages but the test conditions don’t

generally match the user’s application.

Rev 0

18

For more information www.analog.com

LTM4653

APPLICATIONS INFORMATION

0ꢀꢅ0

ꢉꢙꢘꢚꢓꢖꢑ

ꢈꢙꢘꢚꢓꢖꢑ

0ꢀꢂꢂ

ꢆꢙꢘꢚꢓꢖꢑ

ꢄꢙꢘꢚꢓꢖꢑ

ꢅꢙꢘꢚꢓꢖꢑ

0ꢀꢂ0

0ꢀꢄꢂ

0ꢀꢄ0

0ꢀꢆꢂ

0ꢀꢆ0

0ꢀꢈꢂ

0ꢀꢈ0

0ꢀꢉꢂ

0ꢀꢉ0

0ꢀ0ꢂ

0

0ꢀꢉ 0ꢀꢉꢂ 0ꢀꢈ 0ꢀꢈꢂ 0ꢀꢆ 0ꢀꢆꢂ 0ꢀꢄ 0ꢀꢄꢂ 0ꢀꢂ 0ꢀꢂꢂ 0ꢀꢅ 0ꢀꢅꢂ 0ꢀꢁ 0ꢀꢁꢂ 0ꢀꢃ 0ꢀꢃꢂ 0ꢀꢊ

ꢋꢌꢍꢎ ꢏꢎꢏꢐꢑ

ꢄꢅꢂꢆ ꢇ0ꢆ

Figure 3. Normalized Input RMS Ripple Current vs Duty Cycle for One to Six LTM4ꢀ53s (Phases)

ꢓ0

ꢒ0

ꢑ0

ꢔ0

ꢕ0

ꢖ0

ꢗ0

0

ꢓ0

ꢁꢈꢀꢧ ꢇꢄꢧꢅ ꢗ0ꢏ

ꢧꢂꢈꢜ ꢇꢄꢧꢅ ꢗ0ꢏ

ꢁꢈꢀꢧ ꢇꢄꢧꢅ ꢗ0ꢏ

ꢧꢂꢈꢜ ꢇꢄꢧꢅ ꢗ0ꢏ

ꢒ0

ꢑ0

ꢔ0

ꢕ0

ꢖ0

ꢗ0

0

ꢢꢗꢣ ꢞꢤRꢄꢥꢤꢛꢅꢀꢃ

ꢢꢖꢣ ꢍꢈRꢅꢄꢜꢀꢃ

ꢚꢂꢦ ꢃꢄꢁꢄꢅ

ꢢꢗꢣ ꢞꢤRꢄꢥꢤꢛꢅꢀꢃ

ꢢꢖꢣ ꢍꢈRꢅꢄꢜꢀꢃ

ꢚꢂꢦ ꢃꢄꢁꢄꢅ

ꢨ

ꢙꢤRꢁꢀꢃ

ꢘꢗ0

ꢕ0

ꢗꢕ0

ꢖꢕ0

ꢕꢕ0

ꢔꢕ0

ꢑꢕ0

ꢒꢕ0

ꢓꢕ0

ꢠꢕ0

ꢡꢕ0 ꢗ000

ꢕ0

ꢗꢕ0

ꢖꢕ0

ꢕꢕ0

ꢔꢕ0

ꢑꢕ0

ꢒꢕ0

ꢓꢕ0

ꢠꢕ0

ꢡꢕ0 ꢗ000

ꢔꢒꢑꢕ ꢙ0ꢔ

ꢔꢒꢑꢕ ꢙ0ꢑ

ꢙRꢈꢚꢆꢈꢛꢜꢝ ꢉꢁꢞꢟꢐ

Figure 4. Radiated Emissions Scan of the LTM4ꢀ53. Producing

24V_OUTat 4A, from 29.5V_IN. DC2326A Hardware. f_SW= 1.2MHz.

Measured in a 10m Chamber. Peak Detect Method

Figure 5. Radiated Emissions Scan of the LTM4ꢀ53 Producing

24V_OUTat 3.5A, from 48V_IN. DC2326A Hardware. f_SW= 1.2MHz.

Measured in a 10m Chamber. Peak Detect Method

ꢓ0

ꢁꢈꢀꢧ ꢇꢄꢧꢅ ꢗ0ꢏ

ꢧꢂꢈꢜ ꢇꢄꢧꢅ ꢗ0ꢏ

ꢒ0

ꢑ0

ꢔ0

ꢕ0

ꢖ0

ꢗ0

0

ꢢꢗꢣ ꢞꢤRꢄꢥꢤꢛꢅꢀꢃ

ꢢꢖꢣ ꢍꢈRꢅꢄꢜꢀꢃ

ꢚꢂꢦ ꢃꢄꢁꢄꢅ

ꢨ

ꢙꢤRꢁꢀꢃ

ꢘꢗ0

ꢕ0

ꢗꢕ0

ꢖꢕ0

ꢕꢕ0

ꢔꢕ0

ꢑꢕ0

ꢒꢕ0

ꢓꢕ0

ꢠꢕ0

ꢡꢕ0 ꢗ000

ꢔꢒꢑꢕ ꢙ0ꢒ

ꢙRꢈꢚꢆꢈꢛꢜꢝ ꢉꢁꢞꢟꢐ

Figure ꢀ. Radiated Emissions Scan of the LTM4ꢀ53. Producing

12V_OUTat 3A, from 58V_IN. DC2326A Hardware. f_SW= 1.2MHz.

Measured in a 10m Chamber. Peak Detect Method

Rev 0

19

For more information www.analog.com

LTM4653

APPLICATIONS INFORMATION

4. θ , the thermal resistance from junction to the printed

Within the LTM4653, be aware there are multiple power

devices and components dissipating power, with a con-

sequence that the thermal resistances relative to different

junctions of components or die are not exactly linear with

respect to total package power loss. To reconcile this

complicationwithoutsacrificingmodelingsimplicity—but

alsonotignoringpracticalrealities—anapproachhasbeen

taken using FEA software modeling along with laboratory

testing in a controlled-environment chamber to reason-

ably define and correlate the thermal resistance values

supplied in this data sheet: (1) Initially, FEA software is

used to accurately build the mechanical geometry of the

LTM4653 and the specified PCB with all of the correct

material coefficients along with accurate power loss

source definitions; (2) this model simulates a software-

definedJEDECenvironmentconsistentwithJESD51-9and

JESD51-12topredictpowerlossheatflowandtemperature

readings at different interfaces that enable the calculation

of the JEDEC-defined thermal resistance values; (3) the

model and FEA software is used to evaluate the LTM4653

with heat sink and airflow; (4) having solved for and

analyzed these thermal resistance values and simulated

various operating conditions in the software model, a

thorough laboratory evaluation replicates the simulated

conditions with thermocouples within a controlled envi-

ronment chamber while operating the device at the same

power loss as that which was simulated. The outcome of

this process and due diligence yields the set of derating

JB

circuit board, is the junction-to-board thermal resis-

tance where almost all of the heat flows through the

bottom of the µModule regulator and into the board,

and is really the sum of the θ

and the thermal

JCbottom

resistance of the bottom of the part through the solder

joints and through a portion of the board. The board

temperature is measured a specified distance from the

package, using a two sided, two layer board. This board

is described in JESD51-9.

A graphical representation of the aforementioned ther-

mal resistances is given in Figure 7; blue resistances are

contained within the µModule regulator, whereas green

resistances are external to the µModule package.

As a practical matter, it should be clear to the reader that

no individual or sub-group of the four thermal resistance

parameters defined by JESD51-12 or provided in the

Pin Configuration section replicates or conveys normal

operating conditions of a µModule regulator. For example,

in normal board-mounted applications, never does 100%

of the device’s total power loss (heat) thermally conduct

exclusively through the top or exclusively through bot-

tom of the µModule package—as the standard defines

for θ

and θ , respectively. In practice, power

JCbottom

JCtop

loss is thermally dissipated in both directions away from

the package—granted, in the absence of a heat sink and

airflow, a majority of the heat flow is into the board.

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Rꢍꢘꢏꢘꢔꢗꢓꢐꢍ

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Rꢍꢘꢏꢘꢔꢗꢓꢐꢍ

ꢜꢕꢗRꢌꢖꢔꢕꢖꢗꢇꢜꢏꢍꢓꢔ

Rꢍꢘꢏꢘꢔꢗꢓꢐꢍ

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ꢆꢇꢈꢉꢊꢋe ꢌꢍꢎꢏꢐꢍ

Figure 6. Graphical Representaion of JESD51-12 Thermal Coefficients

Rev 0

20

For more information www.analog.com

LTM4653

APPLICATIONS INFORMATION

curves provided in later sections of this data sheet, along

withwell-correlatedJESD51-12-definedθvaluesprovided

in the Pin Configuration section of this data sheet.

at 2.5A

condition is 3.9W. A 4.5W loss is calculated

OUT

by multiplying the 3.9W room temperature loss from the

48V to 24V

power loss curve at 2.5A (Figure 10),

IN

OUT

with the 1.15 multiplying factor at 70°C ambient (from

Table 1). If the 70°C ambient temperature is subtracted

from the 120°C junction temperature, then the difference

The1V,5V,and15V and24VpowerlosscurvesinFigures8,

9 and 10 respectively can be used in coordination with

the load current derating curves in Figures 11 to 28 for

of 50°C divided by 4.5W yields a thermal resistance, θ ,

JA

calculating an approximate θ thermal resistance for the

JA

of 11.1°C/W—in good agreement with Table 4. Tables 2,

3 and 4 provide equivalent thermal resistances for 1V, 5V

and 15V and 24V outputs with and without air flow and

heat sinking. The derived thermal resistances in Tables 2,

3 and 4 for the various conditions can be multiplied by the

calculatedpowerlossasafunctionofambienttemperature

to derive temperature rise above ambient, thus maximum

junction temperature. Room temperature power loss

can be derived from the efficiency curves in the Typical

Performance Characteristics section and adjusted with

ambient temperature multiplicative factors from Table 1.

LTM4653withvariousheatsinkingandairflowconditions.

These thermal resistances represent demonstrated

performance of the LTM4653 on DC2327A hardware; a

4-layerFR4PCBmeasuring99mm×133mm ×1.6mm using

outerandinnercopperweightsof2ozand1oz,respectively.

The power loss curves are taken at room temperature,

and are increased with multiplicative factors with ambient

temperature.TheseapproximatefactorsarelistedinTable1.

(Compute the factor by interpolation, for intermediate

temperatures.) The derating curves are plotted with the

LTM4653’s output initially sourcing 4A and the ambient

temperature at 20°C. The output voltages are 1V, 5V,

15V and 24V. These are chosen to include the lower and

higher output voltage ranges for correlating the thermal

resistance. In all derating curves, the switching frequency

of operation follows guidance provided by Table 7.

Thermal models are derived from several temperature

measurements in a controlled temperature chamber

along with thermal modeling analysis. The junction

temperatures are monitored while ambient temperature is

increased with and without air flow, and with and without

a heat sink attached with thermally conductive adhesive

tape. The power loss increase with ambient temperature

change is factored into the derating curves. The junctions

are maintained at 120°C maximum while lowering output

current or power while increasing ambient temperature.

The decreased output current decreases the internal

module loss as ambient temperature is increased. The

monitored junction temperature of 120°C minus the

ambientoperatingtemperaturespecifieshowmuchmodule

temperaturerisecanbeallowed.AsanexampleinFigure25,

the load current is derated to 2.5A at 70°C ambient

with 200LFM airflow and no heat sink and the room

Table 1. Power Loss Multiplicative Factors vs Ambient

Temperature

POWER LOSS MULTIPLICATIVE

AMBIENT TEMPERATURE

FACTOR

1.00

1.05

1.10

1.15

1.20

1.25

1.30

1.35

1.40

Up to 40°C

50°C

60°C

70°C

80°C

90°C

100°C

110°C

120°C

temperature (25°C) power loss for this 48V to 24V

IN

OUT

Rev 0

21

For more information www.analog.com

LTM4653

APPLICATIONS INFORMATION

Table 2. 1V Output

DERATING CURVE

Figures 11, 12, 13

Figures 14, 15, 16

V

(V)

POWER LOSS CURVE

Figures 8, 9

AIRFLOW (LFM)

HEAT SINK

None

θ

(°C/W)

JA

IN

5, 12, 24

0

13.9

11.4

10.7

13.3

11.0

10.3

Figures 8, 9

200

400

0

None

Figures 8, 9

None

Figures 8, 9

BGA Heat Sink

Figures 8, 9

200

400

Figures 8, 9

Table 3. 5V Output

DERATING CURVE

Figures 17, 18, 19

Figures 20, 21, 22

V

(V)

POWER LOSS CURVE

Figures 8, 9, 10

AIRFLOW (LFM)

HEAT SINK

None

θ

(°C/W)

JA

IN

12, 24, 48

0

13.9

11.4

10.7

13.3

11.0

10.3

200

400

0

None

BGA Heat Sink

200

400

Table 4. 15V and 24V Output

DERATING CURVE

Figures 23, 24, 25

V

(V)

POWER LOSS CURVE

Figures 9, 10

AIRFLOW (LFM)

HEAT SINK

None

θ

(°C/W)

JA

IN

24, 48

0

13.9

11.4

10.7

13.3

11.0

10.3

Figures 23, 24, 25

200

400

0

None

Figures 23, 24, 25

None

Figures 26, 27, 28

BGA Heat Sink

Figures 26, 27, 28

200

400

Figures 26, 27, 28

Table 5. Heat Sink Manufacturer (Thermally Conductive Adhesive Tape Pre-Attached)

HEAT SINK MANUFACTURER

PART NUMBER

WEBSITE

Cool Innovations

3-0504035UT411

www.coolinnovations.com

Table ꢀ. Thermally Conductive Adhesive Tape Vendor

THERMALLY CONDUCTIVE ADHESIVE

TAPE MANUFACTURER

PART NUMBER

WEBSITE

Chomerics

T411

www.chomerics.com

Rev 0

22

For more information www.analog.com

LTM4653

APPLICATIONS INFORMATION

Table 6. LTM4ꢀ53 Output Voltage Response vs Component Matrix. Performance of Figure 30 Circuit with Values Here Indicated.

Load-Stepping from 2A to 4A Load Current, at 2A/μs. Typical Measured Values

C

VENDORS

PART NUMBER

C

OUTH

VENDORS

PART NUMBER

OUTH

AVX

12066D107MAT2A (100μF, 6.3V, 1206 Case Size)

GRM31CR60J107M (100μF, 6.3V, 1206 Case Size)

JMK316BBJ107MLHT (100μF, 6.3V, 1206 Case Size)

C3216X5R0J107M (100μF, 6.3V, 1206 Case Size)

1210YD476MAT2A (47μF, 16V, 1210 Case Size)

GRM32ER61C476M (47μF, 16V, 1210 Case Size)

EMK325BJ476MM (47μF, 16V, 1210 Case Size)

12103D226MAT2A (22μF, 25V, 1210 Case Size)

TMK325BJ226MM (22μF, 25V, 1210 Case Size)

C3225X5R1E226M (22μF, 25V, 1210 Case Size)

AVX

12105D106MAT2A (10μF, 50V, 1210 Case Size)

GRM32ER61H106M (10μF, 50V, 1210 Case Size)

UMK325BJ106M (10μF, 50V, 1210 Case Size)

C3225X5R1H106M (10μF, 50V, 1210 Case Size)

PART NUMBER

Murata

Taiyo Yuden

TDK

Taiyo Yuden

TDK

AVX

C

/C VENDORS

INH D

Murata

Taiyo Yuden

AVX

Murata

AVX

GRM32ER71K475M (4.7μF, 80V, 1210 Case Size)

12065C475MAT2A (4.7μF, 50V, 1206 Case Size)

GRM31CR71H475M (4.7μF, 50V, 1206 Case Size)

UMK316AB7475ML (4.7μF, 50V, 1206 Case Size)

C3216X5R1H475M (4.7μF, 50V, 1206 Case Size)

Murata

Taiyo Yuden

TDK

Taiyo Yuden

TDK

LOAD STEP LOAD STEP

TRANSIENT

DROOP

(mV)

PK-PK

DEVIATION

(mV)

RECOVERY

TIME

(μs)

V

R

C

R

f

R

OUT

(V)

IN

(V)

TH

ISET

(kΩ)

PGDFB

(kΩ)

SW

fSET

EXTVCC

(Ω)

C

OUTH

(Ω)

681

665

649

604

499

(nF)

6.8

8.2

10

(kHz)

400

550

575

600

500

800

1100

1200

750

1200

1400

1200

1500

(kΩ)

N/A

665

576

499

1000

249

143

124

287

124

100

124

90.9

INH

D

1

5

4.7μF

100μF x 3

100μF x 2

47μF x 2

22μF x 2

10μF x 2

20

3.32

4.99

7.5

N/A

20

70

145

190

185

180

260

350

430

440

55

50

45

40

35

1

12

24

5

20

1

20

70

1.2

1.5

1.8

2.5

3.3

5

24

70

12

24

5

24

70

24

70

30.1

36

70

12

24

36

5

7.5

70

7.5

70

7.5

70

10

70

12

24

36

5

36

10

70

36

10

70

36

10

70

50

15.8

22.6

36.5

95.3

121

196

70

12

24

36

48

5

50

70

50

70

50

70

50

70

66.5

100

240

301

481

90

12

24

36

48

12

24

36

48

15

24

36

48

24

36

48

36

48

10

90

10

90

10

90

10

90

10

130

170

220

5

10

20

5

10

20

5

10

20

12

15

24

10

49.9

60.4

100

10

Rev 0

23

For more information www.analog.com

LTM4653

See Table 1 for f_SWand R_EXTVCC

.

APPLICATIONS INFORMATION—DERATING CURVES

ꢄꢀ0

ꢃꢀꢁ

ꢃꢀ0

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ꢇꢎꢏ

0ꢀ0 0ꢀꢁ ꢂꢀ0 ꢂꢀꢁ ꢃꢀ0 ꢃꢀꢁ ꢄꢀ0 ꢄꢀꢁ ꢅꢀ0

0ꢀ0 0ꢀꢃ ꢁꢀ0 ꢁꢀꢃ ꢂꢀ0 ꢂꢀꢃ ꢅꢀ0 ꢅꢀꢃ ꢄꢀ0

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ꢅꢓꢁꢄ ꢔ0ꢕ

ꢄꢆꢃꢅ ꢕꢁ0

Figure 8. 12V_INPower Loss Curve

Figure 9. 24V_INPower Loss Curve

Figure 10. 48V_INPower Loss Curve

ꢁꢕ0

ꢓꢕꢒ

ꢓꢕ0

ꢀꢕꢒ

ꢀꢕ0

ꢄꢕꢒ

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0ꢕꢒ

0ꢕ0

ꢁꢕ0

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ꢓꢕ0

ꢀꢕꢒ

ꢀꢕ0

ꢄꢕꢒ

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0ꢕꢒ

0ꢕ0

ꢁꢕ0

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ꢓꢕ0

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ꢀꢕ0

ꢄꢕꢒ

ꢄꢕ0

0ꢕꢒ

0ꢕ0

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ꢁ00ꢗꢔꢆ

ꢀ00ꢗꢔꢆ

ꢁ00ꢗꢔꢆ

ꢀ00ꢗꢔꢆ

ꢁ00ꢗꢔꢆ

ꢀ0

ꢁ0

ꢂ0

ꢃ0

ꢄ00

ꢄꢀ0

ꢀ0

ꢁ0

ꢂ0

ꢃ0

ꢄ00

ꢄꢀ0

ꢀ0

ꢁ0

ꢂ0

ꢃ0

ꢄ00

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ꢁꢂꢒꢓ ꢔꢄꢀ

ꢁꢂꢒꢓ ꢔꢄꢓ

Figure 11. 5V to 1V_OUTDerating

Curve, No Heat Sink

Figure 12. 12V to 1V_OUT

Derating Curve, No Heat Sink

Figure 13. 24V to 1V_OUT

Derating Curve, No Heat Sink

ꢁꢕ0

ꢓꢕꢒ

ꢓꢕ0

ꢀꢕꢒ

ꢀꢕ0

ꢄꢕꢒ

ꢄꢕ0

0ꢕꢒ

0ꢕ0

ꢁꢕ0

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ꢓꢕ0

ꢀꢕꢒ

ꢀꢕ0

ꢄꢕꢒ

ꢄꢕ0

0ꢕꢒ

0ꢕ0

ꢁꢕ0

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ꢓꢕ0

ꢀꢕꢒ

ꢀꢕ0

ꢄꢕꢒ

ꢄꢕ0

0ꢕꢒ

0ꢕ0

ꢘꢗꢔꢆ

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ꢁ00ꢗꢔꢆ

ꢀ00ꢗꢔꢆ

ꢁ00ꢗꢔꢆ

ꢀ00ꢗꢔꢆ

ꢁ00ꢗꢔꢆ

ꢀ0

ꢁ0

ꢂ0

ꢃ0

ꢄ00

ꢄꢀ0

ꢀ0

ꢁ0

ꢂ0

ꢃ0

ꢄ00

ꢄꢀ0

ꢀ0

ꢁ0

ꢂ0

ꢃ0

ꢄ00

ꢄꢀ0

ꢅꢆꢇꢈꢉꢊꢋ ꢋꢉꢆꢌꢉRꢅꢋꢍRꢉ ꢎꢏꢐꢑ

ꢁꢂꢒꢓ ꢔꢄꢁ

ꢁꢂꢒꢓ ꢔꢄꢒ

ꢁꢂꢒꢓ ꢔꢄꢂ

Figure 14. 5V to 1V_OUTDerating

Curve, with BGA Heat Sink

Figure 15. 12V to 1V_OUTDerating

Curve, with BGA Heat Sink

Figure 1ꢀ. 24V to 1V_OUTDerating

Curve, with BGA Heat Sink

Rev 0

24

For more information www.analog.com

LTM4653

See Table 1 for f_SWand R_EXTVCC

.

APPLICATIONS INFORMATION—DERATING CURVES

ꢁꢖ0

ꢓꢖꢒ

ꢓꢖ0

ꢀꢖꢒ

ꢀꢖ0

ꢄꢖꢒ

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0ꢖ0

ꢙꢘꢔꢆ

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ꢁ0

ꢂ0

ꢃ0

ꢄ00

ꢄꢀ0

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ꢁ0

ꢂ0

ꢃ0

ꢄ00

ꢄꢀ0

ꢀ0

ꢁ0

ꢂ0

ꢃ0

ꢄ00

ꢄꢀ0

ꢅꢆꢇꢈꢉꢊꢋ ꢋꢉꢆꢌꢉRꢅꢋꢍRꢉ ꢎꢏꢐꢑ

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ꢁꢂꢒꢓ ꢔꢄꢃ

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Figure 16. 12V to 5V_OUT

Derating Curve, No Heat Sink

Figure 18. 24V to 5V_OUT

Derating Curve, No Heat Sink

Figure 19. 48V to 5V_OUT

Derating Curve, No Heat Sink

ꢁꢕ0

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ꢓꢕ0

ꢀꢕꢒ

ꢀꢕ0

ꢄꢕꢒ

ꢄꢕ0

0ꢕꢒ

0ꢕ0

ꢁꢕ0

ꢓꢕꢒ

ꢓꢕ0

ꢀꢕꢒ

ꢀꢕ0

ꢄꢕꢒ

ꢄꢕ0

0ꢕꢒ

0ꢕ0

ꢁꢕ0

ꢓꢕꢒ

ꢓꢕ0

ꢀꢕꢒ

ꢀꢕ0

ꢄꢕꢒ

ꢄꢕ0

0ꢕꢒ

0ꢕ0

ꢘꢗꢔꢆ

ꢀ00ꢗꢔꢆ

ꢁ00ꢗꢔꢆ

ꢀ00ꢗꢔꢆ

ꢁ00ꢗꢔꢆ

ꢀ00ꢗꢔꢆ

ꢁ00ꢗꢔꢆ

ꢀ0

ꢁ0

ꢂ0

ꢃ0

ꢄ00

ꢄꢀ0

ꢀ0

ꢁ0

ꢂ0

ꢃ0

ꢄ00

ꢄꢀ0

ꢀ0

ꢁ0

ꢂ0

ꢃ0

ꢄ00

ꢄꢀ0

ꢅꢆꢇꢈꢉꢊꢋ ꢋꢉꢆꢌꢉRꢅꢋꢍRꢉ ꢎꢏꢐꢑ

ꢁꢂꢒꢓ ꢔꢀꢄ

ꢁꢂꢒꢓ ꢔꢀꢀ

ꢁꢂꢒꢓ ꢔꢀ0

Figure 22. 48V to 5V_OUTDerating

Curve, with BGA Heat Sink

Figure 20. 12V to 5V_OUTDerating

Curve, with BGA Heat Sink

Figure 21. 24V to 5V_OUTDerating

Curve, with BGA Heat Sink

ꢁꢕ0

ꢓꢕꢒ

ꢓꢕ0

ꢀꢕꢒ

ꢀꢕ0

ꢄꢕꢒ

ꢄꢕ0

0ꢕꢒ

0ꢕ0

ꢁꢕ0

ꢓꢕꢒ

ꢓꢕ0

ꢀꢕꢒ

ꢀꢕ0

ꢄꢕꢒ

ꢄꢕ0

0ꢕꢒ

0ꢕ0

ꢁꢕ0

ꢓꢕꢒ

ꢓꢕ0

ꢀꢕꢒ

ꢀꢕ0

ꢄꢕꢒ

ꢄꢕ0

0ꢕꢒ

0ꢕ0

ꢘꢗꢔꢆ

ꢀ00ꢗꢔꢆ

ꢁ00ꢗꢔꢆ

ꢀ00ꢗꢔꢆ

ꢁ00ꢗꢔꢆ

ꢀ00ꢗꢔꢆ

ꢁ00ꢗꢔꢆ

ꢀ0

ꢁ0

ꢂ0

ꢃ0

ꢄ00

ꢄꢀ0

ꢀ0

ꢁ0

ꢂ0

ꢃ0

ꢄ00

ꢄꢀ0

ꢀ0

ꢁ0

ꢂ0

ꢃ0

ꢄ00

ꢄꢀ0

ꢅꢆꢇꢈꢉꢊꢋ ꢋꢉꢆꢌꢉRꢅꢋꢍRꢉ ꢎꢏꢐꢑ

ꢁꢂꢒꢓ ꢔꢀꢓ

ꢁꢂꢒꢓ ꢔꢀꢁ

ꢁꢂꢒꢓ ꢔꢀꢒ

Figure 24. 48V to 15V_OUTDerating

Curve, No Heat Sink

Figure 25. 48V to 24V_OUTDerating

Curve, No Heat Sink

Figure 23. 24V to 15V_OUTDerating

Curve, No Heat Sink

Rev 0

25

For more information www.analog.com

LTM4653

See Table 1 for f_SWand R_EXTVCC

.

APPLICATIONS INFORMATION—DERATING CURVES

ꢁꢕ0

ꢓꢕꢒ

ꢓꢕ0

ꢀꢕꢒ

ꢀꢕ0

ꢄꢕꢒ

ꢄꢕ0

0ꢕꢒ

0ꢕ0

ꢁꢖ0

ꢓꢖꢒ

ꢓꢖ0

ꢀꢖꢒ

ꢀꢖ0

ꢄꢖꢒ

ꢄꢖ0

0ꢖꢒ

0ꢖ0

ꢁꢕ0

ꢓꢕꢒ

ꢓꢕ0

ꢀꢕꢒ

ꢀꢕ0

ꢄꢕꢒ

ꢄꢕ0

0ꢕꢒ

0ꢕ0

ꢘꢗꢔꢆ

ꢙꢘꢔꢆ

ꢘꢗꢔꢆ

ꢀ00ꢗꢔꢆ

ꢁ00ꢗꢔꢆ

ꢀ00ꢘꢔꢆ

ꢁ00ꢘꢔꢆ

ꢀ00ꢗꢔꢆ

ꢁ00ꢗꢔꢆ

ꢀ0

ꢁ0

ꢂ0

ꢃ0

ꢄ00

ꢄꢀ0

ꢀ0

ꢁ0

ꢂ0

ꢃ0

ꢄ00

ꢄꢀ0

ꢀ0

ꢁ0

ꢂ0

ꢃ0

ꢄ00

ꢄꢀ0

ꢅꢆꢇꢈꢉꢊꢋ ꢋꢉꢆꢌꢉRꢅꢋꢍRꢉ ꢎꢏꢐꢑ

ꢁꢂꢒꢓ ꢔꢀꢂ

ꢁꢂꢒꢓ ꢔꢀꢕ

ꢁꢂꢒꢓ ꢔꢀꢃ

Figure 26. 48V to 15V_OUTDerating

Curve, with BGA Heat Sink

Figure 28. 48V to 24V_OUTDerating

Curve, with BGA Heat Sink

Figure 2ꢀ. 24V to 15V_OUTDerating

Curve, with BGA Heat Sink

APPLICATIONS INFORMATION

Safety Considerations

• Place high frequency ceramic input and output ca-

pacitors next to the V , V , PGND and V pins to

IN

D

OUT

TheLTM4653doesnotprovidegalvanicisolationfromV

IN

minimize high frequency noise.

to V . There is no internal fuse. If required, a slow blow

OUT

fuse with a rating twice the maximum input current needs

• Place a dedicated power ground layer underneath the

LTM4653.

tobeprovidedtoprotecttheunitfromcatastrophicfailure.

The fuse or circuit breaker, if used, should be selected to

• Tominimizetheviaconductionlossandreducemodule

thermal stress, use multiple vias for interconnection

between top layer and other power layers.

limit the current to the regulator in case of a M MOSFET

T

fault. If M fails, the system’s input supply will source

T

very large currents to V

through M . This can cause

OUT

T

• Do not put vias directly on pads, unless they are capped

or plated over.

excessive heat and board damage depending on how

much power the input voltage can deliver to this system.

A fuse or circuit breaker can be used as a secondary fault

protector in this situation. The LTM4653 does feature

overcurrent and overtemperature protection.

• Use a separate SGND copper plane for components

connected to signal pins. Connect SGND to PGND

directly under the module.

• For parallel module applications, connect the V

,

OUT

Layout Checklist/Example

V

, RUN, ISETa, COMPa and PGOOD pins together

OSNS

The high integration of LTM4653 makes the PCB board

layout straightforward. However, to optimize its electrical

and thermal performance, some layout considerations

are still necessary.

as shown in Figure 32.

• Bring out test points on the signal pins for monitoring.

Figure 29 gives a good example of the recommended

LTM4653 layout.

• Use large PCB copper areas for high current paths,

including V , PGND and V . Doing so helps to

IN

OUT

minimize the PCB conduction loss and thermal stress.

Rev 0

26

For more information www.analog.com

LTM4653

APPLICATIONS INFORMATION

ꢀꢁꢂ

ꢃ

ꢄꢁ

ꢀꢁꢂ

ꢃ

ꢅꢆꢇ

ꢈꢉꢊꢋ ꢌꢍꢎ

Figure 29. Recommend PCB Layout, Package Top View

TYPICAL APPLICATIONS

V

24V

UP TO 4A

,

IN

OUT

NC

SW

V

OSNS

IN

OUT

48V

C

4.7μF

INH

V

SV

IN

C

OUTH

10µF

x2

LOAD

V

D

C

4.7μF

D

SGND

PGND

RUN

GND

INTV

CC

LTM4653

R

196k

R

EXTVCC

PGDFB

CLKIN

R

PGDPUP

100k

100Ω

0.1µF

PGDFB

PGOOD

TEMP+

TEMP–

INTV

CC

+

–

V

VINREG

COMPa

COMPb

CC

V

D

REF

470pF

LTC2997

GND

C

10nF

TH

EXTV

4mV/K

CC

V

PTAT

C

EXTVCC

IMONa

IMONb

4653 F30

R

499Ω

f

SET

1µF

ISETa ISETb

R

90.9k

R

ISET

481k

fSET

OPTIONAL ANALOG OUTPUT

TEMPERATURE INDICATOR

Figure 30. 4A, 24V Output DC/DC μModule Regulator

Rev 0

27

For more information www.analog.com

LTM4653

TYPICAL APPLICATIONS

Rꢀꢁ

ꢂꢃꢄꢅꢆꢃ

ꢆ

ꢇꢈꢉ

ꢀ0ꢆꢃꢄꢅꢆ

ꢊꢋꢇꢇꢄ

ꢌꢆꢃꢄꢅꢆ

ꢀꢁꢂꢃ ꢄꢃꢅ

ꢀꢁꢂꢃꢄꢅꢆ

Figure 31. Start-Up Waveforms at 48V_IN, Figure 30 Circuit

I

OUT1

24V

V

48V

OUT

IN

V

NC

SW

IN

V

OUT

UP TO 8A

C

22µF

×2

C

4.7μF

OUT

INH

V

OSNS

SV

IN

LOAD

V

D

C

4.7μF

D

RUN

GND

SGND

PGND

U1

LTM4653

INTV

CC1

R

INTV

PGDFB1

196k

CLKIN

INTV

CC1

R

PGDPUP

100Ω

PGDFB

PGOOD

EXTV

CC

PGOOD

VINREG

CC

R

100Ω

EXTVCC

COMPa

COMPb

TEMP+

TEMP–

IMONa

C

1µF

EXTVCC

LTC6908-1

ANALOG OUTPUT

CURRENT INDICATOR

f

SET

ISETa

ISETb IMONb

+

V

OUT1

OUT2

MOD

V

IMON

= 0.125Ω • (I

+ I

)

OUT1 OUT2

R

fSET1

90.9k

R

66.5k

SET

I

OUT2

0.1µF

GND

V

NC

SW

IN

V

OUT

C

4.7μF

INH

V

OSNS

SV

IN

V

D

SGND

PGND

RUN

GND

C

D

4.7μF

U2

LTM4653

R

CLKIN

INTV

PGDFB2

196k

R

100Ω

EXTVCC

PGDFB

PGOOD

CC

VINREG

EXTV

CC

+

–

COMPa

COMPb

TEMP

C

10nF

TH

C

1µF

TH

EXTVCC

R

IMONa

IMONb

499Ω

f

SET

ISETa

ISETb

4653 F32

R

90.9k

R

ISET

240k

fSET

Figure 32. 24V Output at Up to 8A from 48V Input, 2-Phase Paralled with Analog Output Current Indicator

Rev 0

28

For more information www.analog.com

LTM4653

TYPICAL APPLICATIONS

ꢄ

ꢃ

ꢂ

ꢁ

ꢀ

0

ꢌꢀ

ꢌꢁ

ꢔꢀ

0

ꢀ

ꢁ

ꢂ

ꢃ

ꢄ

ꢅ

ꢆ

ꢇ

ꢈꢉꢈꢊꢋ ꢉꢌꢈꢍꢌꢈ ꢎꢌRRꢏꢐꢈ ꢑꢊꢒ

ꢃꢅꢄꢂ ꢓꢂꢂ

Figure 33. Current Sharing Performance of LTM4ꢀ53s in Figure 32 Circuit

Rꢈꢎ

ꢊꢆꢃꢄꢅꢆ

ꢆ

ꢇꢈꢉ

ꢊꢆꢃꢄꢅꢆ

ꢋ

ꢆ

ꢇꢈꢉ

ꢊꢆꢃꢄꢅꢆ

ꢌꢍꢇꢇꢄ

ꢊꢆꢃꢄꢅꢆ

ꢀꢁꢂꢃ ꢄꢃꢀ

ꢀꢁꢂꢃꢄꢅꢆ

Figure 34. Concurrent 12V Supply, Output Voltage Start-Up Waveforms, Figure 35 Circuit

Rev 0

29

For more information www.analog.com

LTM4653

PACKAGE PHOTOGRAPH

PACKAGE DESCRIPTION

Table 9. LTM4ꢀ53 Component BGA Pinout

PIN ID

A1

FUNCTION

PIN ID

B1

FUNCTION

CLKIN

NC

PIN ID

C1

FUNCTION

IMONb

PIN ID

D1

FUNCTION

PGOOD

PGDFB

VINREG

GND

PIN ID

E1

FUNCTION

COMPb

PIN ID

F1

FUNCTION

ISETb

V

IN

V

IN

V

IN

A2

B2

C2

IMONa

D2

E2

COMPa

F2

ISETa

A3

B3

V

C3

SV

D3

E3

f

F3

EXTV

CC

IN

SET

A4

V

D

B4

V

D

C4

V

D

D4

E4

SGND

PGND

NC

F4

RUN

PGND

NC

A5

PGND

NC

B5

PGND

NC

C5

PGND

NC

D5

PGND

NC

E5

F5

A6

B6

C6

D6

E6

F6

A7

NC

B7

NC

C7

NC

D7

NC

E7

NC

F7

NC

PIN ID

G1

FUNCTION

PIN ID

H1

FUNCTION

PIN ID

J1

FUNCTION

PIN ID

K1

FUNCTION

PIN ID

L1

FUNCTION

+

V

OSNS

TEMP

V

OSNS

OUT

–

G2

SGND

INTV

H2

SGND

PGND

SW

J2

TEMP

K2

L2

G3

H3

J3

PGND

K3

L3

CC

G4

PGND

NC

H4

J4

K4

PGND

NC

L4

PGND

NC

G5

H5

PGND

NC

J5

K5

L5

+

G6

H6

J6

TEMP

K6

L6

–

G7

NC

H7

NC

J7

TEMP

K7

NC

L7

NC

Rev 0

30

For more information www.analog.com

LTM4653

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/product/LTM4ꢀ53#packaging for the most recent package drawings.

ꢓ

ꢷ ꢷ ꢯ ꢯ ꢯ

ꢓ

ꢪ ꢥ ꢞ ꢎ 0

ꢟ ꢥ ꢜ ꢋ 0

ꢎ ꢥ ꢟ ꢰ 0

0 ꢥ ꢪ ꢎ ꢰ ꢜ

ꢎ ꢥ ꢟ ꢰ 0

0 ꢥ 0 0 0

ꢟ ꢥ ꢜ ꢋ 0

ꢪ ꢥ ꢞ ꢎ 0

Rev 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog

Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications

31

subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

For more information www.analog.com

LTM4653

TYPICAL APPLICATION

I

OUT

V

OUT

12V

V

IN

15V TO 46V

V

NC

SW

V

IN

OUT

C

INH1

4.7μF

UP TO 4A

V

OSNS

SV

IN

C

22µF

×2

OUTH

R

105k

A

LOAD

V

D

C

4.7μF

D1

GND

SGND

PGND

RUN

U1

LTM4653

INTV

CC1

R

PGDFB1

95.3k

CLKIN

R

PGDPUP

100Ω

INTV

CC

CC1

PGDFB

PGOOD

EXTV

PGOOD

VINREG

CC

R

EXTVCC1

49.9Ω

COMPa

COMPb

TEMP+

C

TH

C

1µF

TEMP–

IMONa

EXTVCC1

10nF

TH

R

499Ω

ANALOG OUTPUT

CURRENT INDICATOR,

f

SET

ISETa

ISETb IMONb

V

IMON

= 0.25Ω • I

OUT

C

R

124k

SS

ISET1

fSET1

10nF 240k

V

NC

SW

IN

C

INH2

4.7µF

PGOOD

GND

C

SV

IN

SNS

INOUT

4.7µF

GND

V

D

C

DGND

4.7µF

PGND

C

OUT2

22µF

LOAD

U2

LTM4651

D1*

–

V

OUT

–12V

UP TO 3.25A

–

V

SV

C

D2

4.7µF

OUT

–

OUT

RUN

R

PGDFB2

95.3k

CLKIN

R

B

PGDFB

INTV

CC

10k

R

EXTVCC2

49.9Ω

VINREG

COMPa

EXTV

CC

+

TEMP

COMPb

R

–

TRACK

10k

TEMP

f

SET

ISETa ISETb

C

R

EXTVCC2

1µF

fSET2

124k

ISET2

240k||10k

*D1: CENTRAL SEMI

P/N CMMSH1-40L

4653 F35

Figure 35. Concurrent 12V Supply. See Figure 34 for Output Voltage Start-Up Waveforms

RELATED PARTS

PART NUMBER DESCRIPTION

COMMENTS

LTM4651

LTM8045

LTM8049

EN55022B Compliant, 58Vin, 24W Inverting-Output

3.6V ≤ Vin ≤ 58V, -26.5V ≤ Vout ≤ -0.5V, Iout ≤ 4A. 15mm x 9mm x

5.01mm BGA

μModule Regulator

SEPIC or Inverting µModule DC/DC Converter

2.8V ≤ V ≤ 18V, 2.5V ≤ V

≤

15V. I

≤ 700mA. 6.25mm ×

IN

OUT

OUT(DC)

11.25mm × 4.92mm BGA

Dual, SEPIC and/or Inverting µModule DC/DC Converter 2.6V ≤ V ≤ 20V, 2.5V ≤ V

≤

24V. I

≤ 1A/Channel. 9mm ×

IN

OUT

OUT(DC)

15mm × 2.42mm BGA

LTM8073

LTM8064

LTM4613

60V, 3A Step-Down µModule Regulator

3.4V ≤ V ≤ 60V, 0.8V ≤ V

≤ 15V. 6.25mm × 9mm × 3.32mm BGA

IN

OUT

58V, 6A CVCC Step-Down µModule Regulator

EN55022B Compliant, 36V, 8A µModule Regulator

6V ≤ V ≤ 58V, 1.2V ≤ V

≤ 36V. 11.9mm x 16mm × 4.92mm BGA

≤ 15V. 15mm × 15mm × 4.32mm LGA, and

IN

OUT

5V ≤ V ≤ 36V, 3.3V ≤ V

IN

OUT

15mm × 15mm × 4.92mm BGA

Rev 0

D16803-0-4/18(0)

www.analog.com

32

 ANALOG DEVICES, INC. 2018

For more information www.analog.com


型号：	LTM4653
厂家：	Linear
描述：	EN55022B Compliant 58V, 4A Step-Down DC/DC Î¼Module Regulator
文件：	总32页 (文件大小：1422K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTM4653 [Linear]

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