LTC5599_15 [Linear]
30MHz to 1300MHz Low Power Direct Quadrature Modulator;
| 型号： | LTC5599_15 |
| 厂家： | 
Linear |
| 描述： | 30MHz to 1300MHz Low Power Direct Quadrature Modulator |
| 文件： | 总42页 (文件大小：2025K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC5599
30MHz to 1300MHz
Low Power
Direct Quadrature Modulator
DescripTion
FeaTures
The LTC®5599 is a direct conversion I/Q modulator de-
signed for low power wireless applications that enable
direct modulation of differential baseband I and Q signals
onanRFcarrier.Singleside-bandmodulationorside-band
suppressed upconversion can be achieved by applying
90° phase-shifted signals to the I and Q inputs. The I/Q
baseband input ports can be either AC or DC coupled to a
source with a common mode voltage level of about 1.4V.
The SPI interface controls the supply current, modulator
gain,andallowsoptimizationoftheLOcarrierfeedthrough
and side-band suppression, with sine wave or square
wave LO drive. A fixed LC network on the LO and RF ports
covers a continuous 90MHz to 1300MHz operation. An
on-chip thermometer can be activated to compensate for
gain-temperature variations. More accurate temperature
measurements can be made using an on-chip diode. In
addition, a continuous analog gain control (VCTRL) pin
can be used for fast power control.
n
Frequency Range: 30MHz to 1300MHz
n
Low Power: 2.7V to 3.6V Supply; 28mA
n
Low LO Carrier Leakage: –51.5dBm at 500MHz
n
Side-Band Suppression: –52.6dBc at 500MHz
n
Output IP3: 20.8dBm at 500MHz
n
Low RF Output Noise Floor: –156dBm/Hz at 6MHz
Offset, P = 3dBm
RF
n
Sine Wave or Square Wave LO Drive
n
SPI Control:
Adjustable Gain: –19dB to 0dB in 1dB Steps
Effecting Supply Current from 8mA to 35mA
I/Q Offset Adjust: –65dBm LO Carrier Leakage
I/Q Gain/Phase Adjust: –60dBc Side-Band Suppressed
n
24-Lead QFN 4mm × 4mm Package
applicaTions
n
Wireless Microphones
n
Battery Powered Radios
L, LT, LTC, LTM, Linear Technology, and the Linear logo are registered trademarks and
QuikEval is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners.
n
Ad-Hoc Wireless Infrastructure Networks
n
“White-Space” Transmitters
n
Software Defined Radios (SDR)
n
Military Radios
Typical applicaTion
EVM and Noise Floor vs RF Output
90MHz to 1300MHz Direct Conversion Transmitter Application
Power and Digital Gain Setting
with 1Ms/s 16-QAM Signal
V
CTRL
3.3V
10
1nF + 4.7µF
DG = –19
DG = –16
DG = –12
DG = –8
DG = –4
DG = 0
9
8
7
6
5
4
3
2
1
0
–105
–115
–125
–135
V
CC
LTC5599
SPI
RF = 90MHz
to 1300MHz
V
V
I
I
I-DAC
I-CHANNEL
10nF
PA
0°
–145
–155
EN
90°
Q-DAC
Q-CHANNEL
–165
THERMOMETER
TTCK
–15
–10
–5
0
5
BASEBAND
GENERATOR
RF OUTPUT POWER (dBm)
5599 TA01b
39nH
VCO/SYNTHESIZER
5599 TA01a
15pF
5599f
1
For more information www.linear.com/LTC5599
LTC5599
absoluTe MaxiMuM raTings
pin conFiguraTion
(Note 1)
TOP VIEW
Supply Voltage.........................................................3.8V
Common Mode Level of BBPI, BBMI,
24 23 22 21 20 19
and BBPQ, BBMQ........................................................2V
LOL, LOC DC Voltage ............................................. 0.1V
LOL, LOC Input Power (Note 15)..........................20dBm
Current Sink of TEMP, SDO....................................10mA
V
1
2
3
4
5
6
18 GNDRF
CTRL
GND
GNDRF
RF
17
16
GND
25
LOL
LOC
GND
15 GNDRF
GNDRF
Voltage on Any Pin (Note 16)...........–0.3V to V + 0.3V
CC
14
13 GNDRF
T
JMAX
.................................................................... 150°C
TTCK
Case Operating Temperature Range........–40°C to 105°C
Storage Temperature Range .................. –65°C to 150°C
7
8
9 10 11 12
UF PACKAGE
24-LEAD (4mm × 4mm) PLASTIC QFN
T
= 150°C, θ = 43°C/W, θ = 4.5°C/W (AT EXPOSED PAD)
JA JC
JMAX
EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB
orDer inForMaTion
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
CASE TEMPERATURE RANGE
LTC5599IUF#PBF
LTC5599IUF#TRPBF
5599
–40°C to 105°C
24-Lead (4mm × 4mm) Plastic QFN
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
Please refer to: http://www.linear.com/designtools/packaging/ for the most recent package drawings.
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TC = 25°C. VCC = 3.3V, EN = 3.3V, VCTRL = 3.3V, PLO = 0dBm, BBPI, BBMI, BBPQ,
BBMQ common mode DC voltage VCMBB = 1.4VDC, I and Q baseband input signal = 2MHz, 2.1MHz, 1VP-P(DIFF, I or Q), I and Q 90°
shifted, lower sideband selection, all registers set to default values, unless otherwise noted. Test circuit is shown in Figure 13.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
f
LO
= 150MHz, f
= 147.9MHz, f = 148MHz, Register 0x00 = 0x62
RF2
RF1
S
RF Port Return Loss
–26
116 to 272
–7.5
dB
MHz
22(ON)
f
LO Match Frequency Range
Conversion Voltage Gain
Absolute Output Power
Output 1dB Compression
Output 2nd Order Intercept
Output 3rd Order Intercept
RF Output Noise Floor
S11 < –10dB
LO(MATCH)
Gain
20 • Log (V
/V
)
dB
RF(OUT)(50Ω) IN(DIFF)(I or Q)
P
OUT
1V
P-P(DIFF)
CW Signal, I and Q
–3.5
dBm
dBm
dBm
dBm
dBm/Hz
dBc
OP1dB
OIP2
OIP3
NFloor
SB
5
(Note 5)
(Note 6)
70.5
21.7
No Baseband AC Input Signal (Note 3)
(Note 7)
–155.3
–61.4
Side-Band Suppression
LOFT
Carrier Leakage (LO Feedthrough) (Note 7)
EN = Low (Note 7)
–52.8
–84.8
dBm
dBm
2LOFT
LO Feedthrough at 2xLO
–59
dBm
5599f
2
For more information www.linear.com/LTC5599
LTC5599
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TC = 25°C. VCC = 3.3V, EN = 3.3V, VCTRL = 3.3V, PLO = 0dBm, BBPI, BBMI, BBPQ,
BBMQ common mode DC voltage VCMBB = 1.4VDC, I and Q baseband input signal = 2MHz, 2.1MHz, 1VP-P(DIFF, I or Q), I and Q 90°
shifted, lower sideband selection, all registers set to default values, unless otherwise noted. Test circuit is shown in Figure 13.
SYMBOL
PARAMETER
CONDITIONS
Maximum of 2f – 2f ; 2f – f ; 2f + f ,
BB
MIN
TYP
MAX
UNITS
2LO
Signal Powers at 2xLO
–51
dBc
LO
BB
LO
BB
LO
2f + 2f
LO
BB
3LOFT
3LO
LO Feedthrough at 3xLO
Signal Powers at 3xLO
–57
–10.7
15
dBm
dBc
Maximum of 3f – f ; 3f + f
BB
LO
BB
LO
BW1dB
BW3dB
–1dB Baseband Bandwidth
–3dB Baseband Bandwidth
R
R
= 50Ω, Differential
= 50Ω, Differential
MHz
MHz
BB
SOURCE
SOURCE
28
BB
f
LO
= 500MHz, f
= 497.9MHz, f
= 498MHz, Register 0x00 = 0x2D
RF1
RF2
S
RF Port Return Loss
–26
180 to 1900
–7.7
dB
MHz
dB
22(ON)
f
LO Match Frequency Range
Conversion Voltage Gain
Absolute Output Power
Output 1dB Compression
Output 2nd Order Intercept
Output 3rd Order Intercept
RF Output Noise Floor
S11 < –10dB
LO(MATCH)
Gain
20 • Log (V
/V
)
RF(OUT)(50Ω) IN(DIFF)(I or Q)
P
OUT
1V
P-P(DIFF)
CW Signal, I and Q
–3.7
dBm
dBm
dBm
dBm
OP1dB
OIP2
5.0
(Note 5)
(Note 6)
63.6
OIP3
20.8
NFloor
No Baseband AC Input Signal (Note 3)
= 3dBm (Note 3)
–156.7
–156.0
dBm/Hz
dBm/Hz
P
OUT
SB
Side-Band Suppression
(Note 7)
–52.6
dBc
LOFT
Carrier Leakage (LO Feedthrough) (Note 7)
EN = Low (Note 7)
–51.5
–67.5
dBm
dBm
2LOFT
2LO
LO Feedthrough at 2xLO
Signal Powers at 2xLO
–61
–51
dBm
dBc
Maximum of 2f – 2f ; 2f – f ; 2f + f ,
LO BB
LO
BB
LO
BB
2f + 2f
LO
BB
3LOFT
3LO
LO Feedthrough at 3xLO
Signal Powers at 3xLO
–62
–11.8
29
dBm
dBc
Maximum of 3f – f ; 3f + f
BB
LO
BB
LO
BW1dB
BW3dB
–1dB Baseband Bandwidth
–3dB Baseband Bandwidth
R
R
= 50Ω, Differential
= 50Ω, Differential
MHz
MHz
BB
SOURCE
SOURCE
57
BB
f
LO
= 900MHz, f
= 897.9MHz, f
= 898MHz, Register 0x00 = 0x12
RF1
RF2
S
RF Port Return Loss
–28
223 to 1902
–8.9
dB
MHz
22(ON)
f
LO Match Frequency Range
Conversion Voltage Gain
Absolute Output Power
Output 1dB Compression
Output 2nd Order Intercept
Output 3rd Order Intercept
RF Output Noise Floor
S11 < –10dB
LO(MATCH)
Gain
20 • Log (V
/V
)
dB
RF(OUT)(50Ω) IN(DIFF)(I or Q)
P
OUT
1V
P-P(DIFF)
CW Signal, I and Q
–4.9
dBm
dBm
dBm
dBm
dBm/Hz
dBc
OP1dB
OIP2
OIP3
NFloor
SB
4.1
(Note 5)
(Note 6)
63.5
18.4
No Baseband AC Input Signal (Note 3)
(Note 7)
–155.6
–61.3
Side-Band Suppression
LOFT
Carrier Leakage (LO Feedthrough) (Note 7)
EN = Low (Note 7)
–58.6
–62.3
dBm
dBm
2LOFT
2LO
LO Feedthrough at 2xLO
Signal Powers at 2xLO
–59
–51
dBm
dBc
Maximum of 2f – 2f ; 2f – f ; 2f + f ,
BB
LO
BB
LO
BB
LO
2f + 2f
LO
BB
5599f
3
For more information www.linear.com/LTC5599
LTC5599
The l denotes the specifications which apply over the full operating
elecTrical characTerisTics
temperature range, otherwise specifications are at TC = 25°C. VCC = 3.3V, EN = 3.3V, VCTRL = 3.3V, PLO = 0dBm, BBPI, BBMI, BBPQ,
BBMQ common mode DC voltage VCMBB = 1.4VDC, I and Q baseband input signal = 2MHz, 2.1MHz, 1VP-P(DIFF, I or Q), I and Q 90°
shifted, lower sideband selection, all registers set to default values, unless otherwise noted. Test circuit is shown in Figure 13.
SYMBOL
3LOFT
3LO
PARAMETER
CONDITIONS
MIN
TYP
–60
–19.2
37
MAX
UNITS
dBm
dBc
LO Feedthrough at 3xLO
Signal Powers at 3xLO
–1dB Baseband Bandwidth
–3dB Baseband Bandwidth
Maximum of 3f – f ; 3f + f
BB
LO
BB
LO
BW1dB
BW3dB
R
R
= 50Ω, Differential
= 50Ω, Differential
MHz
MHz
BB
BB
SOURCE
SOURCE
69
Variable Gain Control (V
)
CTRL
V
R
Gain Control Voltage Range
Gain Control Response Time
Gain Control Input Impedance
DC Input Current
Set Bit 6 in Register 0x01
0.9 to 3.3
V
ns
pF
CTRL
Set Bit 6 in Register 0x01 (Note 8)
Set Bit 6 in Register 0x01
20
10
t
CTRL
Z
CTRL
CTRL
I
Set Bit 6 in Register 0x01
Clear Bit 6 in Register 0x01
2.58
0
mA
mA
Baseband Inputs (BBPI, BBMI, BBPQ, BBMQ)
V
DC Common Mode Voltage
Input Resistance
Internally Generated
1.42
1.8
V
kΩ
Ω
CMBB
R
R
Differential
IN(DIFF)
IN(CM)
Common Mode Input Resistance
Baseband Leakage Current
Amplitude Swing
Four Baseband Pins Shorted
Four Baseband Pins Shorted, EN = Low
350
1.3
I
nA
BB(OFF)
V
No Hard Clipping, Single-Ended, Digital Gain
(DG) = –10
1.2
V
P-P
SWING
Power Supply (V
)
CC
V
V
Supply Voltage
2.7
1.6
20
3.3
1.3
3.6
37
9
V
V
CC
Minimum Data Retention Voltage
Supply Current
(Note 14)
RET(MIN)
CC(ON)
CC(RANGE)
CC(OFF)
ON
I
I
I
t
t
t
t
EN = High
28
mA
mA
µA
ns
Supply Current Range
Supply Current, Sleep Mode
Turn-On Time
EN = High, Register 0x01 from 0x00 to 0x13
EN = 0V
8 to 36
0.7
EN = Low to High (Notes 8, 12)
EN = High to Low (Notes 9, 12)
Register 0x00 Change, <–50dBc (Note 12)
Register 0x02 Change, <–60dBm (Note 12)
167
53
Turn-Off Time
ns
OFF
Side-Band Suppression Settling
LO Suppression Settling
500
90
ns
SB
ns
LO
Serial Port (CSB, SCLK, SDI, SDO), Enable (EN) and TTCK, SCLK = 20MHz
l
l
V
V
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Output High Voltage
Output Low Voltage
SDO Leakage Current
Input Trip Point Hysteresis
SCLK High Time
1.1
V
V
IH
IL
0.2
0.7
I
IH
I
IL
0.02
–0.4
nA
nA
V
l
l
V
V
(Note 13)
= 8mA (Note 10)
VCC_L – 0.2
OH
I
V
OL
SINK
I
OH
for SDO = High
0.5
110
25
nA
mV
ns
V
HYS
CKH
l
t
22.5
5599f
4
For more information www.linear.com/LTC5599
LTC5599
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TC = 25°C. VCC = 3.3V, EN = 3.3V, VCTRL = 3.3V, PLO = 0dBm, BBPI, BBMI, BBPQ,
BBMQ common mode DC voltage VCMBB = 1.4VDC, I and Q baseband input signal = 2MHz, 2.1MHz, 1VP-P(DIFF, I or Q), I and Q 90°
shifted, lower sideband selection, all registers set to default values, unless otherwise noted. Test circuit is shown in Figure 13.
SYMBOL
PARAMETER
CONDITIONS
MIN
20
30
20
10
45
45
20
TYP
MAX
UNITS
ns
l
l
l
l
l
l
l
t
t
t
t
t
t
f
CSB Setup Time
CSS
CSH
CS
CSB High Time
ns
SDI to SCLK Setup Time
SDI to SCLK Hold Time
SCLK to SDO Time
SCLK Duty Cycle
ns
ns
CH
ns
DO
50
55
%
C%
CLK
Maximum SCLK Frequency
Temperature Diode Voltage
Temperature Slope
MHz
mV
mV/°C
V
TEMP
I
I
= 100µA
= 100µA
763
1.6
TEMP
TEMP
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
pull-up resistor and V
connected to.
Note 11: I and Q baseband Input signal = 2MHz CW, 0.8V
the digital supply voltage to which R
is
CC_L
PULL-UP
each,
P-P, DIFF
I and Q 0° shifted.
Note 2: The LTC5599 is guaranteed functional over the operating case
temperature range from –40°C to 105°C.
Note 3: At 6MHz offset from the LO signal frequency. 100nF between BBPI
and BBMI, 100nF between BBPQ and BBMQ.
Note 12: f = 500MHz, P = 0dBm, C4 = 1.5nF
LO
LO
Note 13: Maximum V is derated for capacitive load using the following
OH
formula: V
time of one SCLK cycle, R
• exp (–0.5 • T /(R
• C
), with T
the
CC_L
CLK
PULL-UP
LOAD
CLK
the SDO pull-up resistor, V
the
PULL-UP
CC_L
Note 4: The Default Register Settings are listed in Table 1.
digital supply voltage to which R
capacitive load at the SDO pin. For example for T
is connected to, and C
the
PULL-UP
LOAD
= 100ns (10MHz
CLK
Note 5: IM2 is measured at f – 4.1MHz.
LO
SCLK), R
= 1kΩ, C
= 10pF and V
= 3.3V the derating is 3.3
PULL-UP
LOAD
CC_L
Note 6: IM3 is measured at f – 2.2MHz and f – 1.9MHz. OIP3 = lowest
LO
LO
• exp(–5) = 22.2mV, thus maximum V = 3.3V – 0.1 – 0.0222 = 3.177V.
OH
of (1.5 • P{f – 2.1MHz} – 0.5 • P{f – 2.2MHz}) and (1.5 • P{f – 2MHz}
LO
LO
LO
Note 14: Minimum V in order to retain register data content.
CC
– 0.5 • P{f – 1.9MHz}).
LO
Note 15: Guaranteed by design and characterization. This parameter is not
tested.
Note 16: RF pin guaranteed by design while using a 10nF coupling
capacitor. The RF pin is not tested.
Note 7: Without side-band or LO feedthrough nulling (unadjusted).
Note 8: RF power is within 10% of final value.
Note 9: RF power is at least 30dB down from its ON state.
Note 10: V voltage scales linear with current sink. For example for
OL
R
= 1kΩ, V
= 3.3V the SDO sink current is about (3.3 – 0.2)
PULL-UP
CC_L
/1kΩ = 3.1mA. Max V = 0.7 • 3.1/8 = 0.271V, with R
the SDO
OL
PULL-UP
5599f
5
For more information www.linear.com/LTC5599
LTC5599
Typical perForMance characTerisTics VCC = 3.3V, EN = 3.3V, VCTRL = 3.3V, TC = 25°C,
= 500MHz, BBPI, BBMI, BBPQ, BBMQ common mode DC voltage VCMBB = 1.4VDC, I and Q baseband input signal = 2MHz,
LO
PLO = 0dBm,
f
2.1MHz, 1VP-P(DIFF, I or Q), I and Q 90° shifted, lower sideband selection, TEMPUPDT = 0, register 0x00 value according to Table 5, all
other registers set to default values, unless otherwise noted. Test circuit is shown in Figure 13.
Supply Current vs Digital
Gain Setting
Gain vs RF Frequency and
Digital Gain Setting
Supply Current vs Supply Voltage
36
34
32
30
28
26
24
22
20
0
–5
DIGITAL GAIN SETTING (DG) = 0
–40°C
–10°C
25°C
85°C
105°C
2.7V, 25°C
3.3V, 25°C
3.6V, 25°C
3.3V, 85°C
3.3V, –40°C
(REGISTER 0x01 = 0x00)
40
30
20
10
0
–10
–15
–20
–25
DIGITAL GAIN SETTING (DG) = –19
(REGISTER 0x01 = 0x13)
–30
2.7
3
3.3
3.6
–19 –17 –15 –13 –11 –9 –7 –5 –3 –1
50
250
450
650
850 1050 1250
SUPPLY VOLTAGE (V)
DIGITAL GAIN SETTING
RF FREQUENCY (MHz)
5599 G01
5599 G02
5599 G03
Output IP3 vs RF Frequency and
Digital Gain Setting
Output IP2 vs RF Frequency and
Digital Gain Setting
LO Leakage vs RF Frequency and
Digital Gain Setting
80
70
60
50
40
–40
–50
–60
–70
–80
DG 0
DG –1
DG –2
DG –3
DG –4
DG –5
DG –6
DG –7
DG –8
DG 0
DG 0
DG –1
DG –2
DG –3
DG –4
DG –5
DG –6
DG –7
DG –8
DG –9
DG –10
DG –11
DG –12
DG –13
DG –14
DG –15
DG –16
DG –17
DG –18
DG –19
DG –1
DG –2
DG –3
DG –4
DG –5
DG –6
DG –7
DG –8
DG –9
DG –10
DG –11
DG –12
DG –13
DG –14
DG –15
DG –16
DG –17
DG –18
DG –19
20
15
10
5
DG –9
DG –10
DG –11
DG –12
DG –13
DG –14
DG –15
DG –16
DG –17
DG –18
DG –19
0
50
250
450
650
850 1050 1250
50
250
450
RF FREQUENCY (MHz)
50
250 450
650 850 1050 1250
RF FREQUENCY (MHz)
650
850 1050 1250
RF FREQUENCY (MHz)
5599 G04
5599 G06
5599 G05
Side-Band Suppression vs RF
Frequency and Digital Gain Setting
Side-Band Suppression vs LO
Frequency for Gain TempComp Off
Side-Band Suppression vs LO
Frequency for Gain TempComp On
–10
–20
–30
–40
–50
–60
–70
–30
–40
–50
–60
–70
–30
–40
–50
–60
–70
DG 0
3.3V, 25°C
2.7V, 25°C
3.3V, 105°C
3.3V, –40°C
3.6V, 25°C
3.3V, 85°C
3.3V, –10°C
3.3V, 25°C
2.7V, 25°C
3.3V, 105°C
3.3V, –40°C
3.6V, 25°C
3.3V, 85°C
3.3V, –10°C
DG –1
DG –2
DG –3
DG –4
DG –5
DG –6
DG –7
DG –8
DG –9
DG –10
DG –11
DG –12
DG –13
DG –14
DG –15
DG –16
DG –17
DG –18
DG –19
TEMPUPDT = 1
50
250 450
650
850 1050 1250
50
250
450
650
50
250
450
650
850 1050 1250
850 1050 1250
RF FREQUENCY (MHz)
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
5599 G07
5599 G08
5599 G09
5599f
6
For more information www.linear.com/LTC5599
LTC5599
Typical perForMance characTerisTics VCC = 3.3V, EN = 3.3V, VCTRL = 3.3V, TC = 25°C,
= 500MHz, BBPI, BBMI, BBPQ, BBMQ common mode DC voltage VCMBB = 1.4VDC, I and Q baseband input signal = 2MHz,
LO
PLO = 0dBm,
f
2.1MHz, 1VP-P(DIFF, I or Q), I and Q 90° shifted, lower sideband selection, TEMPUPDT = 0, register 0x00 value according to Table 5, all
other registers set to default values, unless otherwise noted. Test circuit is shown in Figure 13.
Output 1dB Compression Point vs
RF Frequency and Digital Gain
Setting and 3.6V Supply
Output 1dB Compression Point vs
RF Frequency and Digital Gain
Setting and 3.3V Supply
Noise Floor vs RF Frequency and
Digital Gain Setting
–140
–145
–150
–155
–160
–165
DG 0
DG 0
DG –1
DG –2
DG –3
DG –4
DG –5
DG –6
DG –7
DG –8
DG –9
DG –10
DG –11
DG –12
DG –13
DG –14
DG –15
DG –16
DG –17
DG –18
DG –19
DG –1
DG –2
DG –3
DG –4
DG –5
DG –6
DG –7
DG –8
DG –9
DG –10
DG –11
DG –12
DG –13
DG –14
DG –15
DG –16
DG –17
DG –18
DG –19
6
2
6
2
DIGITAL GAIN SETTING = 0
(REGISTER 0x01 = 0x00)
–2
–6
–10
–2
–6
–10
DIGITAL GAIN SETTING = –19
(REGISTER 0x01 = 0x13)
–170
50
250
450
650
850 1050 1250
50
250
450
650
850 1050 1250
50
250
450
650
850 1050 1250
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
5599 G11
5599 G12
5599 G10
Output 1dB Compression Point vs
RF Frequency and Digital Gain
Setting and 2.7V Supply
Output 1dB Compression Point vs
RF Frequency and Digital Gain
Setting at –10°C
Output 1dB Compression Point vs
RF Frequency and Digital Gain
Setting at –40°C
DG 0
DG 0
DG 0
DG –1
DG –2
DG –3
DG –4
DG –5
DG –6
DG –7
DG –8
DG –9
DG –10
DG –11
DG –12
DG –13
DG –14
DG –15
DG –16
DG –17
DG –18
DG –19
DG –1
DG –2
DG –3
DG –4
DG –5
DG –6
DG –7
DG –8
DG –9
DG –10
DG –11
DG –12
DG –13
DG –14
DG –15
DG –16
DG –17
DG –18
DG –19
DG –1
DG –2
DG –3
DG –4
DG –5
DG –6
DG –7
DG –8
DG –9
DG –10
DG –11
DG –12
DG –13
DG –14
DG –15
DG –16
DG –17
DG –18
DG –19
6
2
6
6
2
2
–2
–2
–6
–10
–2
–6
–10
–6
–10
50
250
450
650
850 1050 1250
50
250
450
650
850 1050 1250
50
250
450
650
850 1050 1250
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
5599 G13
5599 G14
5599 G15
Output 1dB Compression Point vs
RF Frequency and Digital Gain
Setting at 105°C
Output 1dB Compression Point vs
RF Frequency and Digital Gain
Setting at 85°C
Gain vs RF Frequency and VCTRL
0
DG 0
DG 0
DG –1
DG –2
DG –3
DG –4
DG –5
DG –6
DG –7
DG –8
3.3V
1.8V
DG –1
DG –2
DG –3
DG –4
DG –5
DG –6
DG –7
DG –8
DG –9
DG –10
DG –11
DG –12
DG –13
DG –14
DG –15
DG –16
DG –17
DG –18
DG –19
6
6
1.6V
–20
–40
–60
–80
1.45V
2
–2
2
–2
–6
1.35V
DG –9
1.25V
DG –10
DG –11
DG –12
DG –13
DG –14
DG –15
DG –16
DG –17
DG –18
DG –19
1.15V
1V
–6
AGCTRL = 1
850 1050 1250
RF FREQUENCY (MHz)
–10
–10
50
–100
50
50
250
450
650
850 1050 1250
250
450
650
850 1050 1250
250
450
650
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
5599 G16
5599 G17
5599 G18
5599f
7
For more information www.linear.com/LTC5599
LTC5599
Typical perForMance characTerisTics VCC = 3.3V, EN = 3.3V, VCTRL = 3.3V, TC = 25°C,
= 500MHz, BBPI, BBMI, BBPQ, BBMQ common mode DC voltage VCMBB = 1.4VDC, I and Q baseband input signal = 2MHz,
LO
PLO = 0dBm,
f
2.1MHz, 1VP-P(DIFF, I or Q), I and Q 90° shifted, lower sideband selection, TEMPUPDT = 0, register 0x00 value according to Table 5, all
other registers set to default values, unless otherwise noted. Test circuit is shown in Figure 13.
Input IP3 vs RF Frequency and
VCTRL
Input IP2 vs RF Frequency
and VCTRL
Noise Floor vs RF Frequency and
VCTRL
40
30
20
10
0
80
70
60
50
40
30
20
10
3.3V
2V
3.3V
–150
–154
–158
–162
–166
1.8V
1.9V
1.85V
1.8V
1.75
1.65
1.6V
1.55V
1.5V
1.45V
1.4V
1.3V
1V
1.8V
1.6V
1.45V
3.3V
1.6V
1.45V
1.35V
1.15V
1.35V
1.25V
1V
1.25V
1.15V
1V
AGCTRL = 1
850 1050 1250
RF FREQUENCY (MHz)
AGCTRL = 1
50
250
450
650
50
250
450
650
850 1050 1250
50
250
450
650
850 1050 1250
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
5599 G19
5599 G20
5599 G21
Noise Floor vs RF Power
Noise Floor vs VCTRL Gain
Noise Floor vs RF Frequency
–140
–144
–148
–152
–156
–160
–152
–154
–156
–158
–160
–162
–164
–150
–154
3.3V, 25°C
3.3V, 25°C
3.6V, 25°C
2.7V, 25°C
3.3V, 85°C
3.3V, 105°C
3.3V, –10°C
3.3V, –40°C
3.6V, 25°C
2.7V, 25°C
3.3V, 85°C
3.3V, 105°C
3.3V, –10°C
3.3V, –40°C
DG = 0
DG = –4
DG = –8
–158
–162
DG = –12
DG = –16
DG = –19
AGCTRL = 1
–166
50
250
450
650
–10 –8 –6 –4 –2
RF POWER (dBm)
2
4
850 1050 1250
0
6
–80 –70 –60 –50
–40 –30 –20 –10
RF FREQUENCY (MHz)
V
CTRL
GAIN (dB)
5599 G22
5599 G23
5599 G24
Output IP3 vs RF Frequency for
30MHz LO Match
Side-Band Suppression vs RF
Frequency for 30MHz LO Match
Gain vs RF Frequency for 30MHz
LO Match
–5
–6
21
20
19
18
17
16
–15
–20
–25
–30
–35
–40
–45
–50
3.3V, 25°C
3.3V, 105°C
3.3V, –40°C
3.3V, 0°C
3.3V, 85°C
3.3V, –10°C
3.3V, 55°C
3.3V, 85°C
3.3V, –10°C
3.3V, 55°C
–7
–8
–9
–10
–11
–12
–13
–14
–15
3.3V, 25°C
3.3V, 105°C
3.3V, –40°C
3.3V, 0°C
3.3V, 85°C
3.3V, –10°C
3.3V, 55°C
3.3V, 25°C
3.3V, 105°C
3.3V, –40°C
3.3V, 0°C
15
20
25
30
35
40
45
50
20
25
30
20
25
30
RF FREQUENCY (MHz)
35
40
45
50
35
40
45
50
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
5599 G25
5599 G26
5599 G27
5599f
8
For more information www.linear.com/LTC5599
LTC5599
Typical perForMance characTerisTics VCC = 3.3V, EN = 3.3V, VCTRL = 3.3V, TC = 25°C,
= 500MHz, BBPI, BBMI, BBPQ, BBMQ common mode DC voltage VCMBB = 1.4VDC, I and Q baseband input signal = 2MHz,
LO
PLO = 0dBm,
f
2.1MHz, 1VP-P(DIFF, I or Q), I and Q 90° shifted, lower sideband selection, TEMPUPDT = 0, register 0x00 value according to Table 5, all
other registers set to default values, unless otherwise noted. Test circuit is shown in Figure 13.
Gain vs RF Frequency for 70MHz
LO Match
Output IP3 vs RF Frequency for
70MHz LO Match
Side-Band Suppression vs RF
Frequency for 70MHz LO Match
–5
–6
23
22
21
20
–10
–20
–30
–40
–50
–60
–70
3.3V, 25°C
3.3V, 105°C
3.3V, –40°C
3.3V, 0°C
3.3V, 85°C
3.3V, –10°C
3.3V, 55°C
3.3V, 25°C
3.3V, 105°C
3.3V, –40°C
3.3V, 0°C
3.3V, 85°C
3.3V, –10°C
3.3V, 55°C
–7
–8
3.3V, 25°C
3.3V, 105°C
3.3V, –40°C
3.3V, 0°C
3.3V, 85°C
3.3V, –10°C
3.3V, 55°C
–9
19
18
–10
50
60
70
80
90
50
60
70
80
90
100 110 120
100 110 120
50
60
70
80
90
100 110 120
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
5599 G28
5599 G29
5599 G30
Gain vs LO Power at fLO = 150MHz
Gain vs LO Power at fLO = 500MHz
Gain vs LO Power at fLO = 900MHz
–6
–10
–14
–18
–22
–6
–10
–14
–18
–22
–6
–10
–14
–18
–22
DIGITAL GAIN = –4
DIGITAL GAIN = –4
DIGITAL GAIN = –4
DIGITAL GAIN = –10
DIGITAL GAIN = –10
DIGITAL GAIN = –10
3.3V
3.6V
2.7V
85°C
3.3V
3.6V
2.7V
85°C
3.3V
3.6V
2.7V
85°C
105°C
–10°C
–40°C
105°C
–10°C
–40°C
105°C
–10°C
–40°C
–10 –8 –6 –4
–10 –8 –6 –4 –2
0
2
4
6
–2
0
2
4
6
–10 –8 –6 –4
–2
0
2
4
6
LO POWER (dBm)
LO POWER (dBm)
LO POWER (dBm)
5599 G31
5599 G33
5599 G32
Gain vs LO Power
at fLO = 1260MHz
Output IP3 vs LO Power
at fLO = 500MHz
Output IP3 vs LO Power
at fLO = 150MHz
–6
–10
–14
–18
–22
23
19
15
11
7
23
19
15
11
7
85°C
3.3V
3.6V
2.7V
DIGITAL GAIN = –4
DIGITAL GAIN = –4
105°C
–10°C
–40°C
DIGITAL GAIN = –4
DIGITAL GAIN = –10
DIGITAL GAIN = –10
3.3V
3.6V
2.7V
85°C
3.3V
3.6V
2.7V
85°C
105°C
–10°C
–40°C
DIGITAL GAIN = –10
105°C
–10°C
–40°C
–10 –8 –6 –4
LO POWER (dBm)
–10 –8 –6 –4 –2
0
2
4
6
–10 –8 –6 –4 –2
0
2
4
6
–2
0
2
4
6
LO POWER (dBm)
LO POWER (dBm)
5599 G34
5599 G35
5599 G36
5599f
9
For more information www.linear.com/LTC5599
LTC5599
Typical perForMance characTerisTics
= 500MHz, BBPI, BBMI, BBPQ, BBMQ common mode DC voltage VCMBB = 1.4VDC, I and Q baseband input signal = 2MHz,
LO
VCC = 3.3V, EN = 3.3V, VCTRL = 3.3V, TC = 25°C,
PLO = 0dBm,
f
2.1MHz, 1VP-P(DIFF, I or Q), I and Q 90° shifted, lower sideband selection, TEMPUPDT = 0, register 0x00 value according to Table 5, all
other registers set to default values, unless otherwise noted. Test circuit is shown in Figure 13.
Output IP3 vs LO Power at
fLO = 900MHz
Output IP3 vs LO Power at
fLO = 1260MHz
Output IP2 vs LO Power at
f
LO = 150MHz
23
19
15
11
7
20
16
12
75
70
65
60
55
50
45
40
3.3V
3.6V
2.7V
85°C
DIGITAL GAIN = –4
DIGITAL GAIN = –4
105°C
–10°C
–40°C
DIGITAL GAIN = –10
DIGITAL GAIN = –4 (SOLID)
DIGITAL GAIN = –10 (DASHED)
8
4
85°C
3.3V
3.6V
2.7V
85°C
DIGITAL GAIN = –10
3.3V
3.6V
2.7V
105°C
–10°C
–40°C
105°C
–10°C
–40°C
0
–10 –8 –6 –4
LO POWER (dBm)
–10 –8 –6 –4
–10 –8 –6 –4
LO POWER (dBm)
–2
0
2
4
6
–2
0
2
4
6
–2
0
2
4
6
LO POWER (dBm)
5599 G37
5599 G38
5599 G39
Output IP2 vs LO Power at
fLO = 500MHz
Output IP2 vs LO Power at
fLO = 1260MHz
Output IP2 vs LO Power at
fLO = 900MHz
75
70
65
75
70
65
75
70
65
DIGITAL GAIN = –4 (SOLID)
DIGITAL GAIN = –10 (DASHED)
DIGITAL GAIN = –4 (SOLID)
DIGITAL GAIN = –10 (DASHED)
DIGITAL GAIN = –4 (SOLID)
DIGITAL GAIN = –10 (DASHED)
85°C
3.3V
3.6V
2.7V
105°C
–10°C
–40°C
60
55
50
45
40
60
55
50
45
40
60
55
50
45
40
85°C
85°C
3.3V
3.6V
2.7V
105°C
–10°C
–40°C
3.3V
3.6V
2.7V
105°C
–10°C
–40°C
–10 –8 –6 –4
LO POWER (dBm)
–10 –8 –6 –4
LO POWER (dBm)
–2
0
2
4
6
–2
0
2
4
6
–10 –8 –6 –4
LO POWER (dBm)
–2
0
2
4
6
5599 G40
5599 G41
5599 G42
LO Leakage vs LO Power at
fLO = 150MHz
LO Leakage vs LO Power at
fLO = 500MHz
LO Leakage vs LO Power at
fLO = 900MHz
–45
–50
–55
–60
–65
–45
–50
–45
–50
–55
–60
3.3V
3.6V
2.7V
85°C
DIGITAL GAIN = –4
DIGITAL GAIN = –4
105°C
–10°C
–40°C
DIGITAL GAIN = –4
DIGITAL GAIN = –10
–55
–60
DIGITAL GAIN = –10
3.3V
3.6V
2.7V
85°C
85°C
DIGITAL
GAIN = –10
–65
–70
105°C
–10°C
–40°C
105°C
–10°C
–40°C
3.3V
3.6V
2.7V
–10 –8 –6 –4
–10 –8 –6 –4
LO POWER (dBm)
–2
0
2
4
6
–2
0
2
4
6
–10 –8 –6 –4
LO POWER (dBm)
–2
0
2
4
6
LO POWER (dBm)
5599 G43
5599 G45
5599 G44
5599f
10
For more information www.linear.com/LTC5599
LTC5599
Typical perForMance characTerisTics VCC = 3.3V, EN = 3.3V, VCTRL = 3.3V, TC = 25°C,
= 500MHz, BBPI, BBMI, BBPQ, BBMQ common mode DC voltage VCMBB = 1.4VDC, I and Q baseband input signal = 2MHz,
LO
PLO = 0dBm,
f
2.1MHz, 1VP-P(DIFF, I or Q), I and Q 90° shifted, lower sideband selection, TEMPUPDT = 0, register 0x00 value according to Table 5, all
other registers set to default values, unless otherwise noted. Test circuit is shown in Figure 13.
LO Leakage vs LO Power at
fLO = 1260MHz
Side-Band Suppression vs
LO Power at fLO = 150MHz
Side-Band Suppression vs
LO Power at fLO = 500MHz
–44
–48
–52
–56
–60
–64
–68
–72
–76
–80
–40
–45
–50
–55
–60
–65
–40
–45
–50
–55
–60
–65
DIGITAL GAIN = –4 (SOLID)
DIGITAL GAIN = –10 (DASHED)
DIGITAL GAIN = –4 (SOLID)
DIGITAL GAIN = –10 (DASHED)
DIGITAL GAIN = –4
3.3V
3.6V
2.7V
85°C
105°C
–10°C
–40°C
DIGITAL
GAIN = –10
3.3V
3.6V
2.7V
85°C
85°C
105°C
–10°C
–40°C
105°C
–10°C
–40°C
3.3V
3.6V
2.7V
–10 –8 –6 –4
–10 –8 –6 –4
LO POWER (dBm)
–10 –8 –6
–2
0
2
4
6
–2
0
2
4
6
–4 –2
0
2
4
6
LO POWER (dBm)
LO POWER (dBm)
5599 G46
5599 G47
5599 G48
Side-Band Suppression vs
LO Power at fLO = 900MHz
Side-Band Suppression vs
LO Power at fLO = 1260MHz
Supply Current vs VCTRL Voltage
–40
–45
–50
–55
–60
–65
–40
–41
–42
–43
–44
–45
–46
–47
–48
–49
–50
40
30
DIGITAL GAIN = –4 (SOLID)
DIGITAL GAIN = –10 (DASHED)
20
10
0
2.7V, 25°C
3.3V, 25°C
3.6V, 25°C
3.3V, 85°C
3.3V, –40°C
3.3V, –10°C
DIGITAL GAIN = –4 (SOLID)
DIGITAL GAIN = –10 (DASHED)
85°C
85°C
105°C
–10°C
–40°C
3.3V
3.6V
2.7V
105°C
–10°C
–40°C
3.3V
3.6V
2.7V
AGCTRL = 1
0.9 1.2 1.5 1.8
3.3V, 105°C
2.1 2.4 2.7
VOLTAGE (V)
5599 G51
–10 –8 –6 –4
LO POWER (dBm)
–10 –8 –6 –4
–2
0
2
4
6
–2
0
2
4
6
3
3.3
LO POWER (dBm)
V
CTRL
5599 G49
5599 G50
VCTRL Current vs VCTRL Voltage
Gain vs VCTRL Voltage
Output IP3 vs VCTRL Gain
3.0
2.5
2.0
1.5
0
25
20
15
10
5
AGCTRL = 1
AGCTRL = 1
–20
–40
–60
–80
2.7V, 25°C
3.3V, 25°C
3.6V, 25°C
3.3V, 85°C
3.3V, –40°C
3.3V, –10°C
3.3V, 105°C
2.7V, 25°C
3.3V, 25°C
3.6V, 25°C
3.3V, 85°C
3.3V, –40°C
3.3V, –10°C
3.3V, 105°C
2.7V, 25°C
3.
3.6V, 25°C
3.3V, 85°C
3.3V, –40°C
3.3V, –10°C
3.3V, 105°C
3V, 25°C
0
–5
–10
0.9 1.2 1.5 1.8
0.9 1.2 1.5 1.8
2.1 2.4 2.7
(V)
3
3.3
2.1 2.4 2.7
VOLTAGE (V)
3
3.3
–27
–23
–19
–15
–11
–7
V
V
CTRL
GAIN SET BY V
(dB)
CTRL
CTRL
5599 G52
5599 G53
5599 G54
5599f
11
For more information www.linear.com/LTC5599
LTC5599
Typical perForMance characTerisTics
= 500MHz, BBPI, BBMI, BBPQ, BBMQ common mode DC voltage VCMBB = 1.4VDC, I and Q baseband input signal = 2MHz,
LO
VCC = 3.3V, EN = 3.3V, VCTRL = 3.3V, TC = 25°C,
PLO = 0dBm,
f
2.1MHz, 1VP-P(DIFF, I or Q), I and Q 90° shifted, lower sideband selection, TEMPUPDT = 0, register 0x00 value according to Table 5, all
other registers set to default values, unless otherwise noted. Test circuit is shown in Figure 13.
Side-Band Suppression vs
VCTRL Gain
Output IP2 vs VCTRL Gain
LO Leakage vs VCTRL Gain
70
65
60
55
50
45
40
–30
–40
–50
–60
–70
–80
–20
–25
–30
–35
–40
–45
–50
–55
–60
AGCTRL = 1
2.7V, 25°C
3.3V, 25°C
3.6V, 25°C
3.3V, 85°C
3.3V, –40°C
3.3V, –10°C
3.3V, 105°C
2.7V, 25°C
3.3V, 25°C
3.6V, 25°C
3.3V, 85°C
3.3V, –40°C
3.3V, –10°C
3.3V, 105°C
2.7V, 25°C
3.3V, 25°C
3.6V, 25°C
3.3V, 85°C
3.3V, –40°C
3.3V, –10°C
3.3V, 105°C
AGCTRL = 1
AGCTRL = 1
–27 –17
–17
–15
–13
–77 –67 –57 –47 –37
GAIN SET BY V
–77 –67 –57 –47 –37
GAIN SET BY V
(dB)
CTRL
–11
–9
–7
–27 –17
(dB)
–7
–7
GAIN SET BY V
(dB)
CTRL
CTRL
5599 G55
5599 G56
5599 G57
PRF, IM2, IM3 vs Baseband
Amplitude
Gain Minus Digital Gain vs Digital
Gain Setting
Gain vs Digital Gain Setting
–2
–3
–4
–5
–6
10
–10
–30
–50
–70
–90
2.7V, 25°C
3.3V, 25°C
3.6V, 25°C
3.3V, 85°C
3.3V, –40°C
P
RF
FOR DG = 0, –4, –8, –12, –1
6, –19,
–5
–9
–13
–17
–21
–25
IM3 FOR DG = 0, –19,
–16, –4, –12, –8
2.7V, 25°C
3.3V, 25°C
3.6V, 25°C
3.3V, 85°C
3.3V, –40°C
AGCTRL = 1
IM2 FORDG= 0, –4, –8, –19, –12, –1
6
–19
–15
–11
–7
–3
–19
–15
–11
–7
–3
0.1
1
DIGITAL GAIN SETTING
DIGITAL GAIN SETTING
BASEBAND AMPLITUDE (V
)
PEAK(DIFF)
5599 G58
5599 G59
5599 G60
LO Leakage vs LO Frequency for
Gain TempComp Off
Output IP3 vs Baseband Amplitude
Output IP2 vs Baseband Amplitude
70
60
50
40
30
–40
–45
–50
–55
–60
–65
–70
TEMPUPDT = 1
20
15
10
5
2.7V, 25°C
3.3V, 25°C
3.6V, 25°C
3.3V, 85°C
3.3V, 105°C
0
DG = 0
DG = –8
DG = –16
DG = –4
DG = –12
DG = –19
DG = 0
DG = –8
DG = –16
DG = –4
DG = –12
DG = –19
3.3V, –10°C
3.3V, –40°C
–5
0.1
1
0.1
1
50
250
450
650
850 1050 1250
BASEBAND AMPLITUDE (V
)
BASEBAND AMPLITUDE (V
LO FREQUENCY (MHz)
)
PEAK(DIFF)
PEAK(DIFF)
5599 G61
5599 G62
5599 G63
5599f
12
For more information www.linear.com/LTC5599
LTC5599
Typical perForMance characTerisTics
= 500MHz, BBPI, BBMI, BBPQ, BBMQ common mode DC voltage VCMBB = 1.4VDC, I and Q baseband input signal = 2MHz,
LO
V
CC = 3.3V, EN = 3.3V, VCTRL = 3.3V, TC = 25°C,
PLO = 0dBm,
f
2.1MHz, 1VP-P(DIFF, I or Q), I and Q 90° shifted, lower sideband selection, TEMPUPDT = 0, register 0x00 value according to Table 5, all
other registers set to default values, unless otherwise noted. Test circuit is shown in Figure 13.
Worst-Case LO Leakage Over Five
Parts vs LO Frequency After 25°C
Calibration for Gain TempComp Off
Worst-Case LO Leakage Over Five
Parts vs LO Frequency After 25°C
Calibration for Gain TempComp On
LO Leakage vs LO Frequency for
Gain TempComp On
–40
–50
–60
–70
–80
–40
–50
–60
–70
–80
–40
–45
–50
–55
–60
–65
–70
2.7V, 25°C
3.3V, 25°C
3.6V, 25°C
3.3V, 85°C
3.3V, 105°C
3.3V, 25°C; 3.3V, 85°C; 3.3V, 105°C;
3.3V, –10°C; 3.3V, –40°C; 2.7V, 25°C AND
3.6V, 25°C BETWEEN WORST-CASE AND
BEST-CASE
3.3V, 25°C; 3.3V, 85°C; 3.3V, 105°C;
3.3V, –10°C; 3.3V, –40°C; 2.7V, 25°C AND
3.6V, 25°C BETWEEN WORST-CASE AND
BEST-CASE
3.3V, –10°C
3.3V, –40°C
WORST-CASE: 3.3V, 105°C
WORST-CASE: 3.3V, 105°C
BEST-CASE: 3.3V, 25°C
TEMPUPDT = 1
BEST-CASE: 3.3V, 25°C
50
250
450
650
50
250
450
LO FREQUENCY (MHz)
850 1050 1250
650
850
1050 1250
50
250
450
650
850 1050 1250
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
5599 G65
5599 G66
5599 G64
Worst-Case Side-Band Suppression Over
Five Parts vs LO Frequency After 25°C
Calibration for Gain TempComp Off
LO Leakage vs LO Frequency
and Digital Gain Setting After
Calibration at DG = –4
Worst-Case Side-Band Suppression Over
Five Parts vs LO Frequency After 25°C
Calibration for Gain TempComp On
–30
–40
–50
–60
–70
–30
–40
–50
–60
–70
–40
–50
–60
–70
–80
3.3V, 25°C; 3.3V, 85°C; 3.3V, 105°C;
3.3V, –10°C; 3.3V, –40°C; 2.7V, 25°C AND
3.6V, 25°C BETWEEN WORST-CASE AND
BEST-CASE
3.3V, 25°C; 3.3V, 85°C; 3.3V, 105°C;
3.3V, –10°C; 3.3V, –40°C; 2.7V, 25°C AND
3.6V, 25°C BETWEEN WORST-CASE AND
BEST-CASE
WORST-CASE: 3.3V, 105°C
BEST-CASE: 3.3V, 25°C
DG = –19
DG = –3
DG = 0
DG = –8
WORST-CASE: 3.3V, 105°C
BEST-CASE: 3.3V, 25°C
DG = –4
DG = –17
TEMPUPDT = 1
50
250
450
650
50
250
450
LO FREQUENCY (MHz)
50
250 450
850 1050 1250
650
850
650 850
1050 1250
1050 1250
LO FREQUENCY (MHz)
RF FREQUENCY (MHz)
5599 G67
5599 G68
5599 G69
Side-Band Suppression vs LO
Frequency and Digital Gain Setting
After Calibration at DG = –4
Temperature Sensing Diode
Voltage Cumulative Distribution
Supply Current Cumulative
Distribution
–10
–20
–30
–40
–50
–60
–70
–80
100
80
60
40
20
0
100
80
60
40
20
0
–40°C
105°C
105°C
DG = 0
DG = –19
DG = –12
25°C
25°C
–40°C
DG = –4
DG = –3
850 1050 1250
RF FREQUENCY (MHz)
50
250 450 650
0.6
0.65
0.7
0.75
24
26
28
SUPPLY CURRENT (mA)
0.8
0.85
0.9
30
32
34
DIODE VOLTAGE FOR 100µA (V)
5599 G70
5599 G71
5599 G72
5599f
13
For more information www.linear.com/LTC5599
LTC5599
Typical perForMance characTerisTics VCC = 3.3V, EN = 3.3V, VCTRL = 3.3V, TC = 25°C,
= 500MHz, BBPI, BBMI, BBPQ, BBMQ common mode DC voltage VCMBB = 1.4VDC, I and Q baseband input signal = 2MHz,
LO
PLO = 0dBm,
f
2.1MHz, 1VP-P(DIFF, I or Q), I and Q 90° shifted, lower sideband selection, TEMPUPDT = 0, register 0x00 value according to Table 5, all
other registers set to default values, unless otherwise noted. Test circuit is shown in Figure 13.
Sleep Current Cumulative
Distribution
Gain Cumulative Distribution for
Gain TempComp Off
Gain Cumulative Distribution for
Gain TempComp On
100
80
60
40
20
0
100
80
60
40
20
0
100
80
60
40
20
0
25°C
–40°C
105°C
25°C
25°C
130°C
105°C
–40°C
–40°C
–8.4
–8
–7.6
–7.2
–6.8
–6.4
0
0.2 0.4
–8.4
–8
–7.6
–7.2
–6.8
–6.4
0.6 0.8
1
1.2 1.4 1.6 1.8
2
GAIN (dB)
SLEEP CURRENT (µA)
GAIN (dB)
5599 G74
5599 G73
5599 G75
TEMPUPDT = 1
Gain Cumulative Distribution for
Gain Cumulative Distribution for
VCTRL = 1V
Output IP3 Cumulative Distribution
V
CTRL = 1.75V
100
80
60
40
20
0
100
80
60
40
20
0
100
80
60
40
20
0
NOTE 11
105°C
25°C
–40°C
–40°C
25°C
105°C
105°C
–40°C
25°C
AGCTRL = 1
–12
AGCTRL = 1
–60
–18
–16
–80
–70
15
17
–14
–10
–50
19
21
23
GAIN (dB)
GAIN (dB)
OUTPUT IP3 (dBm)
5599 G76
5599 G77
5599 G78
Output IP2 Cumulative
Distribution
Noise Floor Cumulative
Distribution
LO Leakage Cumulative Distribution
for Floating Baseband Pins
100
80
60
40
20
0
100
80
60
40
20
0
100
80
60
40
20
0
NOTE 11
–40°C
105°C
25°C
–40°C
–40°C
105°C
25°C
105°C
25°C
–160
–158
NOISE FLOOR (dBm/Hz)
–60
–55
–50
LO LEAKAGE (dBm)
–156
–154
–152
–45
–40
–35
50
54
58 62
66
70 74 78
OUTPUT IP2 (dBm)
5599 G80
5599 G81
5599 G79
5599f
14
For more information www.linear.com/LTC5599
LTC5599
Typical perForMance characTerisTics
= 500MHz, BBPI, BBMI, BBPQ, BBMQ common mode DC voltage VCMBB = 1.4VDC, I and Q baseband input signal = 2MHz,
LO
V
CC = 3.3V, EN = 3.3V, VCTRL = 3.3V, TC = 25°C,
PLO = 0dBm,
f
2.1MHz, 1VP-P(DIFF, I or Q), I and Q 90° shifted, lower sideband selection, TEMPUPDT = 0, register 0x00 value according to Table 5, all
other registers set to default values, unless otherwise noted. Test circuit is shown in Figure 13.
LO Leakage Cumulative
Distribution
LO Leakage Cumulative
Side-Band Suppression
Cumulative Distribution
Distribution for VCTRL = 1.75V
100
80
60
40
20
0
100
80
60
40
20
0
100
80
60
40
20
0
AGCTRL = 1
–40°C
105°C
–40°C
105°C
25°C
105°C
25°C
25°C
–40°C
–60
–55
–50
LO LEAKAGE (dBm)
–60 –55 –50
–60
–55
SIDE-BAND SUPPRESSION (dBc)
5599 G84
–45
–40
–35
–45 –40 –35 –30 –25 –20
–50
–45
–40
–35
LO LEAKAGE (dBm)
5599 G82
5599 G83
Side-Band Suppression Cumulative
Distribution for VCTRL = 1.75V
RF Return Loss
100
80
60
40
20
0
0
–5
AGCTRL = 1
25°C
RESONANCE FREQUENCY WITH C4 = 10nF
DG = –19
–10
DG = –18
DG = –17
–15
–20
105°C
–25
–30
–35
–40°C
DG = 0
–60
–55
SIDE-BAND SUPPRESSION (dBc)
10
100
1000
–50
–45
–40
–35
RF FREQUENCY (MHz)
5599 G85
5599 G86
LO Return Loss for 30MHz and
70MHz Match, Schematic in Figure 3
LO Return Loss
0
–5
0
–5
REGISTER 0x00 SET
ACCORDING TO LO
FREQUENCY TABLE 5
–10
–10
70MHz
–15
–20
–15
–20
30MHz
–25
–30
–35
–25
–30
–35
REGISTER 0x00
SET TO 0x7F
10
100
1000
10
100
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
5599 G87
5599 G88
5599f
15
For more information www.linear.com/LTC5599
LTC5599
Typical perForMance characTerisTics
= 500MHz, BBPI, BBMI, BBPQ, BBMQ common mode DC voltage VCMBB = 1.4VDC, I and Q baseband input signal = 2MHz,
LO
VCC = 3.3V, EN = 3.3V, VCTRL = 3.3V, TC = 25°C,
PLO = 0dBm,
f
2.1MHz, 1VP-P(DIFF, I or Q), I and Q 90° shifted, lower sideband selection, TEMPUPDT = 0, register 0x00 value according to Table 5, all
other registers set to default values, unless otherwise noted. Test circuit is shown in Figure 13.
LO Return Loss for Standard,
900MHz and 1260MHz Match
RMS EVM vs RF Output Power
with 1Ms/s 16-QAM Signal
Peak EVM vs RF Output Power
with 1Ms/s 16-QAM Signal
0
–5
20
15
10
5
10
DG = –6
DG = –2
STANDARD REG 0x00 = 0x0A, L1 = 39nH, C5 = 15pF
900MHz REG 0x00 = 0x12, L1 = 8.2nH, C5 = 3.3pF
1260MHz REG 0x00 = 0x01, L1 = 5.6nH, C5 = 3pF
DG = –2
9
8
7
6
5
4
3
2
1
0
DG = –6
DG = 0
DG = –8
DG = –10
DG = –12
DG = –16
DG = –8
DG = –10
DG = 0
STANDARD
–10
DG = –12
DG = –16
–15
–20
900MHz
DG = –19
1260MHz
–25
–30
–35
DG = –19
DG = –4
DG = –4
SOLID: EN = HIGH; DASHED: EN = LOW
0
500 700 900 1100 1300 1500 1700 1900
–20 –16
–12
–8
–4
0
4
–20 –16
–12
–8
–4
0
4
LO FREQUENCY (MHz)
RF POWER (dBm)
RF POWER (dBm)
5599 G89
5599 G91
5599 G90
5599f
16
For more information www.linear.com/LTC5599
LTC5599
pin FuncTions
V
(Pin 1): Variable Gain Control Input. This analog
BBPQ, BBMQ (Pins 10, 11): Baseband Inputs of the
Q-Channel. The input impedance of each input is about
1kΩ. It should be externally biased to a 1.4V common
mode level, or AC-coupled. Do not apply common mode
CTRL
control pin sets the gain. Write a “1” to bit 6 in register
0x01 (AGCTRL = 1) to activate this pin, resulting in about
2.58mAcurrentdrawfromapositivesupply.TypicalV
CTRL
voltage range is 0.9V to 3.3V. Gain transfer function is
voltage beyond 2V . Float if Q-channel is disabled.
DC
not linear-in-dB. Tie to V when not used.
CC
GNDRF (Pins 13, 14, 15, 17, 18): RF Ground. These pins
areconnectedtogetherinternally.ForbestRFperformance
all ground pins should be connected to RF ground.
GND (Pins 2, 5, 12, Exposed Pad 25): Ground. All these
pins are connected together internally. For best RF perfor-
mance all ground pins should be connected to RF ground.
RF (Pin 16): RF Output. The output impedance at RF
frequencies is 50Ω. Its DC output voltage is about 1.7V
if enabled. An AC-coupling capacitor should be used at
this pin with a recommended value of 10nF.
LOL, LOC (Pins 3, 4): LO Inputs. This is not a differen-
tial input. Both pins are 50Ω inputs. An LC diplexer is
recommended to be used at these pins (see Figure 13).
AC-coupling capacitors are required at these pins if the
applied DC level is higher than 100mV.
CSB (Pin 19): Serial Port Chip Select. This CMOS input
initiates a serial port transaction when driven low, ending
the transaction when driven back high. Do not float.
TTCK (Pin 6): Temperature Update. When the TTCK tem-
perature update mode is selected in register 0x01 (bit 7
= High, TEMPUPDT = 1), the temperature readout and
digital gain compensation vs temperature can be updated
through a logic low to logic high transition at this pin. Do
not float.
SCLK (Pin 20): Serial Port Clock. This CMOS input clocks
serial port input data on its rising edge. Do not float.
SDI (Pin 21): Serial Port Data Input. The serial port uses
this CMOS input for data. Do not float.
SDO (Pin 22): Serial Port Data Output. This NMOS output
presentsdatafromtheserialportduringareadtransaction.
Connect this pin to the digital supply voltage through a
pull-up resistor of sufficiently large value, to ensure that
the current does not exceed 10mA when pulled low.
TEMP (Pin 7): Temperature Sensing Diode. This pin is
connected to the anode of a diode that may be used to
measure the die temperature, by forcing a current and
measuring the voltage. This diode is not part of the on-
chip thermometer.
EN (Pin 23): Enable Pin. The chip is completely turned
on when a logic high voltage is applied to this pin, and
completely turned off for a logic low voltage. Do not float.
BBPI,BBMI(Pins8,9):BasebandInputsoftheI-Channel.
The input impedance of each input is about 1kΩ. It should
be externally biased to a 1.4V common mode level, or AC-
coupled.Donotapplycommonmodevoltagebeyond2V .
DC
V
CC
(Pin24):PowerSupply.Itisrecommendedtouse1nF
and4.7µFcapacitorsfordecouplingtogroundonthispin.
5599f
17
For more information www.linear.com/LTC5599
LTC5599
block DiagraM
CSB SCLK SDI SDO
V
CC
EN
23
19
20
21
22
24
SPI
BBPI
8
9
V
V
I
I
I-CHANNEL
Q-CHANNEL
BBMI
16 RF
0°
V
1
CTRL
90°
BBPQ 10
11
THERMOMETER
6
TTCK
BBMQ
7
2
5
12 25
3
4
13 14 15 17 18
GNDRF
5599 BD
GND
TEMP LOL LOC
5599f
18
For more information www.linear.com/LTC5599
LTC5599
applicaTions inForMaTion
The LTC5599 consists of I and Q input differential voltage- resulting RF signal is equal to the LO signal frequency.
to-current converters, I and Q upconverting mixers, an The LO inputs drive a phase shifter which splits the LO
RF output buffer and an LO quadrature phase generator. signalintoin-phaseandquadraturesignalswhichdrivethe
An SPI bus addresses nine control registers, enabling upconverting mixers. In most applications, the LOL input
optimization of side-band suppression, LO leakage, and is driven by the LO source via a 39nH inductor, while the
adjustment of the modulator gain. See Table 1 for a sum- LOC input is driven by the LO source via a 15pF capacitor.
mary of the writable registers and their default values. This inductor and capacitor form a diplexer circuit tuned
A full map of all the registers in the LTC5599 is listed in to 200MHz. The RF output is single-ended and internally
Table 10 and Table 11 in the Appendix.
Table 1. SPI Writable Registers and Default Register Values.
DEFAULT
50Ω matched across a wide RF frequency range from
0.6MHz to 6GHz with better than 10dB return loss using
C4 = 10nF. See Figure 13.
ADDRESS
VALUE
0x2E
0x84
0x80
0x80
0x80
0x10
0x50
0x06
SETTING REGISTER FUNCTION
Baseband Interface
0x00
490MHz LO Frequency Tuning
0x01
DG = –4
0mV
0mV
0dB
Gain
The baseband inputs (BBPI, BBMI, BBPQ, BBMQ) present
a differential input impedance of about 1.8kΩ, as depicted
in Figure 1. The baseband bandwidth depends on the
source impedance and the frequency setting (register
0x00). It is recommended to compensate the baseband
input impedance in the baseband lowpass filter design in
ordertoachievebestgainflatnessvsbasebandfrequency.
The S-parameters for (each of) the baseband inputs are
giveninTable2forvariousLOfrequencyandgainsettings.
0x02
Offset I-Channel
Offset Q-Channel
I/Q Gain Ratio
0x03
0x04
0x05
0°
I/Q Phase Balance
LO Port Matching Override
0x06
OFF
0x07
OFF
Temperature Correction
Override
0x08
0x00
NORMAL Operating Mode
Without using the SPI the registers will use the default
values which may not result in the optimum side-band
suppression (SB). For example: for LO frequency from
about 400MHz to about 580MHz, the SB is about –45dBc;
from 380MHz to 400MHz and 580MHz to 630MHz it falls
to about –40dBc; from 350MHz to 380MHz and 630MHz
to 690MHz the SB falls to about –35dBc.
V
= 3.3V
CC
+
1.4V
EN
V
CTRL
2.5mA
1
1kΩ
1kΩ
BBPI
8
9
Aside of powering up the LTC5599, the register values can
be reset to the default values by setting SRESET = 1 (bit 3,
register 0x08). After about 50ns SRESET is automatically
set back to 0.
V
= 1.4V
CM
BBMI
35Ω
10pF
40Ω
3pF
40Ω
3pF
External I and Q baseband signals are applied to the dif-
ferential baseband input pins: BBPI, BBMI and BBPQ,
BBMQ.Thesevoltagesignalsareconvertedtocurrentsand
translated to RF frequency by means of double-balanced
upconverting mixers. The mixer outputs are combined at
the inputs of the RF output buffer, which also transforms
the output impedance to 50Ω. The center frequency of the
5599 F01
Figure 1. Simplified Circuit Schematic of the Base Band Input
Interface (Only One Channel Is Shown).
5599f
19
For more information www.linear.com/LTC5599
LTC5599
applicaTions inForMaTion
T
able 2. Differential Baseband (BB) Input Impedance vs
T
able 2. Differential Baseband (BB) Input Impedance vs
Frequency for EN = High and VCMBB = 1.4V (continued)
Frequency for EN = High and VCMBB = 1.4V
REFL
REFL
BB
BB
INPUT IMPEDANCE (W)
COEFFICIENT
INPUT IMPEDANCE (W)
FREQUENCY
COEFFICIENT
FREQUENCY
(MHz)
REAL*
IMAG* (CAP)
MAG ANGLE
(MHz)
REAL*
IMAG* (CAP)
MAG ANGLE
EN = Low (Chip Disabled, REGISTER 0X00 = 0x2E)
LO FREQUENCY = 92MHz (REGISTER 0x00 = 0x79), DIGITAL GAIN = –4dB
1
2
2.04k
2.02k
1.91k
1.59k
1.01k
402
–18.2k (8.8pF)
–4.59k (8.7pF)
–1.84k (8.7pF)
–935 (8.5pF)
–502 (7.9pF)
–269 (5.9pF)
–197 (4.0pF)
0.906
0.906
0.901
0.893
0.826
0.644
0.522
–0.6
–2.5
–6.3
–12
–23
–43
–60
1
1.90k
1.76k
1.25k
678
–7.17k (22.2pF)
–1.82k (21.9pF)
–751 (21.2pF)
–429 (18.6pF)
–308 (12.9pF)
0.900
0.893
0.854
0.755
0.585
–1.6
–6.3
–15
–27
–39
4
10
20
40
100
200
10
20
40
342
LO FREQUENCY = 150MHz (REGISTER 0x00 = 0x62), DIGITAL GAIN = –4dB
246
1
4
1.90k
1.82k
1.45k
887
–9.11k (17.5pF)
–2.30k (17.3pF)
–935 (17.0pF)
–507 (15.7pF)
–325 (12.2pF)
–252 (6.3pF)
0.900
0.896
0.872
0.804
0.658
0.457
–1.3
–5.0
–12
–23
–36
–51
*Parallel Equivalent
10
20
40
100
Thecircuitisoptimizedforacommonmodevoltageof1.4V
whichcanbeinternallyorexternallyapplied.IncaseofAC-
coupling to the baseband pins (1.4V internally generated
bias) make sure that the high pass filter corner is not
affecting the low frequency components of the baseband
signal. Even a small error for low baseband frequencies
can result in degraded EVM.
441
226
LO FREQUENCY = 500MHz (REGISTER 0x00 = 0x2D), DIGITAL GAIN = –4dB
1
4
1.91k
1.89k
1.72k
1.35k
786
–14.7k (10.6pF)
–3.74k (10.7pF)
–1.50k (10.7pF)
–769 (10.4pF)
–426 (9.4pF)
0.900
0.899
0.891
0.864
0.785
0.583
0.478
–0.8
–3.0
–7.7
–15
–27
–47
–65
10
20
40
100
200
The baseband input offset voltage depends on the source
resistance. In case of AC-coupling the 1 sigma offset is
about 1.1mV, resulting in about –46.6dBm LO leakage.
For shorted baseband pins (0Ω source resistance), the
LO leakage improves to about –50.1dBm. In case of AC-
coupling the LO leakage can be reduced by connecting a
resistor in parallel with the baseband inputs, thus lower-
ing baseband input impedance and offset. Further, the
low combined baseband input leakage current of 1.3nA
in shutdown mode retains the voltage over the coupling
capacitors, which helps to settle faster when the part is
enabled again. It is recommended to drive the baseband
inputsdifferentiallytoimprovethelinearity.WhenaDACis
usedasthesignalsource, areconstructionfiltershouldbe
placedbetweentheDACoutputandtheLTC5599baseband
inputs to avoid aliasing.
323
–251 (6.4pF)
212
–190 (4.2pF)
LO FREQUENCY = 500MHz (REGISTER 0x00 = 0x2D), DIGITAL GAIN = 0dB
1
4
1.56k
1.56k
1.48k
1.21k
753
–15.0k (10.6pF)
–3.84k (10.4pF)
–1.52k (10.4pF)
–784 (10.2pF)
–432 (9.2pF)
0.879
0.880
0.874
0.849
0.776
0.582
0.478
–0.8
–3.0
–7.5
–15
–27
–47
–65
10
20
40
100
200
323
–251 (6.3pF)
213
–190 (4.2pF)
LO FREQUENCY = 900MHz (REGISTER 0x00 = 0x12), DIGITAL GAIN = –4dB
1
2
1.91k
1.90k
1.77k
1.46k
915
–17.0k (9.4pF)
–4.3k (9.3pF)
–1.72k (9.3pF)
–878 (9.1pF)
–475 (8.4pF)
–261 (6.1pF)
–193 (4.1pF)
0.901
0.900
0.893
0.873
0.811
0.622
0.506
–0.7
–2.7
–6.7
–13
–24
–45
–62
10
20
40
100
200
Internal Gain Trim DACs
371
Four internal gain trim DACs (one for each baseband pin)
are configured as 11-bit each. The usable DAC input value
range is integer continuous from 64 to 2047 and 0 for
shutdown. The DACs are not intended for baseband signal
233
5599f
20
For more information www.linear.com/LTC5599
LTC5599
applicaTions inForMaTion
to implement an automatic gain/temperature correction
which can be activated by setting TEMPCORR = 1. In that
case, the input of the fine digital gain control will be the
on-chipthermometer.Theon-chipthermometergenerates
a 4-bit digital code with code 0 corresponding to –30°C
and code 15 corresponding to 120°C and 10°C spacing
betweenthecodes. Theon-chipthermometeroutputcode
can be updated continuous (by clearing TEMPUPDT, bit 7
in register 0x01, see Table 10) or can be updated by bring-
ing the external pin TTCK from low to high (and setting
TEMPUPTD = 1). In case of continuous update the code
willbeanasynchronousupdatewheneverthetemperature
crosses a certain threshold. In some cases it is desired to
prevent a gain update to happen in the middle of a data
frame. In that case, the gain/temperature update can be
synchronized using the TTCK pin for example at the begin-
ning or end of a data frame. The on-chip temperature can
be read back by reading register 0x1F (TEMP[3:0]).The
decimal value of TEMP[3:0] is given by:
generation but for gain and offset setting only, because
there are no reconstruction filters between the DACs and
the mixer core, and there is only indirect access between
the DAC values and the register settings. The following
functions are implemented in this way:
• Coarse digital gain control with 1dB steps
• Fine digital gain control with 0.1dB steps
• Gain-temperature correction
• DC offset adjustment in the I-channel
• DC offset adjustment in the Q-channel
• I/Q gain balance control
• Disable Q-channel
• Continuous variable gain control
Coarse Digital Gain Control (DG) with 1dB Steps
(Register 0x01)
TEMP[3:0] = round(T/10) + 3
Twenty digital gain positions 1dB apart are implemented
by hardwiring a corresponding DAC code for all four
DACs. The coarse digital gain is set by writing to the five
least-significant bits in register 0x01, see Table 10 and 11.
The gain is the highest for code 00000 (code 0 = 0dB, DG
= 0) and the lowest for code 10011 (code 19 = –19dB,
DG = –19). Note that the gain 0dB set by the digital gain
control is not the same as the voltage gain of the part.
The remaining 12 codes (decimal 20 to 31) are reserved.
with T the actual on-chip temperature in °C. It’s accuracy
is about 10°C. TEMP[3:0] defaults to 7 after an EN low
to high transition with TEMPUPDT = 1. Switching from
TEMPUPDT = 0 to TEMPTUPDT = 1, TEMP[3:0] indicates
the temperature during the last time TTCK went from low
to high. Note that the actual on-chip temperature cannot
be read if TEMPCORR = 1 or when TEMPUPDT = 1 without
toggling TTCK.
The digital gain in dB equals minus the decimal value writ-
ten into the 5 least-significant bits of the gain register. The
formula relating the modulator gain G(in V/V) relative to
the maximum conversion gain therefore equals:
Analog Gain Control
The LTC5599 supports analog control of the conversion
gain through a voltage applied to V
(pin 1). The gain
CTRL
can be controlled downward from the digital gain setting
(DG) programmed in register 0x01. In order to minimize
distortion in the RF output signal the AGCTRL bit (bit 6 in
register 0x01) should be set to 1. If analog gain control is
(DG/20)
G(V/V) = 10
Fine Digital Gain Control(FDG) with 0.1dB Steps and
Gain-Temperature Correction (Register 0x07)
not used, V
should be connected to V and AGCTRL
CTRL
CC
Sixteen digital gain positions about 0.1dB apart can be set
directlyusingthefourleast-significantbitsinregister0x07
combined with bit 2 = 1 in register 0x08 (TEMPCORR = 1).
For coarse digital gain settings code 9 and higher some or
more subsequent codes of the fine digital gain positions
may be the same due to the limited resolution of the 11-
bit DACs. The main purpose of these 0.1dB gain steps is
set to 0; this saves about 2.58mA of supply current. The
typical usable gain control range is from 0.9V to 3.3V.
Setting V
to a voltage lower than V with AGCTRL
CTRL
CC
= 0 significantly impairs the linearity of the RF output
signal and lowers the V response time. A simplified
CTRL
schematic is shown in Figure 1.
5599f
21
For more information www.linear.com/LTC5599
LTC5599
applicaTions inForMaTion
I/Q DC Offset Adjustment (Registers 0x02 and 0x03)
and LO Leakage
A positive offset means that the voltage of the positive
input terminal (BBPI or BBPQ) is increased relative to the
negative input terminal (BBMI or BBMQ).
Offsets in the I- and Q-channel translates into LO leakage
at the RF port. This offset can either be caused by the
I/Q modulator or, in case the baseband connections are
DC-coupled, applied externally. Registers 0x02 and 0x03
(I-offset and Q-offset) can be set to cancel this offset
and hence lower the LO leakage. To adjust the offset in
the I-channel, the BBPI DAC is set to a (slightly) different
value than the BBMI DAC, introducing an offset. These
8-bit registers defaults are 128 and represents 0 offset.
The register value can be set from 1 to 255. The value 0
represents an unsupported code and should not be used.
Since the input referred offset depends on the gain the
I/Q Gain Ratio (Register 0x04) and Side-Band
Suppression
The 8-bit I/Q gain ratio register 0x04 controls the ratio of
the I-channel mixer conversion gain G and the Q-channel
I
mixer conversion gain G . Together with the quadrature
Q
phaseimbalanceregister0x05,register0x04allowsfurther
optimization of the modulator side-band suppression.
TheexpressionrelatingthegainratioG /G tothecontents
I
Q
of the 8-bit register 0x04, represented by decimal N and
IQ
the nominal conversion gain G equals:
input offset value (V ) can be calculated as:
OS
20 log (G /G ) = 20 log ((3632 • G – (N – 128))/
I
Q
IQ
V
= 1260/((3632 • G)/(N – 128) – (N – 128)
OS OS
OS
(3632 • G +(N –128))) (dB)
IQ
/(3632 • G))
The step size of the gain ratio trim in dB vs N is ap-
IQ
andV =0forN =128.GrepresentsthegainfromTable3.
os
os
proximately constant for the same digital gain setting.
For digital gain setting = –4, for example, the step size
is about 7.6mdB. Table 4 lists the gain step size for each
digital gain setting that follows from the formula above.
Table 3. Coarse Digital Gain (DG) Register Settings.
DG (dB)
0
G(V/V)
1.000
0.891
0.794
0.708
0.631
0.562
0.501
0.447
0.398
0.355
0.316
0.282
0.251
0.224
0.200
0.178
0.158
0.141
0.126
0.112
DEC
0
BINARY
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
HEX
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
–1
1
Table 4. I/Q Gain Ratio Step Size vs Digital Gain
Setting
–2
2
–3
3
DG (dB)
0
G (V/V)
1.000
0.891
0.794
0.708
0.631
0.562
0.501
0.447
0.398
0.355
0.316
0.282
0.251
0.224
0.200
0.178
∆G /G (mdB)
I
Q
–4
4
4.8
–5
5
–1
5.4
6.0
–6
6
–2
–7
7
–3
6.8
–8
8
–4
7.6
–9
9
–5
8.5
–10
–11
–12
–13
–14
–15
–16
–17
–18
–19
10
11
12
13
14
15
16
17
18
19
–6
9.6
–7
10.7
12.0
13.5
15.1
17.1
19.2
21.5
24.2
27.3
–8
–9
–10
–11
–12
–13
–14
–15
5599f
22
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LTC5599
applicaTions inForMaTion
Table 4. I/Q Gain Ratio Step Size vs Digital Gain
Table 5. Register 0x00 Setting vs LO Frequency (continued)
Setting
(continued)
REGISTER VALUE
DECIMAL
LO FREQUENCY RANGE (MHz)
DG (dB)
–16
G (V/V)
0.158
0.141
0.126
0.112
∆G /G (mdB)
I
Q
BINARY
0001111
0010000
0010001
0010010
0010011
0010100
0010101
0010110
0010111
0011000
0011001
0011010
0011011
0011100
0011101
0011110
0011111
0100000
0100001
0100010
0100011
0100100
0100101
0100110
0100111
0101000
0101001
0101010
0101011
0101100
0101101
0101110
0101111
0110000
0110001
0110010
0110011
0110100
0110101
0110110
HEX
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
LOWER BOUND UPPER BOUND
30.7
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
961.8
941.3
921.5
895.2
877.6
863.6
843.2
826.9
807.0
792.3
772.2
752.7
734.0
724.2
704.6
688.7
673.2
655.2
638.1
624.6
611.9
598.4
585.1
573.9
563.1
548.1
538.1
529.1
518.5
507.0
497.7
488.0
471.5
457.7
448.7
437.4
426.6
417.5
407.5
398.0
988.2
961.7
941.2
921.4
895.1
877.5
863.5
843.1
826.8
806.9
792.2
772.1
752.6
739.9
724.1
704.5
688.6
673.1
655.1
638.0
624.5
611.8
598.3
585.0
573.8
563.0
548.0
538.0
529.0
518.4
506.9
497.6
487.9
471.4
457.6
448.6
437.3
426.5
417.4
407.4
–17
34.6
39.0
44.1
–18
–19
The conversion gain of the I-channel and Q-channel are
equal for N = 128. The I-channel gain is larger than the
IQ
Q-channel gain for N > 128.
IQ
Disable Q-Channel
If bit 5 in register 0x01 (QDISABLE) is set, the Q-channel
is switched off, turning the I/Q modulator into an upcon-
version mixer. It is recommended to float the BBPQ and
BBMQ pins in this mode. The default mode is Q-channel
is on (QDISABLE = 0).
LO Section (Register 0x00)
The internal LO chain consists of a poly-phase filter which
generates the I and Q signals for the image-reject double-
balanced mixer. The center frequency of the poly-phase
filter is set by the lower seven bits of register 0x00. The
recommendedsettingsvsLOfrequencyaregiveninTable5
(see the QuikEval™ GUI).
Table 5. Register 0x00 Setting vs LO Frequency
REGISTER VALUE
DECIMAL
LO FREQUENCY RANGE (MHz)
BINARY
0000000
0000001
0000010
0000011
0000100
0000101
0000110
0000111
0001000
0001001
0001010
0001011
0001100
0001101
0001110
HEX
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
LOWER BOUND UPPER BOUND
0
1
N/A
N/A
1249.1
1248.6
1238.1
1214.1
1191.2
1165.6
1141.0
1120.6
1100.5
1069.5
1039.6
1023.1
1007.1
988.3
1300.0
1249.0
1248.5
1238.0
1214.0
1191.1
1165.5
1140.9
1120.5
1100.4
1069.4
1039.5
1023.0
1007.0
2
3
4
5
6
7
8
9
10
11
12
13
14
5599f
23
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LTC5599
applicaTions inForMaTion
Table 5. Register 0x00 Setting vs LO Frequency (continued)
Table 5. Register 0x00 Setting vs LO Frequency (continued)
REGISTER VALUE
DECIMAL
LO FREQUENCY RANGE (MHz)
REGISTER VALUE
DECIMAL
LO FREQUENCY RANGE (MHz)
BINARY
0110111
0111000
0111001
0111010
0111011
0111100
0111101
0111110
0111111
1000000
1000001
1000010
1000011
1000100
1000101
1000110
1000111
1001000
1001001
1001010
1001011
1001100
1001101
1001110
1001111
1010000
1010001
1010010
1010011
1010100
1010101
1010110
1010111
1011000
1011001
1011010
1011011
1011100
1011101
1011110
1011111
HEX
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
LOWER BOUND UPPER BOUND
BINARY
1100000
1100001
1100010
1100011
1100100
1100101
1100110
1100111
1101000
1101001
1101010
1101011
1101100
1101101
1101110
1101111
1110000
1110001
1110010
1110011
1110100
1110101
1110110
1110111
1111000
1111001
1111010
1111011
1111100
1111101
1111110
1111111
HEX
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
LOWER BOUND UPPER BOUND
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
390.1
382.8
376.6
369.8
353.1
339.0
332.6
327.2
320.6
313.7
309.1
304.5
288.1
278.3
274.2
270.3
266.0
261.9
258.2
254.1
243.6
233.8
230.8
228.0
220.2
212.6
210.0
207.6
202.1
196.2
193.7
191.2
186.6
182.0
179.4
176.0
170.1
165.0
162.5
160.0
156.7
397.9
390.0
382.7
376.5
369.7
353.0
338.9
332.5
327.1
320.5
313.6
309.0
304.4
288.0
278.2
274.1
270.2
265.9
261.8
258.1
254.0
243.5
233.7
230.7
227.9
220.1
212.5
209.9
207.5
202.0
196.1
193.6
191.1
186.5
181.9
179.3
175.9
170.0
164.9
162.4
159.9
96
153.6
151.1
148.6
142.5
139.6
136.5
134.3
131.2
128.1
126.0
123.8
121.3
118.3
115.7
113.5
111.3
109.5
107.6
105.6
103.0
100.3
98.5
156.6
153.5
151.0
148.5
142.4
139.5
136.4
134.2
131.1
128.0
125.9
123.7
121.2
118.2
115.6
113.4
111.2
109.4
107.5
105.5
102.9
100.2
98.4
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
96.6
94.7
96.5
93.0
94.6
30.0
92.9
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
A simplified circuit schematic of the LOL and LOC inter-
faces is depicted in Figure 2. The LOL and LOC inputs are
not differential LO inputs. They are 50Ω inputs and are
intended to be driven with an inductor going to the LOL
input and a capacitor to the LOC input. Do not switch the
capacitor and inductor, as this will result in very poor
performance. For a wideband LO range an inductor value
of39nHandacapacitorvalueof15pF(standardLOmatch)
5599f
24
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LTC5599
applicaTions inForMaTion
is recommended at these pins, forming a diplexer circuit
with center frequency of 200MHz. This diplexer helps to
improve the uncalibrated side-band suppression signifi-
cantly around 200MHz. Even for LO frequencies far from
200MHz the diplexer performs better than a single-ended
LO drive or a differential drive. Due to factory calibration
of the poly-phase filter the typical side-band suppression
is about 50dBc for frequencies from 100MHz to 700MHz
and 45dBc from 700MHz to 1300MHz. For narrow-band
applications far from 200MHz it may help to tune the
diplexer to a different frequency which can improve the
uncalibrated side-band suppression and the gain vs LO
drivelevel.TheTypicalPerformanceCharacteristicssection
shows the return loss for a 900MHz match (L1 = 8.2nH,
C5 = 3.3pF) and a 1260MHz match (L1 = 5.6nH, C5 = 3pF).
To get a performance with the standard 200MHz match
equivalent to the 900MHz and 1260MHz match, the LO
powershouldbeincreasedby1.5dBand2dBrespectively.
Register 0x00 values of Table 5 may have to be adjusted
as well, in case the standard match is not used.
Table6listsLOLandLOCportinputimpedancevsfrequency
at EN = High and P = 0dBm. The other LO port (LOC or
LO
LOL) is terminated in a 50Ω.
Table 6. LOL, LOC Port Input Impedance vs Frequency for EN
= High and PLO = 0dBm (Other LO Port Terminated with 50Ω to
Ground)
LOL/LOC PORT IMPEDANCE (W) REFL COEFFICIENT
FREQ REG
(MHz) 0x00 REAL*
IMAG* (IND)
24.3 (194nH)
19.0 (101nH)
17.4 (69nH)
MAG
0.750
0.743
0.732
0.716
0.693
0.661
0.618
0.564
0.497
0.419
0.338
0.276
0.247
0.234
0.201
0.160
0.164
0.150
0.116
ANGLE
175
172
169
165
162
158
154
151
148
146
149
150
148
142
143
162
141
135
156
20
30
79
79
79
79
79
79
79
79
75
70
6C
68
64
62
5E
5C
59
57
54
7.9
9.1
40
10.8
13.0
15.7
18.6
21.6
24.4
27.0
29.0
30.3
32.3
34.3
36.2
37.4
37.1
39.6
41.4
40.7
50
17.6 (56nH)
60
18.9 (50nH)
70
21.4 (49nH))
25.0 (50nH)
80
90
30.3 (54nH)
100
110
120
130
140
150
160
170
180
190
200
38.3 (61nH))
51.4 (74nH)
76.1 (101nH)
109.3 (134nH)
121.6 (138nH)
119.4 (127nH)
149.1 (148nH))
357.5 (335nH)
188.6 (167nH)
192.0 (161nH))
418.6 (333nH)
LOL
3
LOC
4
5599 F02
*Parallel Equivalent
Figure 2. Simplified Circuit Schematic for the LOL and LOC Inputs
The circuit schematic of the demo board is shown in
Figure 13.
Below 100MHz the matching network of Figure 3 can be
used.The side-band suppression in that case is largely
defined by the diplexer L1, C5 and the (temperature de-
pendent) LOL and LOC input impedance. See measured
performance in the Typical Performance Characteristics
section.
I/Q Phase Balance Adjustment Register 0x05 and
Side-Band Suppression
Ideally the I-channel LO phase is exactly 90° ahead of the
Q-channelLOphase,socalledquadrature.Inpracticehow-
ever,theI/Qphasedifferencediffersfromexactquadrature
by a small error due to component parameter variations
and harmonic content in the LO signal (see below).
L1
30MHz/70MHz
47nH/43nH
3
LOL
C20
270pF/100pF
L2
120nH/51nH
LO
C5
C19
560pF/120pF
The I/Q phase imbalance register (0x05) allows adjust-
ment of the I/Q phase shift to compensate for such errors.
Together with gain ratio register 0x04, it can thus be used
to optimize the side-band suppression of the modulator.
180pF/47pF
LOC
4
C21
270pF/100pF
5599 F03
Figure 3. Impedance Matching Network for LOL and LOC
Interfaces Matched at 30MHz/70MHz
5599f
25
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Register 0x05 contains two parts (see Table 11); the five
leastsignificantbitsIQPHFrealizeafinephaseadjustment,
while the three most significant bits IQPHE are used for
coarse adjustments. The fine phase adjustment realized
by IQPHF can be approximated as:
As a side effect, the extension bits slightly detune the
centerfrequencyofthepoly-phasefilter,aftercrossingthe
boundary to a new N
value. This can be observed
COARSE
as a large step in the actual phase shift. A solution for this
is to decrease the value in the frequency register 0x00
(increase the poly-phase filter center frequency) at the
ꢀ j = ((N –16)/15) • ln(f /50) (degrees)
–
IQ
ph LO
N
value boundaries. The result is a smooth phase
COARSE
for 30MHz < f < 1300MHz
adjustment. In the demo board QuikEval GUI, this LO fre-
quency register adjustment is automatically taken care of.
LO
where N is the decimal value of IQPHF and f is the
ph
LO
frequency of the LO signal in MHz. A positive value for
Wheneverthepoly-phasefiltercenterfrequencyisadjusted
to improve the smoothness of the phase adjustment, it is
recommendedtomanuallyprogramtheLOportimpedance
match using the CLOO bits in register 0x06. By default,
changing the filter center frequency also automatically
adjusts the matching of the LO port (when CLOEN, bit 4
in register 0x06 is set). However, since the LO carrier
frequency does not change, automatic adjustment of the
LO match is undesirable in this case; it may add another
large step to the phase adjustment. Instead, the LO match
shouldremainunchangedwhilethefiltercenterfrequency
is adjusted. This can be achieved as follows. First, the
current LO matching configuration is read from the CLO
bits in register 0x1D, and written to the CLOO override
bits in register 0x06. Subsequently, the CLOEN bit (bit 4,
register 0x06) is cleared to disable automatic LO match
adjustment. As a result the center frequency can be ad-
justed in register 0x00 without changing the LO match.
j means that the I-channel LO phase is more than 90°
IQ
ahead of the Q-channel LO phase. Notice from the expres-
sion that the phase adjustment range and resolution are
coupled, and dependent on the LO frequency. At low LO
frequenciesthethesmallestadjustmentrangeandhighest
resolution is achieved, while high LO frequencies exhibit
the largest range and lowest resolution.
The extension bits IQPHE provide a larger phase adjust-
ment range, particularly useful at lower LO frequencies,
andovercomeanothertrade-off;betweenphaseadjustment
range and the maximum center frequency of the poly-
phase filter. The latter trade-off is due to the fact that the
capacitancesintheI-channel,C ,andQ-channel,C ,of
ppI
ppQ
the poly-phase filter control both these parameters. Their
differencesetsthephaseshift, whiletheirsumdetermines
the center frequency of the filter.
The extension bits IQPHE introduce a large phase offset in
addition to the fine adjustment realized by the IQPHF bits.
The sign of this large offset can be positive or negative,
controlled by IQPHSIGN (bit 7 in register 0x00). Including
these bits, the total phase shift from quadrature can be
expressed as:
At 100MHz the maximum phase shift is about 9.8°, while
at 1GHz it is about 3°. The extension bits are not useful
above 988.2MHz since the poly-phase center frequency
register 0x00 value cannot be adjusted low enough to
ensure a smooth transition to a new N
value.
COARSE
ꢀ j =
–
(M /15) • ln(f /50) (degrees) with
Square Wave LO Drive
IQ
PH
LO
M
= N
+ N –16 and
Harmonic content of the LO signal adversely affects
quadrature phase error and gain accuracy, whenever a
poly-phase filter is used for quadrature generation. The
LTC5599 can correct for phase and gain errors due to har-
monics in the LO carrier (e.g. in a square wave) by setting
appropriate values in the I/Q gain and I/Q phase registers.
Suchadjustmentsaretypicallyneededwhenthe3rd-order
harmonicoftheLOsignalexceedsthedesirableside-band
suppression minus 13dB. Although the poly-phase filter
is less sensitive to the second harmonic content of the LO
PH
COARSE
PH
IQPHSIGN + 1
N
= 32 • (–1)
• N
EXT
COARSE
where N equals the decimal value of the IQPHE bits. The
valid range of values for (N –16) is thus expanded from
ext
ph
{–16, –15, ... , +15} to {–240, –239, ... , +239}. Table 9 in
the Appendix lists all the possible combinations. The cod-
ing ranges for IQPHSIGN = 0 and IQPHSIGN = 1 overlap
between M = –16 and M = +15, such that IQPHSIGN
ph
ph
only needs to be changed for larger phase shifts.
5599f
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carrier, it’s influence can still be significant. For –15dBc
second harmonic content, the side-band suppression can
degrade to –45dBc; for –20dBc it is –54dBc, assuming no
I/Q gain and phase adjustments are made.
Table 7. RF Output Impedance vs Frequency and Digital Gain
Setting (DG) for EN = High (continued)
REFL
OUTPUT IMPEDANCE (W)
(dB) REAL* IMAG* (CAP)
COEFFICIENT
FREQUENCY
(MHz)
DG
MAG ANGLE
600
600
–16
–18
–19
0
58
62
77
48
51
55
59
73
–1.77k (0.15pF) 0.078
–1.44k (0.18pF) 0.109
–12
–11
–14
RF Output
After upconversion, the RF outputs of the I and Q mixers
are combined. An on-chip buffer performs internal dif-
ferential to single-ended conversion, while transforming
the output signal to 50Ω as shown in Figure 4.
600
–680 (0.39pF)
–802 (0.15pF)
–807 (0.15pF)
–709 (0.17pF)
–526 (0.23pF)
–280 (0.44pF)
0.217
1300
1300
1300
1300
1300
0.035 –119
–12
–16
–18
–19
0.034
0.059
0.098
0.215
–68
–41
–35
–36
V
CC
*Parallel Equivalent
The RF port output impedance for EN = Low is given in
Table 8.
50Ω
RF
16
Table 8. RF Output Impedance vs Frequency for EN = Low
REFL
5599 F04
OUTPUT IMPEDANCE (W)
COEFFICIENT
FREQUENCY
(MHz)
Figure 4. Simplified Circuit Schematic for the RF Output Port
REAL*
IMAG* (CAP)
–7.76k (0.68pF)
–5.24k (0.76pF)
–3.96k (0.80pF)
–3.18k (0.83pF)
–2.66k (0.86pF)
–2.29k (0.87pF)
–2.01k (0.88pF)
–1.79k (0.89pF)
–856 (0.93pF)
–679 (0.94pF)
–563 (0.94pF)
–481 (0.94pF)
–420 (0.95pF)
–373 (0.95pF)
–336 (0.95pF)
–281 (0.94pF)
–241 (0.94pF)
–211 (0.94pF)
–188 (0.94pF)
–169 (0.94pF)
–154 (0.94pF)
–141 (0.94pF)
–129 (0.95pF)
MAG ANGLE
30
40
16.1k
16.2k
15.7k
16.5k
16.8k
16.4k
17.1k
17.9k
14.7k
11.1k
8.55k
7.97k
6.42k
5.27k
4.26k
3.05k
2.32k
1.85k
1.54k
1.30k
1.12k
991
0.994
0.994
0.994
0.994
0.994
0.994
0.994
0.994
0.993
0.991
0.988
0.988
0.985
0.982
0.977
0.969
0.959
0.950
0.941
0.932
0.923
0.914
0.906
–0.7
–1.1
–1.4
–1.8
–2.2
–2.5
–2.9
–3.2
–6.7
–8.4
–10
–12
–14
–15
–17
–20
–23
–27
–30
–33
–36
–39
–42
Table 7 shows the RF port output impedance vs frequency
and digital gain setting for EN = High.
50
Table 7. RF Output Impedance vs Frequency and Digital Gain
Setting (DG) for EN = High
60
70
REFL
80
OUTPUT IMPEDANCE (W)
COEFFICIENT
FREQUENCY
(MHz)
DG
(dB) REAL*
90
IMAG* (CAP)
–413 (12.8pF)
–465 (11.4pF)
–529 (10.0pF)
–623 (8.5pF)
–902 (5.9pF)
–671 (4.7pF)
–762 (4.2pF)
–859 (3.7pF)
–972 (3.3pF)
–1.21k (2.6pF)
–1.08k (1.5pF)
–1.32k (1.2pF)
–1.55k (1.0pF)
MAG ANGLE
100
200
250
300
350
400
450
500
600
700
800
900
1000
1100
1200
1300
30
30
0
59
61
64
69
83
56
58
61
67
81
55
57
60
66
82
54
56
0.104
0.114
0.133
0.166
0.249
0.068
0.082
0.107
0.146
0.239
0.050
0.066
0.096
–43
–35
–27
–19
–10
–38
–27
–19
–13
–8
–12
–16
–18
–19
0
30
30
30
50
50
–12
–16
–18
–19
0
50
50
50
100
100
100
100
100
600
600
–30
–19
–12
–8
–12
–16
–18
–19
0
–1.75k (0.91pF) 0.142
–1.98k (0.80pF) 0.246
–1.35k (0.20pF) 0.040
–1.75k (0.15pF) 0.057
–5
881
–30
–16
*Parallel Equivalent
–12
5599f
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serial bus master device first taking CSB low to enable
the LTC5599’s port. Input data applied on SDI is clocked
on the rising edge of SCLK, with all transfers MSB first.
The communication burst is terminated by the serial bus
master returning CSB high. See Figure 6 for details.
For V = 3.3V and EN = High the RF pin voltage is about
CC
1.68V. For V = 3.3V and EN = Low the RF pin voltage
CC
is about 3.1V.
Enable Interface
Figure 5 shows a simplified schematic of the EN pin
interface. The voltage necessary to turn on the LTC5599 is
1.1V. To disable (shut down) the chip, the enable voltage
must be below 0.2V.
Data is read from the part during a communication burst
using SDO. Readback may be multidrop (more than one
LTC5599 connected in parallel on the serial bus), as SDO
is high impedance (Hi-Z) when CSB = 1, or when data is
not being read from the part. If the LTC5599 is not used
in a multidrop configuration, or if the serial port master
is not capable of setting the SDO line level between read
sequences,itisrecommendedtoattacharesistorbetween
V
CC
INTERNAL
ENABLE
CIRCUIT
EN
23
SDO and V
to ensure the line returns to V
during
CC_L
CC_L
Hi-Z states. The resistor value should be large enough
to ensure that the SDO output current does not exceed
10mA. See Figure 7 for details.
5599 F05
Figure 5. Simplified Circuit Schematic of the EN interface
Single Byte Transfers
SERIAL PORT
The serial port is arranged as a simple memory map, with
status and control available in 9 read/write and 23 read-
only byte-wide registers. All data bursts are comprised of
at least two bytes. The 7 most significant bits of the first
byte are the register address, with an LSB of 1 indicating
a read from the part, and LSB of 0 indicating a write to the
part. The subsequent byte, or bytes, is data from/to the
The SPI-compatible serial port provides control and
monitoring functionality.
Communication Sequence
The serial bus is comprised of CSB, SCLK, SDI and
SDO. Data transfers to the part are accomplished by the
MASTER–CSB
t
t
CSS
CSS
t
t
t
CKL
CKH
CSH
MASTER–SCLK
t
t
CH
CS
MASTER–SDI
DATA
DATA
5599 F06
Figure 6. Serial Port Write Timing Diagram
MASTER–CSB
MASTER–SCLK
LTC5599–SDO
8TH CLOCK
t
t
t
DO
t
DO
DO
DO
DATA
DATA
5599 F07
Figure 7. Serial Port Read Timing Diagram
5599f
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specifiedregisteraddress.SeeFigure8foranexampleofa
detailed write sequence, and Figure 9 for a read sequence.
byte of the second burst contains the destination register
address (Addr1) and an LSB indicating a write. The next
byte on SDI is the data intended for the register at address
Addr1. CSB is then taken high to terminate the transfer.
Figure 10 shows an example of two write communication
bursts. The first byte of the first burst sent from the serial
bus master on SDI contains the destination register ad-
dress (Addr0) and an LSB of 0 indicating a write. The next
byte is the data intended for the register at address Addr0.
CSB is then taken high to terminate the transfer. The first
Note that the written data is transferred to the internal
th
register at the falling edge of the 16 clock cycle (paral-
lel load).
MASTER–CSB
16 CLOCKS
MASTER–SCLK
7-BIT REGISTER ADDRESS
8 BITS OF DATA
D7 D6 D5 D4 D3 D2 D1 D0
0 = WRITE
PARALLEL LOAD
A6 A5 A4 A3 A2 A1 A0
0
MASTER–SDI
LTC5599–SD0
5599 F08
Figure 8. Serial Port Write Sequence
MASTER–CSB
MASTER–SCLK
16 CLOCKS
7-BIT REGISTER ADDRESS
1 = READ
A6 A5 A4 A3 A2 A1 A0
1
MASTER–SDI
LTC5599–SDO
8 BITS OF DATA
X D7 D6 D5 D4 D3 D2 D1 D0 DX
5599 F09
Figure 9. Serial Port Read Sequence
MASTER–CSB
ADDR0 + WR
BYTE 0
ADDR1 + WR
BYTE 1
MASTER–SDI
LTC5599–SDO
5599 F10
Figure 10. Serial Port Single Byte Writes
5599f
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Multiple Byte Transfers
Multidrop Configuration
More efficient data transfer of multiple bytes is accom-
plished by using the LTC5599’s register address auto-
increment feature as shown in Figure 11. The serial port
master sends the destination register address in the first
byteanditsdatainthesecondbyteasbefore,butcontinues
sending bytes destined for subsequent registers. Byte 1’s
address is Addr0+1, Byte 2’s address is Addr0+2, and so
on. If the resister address pointer attempts to increment
past 31 (0x1F), it is automatically reset to 0.
Several LTC5599s may share the serial bus. In this
multidropconfiguration,SCLK,SDI,andSDOarecommon
betweenallparts.Theserialbusmastermustuseaseparate
CSBforeachLTC5599andensurethatonlyonedevicehas
CSB asserted at any time. It is recommended to attach a
high value resistor to SDO to ensure the line returns to a
known level (V
) during Hi-Z states.
CC_L
Serial Port Registers
The memory map of the LTC5599 may be found in the
Appendix in Table 10, with detailed bit descriptions found
in Table 11. The register address shown in hexadecimal
format under the ADDR column is used to specify each
register. Each register is denoted as either read-only (R)
or read-write (R/W). The register’s default value on device
power-up or after a reset (bit 3, register 0x08, SRESET)
is shown at the right.
An example of an auto-increment read from the part is
shown in Figure 12. The first byte of the burst sent from
the serial bus master on SDI contains the destination reg-
ister address (Addr0) and an LSB of 1 indicating a read.
Once the LTC5599 detects a read burst, it takes SDO out
of the Hi-Z condition and sends data bytes sequentially,
beginning with data from register Addr0. The part ignores
all other data on SDI until the end of the burst.
MASTER–CSB
ADDR0 + WR
BYTE 0
BYTE 1
BYTE 2
MASTER–SDI
LTC5599–SDO
5599 F11
Figure 11. Serial Port Auto-Increment Write
MASTER–CSB
MASTER–SDI
LTC5599–SDO
ADDR0 + RD
DON’T CARE
BYTE 1
BYTE 0
BYTE 2
5599 F12
Figure 12. Serial Port Auto-Increment Read
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SPI Signal Levels
is not done properly, the RF performance will degrade.
Figures 14 and 15 show the component side and bottom
side of the evaluation board.
The SPI bus supports signal levels from a digital V
CC_L
from 1.2V to 3.6V. The CSB = 1.2V condition creates an
additional static input sleep current of 0.2µA. For CSB =
1.8V the extra sleep current can be neglected.
Ferrite bead FB1 limits the supply voltage ramping speed
in case V is abruptly connected to a voltage source. In
CC
the application, limit the V ramp speed to a maximum
CC
Evaluation Board
of 1V/µs.
Figure 13 shows the evaluation board schematic. A good
ground connection is required for the exposed pad. If this
VCC_L
1.2V TO 3.6V
C17
100nF
R18
1k
(R
)
PULL-UP
FB1
FERRITE BEAD
R19, 1k
SDO
SDI
TDK, MPZ1608S331AT
R26, 1k
V
CC
2.7V TO 3.6V
R25, 1k
C1
4.7µF
C2
1nF
SCLK
CSB
R23, 1k
C18
2.2pF
C13
2.2pF
C12
2.2pF
C10
2.2pF
EN
R1, 1Ω
23 22 21 20 19
EN SDO SDI SCLK CSB
25 24
GND
V
CTRL
V
C3
100nF
CC
1
18
17
16
15
14
13
V
GNDRF
C4
10nF
CTRL
2
GND
LOL
LOC
GND
GNDRF
L1, 39nH
C5, 15pF
3
4
5
RF
RF
LTC5599IUF
LO
GNDRF
GNDRF
GNDRF
6
TTCK
TTCK
TEMP BBPI BBMI BBPQ BBMQ GND
7
8
9
10
12
11
TEMP
BBPQ
BBPI
BBPQ
BBMQ
R9
49.9Ω
R8
49.9Ω
R10
49.9Ω
R11
49.9Ω
C7
100nF
C6
100nF
C8
100nF
C9
100nF
5599 F13
BOARD NUMBER: DC2091A
Figure 13. Evaluation Circuit Schematic
5599f
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Figure 14. Evaluation Board Component Side
Figure 15. Evaluation Board Bottom Side
5599f
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LTC5599
appenDix
Phase Shift Register (0x05) Map
Table 9. Register 0x05 Phase Shift Register Settings, Including
the Extension Bits and Sign Bit (Bit 7 in Register 0x00) (continued)
Thisappendixsummarizesthedetailedvalueassignments
for the phase shift register, including the extension bits
and sign bit (bit 7 in register 0x00).
M
N
N
PH
B
PH
PH
COARSE
–204
–203
–202
–201
–200
–199
–198
–197
–196
–195
–194
–193
–192
–191
–190
–189
–188
–187
–186
–185
–184
–183
–182
–181
–180
–179
–178
–177
–176
–175
–174
–173
–172
–171
–170
–169
–168
–167
–166
–165
–164
–192
4
5
011000100
011000101
011000110
011000111
011001000
011001001
011001010
011001011
011001100
011001101
011001110
011001111
011010000
011010001
011010010
011010011
011010100
011010101
011010110
011010111
011011000
011011001
011011010
011011011
011011100
011011101
011011110
011011111
010100000
010100001
010100010
010100011
010100100
010100101
010100110
010100111
010101000
010101001
010101010
010101011
010101100
–192
–192
–192
–192
–192
–192
–192
–192
–192
–192
–192
–192
–192
–192
–192
–192
–192
–192
–192
–192
–192
–192
–192
–192
–192
–192
–192
–160
–160
–160
–160
–160
–160
–160
–160
–160
–160
–160
–160
–160
Table 9. Register 0x05 Phase Shift Register Settings, Including
the Extension Bits and Sign Bit (Bit 7 in Register 0x00)
6
7
M
N
N
PH
B
PH
PH
COARSE
8
–240
–239
–238
–237
–236
–235
–234
–233
–232
–231
–230
–229
–228
–227
–226
–225
–224
–223
–222
–221
–220
–219
–218
–217
–216
–215
–214
–213
–212
–211
–210
–209
–208
–207
–206
–205
–224
0
1
011100000
011100001
011100010
011100011
011100100
011100101
011100110
011100111
011101000
011101001
011101010
011101011
011101100
011101101
011101110
011101111
011110000
011110001
011110010
011110011
011110100
011110101
011110110
011110111
011111000
011111001
011111010
011111011
011111100
011111101
011111110
011111111
011000000
011000001
011000010
011000011
9
–224
–224
–224
–224
–224
–224
–224
–224
–224
–224
–224
–224
–224
–224
–224
–224
–224
–224
–224
–224
–224
–224
–224
–224
–224
–224
–224
–224
–224
–224
–224
–192
–192
–192
–192
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
1
2
3
4
5
6
7
8
9
1
10
11
12
2
3
5599f
33
For more information www.linear.com/LTC5599
LTC5599
appenDix
Table 9. Register 0x05 Phase Shift Register Settings, Including
the Extension Bits and Sign Bit (Bit 7 in Register 0x00) (continued)
Table 9. Register 0x05 Phase Shift Register Settings, Including
the Extension Bits and Sign Bit (Bit 7 in Register 0x00) (continued)
M
N
N
PH
B
PH
M
PH
N
N
PH
B
PH
PH
COARSE
COARSE
–163
–162
–161
–160
–159
–158
–157
–156
–155
–154
–153
–152
–151
–150
–149
–148
–147
–146
–145
–144
–143
–142
–141
–140
–139
–138
–137
–136
–135
–134
–133
–132
–131
–130
–129
–128
–127
–126
–125
–124
–123
–160
13
010101101
010101110
010101111
010110000
010110001
010110010
010110011
010110100
010110101
010110110
010110111
010111000
010111001
010111010
010111011
010111100
010111101
010111110
010111111
010000000
010000001
010000010
010000011
010000100
010000101
010000110
010000111
010001000
010001001
010001010
010001011
010001100
010001101
010001110
010001111
010010000
010010001
010010010
010010011
010010100
010010101
–122
–121
–120
–119
–118
–117
–116
–115
–114
–113
–112
–111
–110
–109
–108
–107
–106
–105
–104
–103
–102
–101
–100
–99
–128
22
010010110
010010111
010011000
010011001
010011010
010011011
010011100
010011101
010011110
010011111
001100000
001100001
001100010
001100011
001100100
001100101
001100110
001100111
001101000
001101001
001101010
001101011
001101100
001101101
001101110
001101111
001110000
001110001
001110010
001110011
001110100
001110101
001110110
001110111
001111000
001111001
001111010
001111011
001111100
001111101
001111110
–160
–160
–160
–160
–160
–160
–160
–160
–160
–160
–160
–160
–160
–160
–160
–160
–160
–160
–128
–128
–128
–128
–128
–128
–128
–128
–128
–128
–128
–128
–128
–128
–128
–128
–128
–128
–128
–128
–128
–128
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
–128
–128
–128
–128
–128
–128
–128
–128
–128
–96
–96
–96
–96
–96
–96
–96
–96
–96
–96
–96
–96
–96
–96
–96
–96
–96
–96
–96
–96
–96
–96
–96
–96
–96
–96
–96
–96
–96
–96
–96
23
24
25
26
27
28
29
30
31
0
1
2
3
4
5
6
7
8
9
1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
2
3
4
5
–98
6
–97
7
–96
8
–95
9
–94
10
11
12
13
14
15
16
17
18
19
20
21
–93
–92
–91
–90
–89
–88
–87
–86
–85
–84
–83
–82
5599f
34
For more information www.linear.com/LTC5599
LTC5599
appenDix
Table 9. Register 0x05 Phase Shift Register Settings, Including
the Extension Bits and Sign Bit (Bit 7 in Register 0x00) (continued)
Table 9. Register 0x05 Phase Shift Register Settings, Including
the Extension Bits and Sign Bit (Bit 7 in Register 0x00) (continued)
M
N
N
PH
B
PH
M
PH
N
N
PH
B
PH
PH
COARSE
COARSE
–81
–80
–79
–78
–77
–76
–75
–74
–73
–72
–71
–70
–69
–68
–67
–66
–65
–64
–63
–62
–61
–60
–59
–58
–57
–56
–55
–54
–53
–52
–51
–50
–49
–48
–47
–46
–45
–44
–43
–42
–41
–96
31
001111111
001000000
001000001
001000010
001000011
001000100
001000101
001000110
001000111
001001000
001001001
001001010
001001011
001001100
001001101
001001110
001001111
001010000
001010001
001010010
001010011
001010100
001010101
001010110
001010111
001011000
001011001
001011010
001011011
001011100
001011101
001011110
001011111
000100000
000100001
000100010
000100011
000100100
000100101
000100110
000100111
–40
–39
–38
–37
–36
–35
–34
–33
–32
–31
–30
–29
–28
–27
–26
–25
–24
–23
–22
–21
–20
–19
–18
–17
–16
–15
–14
–13
–12
–11
–10
–9
–32
8
9
000101000
000101001
000101010
000101011
000101100
000101101
000101110
000101111
000110000
000110001
000110010
000110011
000110100
000110101
000110110
000110111
000111000
000111001
000111010
000111011
000111100
000111101
000111110
000111111
x00000000
x00000001
x00000010
x00000011
x00000100
x00000101
x00000110
x00000111
x00001000
x00001001
x00001010
x00001011
x00001100
x00001101
x00001110
x00001111
x00010000
–64
–64
–64
–64
–64
–64
–64
–64
–64
–64
–64
–64
–64
–64
–64
–64
–64
–64
–64
–64
–64
–64
–64
–64
–64
–64
–64
–64
–64
–64
–64
–64
–32
–32
–32
–32
–32
–32
–32
–32
0
1
–32
–32
–32
–32
–32
–32
–32
–32
–32
–32
–32
–32
–32
–32
–32
–32
–32
–32
–32
–32
–32
–32
–32
0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
–8
0
8
–7
0
9
1
–6
0
10
11
12
13
14
15
16
2
–5
0
3
–4
0
4
–3
0
5
–2
0
6
–1
0
7
0
0
5599f
35
For more information www.linear.com/LTC5599
LTC5599
appenDix
Table 9. Register 0x05 Phase Shift Register Settings, Including
Table 9. Register 0x05 Phase Shift Register Settings, Including
the Extension Bits and Sign Bit (Bit 7 in Register 0x00) (continued)
the Extension Bits and Sign Bit (Bit 7 in Register 0x00) (continued)
M
N
N
PH
B
PH
M
PH
N
N
PH
B
PH
PH
COARSE
COARSE
1
0
17
x00010001
x00010010
x00010011
x00010100
x00010101
x00010110
x00010111
x00011000
x00011001
x00011010
x00011011
x00011100
x00011101
x00011110
x00011111
100100000
100100001
100100010
100100011
100100100
100100101
100100110
100100111
100101000
100101001
100101010
100101011
100101100
100101101
100101110
100101111
100110000
100110001
100110010
100110011
100110100
100110101
100110110
100110111
100111000
100111001
42
32
26
100111010
100111011
100111100
100111101
100111110
100111111
101000000
101000001
101000010
101000011
101000100
101000101
101000110
101000111
101001000
101001001
101001010
101001011
101001100
101001101
101001110
101001111
101010000
101010001
101010010
101010011
101010100
101010101
101010110
101010111
101011000
101011001
101011010
101011011
101011100
101011101
101011110
101011111
101100000
101100001
101100010
2
0
0
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
32
32
32
32
32
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
96
96
96
27
28
29
30
31
0
3
4
0
5
0
6
0
7
0
8
0
1
9
0
2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
0
3
0
4
0
5
0
6
0
7
0
8
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
9
1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
5599f
36
For more information www.linear.com/LTC5599
LTC5599
appenDix
Table 9. Register 0x05 Phase Shift Register Settings, Including
the Extension Bits and Sign Bit (Bit 7 in Register 0x00) (continued)
Table 9. Register 0x05 Phase Shift Register Settings, Including
(continued)
the Extension Bits and Sign Bit (Bit 7 in Register 0x00)
M
PH
N
N
PH
B
PH
M
N
N
PH
B
PH
COARSE
PH
COARSE
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
128
12
110001100
110001101
110001110
110001111
110010000
110010001
110010010
110010011
110010100
110010101
110010110
110010111
110011000
110011001
110011010
110011011
110011100
110011101
110011110
110011111
110100000
110100001
110100010
110100011
110100100
110100101
110100110
110100111
110101000
110101001
110101010
110101011
110101100
110101101
110101110
110101111
110110000
110110001
110110010
110110011
110110100
83
96
3
4
101100011
101100100
101100101
101100110
101100111
101101000
101101001
101101010
101101011
101101100
101101101
101101110
101101111
101110000
101110001
101110010
101110011
101110100
101110101
101110110
101110111
101111000
101111001
101111010
101111011
101111100
101111101
101111110
101111111
110000000
110000001
110000010
110000011
110000100
110000101
110000110
110000111
110001000
110001001
110001010
110001011
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
160
160
160
160
160
160
160
160
160
160
160
160
160
160
160
160
160
160
160
160
160
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
84
85
96
96
5
86
96
6
87
96
7
88
96
8
89
96
9
90
96
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
91
96
92
96
93
96
94
96
95
96
96
96
97
96
98
96
99
96
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
96
96
96
96
1
96
2
96
3
96
4
96
5
96
6
96
7
96
8
96
9
128
128
128
128
128
128
128
128
128
128
128
128
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
10
11
5599f
37
For more information www.linear.com/LTC5599
LTC5599
appenDix
Table 9. Register 0x05 Phase Shift Register Settings, Including
the Extension Bits and Sign Bit (Bit 7 in Register 0x00) (continued)
Table 9. Register 0x05 Phase Shift Register Settings, Including
the Extension Bits and Sign Bit (Bit 7 in Register 0x00)
(continued)
M
N
N
PH
B
PH
M
PH
N
N
PH
B
PH
PH
COARSE
COARSE
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
160
21
110110101
110110110
110110111
110111000
110111001
110111010
110111011
110111100
110111101
110111110
110111111
111000000
111000001
111000010
111000011
111000100
111000101
111000110
111000111
111001000
111001001
111001010
111001011
111001100
111001101
111001110
111001111
111010000
111010001
111010010
111010011
111000100
111010101
111010110
111010111
111011000
111011001
111011010
111011011
111011100
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
192
29
111011101
111011110
111011111
111100000
111100001
111100010
111100011
111100100
111100101
111100110
111100111
111101000
111101001
111101010
111101011
111101100
111101101
111101110
111101111
111110000
111110001
111110010
111110011
111110100
111110101
111110110
111110111
111111000
111111001
111111010
111111011
111111100
111111101
111111110
111111111
160
160
160
160
160
160
160
160
160
160
192
192
192
192
192
192
192
192
192
192
192
192
192
192
192
192
192
192
192
192
192
192
192
192
192
192
192
192
192
22
23
24
25
26
27
28
29
30
31
0
192
192
224
224
224
224
224
224
224
224
224
224
224
224
224
224
224
224
224
224
224
224
224
224
224
224
224
224
224
224
224
224
224
224
30
31
0
1
2
3
4
5
6
7
8
1
9
2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
5599f
38
For more information www.linear.com/LTC5599
LTC5599
appenDix
Table 10. Serial Port Register Contents
ADDR
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
MSB
[6]
[5]
[4]
[3]
[2]
[1]
LSB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
DEFAULT
0x2E
0x84
0x80
0x80
0x80
0x10
0x50
0x06
0x00
0x00
0x01
0x0X
0xXX
0x0X
0xXX
0x0X
0x08
0xFF
0x01
0x08
0xFF
0x01
0x08
0xFF
0x01
0x08
0xFF
0x01
0x00
0x00
0x04
0x0Y
IQPHSIGN
FREQ[6]
FREQ[5]
QDISABLE
FREQ[4]
GAIN[4]
FREQ[3]
GAIN[3]
FREQ[2]
GAIN[2]
FREQ[1]
GAIN[1]
FREQ[0]
GAIN[0]
TEMPUPDT AGCTRL
OFFSETI[7] OFFSETI[6] OFFSETI[5] OFFSETI[4] OFFSETI[3] OFFSETI[2] OFFSETI[1] OFFSETI[0]
OFFSETQ[7] OFFSETQ[6] OFFSETQ[5] OFFSETQ[4] OFFSETQ[3] OFFSETQ[2] OFFSETQ[1] OFFSETQ[0]
IQGR[7]
IQGR[6]
IQGR[5]
IQGR[4]
IQPHF[4]
CLOEN
IQGR[3]
IQPHF[3]
CLOO[3]
GAINF[3]
SRESET
IQGR[2]
IQPHF[2]
CLOO[2]
GAINF[2]
IQGR[1]
IQPHF[1]
CLOO[1]
GAINF[1]
IQGR[0]
IQPHF[0]
CLOO[0]
GAINF[0]
IQPHE[2]
IQPHE[1]
IQPHE[0]
*
*
*
†
†
†
†
0
0
0
0
†
†
†
†
0
0
0
0
TEMPCORR THERMINP
*
†
†
†
†
†
†
†
†
0
0
0
0
0
0
0
0
CHIPID[7] CHIPID[6] CHIPID[5] CHIPID[4] CHIPID[3] CHIPID[2] CHIPID[1] CHIPID[0]
R
†
†
†
†
†
†
†
†
†
0
0
0
0
0
0
0
0
0
0
FUSE[3]
CPPP0[3]
CPPP1[3]
FUSE[2]
CPPP0[2]
CPPP1[2]
FUSE[1]
CPPP0[1]
CPPP1[1]
FUSE[0]
CPPP0[0]
CPPP1[0]
R
†
CPPP0[5]
CPPP1[5]
CPPP0[4]
CPPP1[4]
R
CPPP1[6]
R
†
0
CPPM0[5] CPPM0[4] CPPM0[3] CPPM0[2] CPPM0[1] CPPM0[0]
R
CPPM1[6] CPPM1[5] CPPM1[4] CPPM1[3] CPPM1[2] CPPM1[1] CPPM1[0]
R
GPI0[6]
GPI1[6]
GPI2[6]
GMI0[6]
GMI1[6]
GMI2[6]
GPQ0[6]
GPQ1[6]
GPQ2[6]
GMQ0[6]
GMQ1[6]
GMQ2[6]
GPI0[5]
GPI1[5]
GPI2[5]
GMI0[5]
GMI1[5]
GMI2[5]
GPQ0[5]
GPQ1[5]
GPQ2[5]
GMQ0[5]
GMQ1[5]
GMQ2[5]
GPI0[4]
GPI1[4]
GPI2[4]
GMI0[4]
GMI1[4]
GMI2[4]
GPQ0[4]
GPQ1[4]
GPQ2[4]
GMQ0[4]
GMQ1[4]
GMQ2[4]
GPI0[3]
GPI1[3]
GPI2[3]
GMI0[3]
GMI1[3]
GMI2[3]
GPQ0[3]
GPQ1[3]
GPQ2[3]
GMQ0[3]
GMQ1[3]
GMQ2[3]
GPI0[2]
GPI1[2]
GPI2[2]
GMI0[2]
GMI1[2]
GMI2[2]
GPQ0[2]
GPQ1[2]
GPQ2[2]
GMQ0[2]
GMQ1[2]
GMQ2[2]
GPI0[1]
GPI1[1]
GPI2[1]
GMI0[1]
GMI1[1]
GMI2[1]
GPQ0[1]
GPQ1[1]
GPQ2[1]
GMQ0[1]
GMQ1[1]
GMQ2[1]
GPI0[0]
GPI1[0]
GPI2[0]
GMI0[0]
GMI1[0]
GMI2[0]
GPQ0[0]
GPQ1[0]
GPQ2[0]
GMQ0[0]
GMQ1[0]
GMQ2[0]
R
GPI1[7]
R
†
0
R
†
0
R
GMI1[7]
R
†
0
R
†
0
R
GPQ1[7]
R
†
0
R
†
0
R
GMQ1[7]
R
†
0
R
†
†
†
†
†
†
†
†
0
0
0
0
0
0
0
0
R
†
†
†
†
0
0
0
0
CLO[3]
IDT[3]
CLO[2]
IDT[2]
CLO[1]
IDT[1]
CLO[0]
IDT[0]
R
†
†
†
0
0
0
GOR
R
†
†
†
†
0x1F
0
0
0
0
TEMP[3]
TEMP[2]
TEMP[1]
TEMP[0]
R
†
*unused read-only; values written are disregarded, X = production dependent, Y = resets to 7 after EN from Low to High with TEMPUPDT = 1, for EN =
Low all read-only (R) registers default to 0x00.
5599f
39
For more information www.linear.com/LTC5599
LTC5599
appenDix
Table 11. Serial Port Register Bit Field Summary
BITS
FUNCTION
DESCRIPTION
VALID VALUES DEFAULT
AGCTRL
CHIPID[7:0]
CLO[3:0]
CLOO[3:0]
CLOEN
Analog Gain Control Enable
Chip ID
Enables analog control through V
(Pin 1) when AGCTRL = 1.
0, 1
1
1
1
CTRL
LO Port Match Cap Array
LO Port Cap Array Override
Automatic LO Match Enable
LO port match, automatically adjusted through programming FREQ[6:0]
Programs LO port match capacitor array when CLOEN = 0
0x00 to 0x0F
0x00 to 0x0F
0, 1
0x00
0x00
1
Automatic LO port impedance matching enabled when CLOEN = 1. Override
bits CLOO[3:0] control LO port match when CLOEN = 0.
CPPM0[5:0]
CPPM1[6:0]
CPPP0[5:0]
CPPP1[6:0]
FREQ[6:0]
FUSE[3:0]
GAIN[4:0]
GAINF[3:0]
GMI0[6:0]
GMI1[7:0]
GMI2[6:0]
GMQ0[6:0]
GMQ1[7:0]
GMQ2[6:0]
GOR
C
C
C
C
Fine Control
Coarse Control
Fine Control
C
= CPPM0[5:0] + number of 1’s in CPPM1[6:0] × 64
0x00 to 0x5F
0x00 to 0x7F
0x00 to 0x5F
0x00 to 0x7F
0x00 to 0x79
0x00 to 0x0F
0x00 to 0x13
0xXX
0x0X
0xXX
0x0X
0x2E
0x0X
0x04
0x00
0x08
0xFF
0x01
0x08
0xFF
0x01
0
ppQ
ppQ
ppI
ppQ
C
= CPPP0[5:0] + number of 1’s in CPPP1[6:0] × 64
ppI
Coarse Control
ppI
Poly-Phase Filter Frequency
Fuse Read Out
Programs the center frequency of the poly-phase filter, according to Table 5.
Programs the conversion gain in 1dB steps, according to Table 3.
Coarse Digital Gain Control
Fine Digital Gain Control
Fine GMI DAC Read-Out
Coarse GMI DAC Read-Out1
Coarse GMI DAC Read-Out2
Fine GMQ DAC Read-Out
Conversion gain control in approximately 0.1dB steps, when TEMPCORR = 1. 0x00 to 0x0F
BBMI input stage gain GmI.
0x00 to 0x7F
0x00 to 0x07
0x00 to 0x07
0x00 to 0x7F
0x00 to 0x07
0x00 to 0x07
0, 1
GmI = GMI0[6:0] + (number of 1’s in GMI1[7:0] and GMI2[6:0]) × 128
BBMQ input stage gain GmQ.
Coarse GMQ DAC Read-Out1 GmQ = GMQ0[6:0] + (number of 1’s in GMQ1[7:0] and GMQ2[6:0]) × 128
Coarse GMQ DAC Read-Out2
Gain Out of Range
For DG < –19 GOR = 1; Else GOR = 0
GPI0[6:0]
GPI1[7:0]
GPI2[6:0]
GPQ0[6:0]
GPQ1[7:0]
GPQ2[6:0]
IDT[3:0]
Fine GPI DAC Read-Out
Coarse GPI DAC Read-Out1
Coarse GPI DAC Read-Out2
Fine GPQ DAC Read-Out
Coarse GPQ DAC Read-Out1
Coarse GPQ DAC Read-Out2
RF Buffer Bias
BBPI input stage gain GpI.
0x00 to 0x7F
0x00 to 0x07
0x00 to 0x07
0x00 to 0x7F
0x00 to 0x07
0x00 to 0x07
0x00 to 0x0D
0x00 to 0xFF
0x00 to 0x07
0x00 to 0x1F
0x08
0xFF
0x01
0x08
0xFF
0x01
0x04
0x80
0x00
0x10
GpI = GPI0[6:0] + (number of 1’s in GPI1[7:0] and GPI2[6:0]) × 128
BBPQ input stage gain GpQ.
GpQ = GPQ0[6:0] + (number of 1’s in GPQ1[7:0] and GPQ2[6:0]) × 128
IQGR[7:0]
IQPHE[2:0]
IQPHF[4:0]
I/Q Gain Ratio Control
I/Q Phase Extension Bits
Adjust the gain difference in approximate constant steps in dB. See Table 4.
Extend the IQ phase adjustment range. See Table 9.
Fine I/Q Phase Balance
Control
Fine adjustment of IQ LO phase difference. See Table 9. Zero phase shift for
0x10.
IQPHSIGN
Sign IQ Phase Extension Bits Encodes the sign of the IQ phase extension bits IQPHE[2:0]. Positive for
IQPHSIGN = 1.
0, 1
0
OFFSETI[7:0] I-Channel Offset Control
OFFSETQ[7:0] Q-Channel Offset Control
Adjusts DC offset in the I-channel. Zero offset for 0x80. See page 19.
Adjusts DC offset in the Q-channel. Zero offset for 0x80. See page 19.
0x01 to 0xFF
0x01 to 0xFF
0, 1
0x80
0x80
0
QDISABLE
Disable Q-Channel
QDISABLE = 1 shuts down the Q-channel, turning the LTC5599 into an
upconversion mixer.
SRESET
Soft Reset
Writing 1 to this bit resets all registers to their default values.
Digital representation of die temperature. Step size about 10°C.
0, 1
0x00 to 0x07
0, 1
0
0x07
0
TEMP[3:0]
TEMPCORR
Thermometer Output
Temperature Correction
Disable
TEMPCORR = 1 disables temperature correction of the gain, and enables
manual fine-adjustment using bits GAINF[3:0].
TEMPUPDT
THERMINP
Temperature Correction
Update
TEMPUPDT = 1 synchronizes temperature correction of the gain to a LOW
0, 1
0
1
- HIGH transition on the TTCK pin. Asynchronous correction for TEMPUPDT
= 0.
Thermometer Input Select
For test purposes only. Should be set to 0.
For more information www.linear.com/LTC5599
0
5599f
40
LTC5599
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-ꢀ697 Rev B)
0.70 0.05
4.50 0.05
3.ꢀ0 0.05
2.45 0.05
(4 SIDES)
PACKAGE OUTLINE
0.25 0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
BOTTOM VIEW—EXPOSED PAD
R = 0.ꢀꢀ5
PIN ꢀ NOTCH
R = 0.20 TYP OR
0.35 × 45° CHAMFER
0.75 0.05
4.00 0.ꢀ0
(4 SIDES)
TYP
23 24
PIN ꢀ
TOP MARK
(NOTE 6)
0.40 0.ꢀ0
ꢀ
2
2.45 0.ꢀ0
(4-SIDES)
(UF24) QFN 0ꢀ05 REV B
0.200 REF
0.25 0.05
0.50 BSC
0.00 – 0.05
NOTE:
ꢀ. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.ꢀ5mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
5599f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
41
LTC5599
Typical applicaTion
V
CTRL
3.3V
22, 21, 20, 19
24
1nF + 4.7µF
V
CC
LTC5599
SPI
RF = 90MHz
to 1300MHz
8
9
V
V
I
I
I-DAC
I-CHANNEL
10nF
16
PA
1
0°
23
EN
90°
13, 14, 15, 17, 18
10
11
Q-DAC
Q-CHANNEL
6
THERMOMETER
TTCK
BASEBAND
GENERATOR
3
4
2, 5, 12
5599 TA01a
39nH
VCO/SYNTHESIZER
15pF
Figure 16. 90MHz to 1300MHz Direct Conversion Transmitter Application
relaTeD parTs
PART NUMBER DESCRIPTION
COMMENTS
22.8dBm OIP3 at 2GHz, –158.2dBm/Hz Noise Floor, 3kΩ 2.1V
Infrastructure
LT5518
LT5528
LT5558
LT5568
LT5571
LT5572
1.5GHz to 2.4GHz High Linearity Direct Quadrature Modulator
1.5GHz to 2.4GHz High Linearity Direct Quadrature Modulator
DC
Baseband Interface, 5V/128mA Supply
21.8dBm OIP3 at 2GHz, –159.3dBm/Hz Noise Floor, 50Ω 0.5V
Baseband Interface, 5V/128mA Supply
DC
600MHz to 1100MHz High Linearity Direct Quadrature Modulator 22.4dBm OIP3 at 900MHz, –158dBm/Hz Noise Floor, 3kΩ 2.1V
Baseband Interface, 5V/108mA Supply
DC
700MHz to 1050MHz High Linearity Direct Quadrature Modulator 22.9dBm OIP3 at 850MHz, –160.3dBm/Hz Noise Floor, 50Ω 0.5V
Baseband Interface, 5V/117mA Supply
DC
620MHz to 1100MHz High Linearity Direct Quadrature Modulator 21.7dBm OIP3 at 900MHz, –159dBm/Hz Noise Floor, Hi-Z 0.5V
Baseband Interface, 5V/97mA Supply
DC
1.5GHz to 2.5GHz High Linearity Direct Quadrature Modulator
21.6dBm OIP3 at 2GHz, –158.6dBm/Hz Noise Floor, Hi-Z 0.5V
Baseband Interface, 5V/120mA Supply
DC
LTC5598
LT5560
5MHz to 1600MHz High Linearity Direct Quadrature Modulator
0.01MHz to 4GHz Low Power Active Mixer
27.7dBm OIP3 at 140MHz, –160dBm/Hz Noise Floor with P
= 5dBm
OUT
IIP3 = 9dBm, 2.6dB Conversion Gain, 9.3dB NF, 3.0V/10mA Supply
Current
LT5506/5546
40MHz to 500MHz Quadrature Demodulator with VGA
56dB Gain, –49 to 0dBm IIP3, 6.8dB NF, 1.8V to 5.25V/26.5mA
Supply Current
LTC5510
1MHz to 6GHz, 3.3V Wideband High Linearity Active Mixer
1.5dB Gain, 27dBm IIP3, 11.6dB NF, 3.3V/105mA Supply Current
RF Power Detector
LT5581
6GHz Low Power RMS Detector
40dB Dynamic Range, 1dB Accuracy Over Temperature, 1.5mA
Supply Current
LTC5582
40MHz to 10GHz RMS Power Detector
57dB Dynamic Range, 1dB Accuracy Over Temperature, Single-Ended
RF Input (No Transformer)
LT5534
LT5537
50MHz to 3GHz RF Power Detector with 60dB Dynamic Range
LF to 1GHz Wide Dynamic Range RF/IF Log Detector
60dB Dynamic Range, Linear-in-dB Response, 2.7V to 5.25V/7mA
83dB Dynamic Range, Linear-in-dB Response, 2.7V to 5.25V/13.5mA
5599f
LT 0814 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
42
●
●
ꢀLINEAR TECHNOLOGY CORPORATION 2014
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC5599
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