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LTC4367HDD-1#PBF [Linear]

LTC4367 - 100V Overvoltage, Undervoltage and Reverse Supply Protection Controller; Package: DFN; Pins: 8; Temperature Range: -40°C to 125°C;
LTC4367HDD-1#PBF
型号： LTC4367HDD-1#PBF
厂家： Linear    Linear
描述：

LTC4367 - 100V Overvoltage, Undervoltage and Reverse Supply Protection Controller; Package: DFN; Pins: 8; Temperature Range: -40°C to 125°C
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LTC4367  
100V Overvoltage,  
Undervoltage and Reverse  
Supply Protection Controller  
DESCRIPTION  
FEATURES  
n
Wide Operating Voltage Range: 2.5V to 60V  
The LTC®4367 protects applications where power sup-  
ply input voltages may be too high, too low or even  
negative. It does this by controlling the gate voltages of  
a pair of external N-channel MOSFETs to ensure that the  
output stays within a safe operating range.The LTC4367  
withstands voltages between –40V and 100V and has an  
operating range of 2.5V to 60V, while consuming only  
70µA in normal operation.  
n
Overvoltage Protection to 100V  
n
Reverse Supply Protection to –40V  
n
LTC4367: Blocks 50Hz and 60Hz AC Power  
n
LTC4367: 32ms Recovery from Fault  
n
LTC4367-1: Fast 500µs Recovery from Fault  
n
No Input Capacitor or TVS Required for Most  
Applications  
n
Adjustable Undervoltage and Overvoltage Thresholds  
Two comparator inputs allow configuration of the over-  
voltage (OV) and undervoltage (UV) set points using an  
externalresistivedivider.Ashutdownpinprovidesexternal  
control for enabling and disabling the MOSFETs as well  
as placing the device in a low current shutdown state. A  
faultoutputindicatesthattheGATEpinispullinglowwhen  
the part is in shutdown or the input voltage is outside the  
UV and OV set points.  
n
Controls Back-to-Back N-Channel MOSFETs  
n
Low Operating Current: 70µA  
Low Shutdown Current: 5µA  
n
n
8-Pin MSOP and 3mm × 3mm DFN Packages  
APPLICATIONS  
n
Portable Instrumentation  
The LTC4367 has a 32ms turn-on delay that debounces  
live connections and blocks 50Hz to 60Hz AC power. For  
fast recovery after faults, the LTC4367-1 has a reduced  
turn-on delay of 500µs.  
n
Industrial Automation  
n
Automotive Surge (Load Dump) Protection  
Network Equipment  
n
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and  
ThinSOT is a trademark of Analog Devices, Inc. All other trademarks are the property of their  
respective owners.  
TYPICAL APPLICATION  
24V Automotive Application with +100V, –40V Protection  
Load Protected from Reverse and Overvoltage at VIN  
Si7942  
V
V
OUT  
2A  
OV = 36V  
UV = 7V  
IN  
+70V  
20V/DIV  
24V  
V
IN  
GATE  
V
V
OUT  
IN  
VALID WINDOW  
464k  
GND  
SHDN  
V
V
OUT  
OUT  
1500k  
121k  
UV  
OV  
–40V  
20V/DIV  
FAULT  
V
IN  
OV = 36V  
UV = 7V  
29.4k  
GND  
4367 TA01b  
4367 TA01a  
200ms/DIV  
LTC4367  
4367fb  
1
For more information www.linear.com/LTC4367  
LTC4367  
ABSOLUTE MAXIMUM RATINGS  
(Note 1, Note 2)  
Supply Voltage  
Input Currents  
V ........................................................ –40V to 100V  
SHDN, UV .........................................................–1mA  
OV......................................................................–1mA  
Operating Ambient Temperature Range  
IN  
Input Voltages (Note 3)  
UV, SHDN .............................................. –0.3V to 80V  
OV............................................................ –0.3V to 5V  
LTC4367C................................................ 0°C to 70°C  
LTC4367I.............................................–40°C to 85°C  
LTC4367H.......................................... –40°C to 125°C  
Storage Temperature Range .................. –65°C to 150°C  
Lead Temperature (Soldering, 10sec)  
V ....................................................... –0.3V to 80V  
OUT  
Output Voltages  
FAULT..................................................... –0.3V to 80V  
GATE (Note 4)......................................... –40V to 75V  
for MSOP Only..................................................300°C  
PIN CONFIGURATION  
TOP VIEW  
TOP VIEW  
V
1
2
3
4
8
7
6
5
GATE  
IN  
V
UV 2  
OV 3  
1
8 GATE  
UV  
OV  
V
IN  
OUT  
9
7 V  
OUT  
FAULT  
SHDN  
6
FAULT  
GND  
GND 4  
5 SHDN  
MS8 PACKAGE  
8-LEAD PLASTIC MSOP  
= 150°C, θ = 160°C/W  
DD PACKAGE  
8-LEAD (3mm × 3mm) PLASTIC DFN  
T
JMAX  
JA  
EXPOSED PAD (PIN 9) PCB GROUND CONNECTION OPTIONAL  
T
= 150°C, θ = 43°C/W, θ = 5.5°C/W  
JMAX  
JA JC  
4367fb  
2
For more information www.linear.com/LTC4367  
LTC4367  
ORDER INFORMATION  
http://www.linear.com/product/LTC4367#orderinfo  
LEAD FREE FINISH  
LTC4367CDD#PBF  
LTC4367CDD-1#PBF  
LTC4367IDD#PBF  
TAPE AND REEL  
PART MARKING*  
LGTF  
PACKAGE DESCRIPTION  
TEMPERATURE RANGE  
0°C to 70°C  
LTC4367CDD#TRPBF  
LTC4367CDD-1#TRPBF  
LTC4367IDD#TRPBF  
LTC4367IDD-1#TRPBF  
LTC4367HDD#TRPBF  
LTC4367HDD-1#TRPBF  
LTC4367CMS8#TRPBF  
LTC4367CMS8-1#TRPBF  
LTC4367IMS8#TRPBF  
LTC4367IMS8-1#TRPBF  
LTC4367HMS8#TRPBF  
LTC4367HMS8-1#TRPBF  
8-Lead (3mm × 3mm) Plastic DFN  
8-Lead (3mm × 3mm) Plastic DFN  
8-Lead (3mm × 3mm) Plastic DFN  
8-Lead (3mm × 3mm) Plastic DFN  
8-Lead (3mm × 3mm) Plastic DFN  
8-Lead (3mm × 3mm) Plastic DFN  
8-Lead Plastic MSOP  
LGVW  
0°C to 70°C  
LGTF  
–40°C to 85°C  
–40°C to 85°C  
–40°C to 125°C  
–40°C to 125°C  
0°C to 70°C  
LTC4367IDD-1#PBF  
LTC4367HDD#PBF  
LTC4367HDD-1#PBF  
LTC4367CMS8#PBF  
LTC4367CMS8-1#PBF  
LTC4367IMS8#PBF  
LTC4367IMS8-1#PBF  
LTC4367HMS8#PBF  
LTC4367HMS8-1#PBF  
LGVW  
LGTF  
LGVW  
LTGTD  
LTGVX  
LTGTD  
LTGVX  
LTGTD  
LTGVX  
8-Lead Plastic MSOP  
0°C to 70°C  
8-Lead Plastic MSOP  
–40°C to 85°C  
–40°C to 85°C  
–40°C to 125°C  
–40°C to 125°C  
8-Lead Plastic MSOP  
8-Lead Plastic MSOP  
8-Lead Plastic MSOP  
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.  
For more information on lead free part marking, go to: http://www.linear.com/leadfree/  
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through  
designated sales channels with #TRMPBF suffix.  
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating  
temperature range, otherwise specifications are at TA = 25°C. VIN = 2.5V to 60V, unless otherwise noted. (Note 2)  
SYMBOL PARAMETER  
V , V  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
IN OUT  
l
l
V
Input Voltage:Operating Range  
Protection Range  
2.5  
–40  
60  
100  
V
V
IN  
l
V
Input Supply Undervoltage Lockout  
V
Rising  
IN  
1.8  
2.2  
2.4  
V
IN(UVLO)  
VIN  
l
l
I
Input Supply Current: On  
Off  
SHDN = 2.5V  
SHDN = 0V, V = V  
30  
5
90  
20  
µA  
µA  
IN  
OUT  
l
I
I
Reverse Input Supply Current  
V
= –40V, V = 0V  
OUT  
–1.5  
–2.5  
mA  
VIN(R)  
VOUT  
IN  
l
l
l
V
Input Current: On  
Off  
SHDN = 2.5V, V = V  
OUT  
40  
3
20  
110  
15  
50  
µA  
µA  
µA  
OUT  
IN  
SHDN = 0V, V = V  
IN  
OUT  
OUT  
= 0V  
Reverse  
V
= –40V, V  
IN  
GATE  
l
l
ΔV  
Gate Drive (GATE – V  
Gate Pull Up Current  
)
V
V
= V  
= V  
= 5.0V, I = 0µA, –1µA  
GATE  
7.2  
10  
8.7  
11  
10.8  
13.1  
V
V
GATE  
OUT  
IN  
IN  
OUT  
OUT  
= 12V to 60V, I  
= 0µA, –1µA  
GATE  
l
l
l
l
l
I
I
I
t
t
GATE = 15V, V = V = 12V  
OUT  
–20  
50  
–35  
90  
–60  
160  
90  
µA  
µA  
mA  
µs  
GATE(UP)  
IN  
Gate Slow Pull Down Current  
Gate Fast Pull Down Current  
Slow Turn Off Delay  
GATE = 20V, V = V = 12V  
IN OUT  
GATE(SLOW)  
GATE(FAST)  
GATE(SLOW)  
GATE(FAST)  
GATE = 20V, V = V = 12V  
30  
60  
IN  
OUT  
C
= 2.2nF, SHDN Falling, V = V  
= 12V  
150  
250  
2
575  
6
GATE  
GATE  
IN  
OUT  
Gate Fast Turn Off Delay  
C
= 2.2nF, UV or OV Fault  
µs  
4367fb  
3
For more information www.linear.com/LTC4367  
LTC4367  
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating  
temperature range, otherwise specifications are at TA = 25°C. VIN = 2.5V to 60V, unless otherwise noted. (Note 2)  
SYMBOL PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
t
GATE Turn-On Delay Time  
V
= 12V, Power Good to ΔV  
> 0V, C  
= 2.2nF  
D(ON)  
IN  
GATE  
GATE  
l
l
LTC4367  
22  
0.2  
32  
0.5  
45  
1.2  
ms  
ms  
LTC4367-1  
UV, OV  
l
l
l
l
l
l
V
V
V
V
UV Input Threshold Voltage  
OV Input Threshold Voltage  
UV Input Hysteresis  
UV Falling  
OV Rising  
492.5  
492.5  
20  
500  
500  
25  
507.5  
507.5  
32  
mV  
mV  
mV  
mV  
nA  
UV  
OV  
V
V
= V  
= V  
= 12V  
= 12V  
UVHYST  
OVHYST  
LEAK  
IN  
IN  
OUT  
OUT  
OV Input Hysteresis  
20  
25  
32  
I
t
UV, OV Leakage Current  
UV, OV Fault Propagation Delay  
V = 0.5V, V = 60V  
10  
IN  
Overdrive = 50mV  
1
2
µs  
FAULT  
V
= V  
= 12V  
IN  
OUT  
SHDN  
l
l
l
V
SHDN Input Threshold  
SHDN Falling  
SHDN = 10V, V = 60V  
0.4  
0.75  
1.2  
15  
V
SHDN  
SHDN  
START  
I
t
SHDN Input Current  
nA  
IN  
Delay Coming Out of Shutdown Mode  
SHDN Rising to FAULT Released, V = V  
LTC4367  
LTC4367-1  
= 12V  
IN  
OUT  
400  
125  
800  
250  
1400  
500  
µs  
µs  
l
t
t
SHDN to FAULT Asserted  
V
= V  
= 12V  
= 12V  
1.5  
3
µs  
SHDN(F)  
IN  
OUT  
Delay from Turn Off to Low Power  
Operation  
V
= V  
LOWPWR  
IN  
OUT  
l
l
LTC4367  
20  
0.125  
32  
0.3  
48  
0.6  
ms  
ms  
LTC4367-1  
FAULT  
l
l
V
FAULT Output Voltage Low  
FAULT Leakage Current  
I
= 500µA, V = 12V  
0.15  
0.4  
V
OL  
FAULT  
IN  
I
FAULT = 5V, V = 60V  
200  
nA  
FAULT  
IN  
Note 1. Stresses beyond those listed under Absolute Maximum Ratings  
may cause permanent damage to the device. Exposure to any Absolute  
Maximum Rating condition for extended periods may affect device  
reliability and lifetime.  
Note 3. These pins have a diode to GND. They may go below –0.3V if the  
current magnitude is limited to less than 1mA.  
Note 4. The GATE pin is referenced to V  
and does not exceed 73V for  
OUT  
the entire operating range.  
Note 2. All currents into pins are positive; all voltages are referenced to  
GND unless otherwise noted.  
4367fb  
4
For more information www.linear.com/LTC4367  
LTC4367  
TYPICAL PERFORMANCE CHARACTERISTICS  
VIN Operating Current vs  
Temperature  
VIN Shutdown Current vs  
Voltage  
VIN Supply Current vs Voltage  
(–40V to 100V)  
8
6
4
2
0
50  
40  
30  
20  
10  
0
500  
0
SHDN = 0V  
UV = SHDN = 0V  
SHDN = 2.5V  
V
IN  
= V  
V
= 0V  
V
IN  
= V  
OUT  
OUT  
OUT  
V
= 60V  
IN  
–500  
–1000  
–1500  
–2000  
V
= 12V  
IN  
V
= 2.5V  
IN  
T
T
T
T
= 125°C  
= 70°C  
= 25°C  
= –45°C  
A
A
A
A
T
T
T
= 125°C  
= 25°C  
= –45°C  
A
A
A
0
10  
20  
30  
(V)  
40  
50  
60  
–50 –25  
0
25  
50  
75 100 125  
–50  
–25  
0
25  
(V)  
50  
75  
100  
V
TEMPERATURE (°C)  
V
IN  
IN  
4367 G02  
4367 G01  
4367 G03  
VOUT Operating Current vs  
Temperature  
VOUT Shutdown Current vs  
Temperature  
VOUT Current vs Reverse VIN  
50  
40  
30  
20  
10  
0
6
5
4
3
2
1
0
20  
15  
10  
5
SHDN = 0V  
V
= 0V  
SHDN = 2.5V  
OUT  
V
= 60V  
OUT  
–45°C  
V
IN  
= V  
V
= V  
OUT  
IN  
OUT  
V
= 60V  
OUT  
V
= 12V  
OUT  
25°C  
V
= 2.5V  
V
= 12V  
OUT  
OUT  
125°C  
V
OUT  
= 2.5V  
0
–50 –25  
0
25  
50  
75 100 125  
–50 –25  
0
25  
50  
75 100 125  
0
–10  
–20  
(V)  
–30  
–40  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
V
IN  
4367 G04  
4367 G05  
4367 G06  
GATE Drive vs  
GATE Drive vs GATE Current  
VIN Supply Voltage  
GATE Drive vs Temperature  
16  
12  
8
15  
12  
9
12  
10  
8
I
= 1µA  
GATE  
T
T
T
= 125°C  
V
= V  
= 12V  
OUT  
A
A
A
IN  
V
= 0V  
= 25°C  
OUT  
V
= V  
= 60V  
OUT  
IN  
= –45°C  
V
= V  
= 12V  
OUT  
IN  
V
= V  
OUT  
IN  
6
6
4
4
V
= V  
= 2.5V  
OUT  
IN  
3
2
T
GATE  
= 25°C  
A
I
= –1µA  
0
0
0
0
10  
20  
30  
(V)  
40  
50  
60  
–50 –25  
0
25  
50  
75 100 125  
0
–10  
–20  
–30  
–40  
–50  
–60  
TEMPERATURE (°C)  
I
(µA)  
V
IN  
GATE(UP)  
4367 G08  
4367 G09  
4367 G07  
4367fb  
5
For more information www.linear.com/LTC4367  
LTC4367  
TYPICAL PERFORMANCE CHARACTERISTICS  
UV/OV/SHDN Leakage vs  
OV Threshold vs Temperature  
Temperature  
UV Threshold vs Temperature  
508  
504  
500  
496  
492  
508  
504  
500  
496  
492  
8
6
V
= V  
= 60V  
OUT  
IN  
V
= V  
= 12V  
V
= V  
= 12V  
OUT  
IN  
OUT  
IN  
4
SHDN = 60V  
2
0
UV/OV = 0.5V  
–2  
–50 –25  
0
25  
50  
75 100 125  
–50 –25  
0
25  
50  
75 100 125  
–50 –25  
0
25  
50  
75 100 125  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
4367 G10  
4367 G11  
4367 G12  
UV/OV Propagation Delay vs  
Overdrive  
LTC4367 GATE Turn-On Delay  
Time vs Temperature  
Recovery Delay Time vs  
Temperature  
LTC4367 GATE Turn-On Delay  
Time vs VIN  
50  
40  
30  
20  
10  
0
50  
40  
30  
20  
10  
0
50  
40  
30  
20  
10  
0
V
= V  
= 12V  
OUT  
A
IN  
T
= 25°C  
T
= 125°C  
T = –45°C  
A
A
T
= 25°C  
V
= 12V, 60V  
A
IN  
V
= 2.5V  
IN  
1
10  
100  
1k  
–50 –25  
0
25  
50  
75 100 125  
0
10  
20  
30  
(V)  
40  
50  
60  
OVERDRIVE (mV)  
TEMPERATURE (°C)  
V
IN  
4367 G13  
4367 G14  
4367 G15  
LTC4367 AC Blocking  
Turn-On Timing  
Turn-Off Timing  
V
1V/DIV  
OUT  
DUAL Si7942 MOSFET  
100µF, 12Ω LOAD  
GND  
GATE  
GATE  
5V/DIV  
V
IN  
= 12V  
V
OUT  
V
IN  
20V/DIV  
V
5V/DIV  
OUT  
GND  
GATE  
GND  
GND  
V
= 12V  
IN  
DUAL Si7942 MOSFET  
100µF, 12Ω LOAD  
DUAL Si7942  
1k, 10µF LOAD ON V  
SHDN  
OUT  
3V/DIV  
SHDN  
3V/DIV  
4367 G16  
4367 G18  
4367 G17  
400µs/DIV  
400µs/DIV  
5ms/DIV  
4367fb  
6
For more information www.linear.com/LTC4367  
LTC4367  
PIN FUNCTIONS  
Exposed Pad: The exposed pad may be left open or con-  
nected to device ground.  
SHDN: Shutdown Control Input. SHDN high enables the  
GATE charge pump which in turn enhances the gate of an  
external N-channel MOSFET. A low on SHDN generates a  
pull down on the GATE output with a 90µA current sink  
and places the LTC4367 in low current mode (5µA). If  
FAULT: FaultIndicationOutput.Thishighvoltageopendrain  
output is pulled low if UV is below its monitor threshold,  
if OV is above its monitor threshold, if SHDN is low, or if  
unused, connect to V with a 510k resistor. If V goes  
IN  
IN  
V has not risen above V  
IN  
.
IN(UVLO)  
above 80V, the SHDN pin voltage must be kept below 80V  
(see Applications Information).  
GATE:GateDriveOutputforExternalN-channelMOSFETs.  
An internal charge pump provides 35µA of pull-up current  
and up to 13.1V of enhancement to the gate of an external  
N-channel MOSFET. When turned off, GATE is pulled just  
UV:UndervoltageComparatorInput.Connectthispintoan  
external resistive divider to set the desired V undervolt-  
IN  
age fault threshold. This input connects to an accurate,  
fast (1µs) comparator with a 0.5V falling threshold and  
25mV of hysteresis. When UV falls below its threshold, a  
60mA current sink pulls down on the GATE output. When  
UV rises back above 0.525V, and after a 32ms GATE turn-  
on delay waiting period (500µs for LTC4367-1), the GATE  
charge pump is enabled. The low leakage current of the  
UV input allows the use of large valued resistors for the  
below the lower of V or V . When V goes negative,  
IN  
OUT  
IN  
GATE is automatically connected to V .  
IN  
GND: Device Ground.  
OV: Overvoltage Comparator Input. Connect this pin to an  
externalresistivedividertosetthedesiredV overvoltage  
IN  
fault threshold. This input connects to an accurate, fast  
(1µs) comparator with a 0.5V rising threshold and 25mV  
of hysteresis. When OV rises above its threshold, a 60mA  
currentsinkpullsdownontheGATEoutput. WhenOVfalls  
back below 0.475V, and after a 32ms GATE turn-on delay  
waiting period (500µs for LTC4367-1), the GATE charge  
pump is enabled. The low leakage current of the OV input  
allows the use of large valued resistors for the external  
resistive divider. Connect to GND if unused. If the voltage  
at the OV pin can rise above 5V, place a low leakage Zener  
clamp on the OV pin.  
external resistive divider. If unused and V is less than  
IN  
80V, connect to V with a 510k resistor.  
IN  
V : Power Supply Input. Maximum protection range:  
IN  
–40V to 100V. Operating range: 2.5V to 60V.  
V
:OutputVoltageSenseInput.Thispinsensesthevolt-  
OUT  
age at the output side of the external N-channel MOSFET.  
The GATE charge pump voltage is referenced to V . It  
is used as the charge pump input when V  
than approximately 5V.  
OUT  
is greater  
OUT  
4367fb  
7
For more information www.linear.com/LTC4367  
LTC4367  
BLOCK DIAGRAM  
REVERSE  
PROTECTION  
V
IN  
GATE  
–40V TO 100V  
–
+
CLOSES SWITCH  
WHEN V IS NEGATIVE  
5V INTERNAL  
SUPPLY  
IN  
LDO  
5V INTERNAL  
SUPPLY  
I
GATE  
35µA  
GATE  
CHARGE  
PUMP  
V
OUT  
f = 400kHz  
ENABLE  
2.2V  
UVLO  
FAULT  
OFF  
TURN  
OFF  
DELAY TIMERS  
LOGIC  
SHDN  
FAULT  
SHDN  
UV  
0.5V  
OV  
0.5V  
–
+
60mA  
90µA  
25mV  
HYSTERESIS  
GATE PULLDOWN  
+
–
GND  
4367 BD  
4367fb  
8
For more information www.linear.com/LTC4367  
LTC4367  
OPERATION  
Many of today’s electronic systems get their power from  
external sources such as AC or wall adaptors, batteries  
and custom power supplies. Figure 1 shows a supply ar-  
rangementusingaDCbarrelconnector. Powerissupplied  
by an AC adaptor or, if the plug is withdrawn, by a remov-  
able battery. Note that the polarity of the AC adaptor and  
barrel connector varies by manufacturer. Trouble arises  
when any of the following occurs:  
unexpected supply voltage conditions, while providing a  
low loss path for qualified power.  
In the past, to protect electronic systems from improperly  
connected power supplies, system designers often added  
discretediodes,transistorsandhighvoltagecomparators.  
The high voltage comparators enable system power only  
if the input supply falls within a desired voltage window.  
A Schottky diode or P-channel MOSFET typically added  
in series with the supply protects against reverse supply  
connections.  
• The battery is installed backwards  
• An AC adaptor of opposite polarity is attached  
• An AC adaptor of excessive voltage is attached  
• The battery is discharged below a safe level  
TheLTC4367providesaccurateovervoltageandundervolt-  
age comparators to ensure that power is applied to the  
system only if the input supply meets the user selectable  
voltage window. Reverse supply protection circuits au-  
tomatically isolate the load from negative input voltages.  
During normal operation, a high voltage charge pump  
enhances the gate of external N-channel power MOSFETs.  
Power consumption is 5µA during shutdown and 70µA  
while operating. The LTC4367 integrates all these func-  
tions in 8-lead MSOP and 3mm × 3mm DFN packages.  
This can lead to supply voltages that are too high, too  
low, or even negative. If these power sources are applied  
directly to the electronic systems, the systems could be  
subject to damage. The LTC4367 is an input voltage fault  
protectionN-channelMOSFETcontroller.Thepartisolates  
an input supply from its load to protect the load from  
–40V TO 100V PROTECTION RANGE  
M1  
M2  
+
–
AC  
ADAPTOR  
INPUT  
BATTERY  
LOAD  
CIRCUIT  
GATE  
V
V
OUT  
IN  
LTC4367  
R4  
R3  
SHDN  
FAULT  
OV, UV PROTECTION  
THRESHOLDS SET TO  
SATISFY LOAD CIRCUIT  
UV  
OV  
R2  
R1  
2.5V TO 60V  
OPERATING RANGE  
GND  
4367 F01  
Figure 1. Polarity Protection for DC Barrel Connectors  
4367fb  
9
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LTC4367  
APPLICATIONS INFORMATION  
The LTC4367 is an N-channel MOSFET controller that  
protects a load from faulty supply connections. A basic  
application circuit using the LTC4367 is shown in Figure 2  
GATE Drive  
TheLTC4367turnsontheexternalN-channelMOSFETsby  
driving the GATE pin above V . The voltage difference  
OUT  
The circuit provides a low loss connection from V to  
IN  
between the GATE and V  
pins (gate drive) is a function  
OUT  
V
as long as the voltage at V is between 3.5V and  
OUT  
IN  
of V and V  
.
IN  
OUT  
18V. Voltages at V outside of the 3.5V to 18V range are  
IN  
Figure3highlightsthedependenceofthegatedriveonV  
prevented from getting to the load and can be as high as  
IN  
and V . When system power is first turned on (SHDN  
100V and as low as –40V. The circuit of Figure 2 protects  
OUT  
low to high, V  
= 0V), gate drive is at a maximum for all  
againstnegativevoltagesatV asshown.Nootherexternal  
OUT  
IN  
values of V . This helps prevent start-up problems into  
components are needed.  
IN  
heavy loads by ensuring that there is enough gate drive  
During normal operation, the LTC4367 provides up to  
13.1V of gate enhancement to the external back-to-back  
N-channel MOSFETs. This turns on the MOSFETs, thus  
to support the load.  
As V  
ramps up from 0V, the absolute value of the GATE  
OUT  
voltage remains fixed until V  
is greater than the lower  
OUT  
crosses this threshold,  
OUT  
connecting the load at V  
to the supply at V .  
OUT  
IN  
of (V – 1V) or 5V. Once V  
IN  
gate drive begins to increase up to a maximum of 13.1V  
Si7942  
(for V ≥ 12V). The curves of Figure 3 were taken with  
100V DUAL  
IN  
V
IN  
V
OUT  
12V NOMINAL  
3.5V TO 18V  
a GATE load of –1µA. If there were no load on GATE, the  
+
M1  
M2  
C
OUT  
gate drive for each V would be slightly higher.  
IN  
100µF  
GATE  
V
LTC4367  
Note that when V is at the lower end of the operating  
IN  
V
OUT  
IN  
range, the external N-channel MOSFET must be selected  
R4  
453k  
with a corresponding lower threshold voltage.  
SHDN  
R3  
1370k  
14  
T
GATE  
= 25°C  
= –1µA  
A
UV  
OV  
FAULT  
I
12  
10  
8
R2  
243k  
V
= 60V  
IN  
OV = 18V  
UV = 3.5V  
V
= 12V  
IN  
R1  
59k  
GND  
V
IN  
= 5V  
4367 F02  
6
V
= 3.3V  
IN  
Figure 2. LTC4367 Protects Load from –40V  
to 100V VIN Faults  
4
V
IN  
= 2.5V  
2
0
15  
0
5
10  
V
(V)  
OUT  
4367 F03  
Figure 3. Gate Drive (GATE – VOUT) vs VOUT  
4367fb  
10  
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LTC4367  
APPLICATIONS INFORMATION  
Table 1 lists some external MOSFETs compatible with  
Overvoltage and Undervoltage Protection  
different V supply voltages.  
IN  
TheLTC4367providestwoaccuratecomparatorstomoni-  
torforovervoltage(OV)andundervoltage(UV)conditions  
Table 1. Dual MOSFETs for Various Supply Ranges  
at V . If the input supply rises above the user adjustable  
V
MOSFET  
V
V
V
R
DS(ON)  
IN  
IN  
TH(MAX)  
GS(MAX)  
DS(MAX)  
(Ω)  
OV threshold, the gate of the external MOSFET is quickly  
turned off, thus disconnecting the load from the input.  
Similarly, if the input supply falls below the user adjust-  
able UV threshold, the gate of the external MOSFET also  
is quickly turned off. Figure 4 shows a UV/OV application  
for an input supply of 12V.  
2.5V  
3.3V  
3.3V  
5V  
SiA920  
SiA910  
Si6926  
SiA906  
Si9926  
SiZ340  
Si4288  
Si7220  
Si4946  
FDS3890  
Si7942  
FDS3992  
Si7956  
0.7V  
1.0V  
1.0V  
1.4V  
1.5V  
2.4V  
2.5V  
3V  
5V  
8V  
12V  
20V  
20V  
20V  
30V  
40V  
60V  
60V  
80V  
100V  
100V  
150V  
0.027  
0.028  
0.030  
0.046  
0.018  
0.010  
0.020  
0.060  
0.040  
0.044  
0.049  
0.054  
0.105  
8V  
8V  
12V  
12V  
20V  
20V  
20V  
20V  
20V  
20V  
20V  
20V  
5V  
>12V  
>12V  
>12V  
>12V  
>12V  
>12V  
>12V  
>12V  
The external resistive divider allows the user to select  
an input supply range that is compatible with the load at  
V . Furthermore, the UV and OV inputs have very low  
OUT  
3V  
leakage currents (typically < 1nA at 100°C), allowing for  
large values in the external resistive divider. In the applica-  
tion of Figure 4, the load is connected to the supply only if  
4V  
4V  
4V  
V lies between 3.5V and 18V. In the event that V goes  
IN  
IN  
4V  
above18Vorbelow3.5V,thegateoftheexternalN-channel  
MOSFET is immediately discharged with a 60mA current  
sink, thus isolating the load from the supply.  
LTC4367  
12V  
V
IN  
UV  
COMPARATOR  
R3  
1820k  
–
UV  
UV = 3.5V  
25mV  
OV  
+
R2  
243k  
0.5V  
DISCHARGE GATE  
WITH 60mA SINK  
COMPARATOR  
OV  
OV = 18V  
+
25mV  
R1  
59k  
0.5V  
–
4367 F04  
Figure 4. UV, OV Comparators Monitor 12V Supply  
4367fb  
11  
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LTC4367  
APPLICATIONS INFORMATION  
Figure 5 shows the timing associated with the UV pin.  
Once a UV fault propagates through the UV comparator  
Procedure for Selecting UV/OV External Resistor Values  
The following 3-step procedure helps select the resistor  
values for the resistive divider of Figure 4. This procedure  
minimizes UV and OV offset errors caused by leakage  
currents at the respective pins.  
(t  
), the FAULT output is asserted low and a 60mA  
FAULT  
current sink discharges the GATE pin. As V  
falls, the  
OUT  
GATE pin tracks V  
.
OUT  
1. ChoosemaximumtolerableoffseterrorattheUVpin,  
V
V
+ V  
UV  
UV UVHYST  
UV  
V
. Divide by the worst case leakage current at  
OS(UV)  
theUVpin,I  
(10nA).SetthesumofR1+R2equal  
t
FAULT  
LEAK  
to V  
divided by 10nA. Note that due to the  
OS(UV)  
FAULT  
presence of R3, the actual offset at UV will be slightly  
t
t
GATE(FAST)  
D(ON)  
lower:  
EXTERNAL N-CHANNEL MOSFETS  
TURN OFF  
VOS(UV)  
R1+R2 ≤  
GATE  
4367 F05  
ILEAK  
Figure 5. UV Timing (OV < (VOV – VOVHYST), SHDN > 1.2V)  
2. Select the desired V UV trip threshold, UV . Find  
IN  
TH  
the value of R3:  
Figure 6 shows the timing associated with the OV pin.  
Once an OV fault propagates through the OV comparator  
⎛
⎜
⎝
⎞
VOS(UV)  
R3 =  
UVTH – 0.5V  
•
⎟
⎠
(t  
), the FAULT output is asserted low and a 60mA  
ILEAK  
0.5V  
FAULT  
current sink discharges the GATE pin. As V  
falls, the  
OUT  
GATE pin tracks V  
.
3. Select the desired V OV trip threshold, OV . Find  
OUT  
IN  
TH  
the values of R1 and R2:  
V
OV  
OV  
V
OV  
– V  
OVHYST  
⎛
⎜
⎝
⎞
⎟
⎠
VOS(UV)  
t
+R3  
FAULT  
ILEAK  
R1=  
R2 =  
• 0.5V  
FAULT  
OVTH  
t
t
D(ON)  
GATE(FAST)  
VOS(UV)  
EXTERNAL N-CHANNEL MOSFET  
TURNS OFF  
GATE  
– R1  
4367 F06  
ILEAK  
Figure 6. OV Timing (UV > (VUV + VUVHYST), SHDN > 1.2V)  
TheexampleofFigure4usesstandard1%resistorvalues.  
The following parameters were selected:  
When both the UV and OV faults are removed, the ex-  
ternal MOSFET is not immediately turned on. The input  
supply must remain within the user selected power good  
V
= 3mV  
OS(UV)  
I
= 10nA  
LEAK  
window for at least 32ms (t  
) before the load is again  
D(ON)  
UV = 3.5V  
TH  
connected to the supply. This GATE turn-on delay period  
filters noise (including line noise) at the input supply and  
prevents chattering of power at the load. For applications  
that require faster turn-on after a fault, the LTC4367-1  
provides a 500µs GATE turn-on delay.  
OV = 18V  
TH  
4367fb  
12  
For more information www.linear.com/LTC4367  
 
 
LTC4367  
APPLICATIONS INFORMATION  
The resistor values can then be solved:  
3mV  
As shown in Figure 7, external back-to-back N-channel  
MOSFETsarerequiredforreversesupplyprotection.When  
V goes negative, the reverse V comparator closes the  
1. R1+R2 =  
= 300k  
IN  
IN  
10nA  
internal switch, which in turn connects the gates of the  
external MOSFETs to the negative V voltage. The body  
IN  
diode (D1) of M1 turns on, but the body diode (D2) of  
M2 remains in reverse blocking mode. This means that  
the common source connection of M1 and M2 remains  
3.5V – 0.5V  
0.5V  
3mV  
10nA  
(
)
2. R3 =  
•
= 1.8M  
The closest 1% value: R3 = 1.82M:  
about a diode drop higher than V . Since the gate voltage  
IN  
of M2 is shorted to V , M2 will be turned off and no cur-  
IN  
300k+1.82M  
rent can flow from V to the load at V . Note that the  
IN  
OUT  
3. R1 =  
= 58.9k  
voltage rating of M2 must withstand the reverse voltage  
2 •18V  
excursion at V .  
IN  
The closest 1% value: R1 = 59k:  
R2 = 300k – 59k = 241k  
Figure 8 illustrates the waveforms that result when V  
IN  
is hot plugged to –20V. V , GATE and V  
start out at  
IN  
OUT  
ground just before the connection is made. Due to the  
The closest 1% value: R2 = 243k  
Therefore: OV = 17.93V, UV = 3.51V.  
parasitic inductance of the V and GATE connections, the  
IN  
voltage at the V and GATE pins ring significantly below  
IN  
–20V. Therefore, a 40V N-channel MOSFET was selected  
Reverse V Protection  
IN  
to survive the overshoot.  
The LTC4367’s rugged and hot-swappable V input helps  
IN  
The speed of the LTC4367 reverse protection circuits is  
protect the more sensitive circuits at the output load. If  
the input supply is plugged in backwards, or a negative  
supply is inadvertently connected, the LTC4367 prevents  
this negative voltage from passing to the output load.  
evident by how closely the GATE pin follows V during  
IN  
the negative transients. The two waveforms are almost  
indistinguishable on the scale shown.  
The trace at V , on the other hand, does not respond  
OUT  
The LTC4367 employs a novel, high speed reverse supply  
to the negative voltage at V , demonstrating the desired  
IN  
voltagemonitor.WhenthenegativeV voltageisdetected,  
IN  
reversesupplyprotection.ThewaveformsofFigure8were  
an internal switch connects the gates of the external back-  
captured using a 40V dual N-channel MOSFET, a 10µF  
to-back N-channel MOSFETs to the negative input supply.  
ceramic output capacitor and no load current on V  
.
OUT  
D1  
D2  
GND  
M1  
M2  
TO LOAD  
V
IN  
= –40V  
V
OUT  
+
C
OUT  
5V/DIV  
V
GATE  
V
OUT  
IN  
V
IN  
–20V  
LTC4367  
GATE  
REVERSE V  
IN  
COMPARATOR  
–
+
CLOSES SWITCH  
WHEN V IS NEGATIVE  
GND  
4367 F08  
IN  
400ns/DIV  
4367 F07  
Figure 8. Hot Swapping VIN to –20V  
Figure 7. Reverse VIN Protection Circuits  
4367fb  
13  
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LTC4367  
APPLICATIONS INFORMATION  
GATE Turn-On Delay Timer  
further decrease GATE pin slew rate, place a capacitor  
across the gate and source terminals of the external MOS-  
FETs. The waveforms of Figure 10 were captured using  
the Si7942 dual N-channel MOSFETs, and a 2A load with  
100µF output capacitor.  
The LTC4367 has a GATE turn-on delay timer that filters  
noise at V and helps prevent chatter at V . After either  
IN  
OUT  
an OV or UV fault has occurred, the input supply must  
return to the desired operating voltage window for at least  
32ms (t  
) in order to turn the external MOSFET back  
D(ON)  
100µF, 6Ω LOAD ON V  
OUT  
GATE  
on as illustrated in Figure 5 and Figure 6. For applications  
that require faster turn-on after a fault, the LTC4367-1  
provides a 500µs GATE turn-on delay.  
DUAL Si7942 MOSFET  
= 12V  
V
IN  
V
OUT  
5V/DIV  
Going out of and then back into fault in less than t  
D(ON)  
will keep the MOSFET off continuously. Similarly, coming  
out of shutdown (SHDN low to high) triggers an 800µs  
start-up delay timer (see Figure 11).  
SHDN  
GND  
The GATE turn-on delay timer is also active while the part  
4367 F10  
400µs/DIV  
is powering up. The timer starts once V rises above  
IN  
V
and V lies within the user selectable UV/OV  
Figure 10. Shutdown: GATE Tracks VOUT as VOUT Decays  
IN(UVLO)  
IN  
power good window. See Figure 9.  
FAULT Status  
The FAULT high voltage open drain output is driven low if  
SHDN is asserted low, if V is outside the desired UV/OV  
V
V
IN(UVLO)  
IN  
IN  
voltage window, or if V has not risen above V  
.
IN  
IN(UVLO)  
t
D(ON)  
Figure 5, Figure 6 and Figure 11 show the FAULT output  
timing.  
GATE  
MOSFET OFF  
MOSFET ON  
4367 F09  
SHDN  
Figure 9. GATE Turn-On Delay Timing During  
Power-On (OV = GND, UV = SHDN = VIN)  
t
t
START  
GATE(SLOW)  
GATE  
∆V  
GATE  
Shutdown  
GATE = V  
OUT  
V
OUT  
The SHDN input turns off the external MOSFETs in a  
controlled manner. When SHDN is asserted low, a 90µA  
currentsinkslowlybeginstoturnofftheexternalMOSFETs.  
t
SHDN(F)  
FAULT  
4367 F11  
Once the voltage at the GATE pin falls below the voltage  
at the V  
pin, the current sink is throttled back and a  
OUT  
Figure 11. Shutdown Timing  
feedbacklooptakesover.ThisloopforcestheGATEvoltage  
to track V , thus keeping the external MOSFETs off as  
OUT  
V
decays. Note that when V  
is pulled to within 400mV of ground.  
< 2.2V, the GATE pin  
Select Between Two Input Supplies  
With the part in shutdown, the V and V  
OUT  
OUT  
pins can be  
OUT  
IN  
Weak gate turn off reduces load current slew rates and  
mitigates voltage spikes due to parasitic inductances. To  
driven by separate power supplies. The LTC4367 then  
automatically drives the GATE pin just below the lower of  
4367fb  
14  
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LTC4367  
APPLICATIONS INFORMATION  
thetwosupplies,thusturningofftheexternalback-to-back  
MOSFETs.TheapplicationofFigure12usestwoLTC4367s  
toselectbetweentwopowersupplies.Careshouldbetaken  
to ensure that only one of the two LTC4367s is enabled  
at any given time.  
Limiting Inrush Current During Turn-On  
The LTC4367 turns on the external N-channel MOSFET  
with a 35µA current source. The maximum slew rate at  
the GATE pin can be reduced by adding a capacitor on  
the GATE pin:  
M1  
M2  
V1  
35µA  
CGATE  
Slew Rate =  
GATE  
V
V
IN  
OUT  
Since the MOSFET acts like a source follower, the slew  
LTC4367  
OUT  
rate at V  
equals the slew rate at GATE.  
OUT  
SHDN  
Therefore, inrush current is given by:  
COUT  
SEL OUT  
0
1
V1  
V2  
IINRUSH  
=
• 35µA  
M1  
M2  
V2  
CGATE  
For example, a 1A inrush current to a 330µF output  
capacitance requires a GATE capacitance of:  
GATE  
V
V
OUT  
IN  
LTC4367  
35µA •COUT  
IINRUSH  
SHDN  
SEL  
CGATE  
=
4367 F12  
Figure 12. Selecting One of Two Supplies  
35µA • 330µF  
1A  
CGATE  
=
= 11.6nF  
Single MOSFET Application  
WhenreverseV protectionisnotneeded,asingleexternal  
IN  
The 12nF C  
capacitor in the application circuit of  
GATE  
N-channel MOSFET may be used. The application circuit of  
Figure 14 limits the inrush current to just under 1A. R  
GATE  
Figure 13 connects the load to V when V is less than  
IN  
IN  
makes sure that C  
does not affect the fast GATE turn  
GATE  
30V, and uses the minimal set of external components.  
off characteristics during UV/OV faults, or during reverse  
V connection. R5A and R5B help prevent high frequency  
IN  
oscillations with the external N-channel MOSFET and  
SiR870  
100V  
V
IN  
related board parasitics.  
V
OUT  
24V  
+
C
OUT  
100µF  
M1  
M2  
GATE  
V
V
OUT  
V
V
OUT  
IN  
IN  
R4  
499k  
LTC4367  
+
C
OUT  
R5A  
10Ω  
R5B  
10Ω  
330µF  
SHDN  
FAULT  
UV  
R2  
R
GATE  
1870k  
V
GATE  
LTC4367  
V
OUT  
IN  
5.1k  
OV = 30V  
OV  
C
GATE  
R1  
40.2k  
12nF  
GND  
4367 F13  
4367 F14  
Figure 13. Single MOSFET Application Protects Against 100V  
Figure 14. Limiting Inrush Current with CGATE  
4367fb  
15  
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LTC4367  
APPLICATIONS INFORMATION  
Transients During OV Fault  
pacitance at the V node. D1 is an optional power clamp  
IN  
(TVS, TransZorb) recommended for applications where  
The circuit of Figure 15 is used to display transients dur-  
ing an overvoltage condition. The nominal input supply  
is 48V and it has an overvoltage threshold of 60V. The  
parasiticinductanceisthatofa1footwire(roughly300nH).  
Figure 16 shows the waveforms during an overvoltage  
V can ring above 100V. No clamp was used to capture  
IN  
the waveforms of Figure 16. In order to maintain reverse  
supply protection, D1 must be a bidirectional clamp rated  
for at least 225W peak pulse power dissipation.  
condition at V . These transients depend on the parasitic  
IN  
inductance and resistance of the wire along with the ca-  
12 INCH WIRE  
LENGTH  
Si7942  
100V DUAL  
V
OUT  
V
IN  
48V  
+
+
C
IN  
C
OUT  
100µF  
M1  
M2  
1000µF  
22Ω  
GATE  
V
V
OUT  
IN  
R4  
523k  
LTC4367  
D1  
OPTIONAL  
SHDN  
UV  
FAULT  
R2  
2430k  
OV  
OV = 60V  
R1  
20.5k  
GND  
4367 F15  
Figure 15. OV Fault with Large VIN Inductance  
GATE  
60V  
60V  
V
OUT  
20V/DIV  
V
IN  
20V/DIV  
I
IN  
2A/DIV  
0A  
4367 F16  
400ns/DIV  
Figure 16. Transients During OV Fault When No  
TransZorb (TVS) Is Used  
4367fb  
16  
For more information www.linear.com/LTC4367  
 
 
LTC4367  
APPLICATIONS INFORMATION  
REGULATOR APPLICATIONS  
from the parasitic inductance of the V connector. See  
IN  
Transient During 0V Fault section for more details.  
Hysteretic Regulator  
Solar Charger  
Built-in hysteresis and the availability of both inverting  
and noninverting control inputs (OV and UV) facilitate the  
design of hysteretic regulators. Figure 17 shows how the  
LTC4367-1 can protect a load from OV transients, while  
regulating the output voltage at a user-defined level. When  
the output voltage reaches its OV limit, the LTC4367-1  
turns off the external MOSFETs. The load current then  
discharges the output capacitance until OV falls below the  
hysteresis voltage. The external MOSFETs are turned back  
on after a 500µs delay. Figure 18 shows the waveforms for  
Figure 19 shows a series regulator for a solar charger.  
The LTC4367-1 connects the solar charger to the battery  
when the battery voltage falls below 13.9V (after a 500µs  
delay). Conversely, when the battery reaches 14.6V, the  
LTC4367-1 immediately (2µs) opens the charging path.  
Regulation of the battery voltage is achieved by connect-  
ing a resistive divider from the battery to the accurate OV  
comparator input (with 5% hysteresis). The fast rising  
responseoftheOVcomparatorpreventsthebatteryvoltage  
from rising above the user-selected threshold.  
the circuit of Figure 17. The voltage spikes on V result  
IN  
Si4946  
DUAL  
V
IN  
V
V
OUT  
IN  
+
R7  
1Ω  
R
C
LOAD  
LOAD  
100Ω  
47µF  
OPTIONAL  
SNUBBER  
1µF  
GATE  
5V/DIV  
R4  
510k  
V
V
OUT  
IN  
V
OUT  
LTC4367-1  
UV  
R2  
1820k  
SHDN  
FAULT  
GND  
OV  
C
R1  
59k  
OV  
GND  
220pF  
4367 F17  
4367 F18  
1ms/DIV  
Figure 17. Hysteretic Regulation of VOUT During OV Transients  
Figure 18. VOUT Regulates at 16V When VIN  
Rises Above Desired Level  
1/2 OF Si4214  
1/2 OF Si4214  
D2  
D1  
D4  
B130  
M1  
M2  
TO LOAD  
+
C
BYP  
C
BATT  
15W  
SOLAR  
PANEL  
100nF  
100µF  
12V, 8Ah  
GELCELL  
SHDN UV V  
GATE  
V
OUT  
IN  
R2  
LTC4367-1  
GND  
3.24M  
OV  
C
R1  
115k  
OV  
220pF  
14.6V OFF  
13.9V ON  
4367 F19  
Figure 19. Series Hysteretic Solar Charger with Reverse-Battery and Solar Panel Protection  
4367fb  
17  
For more information www.linear.com/LTC4367  
 
 
 
LTC4367  
APPLICATIONS INFORMATION  
Note that during initial start-up, the LTC4367-1 will not handling capability, drain and gate breakdown voltages,  
and threshold voltage.  
turn on the external MOSFETs until a battery is first con-  
nected to the V pin. To begin operation, V must initially  
rise above the 2.2V UVLO lockout voltage. Connecting the  
battery ensures that the LTC4367-1 comes out of UVLO.  
IN  
IN  
The drain to source breakdown voltage must be higher  
thanthemaximumvoltageexpectedbetweenV andV  
Notethatifanapplicationgenerateshighenergytransients  
during normal operation or during hot swap, the external  
MOSFET must be able to withstand this transient voltage.  
.
IN  
OUT  
12V Application with 150V Transient Protection  
Figure 20 shows a 12V application that withstands input  
supply transients up to 150V. When the input voltage ex-  
ceeds 17.9V, the OV resistive divider turns off the external  
Due to the high impedance nature of the charge pump  
that drives the GATE pin, the total leakage on the GATE pin  
must be kept low. The gate drive curves of Figure 3 were  
measured with a 1µA load on the GATE pin. Therefore,  
the leakage on the GATE pin must be no greater than 1µA  
in order to match the curves of Figure 3. Higher leakage  
currents will result in lower gate drive. The dual N-channel  
MOSFETsshowninTable1allhaveamaximumgateleakage  
current of 100nA. Additionally, Table 1 lists representative  
MOSFETs. As V rises to 150V, the gate of transistor M1  
IN  
remains in the Off condition, thus preventing conduction  
from V to V . Note that M1 must have an operating  
IN  
OUT  
range above 150V.  
Resistor R6 and diode D3 clamp the LTC4367 supply volt-  
age to 50V. To prevent R6 from interfering with reverse  
operation, the recommended value is 1k or less. Note that  
the power handling capability of R6 must be considered in  
order to avoid overheating during transients. D3 is shown  
asabidirectionalclampinordertoachievereverse-polarity  
MOSFETs that would work at different values of V .  
IN  
Layout Considerations  
The trace length between the V pin and the drain of the  
IN  
protection at V . M2 is also required in order to protect  
IN  
externalMOSFETshouldbeminimized,aswellasthetrace  
length between the GATE pin of the LTC4367 and the gates  
of the external MOSFETs.  
V
OUT  
from negative voltages at V and should have an  
IN  
operating range beyond the breakdown of D3. If reverse  
protection is not desired remove M2 and connect the  
source of M1 directly to V  
.
Place the bypass capacitors at V  
as close as possible  
OUT  
OUT  
to the external MOSFET. Use high frequency ceramic  
capacitors in addition to bulk capacitors to mitigate hot  
swap ringing. Place the high frequency capacitors closest  
to the MOSFET. Note that bulk capacitors mitigate ringing  
by virtue of their ESR. Ceramic capacitors have low ESR  
and can thus ring near their resonant frequency.  
MOSFET Selection  
To protect against a negative voltage at V , the external  
IN  
N-channel MOSFETs must be configured in a back-to-  
back arrangement. Dual N-channel packages are thus the  
best choice. The MOSFET is selected based on its power  
M1  
M2  
FDD2572 FDS5680  
V
IN  
V
OUT  
12V  
R6  
1k  
GATE  
V
V
OUT  
IN  
R4  
510k  
LTC4367  
D3  
SHDN  
UV  
R2  
2050k  
OV = 17.9V  
FAULT  
OV  
R1  
59k  
GND  
D3: SMAJ43CA BI-DIRECTIONAL  
4367 F20  
Figure 20. 12V Application Protected from 150V Transients  
4367fb  
18  
For more information www.linear.com/LTC4367  
 
LTC4367  
PACKAGE DESCRIPTION  
Please refer to http://www.linear.com/product/LTC4367#packaging for the most recent package drawings.  
MS8 Package  
8-Lead Plastic MSOP  
(Reference LTC DWG # 05-08-1ꢀꢀ0 Rev G)  
0.889 0.127  
(.035 .005)  
5.10  
3.20 – 3.45  
(.201)  
(.12ꢀ – .13ꢀ)  
MIN  
3.00 0.102  
(.118 .004)  
(NOTE 3)  
0.52  
(.0205)  
REF  
0.ꢀ5  
(.025ꢀ)  
BSC  
0.42 0.038  
(.01ꢀ5 .0015)  
TYP  
8
7 ꢀ 5  
RECOMMENDED SOLDER PAD LAYOUT  
3.00 0.102  
(.118 .004)  
(NOTE 4)  
4.90 0.152  
(.193 .00ꢀ)  
DETAIL “A”  
0.254  
(.010)  
0° – ꢀ° TYP  
GAUGE PLANE  
1
2
3
4
0.53 0.152  
(.021 .00ꢀ)  
1.10  
(.043)  
MAX  
0.8ꢀ  
(.034)  
REF  
DETAIL “A”  
0.18  
(.007)  
SEATING  
PLANE  
0.22 – 0.38  
0.101ꢀ 0.0508  
(.009 – .015)  
(.004 .002)  
0.ꢀ5  
(.025ꢀ)  
BSC  
TYP  
MSOP (MS8) 0213 REV G  
NOTE:  
1. DIMENSIONS IN MILLIMETER/(INCH)  
2. DRAWING NOT TO SCALE  
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.  
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.00ꢀ") PER SIDE  
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.  
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.00ꢀ") PER SIDE  
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX  
4367fb  
19  
For more information www.linear.com/LTC4367  
LTC4367  
PACKAGE DESCRIPTION  
Please refer to http://www.linear.com/product/LTC4367#packaging for the most recent package drawings.  
DD Package  
8-Lead Plastic DFN (3mm × 3mm)  
(Reference LTC DWG # 05-08-1698 Rev C)  
0.70 ±0.05  
3.5 ±0.05  
2.10 ±0.05 (2 SIDES)  
1.65 ±0.05  
PACKAGE  
OUTLINE  
0.25 ±0.05  
0.50  
BSC  
2.38 ±0.05  
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS  
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED  
R = 0.125  
0.40 ±0.10  
TYP  
5
8
3.00 ±0.10  
(4 SIDES)  
1.65 ±0.10  
(2 SIDES)  
PIN 1  
TOP MARK  
(NOTE 6)  
(DD8) DFN 0509 REV C  
4
1
0.25 ±0.05  
0.75 ±0.05  
0.200 REF  
0.50 BSC  
2.38 ±0.10  
BOTTOM VIEW—EXPOSED PAD  
0.00 – 0.05  
NOTE:  
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)  
2. DRAWING NOT TO SCALE  
3. ALL DIMENSIONS ARE IN MILLIMETERS  
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE  
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE  
5. EXPOSED PAD SHALL BE SOLDER PLATED  
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION  
ON TOP AND BOTTOM OF PACKAGE  
4367fb  
20  
For more information www.linear.com/LTC4367  
LTC4367  
REVISION HISTORY  
REV  
DATE  
DESCRIPTION  
PAGE NUMBER  
A
03/16 Updated Typical Application and Figures 1, 2, 13, 15  
1, 9, 10, 15, 16  
Updated SHDN, UV input current rating  
2
4
Changed I  
test condition to 10V from 0.75V  
SHDN  
Updated graphs G09 and G12  
5, 6  
7
Updated SHDN and UV Pin Functions  
B
10/17 Increased t  
Increased t  
max limit to 575µs  
GATE(SLOW)  
max limit to 6µs  
GATE(FAST)  
3
3
Increased t  
max limit to 1400µs  
4
START  
4367fb  
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.  
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-  
21  
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.  
LTC4367  
TYPICAL APPLICATION  
LTC4367 Protects Step Down Regulator from –30V to 30V VIN Faults  
Si4214 30V  
DUAL N-CHANNEL  
V
OUT  
OUTPUT  
5V  
3.5A  
V
IN  
12V NOMINAL  
10µF  
V
PROTECTED  
OUT  
V
BD  
IN  
FROM –30V TO 30V  
RUN/SS BOOST  
LT1913  
0.47µF  
4.7µH  
GATE  
V
V
OUT  
IN  
15k  
680pF  
LTC4367  
V
SW  
C
510k  
SHDN  
RT  
PG  
1820k  
536k  
100k  
FB  
UV  
FAULT  
GND  
SYNC  
63.4k  
47µF  
243k  
59k  
OV  
OV = 18V  
UV = 3.5V  
4367 TA02  
GND  
RELATED PARTS  
PART NUMBER  
DESCRIPTION  
COMMENTS  
LTC4365  
Overvoltage, Undervoltage and Reverse Supply  
Protection Controller  
Wide Operating Range: 2.5V to 34V, Protection Range: –40V to 60V,  
No TVS Required for Most Applications  
LTC4368  
LTC4367 + Bidirectional Circuit Breaker  
50mV or 50mV/–3mV Circuit Breaker Thresholds;  
MSOP-10, DFN-10 Packages  
LTC4380  
LT4363  
8µA Quiescent Current Surge Stopper  
4V to 72V Operation; –60V Input Protection; Pin-Selectable Clamp  
Surge Stopper Overvoltage/Overcurrent Protection  
Regulator  
Wide Operating Range: 4V to 80V, Reverse Protection to –60V, Adjustable  
Output Clamp Voltage  
LTC4364  
Surge Stopper with Ideal Diode  
Floating Surge Stopper  
4V to 80V Operation, –40V Reverse Input, –20V Reverse Output  
9V to >500V Operation, 8-Pin TSOT and 3mm × 2mm DFN Packages  
5.8V Overvoltage Threshold, 85V Absolute Maximum  
Pin Selectable Input Polarity Allows Negative and OV Monitoring  
Adjustable UV and OV Trip Values, 1.5% Threshold Accuracy  
For Positive and Negative Supplies  
LTC4366  
LTC4361  
Overvoltage/Overcurrent Protection Controllers  
Triple/Dual Inputs UV/OV Negative Monitor  
Single/Dual UV/OV Voltage Monitor  
Quad UV/OV Monitor  
LTC2909  
LTC2912/LTC2913  
LTC2914  
LTC2955  
Pushbutton On/Off Controller  
Automatic Turn-On, 1.5V to 36V Input, 36V PB Input  
LT4256  
Positive 48V Hot Swap Controller with  
Open-Circuit Detect  
Foldback Current Limiting, Open-Circuit and Overcurrent Fault Output,  
Up to 80V Supply  
LTC4260  
Positive High Voltage Hot Swap Controller with  
Wide Operating Range 8.5V to 80V  
2
ADC and I C  
LTC4352  
LTC4354  
LTC4355  
LT1913  
Ideal MOSFET ORing Diode  
External N-Channel MOSFETs Replace ORing Diodes, 0V to 18V  
Controls Two N-Channel MOSFETs, 1.2µs Turn-Off, –80V Operation  
Controls Two N-Channel MOSFETs, 0.4µs Turn-Off, 80V Operation  
3.6V to 25V Input, 3.5A Maximum Current, 200kHz to 2.4MHz  
Negative Voltage Diode-OR Controller  
Positive Voltage Diode-OR Controller  
Step-Down Switching Regulator  
4367fb  
LT 1017 REV B • PRINTED IN USA  
www.linear.com/LTC4367  
22  
LINEAR TECHNOLOGY CORPORATION 2015  

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