LTC4370CDE#PBF [Linear]
LTC4370 - Two-Supply Diode-OR Current Balancing Controller; Package: DFN; Pins: 16; Temperature Range: 0°C to 70°C;
| 型号： | LTC4370CDE#PBF |
| 厂家： | 
Linear |
| 描述： | LTC4370 - Two-Supply Diode-OR Current Balancing Controller; Package: DFN; Pins: 16; Temperature Range: 0°C to 70°C 光电二极管 |
| 文件： | 总20页 (文件大小：251K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC4370
Two-Supply Diode-OR
Current Balancing Controller
FeaTures
DescripTion
The LTC®4370 is a two-supply current sharing controller
which incorporates MOSFET ideal diodes. The diodes
block reverse and shoot-through currents during start-up
and fault conditions. Their forward voltage is adjusted to
share the load currents between supplies. Unlike other
sharing methods, neither a share bus nor trim pins on
the supply are required.
n
Shares Load Between Two Supplies
n
Eliminates Need for Active Control of
Input Supplies
n
No Share Bus Required
n
Blocks Reverse Current
n
No Shoot-Through Current During Start-Up or Faults
n
0V to 18V High Side Operation
n
Enable Inputs
The maximum MOSFET voltage drop can be set with a
resistor. A fast gate turn-on reduces the load voltage
droop during supply switchover. If the input supply fails
or is shorted, a fast turn-off minimizes reverse current
transients.
n
MOSFET On Status Outputs
n
Dual Ideal Diode Mode
n
16-Lead DFN (4mm × 3mm) and MSOP Packages
applicaTions
The controller operates with supplies from 2.9V to 18V.
For lower rail voltages, an external supply is needed at
n
Redundant Power Supplies
n
High Availability Systems and Servers
the V pin. Enable inputs can be used to turn off the
CC
n
Telecom and Network Infrastructure
MOSFET and put the controller in a low current state.
Status outputs indicate whether the MOSFETs are on or
off. The load sharing function can be disabled to turn the
LTC4370 into a dual ideal diode controller.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
PowerPath and ThinSOT are trademarks of Linear Technology Corporation. All other trademarks
are the property of their respective owners. Protected by U.S. Patents, including 7920013 and
8022679. Additional patent pending.
Typical applicaTion
12V, 10A Load Share
Current Sharing Error vs Supply Difference
SUM85N03-06P
V
INA
12V
20
15
39nF*
10
EN1 CPO1
V
GATE1
IN1
OUT1
5
V
CC
2mΩ
2mΩ
FETON1
FETON2
0.1µF
NC
OUT
12V, 10A
0
GND
LTC4370
–5
RANGE
OUT2
–10
–15
–20
EN2 CPO2
V
GATE2 COMP
IN2
0.18µF
39nF*
–750 –500 –250
0
250
500
750
V
INB
V
– V (mV)
INB
INA
4370 TA01
4370 TA01b
12V
SUM85N03-06P
*OPTIONAL, FOR FAST TURN-ON
4370f
1
LTC4370
absoluTe MaxiMuM raTings
(Notes 1, 2)
V
V
, V , OUT1, OUT2 Voltages...................−2V to 24V
FETON1, FETON2 Currents.......................................5mA
Operating Ambient Temperature Range
IN1 IN2
Voltage............................................... −0.3V to 6.5V
CC
GATE1, GATE2 Voltages (Note 3) ............... −0.3V to 34V
CPO1, CPO2 Voltages (Note 3)................... −0.3V to 34V
LTC4370C................................................ 0°C to 70°C
LTC4370I .............................................−40°C to 85°C
Storage Temperature Range .................. −65°C to 150°C
Lead Temperature (Soldering, 10 sec)
RANGE Voltage ................................−0.3V to V + 0.3V
CC
COMP Voltage.............................................. −0.3V to 3V
EN1, EN2, FETON1, FETON2 Voltages .........−0.3V to 24V
CPO1, CPO2 Average Current.................................10mA
MS Package......................................................300°C
pin conFiguraTion
TOP VIEW
EN2
RANGE
COMP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
EN1
TOP VIEW
GND
EN2 1
RANGE 2
COMP 3
16 EN1
V
V
CC
15 GND
14 V
CC
13 V
IN1
V
IN2
17
IN1
V
4
IN2
GATE2
CPO2
GATE1
CPO1
GATE2 5
CPO2 6
12 GATE1
11 CPO1
10 OUT1
OUT2 7
OUT2
OUT1
FETON2 8
9
FETON1
FETON2
FETON1
MS PACKAGE
16-LEAD PLASTIC MSOP
DE PACKAGE
16-LEAD (4mm × 3mm) PLASTIC DFN
T
= 125°C, θ = 125°C/W
JA
JMAX
T
= 125°C, θ = 43°C/W
JA
JMAX
EXPOSED PAD (PIN 17) PCB GND CONNECTION IS OPTIONAL
orDer inForMaTion
LEAD FREE FINISH
LTC4370CDE#PBF
LTC4370IDE#PBF
LTC4370CMS#PBF
LTC4370IMS#PBF
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
0°C to 70°C
LTC4370CDE#TRPBF
LTC4370IDE#TRPBF
LTC4370CMS#TRPBF
LTC4370IMS#TRPBF
4370
4370
4370
4370
16-Lead (4mm × 3mm) Plastic DFN
16-Lead (4mm × 3mm) Plastic DFN
16-Lead Plastic MSOP
–40°C to 85°C
0°C to 70°C
16-Lead Plastic MSOP
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
4370f
2
LTC4370
elecTrical characTerisTics The l denotes those specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN1 = VIN2 = 12V, OUT = VIN, VCC open, unless otherwise noted.
SYMBOL
Supplies
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
V
IN
V
, V Operating Range
IN1 IN2
2.9
0
18
CC
V
V
With External V Supply
V
CC
l
l
V
V
V
V
V
External Supply Operating Range
Regulated Voltage
V
, V ≤ V
CC
2.9
4.5
6
V
V
CC(EXT)
CC(REG)
CC
IN1 IN2
5
5.5
CC
I
IN
, V Current
IN1 IN2
l
l
l
l
Enabled, Higher Supply
Other V = 11.7V, Both EN = 0V
2.1
320
–110
80
3
mA
µA
µA
µA
IN
IN
IN
Enabled, Lower Supply
Pull-Up
Other V = 12.3V, Both EN = 0V
450
–180
180
Both V = 0V, V = 5V, Both EN = 0V
CC
Disabled
Both EN = 1V
I
CC
V
Current
CC
Enabled
Disabled
l
l
V
CC
V
CC
= 5V, Both V = 1.2V, Both EN = 0V
2
105
2.8
220
mA
µA
IN
= 5V, Both V = 1.2V, Both EN = 1V
IN
l
l
V
V
V
Undervoltage Lockout Threshold
V
CC
Rising
2.3
40
2.55
120
2.7
V
CC(UVLO)
CC
CC
ΔV
Undervoltage Lockout Hysteresis
300
mV
CC(HYST)
Load Share
l
V
Error Amplifier Input Offset
Error Amplifier Gain (–ΔI
0
2
mV
µS
EA(OS)
m(EA)
g
/ΔV
)
150
COMP
OUT
l
l
V
Minimum Forward Regulation Voltage
IN
V
V
= 1.2V, V = 5V
2
2
12
25
25
50
mV
mV
FR(MIN)
IN
IN
CC
(V – OUT)
= 12V
l
l
l
l
V
Maximum Forward Regulation Voltage
IN
R
RANGE
R
RANGE
R
RANGE
R
RANGE
= 4.99k, V = 1.2V, V = 5V
40
45
425
440
62
75
511
524
82
mV
mV
mV
mV
FR(MAX)
IN
CC
(V – OUT)
= 4.99k, V = 12V
100
575
590
IN
= 49.9k, V = 1.2V, V = 5V
IN
CC
= 49.9k, V = 12V
IN
l
l
I
RANGE Pull-Up Current
RANGE = 0.2V
–8.8
–10
–11.2
µA
V
RANGE
V
RANGE Load Share Disable Threshold
V
– 0.5 V – 0.3 V – 0.1
CC CC CC
RANGE(TH)
Gate Drive
l
l
ΔV
MOSFET Gate Drive (GATE – V )
V
V
= 0.2V; I = 0, −1μA; Highest V = 12V
10
12
14
V
V
GATE
IN
FWD
FWD
IN
= 0.2V; I = 0, −1μA; Highest V = 2.9V
4.5
7
9
1
1
IN
l
l
t
t
I
GATE1, GATE2 Turn-On Propagation Delay
GATE1, GATE2 Turn-Off Propagation Delay
V
V
(= V – OUT) Step: –0.3V 0.3V
0.4
0.4
µs
µs
ON(GATE)
OFF(GATE)
GATE(PK)
FWD
FWD
IN
Step: 0.3V –0.3V
l
l
GATE1, GATE2 Peak Pull-Up Current
GATE1, GATE2 Peak Pull-Down Current
V
V
= 0.4V, ΔV
= 0V, CPO = 17V
= 5V
–0.9
0.9
–1.4
1.4
–1.9
1.9
A
A
FWD
FWD
GATE
GATE
= −2V, ΔV
l
I
GATE1, GATE2 Off Pull-Down Current
Corresponding EN = 1V, ΔV
= 2.5V
GATE
65
110
160
µA
GATE(OFF)
Input/Output Pins
l
l
l
V
EN1, EN2 Threshold Voltage
EN1, EN2 Threshold Hysteresis
EN1, EN2 Current
EN Falling
580
2
600
8
620
20
1
mV
mV
µA
EN(TH)
ΔV
EN(TH)
I
I
At 0.6V
0
EN
OUT1, OUT2 Current
Enabled
Disabled
OUT
l
l
OUTn = 0V, 12V; Both EN = 0V
Both EN = 1V
–70
–40
260
40
µA
µA
16
l
I
CPO1, CPO2 Pull-Up Current
CPO = V
–70
–115
µA
CPO(UP)
IN
l
l
V
OL
FETON1, FETON2 Output Low Voltage
I = 1mA
I = 3mA
0.12
0.36
0.4
1.2
V
V
l
V
OH
FETON1, FETON2 Output High Voltage
I = −1μA, V
= 1V
V
CC
– 1.4 V – 0.9 V – 0.5
V
FWD
CC
CC
4370f
3
LTC4370
elecTrical characTerisTics
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
0
MAX
1
UNITS
µA
l
l
I
FETON1, FETON2 Leakage Current
MOSFET On Detect Threshold
At 12V
FETON
ΔV
GATE(ON)
FETON Transitions High
0.28
0.7
1.1
V
(GATE – V )
IN
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 3: Internal clamps limit the GATE and CPO pins to a minimum of 10V
above, and a diode below the corresponding V pin. Driving these pins to
IN
voltages beyond the clamp may damage the device.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to GND unless otherwise
specified.
Typical perForMance characTerisTics
TA = 25°C, VIN1 = VIN2 = 12V, OUT = VIN, VCC open,
unless otherwise noted.
VIN Current vs Voltage with
VIN Current vs Voltage
External VCC
VCC Current vs Voltage
3
2.5
2
300
250
200
150
100
50
2.5
V
= 6V
BOTH V = 0V
IN
CC
OTHER V = 0V
IN
OTHER V = 0V
IN
2
1.5
1
1.5
1
0
0.5
0
OTHER V = 12V
IN
–50
–100
–150
0.5
0
–0.5
0
3
6
9
12
15
18
0
1
2
3
4
5
6
0
1
2
3
4
5
6
V
(V)
V
IN
(V)
V
(V)
IN
CC
4370 G01
4370 G02
4370 G03
Minimum Forward Regulation
Voltage vs VIN Voltage with
External VCC
OUT Current vs Voltage
30
25
20
15
10
5
300
250
200
150
100
50
V
= 3.3V
V
= 5V
CC
CC
0
–50
0
0
3
6
9
12
15
18
0
1
2
3
4
5
V
(V)
V
(V)
OUT
IN
4370 G04
4370 G05
4370f
4
LTC4370
Typical perForMance characTerisTics
TA = 25°C, VIN1 = VIN2 = 12V, OUT = VIN, VCC open,
unless otherwise noted.
�VGATE and VCC Voltages
vs VIN Voltage
�VGATE Voltage vs Current
15
12
9
14
12
10
8
∆V
GATE
V
IN
= 18V
6
6
V
CC
V
= 2.9V
IN
3
4
0
2
–3
0
0
–20
–40
I
–60
(µA)
–80 –100 –120
18
0
3
6
9
12
15
V
(V)
GATE
IN
4370 G06
4370 G07
Error Amplifier Transfer
Characteristic
Maximum Forward Regulation
Voltage vs RANGE Resistor
30
20
700
600
500
400
300
200
100
0
10
0
–10
–20
–30
0
20
40
60
80
100
–300 –200 –100
0
100
200
300
R
(kΩ)
V
OUT1
– V
(mV)
RANGE
OUT2
4370 G08
4370 G09
FETON Output Low Voltage
vs Current
FETON Output High Voltage
vs Current
700
600
500
400
300
200
100
0
5
4
3
2
1
0
0
1
2
3
4
5
0
–2
–4
–6
–8
–10
I
(mA)
I
(µA)
FETON
FETON
4370 G10
4370 G11
4370f
5
LTC4370
pin FuncTions
COMP:ErrorAmplifierCompensation.Connectacapacitor
GATE1, GATE2: MOSFET Gate Drive Output.Connect this
pin to the gate of the external N-channel MOSFET switch.
An internal clamp limits the gate voltage to 12V above,
and a diode below the input supply. During fast turn-on,
a 1.4A pull-up current charges GATE to CPO. During fast
from this pin to GND. The value of this capacitor should be
approximately 10 to 50 times the gate capacitance (C
)
ISS
of the MOSFET switch. Maintain low board leakage on this
pin for best load sharing accuracy. For example, 100nA
of leakage current (equal to 1V across 10MΩ) increases
the error amplifier offset by 0.7mV. Leave this pin open
if only using ideal diode mode.
turn-off, a1.4Apull-downcurrentdischargesGATEtoV .
IN
GND: Device Ground.
OUT1, OUT2: Output Voltage and Current Sense Input.
Connect this pin to the input side of the supply’s current
sense resistor. A Kelvin connection is important for ac-
curate current sharing. The voltage sensed at this pin is
used to control the MOSFET gate.
CPO1, CPO2: Charge Pump Output. Connect a capacitor
from this pin to the corresponding V pin. The value of
IN
this capacitor should be approximately 10× the gate ca-
pacitance (C ) of the MOSFET switch. The charge stored
ISS
on this capacitor is used to pull up the gate during a fast
RANGE: Supply Differential Voltage Load Sharing Range.
Connect a resistor (below 60k) from this pin to GND. A
10μA internal pull-up current source into this resistor
turn-on. Leave this pin open if fast turn-on is not needed.
EN1,EN2:EnableInput.Keepthispinbelow0.6Vtoenable
sharing and diode control on the corresponding supply.
Driving this pin high shuts off the MOSFET gate (current
can still flow through its body diode). The comparator has
a built-in hysteresis of 8mV. Having both EN pins high
lowers the current consumption of the device.
sets the pin voltage V
. The two supplies will typi-
RANGE
cally share the load current if their voltage difference is
within V . The maximum sharing range is 0.6V,
RANGE
obtained by leaving RANGE open. Connecting this pin to
disables load share control and the device behaves
V
CC
Exposed Pad (DE Package Only): The exposed pad may
be left open or connected to device ground.
as a dual ideal diode controller.
V : Low Voltage Supply. Connect a 0.1μF capacitor from
CC
FETON1, FETON2: MOSFET Status Output. This pin is
this pin to ground. For V ≥ 2.9V this pin provides decou-
IN
pulled low by an internal switch when GATE is less than
pling for an internal regulator that generates a 5V supply.
0.7VaboveV toindicateanoffMOSFET. Becauseofthis,
For applications where both V < 2.9V, also connect an
IN
IN
it may also signal off if small currents are flowing through
external supply in the 2.9V to 6V range to this pin.
a high-g MOSFET with a large forward voltage across
m
V
, V : Voltage Sense and Supply Input. Connect
IN2
IN1
it. An internal 500k resistor pulls this pin up to a diode
this pin to the supply side of the MOSFET. The low volt-
below V . It may be pulled above V using an external
CC
CC
age supply V is generated from the higher of V and
CC
IN1
pull-up. Tie to GND or leave open if unused.
V
IN2
. The voltage sensed at this pin is used to control the
MOSFET gate.
4370f
6
LTC4370
FuncTional DiagraM
R1
M1
12
V
SUPPLY1
C1
13
11
GATE1 CPO1
10
OUT1
V
IN1
V
CC
–
+
0.6V
DISABLE1
500k
EN1
16
CP1
FETON1
9
3
V
+
–
IN1
CHARGE
PUMP1
V
V
IN2
IN1
0.7V
SA1
f = 3MHz
GATE1
+
–
V
CP4
FR1
LDO
COMP
C
C
+
OUT1
OUT2
GATE1
OFF
V
–
CC
14
EA
TO
LOAD
SERVO
ADJUST
V
CC
LOW
C
VCC
–
V
CC
+
g
= 150µS
m
2.55V
GATE2
OFF
10µA
CP2
RANGE
2
R3
+
–
V
–
FR2
+
V
CC
0.3V
–
+
CHARGE
PUMP2
f = 3MHz
DISABLE
LOAD SHARE
0.6V
SA2
V
CC
500k
DISABLE2
CP5
EN2
1
CP3
FETON2
8
V
+
–
IN2
0.7V
Z
GATE2
OUT2
EXPOSED
PAD*
CP6
GND
V
GATE2
CPO2
IN2
15
17
4
5
6
7
C2
*DE PACKAGE ONLY
R2
V
SUPPLY2
4370 BD
M2
4370f
7
LTC4370
operaTion
The LTC4370 controls N-channel MOSFETs, M1 and M2,
to share the load between two supplies. Error amplifier
EA compares OUT1 to OUT2 and sets the servo com-
In the case of an input supply short-circuit, when the
MOSFET is conducting, a large reverse current starts
flowing from the load towards the input. SA detects this
failure condition as soon as it appears and turns off the
MOSFET by rapidly pulling down its gate.
mand voltages, V and V , for servo amplifiers, SA1
FR1
FR2
and SA2. When enabled, each servo amplifier controls
the gate of the external MOSFET to regulate its forward
SA quickly pulls up the gate whenever it senses a large
forward voltage drop. An external capacitor (C1, C2)
voltage drop (V
= V – OUT) to V . The combined
IN FR
FWD
action of EA and SA forces OUT1 to equal OUT2. Having
the power path resistance from OUT1 to the load (R1)
equal that from OUT2 to the load (R2) forces each supply
to source half of the load current.
between the CPO and V pins is needed for fast gate
IN
pull-up. This capacitor is charged up, at device power-up,
by the internal charge-pump. The stored charge is used
for the fast gate pull-up.
ThelowerlimitofV adjustmentis25mVathighersupply
FR
The GATE pin sources current from the CPO pin and sinks
voltages (reducing to 12mV at lower voltages to conserve
current to the V and GND pins. Clamps limit the GATE
IN
powerandvoltagedrop).TheupperlimitisV
+25mV
RANGE
and CPO voltages to 12V above and a diode below V .
IN
(or V
+ 12mV). V
itself is set by the 10µA pull-
RANGE
RANGE
Internal switches pull the FETON pins low when the GATE
up current source into resistor R3. The servo adjust block
to V voltage is below 0.7V to indicate that the external
IN
ensures that only the higher supply’s V is adjusted up
FR
MOSFET is off (body diode could still conduct).
while the other is pinned to the minimum. Tying RANGE to
LDO is a low dropout regulator that generates a 5V supply
at the V pin from the highest V input. When supplies
V
(CP5) forces both V to the minimum, transforming
CC
FR
the device into a dual ideal diode controller.
CC
IN
below 2.9V are being shared, an external supply in the
The servo amplifier raises the gate voltage to enhance
the MOSFET whenever the load current causes the drop
2.9V to 6V range is required at the V pin.
CC
V
and EN pin comparators, CP1 to CP3, control power
to exceed V . For large output currents the MOSFET
CC
FR
passage. The MOSFET is held off whenever the EN pin is
gate is driven fully on and the voltage drop is equal to
above 0.6V, or the V pin is below 2.55V. A high on both
EN pins lowers the current consumption of the device.
I
• R
.
CC
FET
DS(ON)
4370f
8
LTC4370
applicaTions inForMaTion
High availability systems often employ parallel-connected
power supplies or battery feeds to achieve redundancy
and enhance system reliability. ORing diodes have been
a popular means of connecting these supplies at the point
ofload.Systemuptimeimprovesfurtheriftheseparalleled
supplies also share the load current.
Current Sharing Characteristic
The LTC4370 load shares the two supplies by dropping
their voltage difference across the MOSFETs in series
with them (see Figure 1). The MOSFET on the lower sup-
ply drops the minimum servo voltage V
(12mV
FR(MIN)
or 25mV depending on supply voltage levels), while the
other MOSFET drops V plus the supply voltage
M1
SUM85N03-06P
FR(MIN)
V
INA
5V
difference. This equalizes both the OUT pin voltages, and
by Ohm’s law the current that flows through the sense
resistors. Figure 2a illustrates this. It shows the higher
supply’s MOSFET forward voltage drop, V , increasing
to compensate the supply difference up to 500mV.
C1
39nF
EN1 CPO1
V
IN1
GATE1
OUT1
D1
V
R4
CC
R1
C
VCC
0.1µF
FWD
FETON1
FETON2
820Ω
2.5mΩ
OUT
10A
GND
LTC4370
R2
2.5mΩ
SHARE
OFF
RANGE
R3
30.1k
The upper limit of the servo command adjustment is the
minimum servo plus the RANGE pin voltage (500mV in
Figure 2). Hence, when the two supplies differ by a volt-
OUT2
EN2 CPO2
V
GATE2 COMP
IN2
C
C
C2
39nF
0.18µF
D1: RED LED
LN1251C
V
INB
5V
age equal to V
, the higher supply’s V
is pinned
. If the supplies
4370 F01
RANGE
FWD
M2
SUM85N03-06P
at the maximum servo voltage V
FR(MAX)
diverge by more than V
, the OUT pin voltages start
RANGE
Figure 1. 5V Diode-OR Load Share with Status Light
NORMALIZED
CURRENT
V
= 500mV
NORMALIZED
CURRENT
V
= 500mV
1
RANGE
RANGE
I
2
I
1
I
2
I
1
1
1
= 2R
S
1
SLOPE
= 2R
S
SLOPE
2R + R
S
DS(ON)
0.5
0
0.5
0
V
FR(MIN)
I
• R
L
DS(ON)
I
1
I
2
I
1
I
2
V
– V
V
– V
IN2
–500mV
0
500mV
IN(SH)
IN1
IN2
–400mV
0
400mV
IN1
100mV + I • R
S
SHARING CAPTURE RANGE ∆V
I
L
• R
S
SHARING CAPTURE RANGE
∆V
L
IN(SH)
MAXIMUM M2
MOSFET POWER
DISSIPATION
MOSFET
FORWARD
DROP
MAXIMUM M1
MOSFET POWER
DISSIPATION
MOSFET
FORWARD
DROP
V
FR(MAX)
525mV
525mV
V
V
V
V
FWD1
FWD2
FWD1
FWD2
0.5I • R
125mV
25mV
L
DS(ON)
V
25mV
FR(MIN)
V
– V
V
– V
IN1 IN2
–500mV
0
500mV
IN1
IN2
–400mV
0
400mV
4370 F02
DRAWING IS NOT TO SCALE!
(2a) Low R
: Can Servo 25mV Minimum
DS(ON)
(2b) High R
: Fully-On MOSFET
DS(ON)
Forward Regulation Voltage at Half Load
Drops 125mV at Half Load
Figure 2. Load Sharing Characteristics
4370f
9
LTC4370
applicaTions inForMaTion
diverging, and so too, the supply currents. As the supply
voltages separate, the entire load current is steered to the
highersupply.Now,theservocommandacrossthehigher
supply’s MOSFET is folded back from the maximum to
the minimum servo to minimize power dissipated in the
loss of sharing control. Also note that an open RANGE pin
biases itself to a voltage greater than 600mV.
ConnectingtheRANGEpintoV disablestheloadsharing
CC
loop. The servo voltages for both MOSFETs are fixed at the
minimum with no adjustment. The device now behaves
as a dual ideal diode controller. This is handy for testing
purposes. Use the LTC4353 if only a dual ideal diode
controller is needed.
MOSFET.Thesharingcapturerange,ΔV ,inFigure2a
IN(SH)
is 500mV, set by V . Figure 2b will be discussed
RANGE
later in the MOSFET Selection section.
RANGE Pin Configuration
Power Supply Configuration
The RANGE pin resistor is decided by the design trade-off
betweenthesharingcapturerangeandthepowerdissipated
in the MOSFET. A larger R
range at the expense of enhanced power dissipation and
reduced load voltage. On the other hand, supplies with
tight tolerances can afford a smaller capture range and
therefore cooler operation of the MOSFETs.
The LTC4370 can load share high side supplies down to
0V rail voltage. This requires powering the V pin with an
early external supply in the 2.9V to 6V range. In this range
CC
increases the capture
RANGE
of operation V should be lower than V . If V powers
IN
CC
CC
upafterV , andbackfeedingofV bytheinternal5VLDO
IN
CC
isaconcern, thenaseriesresistor(few100Ω)orSchottky
diode limits device power dissipation and backfeeding of
As mentioned, the upper limit of the servo command ad-
a low V supply when any V is high. A 0.1µF bypass
CC
IN
justment is V
plus the minimum forward regulation
capacitor should also be connected between the V and
GND pins, close to the device. Figure 3 illustrates this.
RANGE
CC
voltage. Since an internal 10μA pull-up current flowing
through the external resistor sets V
:
RANGE
If either V operates above 2.9V, then the external supply
IN
V
= 10µA • R
+ V
(1)
at V is not needed. The 0.1µF capacitor is still required
FR(MAX)
RANGE
FR(MIN)
CC
for bypassing.
If R
is larger than 60k (including the pin open
RANGE
state), the internal limit for the first term on the right-
Start of Sharing
hand side of Equation 1 is 600mV, setting V
to
FR(MAX)
When currents are not being shared either because the
load current or one of the supplies is off, the COMP volt-
age is railed towards 0V or 2V depending on the input
signal to the error amplifier and its offset. For example,
612mV or 625mV. Note that servo voltages nearing the
MOSFET’s body diode voltage may divert some or all cur-
rent to the diode especially at hot temperatures. This may
either cause FETON to go low if V falls below 0.7V, or
GS
M1
M1
0V TO V
2.9V TO 18V
(0V TO 18V)
CC
V
V
GATE1
LTC4370
GATE2
V
V
GATE1
LTC4370
GATE2
OPTIONAL
OR
IN1
IN1
2.9V TO 6V
HERE
V
CC
V
CC
C
C
VCC
0.1µF
VCC
0.1µF
IN2
IN2
0V TO 18V
(2.9V TO 18V)
0V TO V
CC
4370 F03
M2
M2
Figure 3. Power Supply Configurations
4370f
10
LTC4370
applicaTions inForMaTion
in the absence of load current the differential input volt-
age to the error amplifier is zero and the COMP current is
MOSFET Selection
The LTC4370 drives N-channel MOSFETs to conduct the
load current. The important parameters of the MOSFET
are its maximum drain-source voltage BV , maximum
gate-source voltage V
maximum power dissipation P
g
• V
. Before sharing can start, the COMP
m(EA)
EA(OS)
voltage has to slew towards its operating point of 0.7V
(when V < V ) or 1.24V (V > V ). This delay is
DSS
IN1
IN2
IN1
IN2
, on-resistance R
, and
GS(MAX)
DS(ON)
determined by the differential input signal to the error
.
D(MAX)
amplifier (which is ΔV
= OUT1 – OUT2 = (I − I ) • R ),
OUT
1 2 S
If an input is connected to ground, the full supply voltage
its g and the COMP capacitor value. Depending on how
m
can appear across the MOSFET. To survive this, the BV
the currents split before converging, the delay can vary
DSS
GS(MAX)
must be higher than the supply voltages. The V
from 1 to 5 times:
rating of the MOSFET should exceed 14V since that is the
CC •ΔVCOMP
gm(EA) • IL • RS
upper limit of the internal GATE to V clamp.
IN
To obtainthemaximumsharingcapturerange,theR
DS(ON)
Figure 4a shows the case where a 5.1V V is turned
shouldbelowenoughfortheservoamplifiertoregulatethe
minimum forward regulation voltage across the MOSFET
while it’s conducting half of the load current. If it cannot,
IN1
on while V is at 4.9V supplying 10A. Initially, COMP
IN2
is railed low to 0.1V since ΔV
(−I • R ) is negative,
OUT
2 S
and needs to rise to 1.24V as the final V is higher than
thegatevoltagewillberailedhigh.Hence,theR
value
IN1
DS(ON)
V
. With V off, ΔV is large and negative, causing the
in the MOSFET data sheet should be looked up for 10V or
IN2
IN1
IN
forwardregulationvoltageofthesecondsupplyV tobe
4.5V gate drive depending on the V voltage. Since the
FR2
IN
folded back to the minimum V
(travelling from left
OUT voltages are equal, the breakpoint for exact sharing
FR(MIN)
to right in Figure 2a). As the ΔV magnitude decreases,
in the higher R
case is:
IN
, lowering I and the
FR(MAX) 2
DS(ON)
V
rises to the maximum V
load voltage. COMP is around 0.7V when V
FR2
ΔV
= V
– 0.5I • R
(2)
IN(SH)
FR(MAX)
L
DS(ON)
is being
FR2
adjusted. When COMP reaches 1.24V, V is kept at the
FR2
minimumandV isadjustedappropriatelytocompensate
FR1
IN
IN1
for the 0.2V of ΔV . The sharing closure is smoother for
the case where V < V since COMP only has to slew
IN2
to 0.7V to lower V (Figure 4b).
FR2
V
V
L
= 5.1V
= 4.9V
V
V
L
= 4.9V
= 5.1V
IN1
IN2
IN1
IN2
I
I
I
I
2
1
2
I = 10A
I = 10A
CURRENT
5A/DIV
CURRENT
5A/DIV
1
OUT
OUT
VOLTAGE
2V/DIV
VOLTAGE
2V/DIV
V
IN1
V
IN1
COMP
(0.5V/DIV)
COMP
(1V/DIV)
4370 F04a
4370 F04b
25ms/DIV
25ms/DIV
(4a) VIN1 > VIN2
(4b) VIN1 < VIN2
Figure 4. Start of Sharing at VIN1 Turn-On
4370f
11
LTC4370
applicaTions inForMaTion
In Figure 2b, 0.5I • R
is 125mV. The higher R
Sense Resistor Selection
L
DS(ON)
DS(ON)
railstheservoamplifierhighasitcannotregulatethe25mV
across the lower supply’s MOSFET. Compared
Thesenseresistorvoltagedropdictatesthecurrentsharing
accuracy. Sharing error, due to the error amplifier input
offset, decreases with increasing sense voltage as:
V
FR(MIN)
to Figure 2a, the sharing capture range shrinks by 100mV
(125mV – 25mV) to 400mV. However, the ΔV over
IN
| VEA(OS)
|
ΔI
IL
|I1 – I2 |
IL
2mV
IL • RS
which currents are shared partially stays the same at
=
=
=
500mV+I • R .Evenwhennotmaximizingsharingrange,
IL • RS
L
S
(4)
I • R
should be kept below 75mV for optimum
L
DS(ON)
performance.
I and I are the two supply currents, I is the load current
1
2
L
(I + I = I ), R is the sense resistor value, and V
1
2
L
S
EA(OS)
The peak power dissipation in the MOSFET occurs when
the entire load current is being sourced by one supply
with the maximum forward regulation voltage dropped
across the MOSFET (as shown in Figure 2a). Therefore,
is the input offset of the internal error amplifier. A 25mV
sense resistor voltage drop with half of the load cur-
rent flowing through it (i.e., I • R = 50mV) gives a 4%
L
S
sharing error. A larger sense resistance may also be
needed if there is a connector in between the OUT pins
and the load to minimize the effect of its resistance. At
larger sense voltages the accuracy will be limited by the
sense resistor tolerance.
the P
rating of the MOSFET should satisfy:
D(MAX)
P
≥ I • V
FR(MAX)
(3)
D(MAX)
L
Table 1 provides starting guidelines for the type of
MOSFET package and heat sink required at various levels
of power dissipation. These are typical ranges for a room
temperature ambient with no air flow.
If sharing accuracy requirements can be relaxed, power
dissipatedinthesenseresistorcanbereducedbyselecting
alowerresistance.Worst-casepowerdissipationhappens
at full load, i.e., when load current is not being shared.
While reducing the sense resistance, note that the sharing
Table 1. Guidelines for MOSFET Power Dissipation
MAXIMUM POWER
DISSIPATED
0.5W to 1W
1W to 2W
MOSFET PACKAGE
HEAT SINK
loop does not close for load currents below V
/R .
EA(OS)
S
SO-8
PCB
The two sense resistors can have different values if the
application does not require the load current to be shared
equally between the supplies. In such a case:
SO-8 With Exposed Pad,
D-Pak (TO-252)
PCB
TO-220
DD-Pak (TO-263), TO-220
TO-220
Standing in Free Air
PCB
2W to 4W
RS1
RS2
I2
I1
4W to 10W
10W to 20W
20W to 50W
Stamping
=
(5)
TO-220
Casting, Extrusion
Extrusion
TO-247, TO-3P
CPO Capacitor Selection
TherecommendedvalueofthecapacitorbetweentheCPO
andV pinsisapproximately10×theinputcapacitanceC
IN
ISS
oftheMOSFET. Alargercapacitortakesacorrespondingly
longer time to be charged by the internal charge pump. A
smaller capacitor suffers more voltage drop during a fast
gate turn-on event as it shares charge with the MOSFET
gate capacitance.
4370f
12
LTC4370
applicaTions inForMaTion
External CPO Supply
pense of increased sharing closure delay, while a smaller
capacitorcancausethetwosupplycurrentstoswitchback
and forth before settling. The COMP capacitor can be just
The internal charge pump takes milliseconds to charge
up the CPO capacitor especially during device power-up.
This time can be shortened by connecting an external
supply to the CPO pin. A series resistor is needed to limit
the current into the internal clamp between the CPO and
10× C when a CPO capacitor is omitted, i.e., when fast
ISS
gate turn-on is not used (see Figure 6).
Input and Output Capacitance for Pulsed Loads
V pins. The CPO supply should also be higher than the
IN
Forpulsedloads,theloadcurrentwillbesharedeverycycle
at frequencies below 100Hz. At higher frequencies, each
cycle’s current may not be shared but the time average of
the currents will be. Bypassing capacitance on the inputs
should be provided to minimize glitches and ripple. This
is important since the controller tries to compensate for
the supply voltage differences to achieve load sharing.
Sufficient load capacitance should also be provided to
enhance the DC component of the load current presented
to the load share circuit. It is also important to design
main input supply to meet the gate drive requirements
of the MOSFET. Figure 5 shows such a 3.3V load share
application, where a 12V supply is connected to the CPO
pins through a 1k resistor. The 1k limits the current into
the CPO pin when the V pin is grounded. For the 8.7V
IN
of gate drive (12V – 3.3V), logic-level MOSFETs would be
an appropriate choice for M1 and M2.
Loop Stability
The servo amplifier loop is compensated by the gate
capacitance of the N-channel power MOSFET. No further
compensation components are normally required. In the
case when a MOSFET with less than 1nF gate capacitance
ischosen,a1nFcompensationcapacitorconnectedacross
the gate and source might be required.
I • R
below 75mV, as mentioned earlier.
L
DS(ON)
With very low duty cycle or very low frequency loads,
the COMP voltage will rail whenever the load current falls
belowthesharingthresholdofV
/R forhundredsof
EA(OS)
S
milliseconds. At the start of the next load cycle there will
be a sharing closure delay as COMP slews to its operating
point around 0.7V or 1.24V. To avoid this delay, maintain
The load sharing control loop is compensated by the
capacitor from the COMP pin to ground. This capacitor
the load current above V
/R .
EA(OS)
S
should be at least 50× the input capacitance C of the
ISS
MOSFET. A larger capacitor improves stability at the ex-
M1
SUM85N03-06P
M1
V
TO SENSE
RESISTOR
V
INA
INA
12V
3.3V
NC
C1
39nF
EN1
CPO1
V
GATE1
IN1
OUT1
V
CC
V
IN1
V
IN2
GATE1
R4
R1
C
VCC
FETON1
FETON2
2.7k
2.5mΩ
1k
1k
0.1µF
OUT
10A
LTC4370
GND
CPO1
CPO2
R2
2.5mΩ
D1
LTC4370
12V
RANGE
R3
47.5k
OUT2
GATE2 COMP
EN2 CPO2
V
IN2
C
C
GATE2
0.039µF
4370 F05
NC
INB
12V
C2
39nF
V
4370 F06
M2
SUM85N03-06P
D1: RED LED, LN1251C
V
TO SENSE
RESISTOR
INB
3.3V
M2
Figure 5. 3.3V Load Share with External 12V Supply
Powering CPO for Faster Start-Up and Refresh
Figure 6. Current Sharing 12V Supplies
4370f
13
LTC4370
applicaTions inForMaTion
Input Transient Protection
Equation 3 gives the maximum power dissipation in the
MOSFET to be:
When the capacitances at the input and output are very
small, rapid changes in current can cause transients that
exceed the 24V absolute maximum rating of the V and
OUT pins. In ORing applications, one surge suppressor
connected from OUT to ground clamps all the inputs. In
the absence of a surge suppressor, an output capacitance
of 10μF is sufficient in most applications to prevent the
transient from exceeding 24V.
P
= 10A • 500mV = 5W
D(MAX)
IN
Sufficient PCB area with air flow needs to be provided
around the MOSFET drain to keep its junction temperature
below the 175°C maximum.
A 2.5mΩ sense resistor drops 25mV at full load and
yields an error amplifier offset induced sharing error of
2mV/(10A • 2.5mΩ) or 8% (Equation 4). At full load, the
2
12V Design Example
sense resistor dissipates 10A • 2.5mΩ or 250mW. Since
a 12V supply is large enough to tolerate a diode drop, fast
gate turn-on is not needed. Hence, the CPO capacitor is
This design example demonstrates the selection of
components in a 12V system with a 10A maximum load
current and 2% tolerance supplies (Figure 6). That is
followed by the recalculations involved for a similar 5V
system (Figure 1).
omitted. The input capacitance, C , of the MOSFET is
ISS
about 3800pF. Since fast turn-on is not used, the COMP
capacitor C can be just 10× C at 0.039µF.
C
ISS
Red LED, D1, turns on when any one of the MOSFETs is
off, indicating a break in sharing. It requires around 3mA
for good luminous intensity. Accounting for a 2V diode
First, calculate the R
of the MOSFET to achieve
DS(ON)
the desired forward drop at full load. Assuming a V
of 50mV:
FWD
drop and 0.6V V , R4 is set to 2.7k.
OL
V
50mV
10A
FWD
RDS(ON)
≤
=
= 5mΩ
ILOAD
5V Design Example
For a 5V, 10A system with 3% tolerance supplies and
fast gate turn-on (Figure 1), the following components
The SUM85N03-06P offers a good solution in a DD-Pak
(TO-263) sized package with a 4.5mΩ R , 30V
DS(ON)
is22.5mV,
need to be recalculated: R3, C1, C2, C , and R4. R3 is
C
BV
and 20V V
. Since 0.5I • R
DSS
GS(MAX)
L
DS(ON)
set to 30.1k to account for possible supply differences
(2 • 3% • 5V yields 300mV). C1 and C2 are set to 10×
the servo amplifier will be able to regulate the 25mV mini-
mum forward regulation voltage leading to the maximum
C
at 0.039µF. With fast turn-on, C is selected closer
ISS
C
possible sharing range set by V
.
RANGE
to 50× C at 0.18µF. With the 5V supply, R4 needs to
ISS
2%of12V is240mV. Thesharingcapturerange, ΔV
,
IN(SH)
be 820Ω to allow 3mA into the LED.
needs to be about 2× 240mV ( 480mV) to work for most
supply voltage differences. A 47.5k R3 sets V to
RANGE
475mV. Equation 1 is used to calculate the maximum
forward regulation voltage:
V
= 10µA • 47.5k + 25mV = 500mV
FR(MAX)
4370f
14
LTC4370
applicaTions inForMaTion
PCB Layout Considerations
management techniques such as sufficient drain cop-
per area or heat sinks should be considered for optimal
MOSFET power dissipation. See Figure 7.
Kelvin connection of the OUT pins to the sense resis-
tors is important for accurate current sharing. Place the
MOSFETascloseaspossibletothesenseresistor.Keepthe
traces to the MOSFET wide and short to minimize resistive
losses. The PCB traces associated with the power path
throughtheMOSFETshouldhavelowresistance. Thermal
It is also important to put C , the bypass capacitor, as
VCC
close as possible between V and GND. Place C1 and
CC
C2 near the CPO and V pins. The COMP pin may need
IN
a guard ring to maintain low board leakage.
CURRENT FLOW
G
FROM
W
M1
D
SUPPLY
DD-PAK
A
S
VIA TO
GROUND
PLANE
C
VCC
R1
TRACK WIDTH
W: 0.03 PER AMPERE
ON 1oz Cu FOIL
MSOP-16
LTC4370
TO
LOAD
DRAWING IS NOT TO SCALE!
R2
G
S
FROM
SUPPLY
B
M2
D
W
DD-PAK
4370 FO7
CURRENT FLOW
Figure 7. Recommended PCB Layout for M1, M2, CVCC, R1, R2
4370f
15
LTC4370
Typical applicaTions
Current Sharing 3.3V Supplies for 20A Output
M1
IRLS3034PBF
V
INA
3.3V 3ꢀ
C1
0.1µF
EN1
CPO1
V
GATE1
IN1
V
OUT1
CC
C
0.1µF
VCC
R1
GND
FETON1
FETON2
2mΩ
OUT
20A
LTC4370
R2
2mΩ
RANGE
EN2
R3
20k
OUT2
V
IN2
GATE2
COMP
CPO2
C
C
C2
0.1µF
0.47µF
V
INB
3.3V 3ꢀ
4370 TA02
M2
IRLS3034PBF
4370f
16
LTC4370
Typical applicaTions
12V Ideal Diode-OR by Tying RANGE to VCC (to Compare Against Load Share).
Use LTC4353 if Load Share Is Not Desired
M1
SUM85N03-06P
V
INA
12V
NC
CPO1
V
GATE1
OUT1
IN1
EN1
RANGE
FETON1
COMP
OUT
10A
V
LTC4370
NC
CC
C
VCC
0.1µF
GND
FETON2
OUT2
EN2
CPO2
NC
V
GATE2
M2
IN2
V
INB
12V
4370 TA03
SUM85N03-06P
4370f
17
LTC4370
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
DE Package
16-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1732 Rev Ø)
0.70 0.05
3.30 0.05
1.70 0.05
3.60 0.05
2.20 0.05
PACKAGE
OUTLINE
0.25 0.05
0.45 BSC
3.15 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
R = 0.115
TYP
0.40 0.10
16
4.00 0.10
(2 SIDES)
9
R = 0.05
TYP
3.30 0.10
3.00 0.10
(2 SIDES)
1.70 0.10
PIN 1 NOTCH
R = 0.20 OR
PIN 1
TOP MARK
(SEE NOTE 6)
0.35 × 45°
CHAMFER
(DE16) DFN 0806 REV Ø
8
1
0.23 0.05
0.45 BSC
0.75 0.05
0.200 REF
3.15 REF
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
4370f
18
LTC4370
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
MS Package
16-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1669 Rev Ø)
0.889 ± 0.127
(.035 ± .005)
5.23
3.20 – 3.45
(.206)
(.126 – .136)
MIN
4.039 ± 0.102
(.159 ± .004)
(NOTE 3)
0.50
(.0197)
BSC
0.305 ± 0.038
(.0120 ± .0015)
TYP
0.280 ± 0.076
(.011 ± .003)
REF
16151413121110
9
RECOMMENDED SOLDER PAD LAYOUT
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
DETAIL “A”
0.254
4.90 ± 0.152
(.193 ± .006)
(.010)
0° – 6° TYP
GAUGE PLANE
0.53 ± 0.152
(.021 ± .006)
1 2 3 4 5 6 7 8
0.86
(.034)
REF
1.10
(.043)
MAX
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.1016 ± 0.0508
(.004 ± .002)
MSOP (MS16) 1107 REV Ø
0.50
(.0197)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
4370f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC4370
Typical applicaTion
1.2V Load Share
SUM85N03-06P
V
INA
1.2V
39nF
EN1 CPO1
V
GATE1
GATE2
IN1
5V
OUT1
FETON1
FETON2
V
CC
0.1µF
2mΩ
2mΩ
GND
LTC4370
OUT
RANGE
OUT2
7.5k
EN2 CPO2
V
COMP
IN2
0.18µF
39nF
V
INB
1.2V
4370 TA04
SUM85N03-06P
relaTeD parTs
PART NUMBER
DESCRIPTION
COMMENTS
LTC1473/
LTC1473L
Dual PowerPathTM Switch Driver
N-Channel, 4.75V to 30V/3.3V to 10V, SSOP-16 Package
LTC1479
LTC4352
LTC4353
LTC4354
LTC4355
PowerPath Controller for Dual Battery Systems
Three N-Channel Drivers, 6V to 28V, SSOP-36 Package
N-Channel, 0V to 18V, UV, OV, MSOP-12 and DFN-12 Packages
Dual N-Channel, 0V to 18V, MSOP-16 and DFN-16 Packages
Dual N-Channel, −4.5V to −80V, SO-8 and DFN-8 Packages
Dual N-Channel, 9V to 80V, SO-16 and DFN-14 Packages
Low Voltage Ideal Diode Controller with Monitoring
Dual Low Voltage Ideal Diode Controller
Negative Voltage Diode-OR Controller and Monitor
Positive High Voltage Ideal Diode-OR with Supply and
Fuse Monitors
LTC4357
LTC4358
LTC4411
Positive High Voltage Ideal Diode Controller
5A Ideal Diode
2.6A Low Loss Ideal Diode in ThinSOTTM
N-Channel, 9V to 80V, MSOP-8 and DFN-6 Packages
Internal N-Channel, 9V to 26.5V, TSSOP-16 and DFN-14 Packages
Internal P-Channel, 2.6V to 5.5V, 40μA I , SOT-23 Package
Q
LTC4412/
LTC4412HV
Low Loss PowerPath Controller in ThinSOT
P-Channel, 2.5V to 28V/36V, 11μA I , SOT-23 Package
Q
LTC4413/
LTC4413-1
Dual 2.6A, 2.5V to 5.5V, Ideal Diodes in DFN-10
Dual Internal P-Channel, 2.5V to 5.5V, DFN-10 Package
LTC4414
36V Low Loss PowerPath Controller for Large
P-Channel MOSFETs
P-Channel, 3V to 36V, 30μA I , MSOP-8 Package
Q
LTC4415
Dual 4A Ideal Diodes with Adjustable Current Limit
Dual P-Channel 50mΩ Ideal Diodes, 1.7V to 5.5V, 15mV Forward
Drop, MSOP-16 and DFN-16 Packages
LTC4416/
LTC4416-1
36V Low Loss Dual PowerPath Controller for Large
P-Channel MOSFETs
Dual P-Channel, 3.6V to 36V, 70μA I , MSOP-10 Package
Q
4370f
LT 0512 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
●
LINEAR TECHNOLOGY CORPORATION 2012
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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