LTC4366ITS8-2#TRMPBF

LTC4366

High Voltage Surge Stopper

FEATURES

DESCRIPTION

The LTC^®4366 surge stopper protects loads from high

voltage transients. By controlling the gate of an external

N-channel MOSFET, the LTC4366 regulates the output

during an overvoltage transient. The load may remain

operational while the overvoltage is dropped across the

MOSFET. Placing a resistor in the return line isolates the

LTC4366andallowsittofloatupwiththesupply;therefore,

the upper limit on the output voltage depends only on the

availability of high valued resistors and MOSFET ratings.

n

Rugged Floating Topology

n

Wide Operating Voltage Range: 9V to >500V

n

Adjustable Output Clamp Voltage

n

Controls N-Channel MOSFET

n

Adjustable Protection Timer

n

Internal 9-Second Cool-Down Timer

n

Shutdown I < 14µA

Q

n

8-Lead TSOT and 3mm × 2mm DFN Packages

An adjustable overvoltage timer prevents MOSFET dam-

age during the surge while an additional 9-second timer

provides for MOSFET cool down. A shutdown pin reduces

the quiescent current to less than 14µA during shutdown.

AfterafaulttheLTC4366-1latchesoffwhiletheLTC4366-2

will auto-retry.

APPLICATIONS

n

Industrial, Automotive and Avionic Surge Protection

High Voltage DC Distribution

n

28V Vehicle Systems

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property

of their respective owners. Patents pending.

TYPICAL APPLICATION

Overvoltage Protected 1.5A, 28V Supply

IXTK90N25L2

Overvoltage Protector Regulates Output at 43V During Transient

V

IN

V

OUT

28V

1.5A

250V INPUT SURGE

2nF

V

10Ω

324k

0.47µF

IN

100V/DIV

28V

V

GATE

LTC4366-2

OUT

FB

BASE

DD

12.4k

422k

43V CLAMP

SD

V

OUT

28V

20V/DIV

TIMER

1µF

V

SS

436612 TA01a

436612 TA01b

100ms/DIV

46.4k

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LTC4366

ABSOLUTE MAXIMUM RATINGS ^{(Notes 1, 2) All voltages relative to V}_SS, unless otherwise noted.

Supply Voltage (V ) ................................ –0.3V to 10V

Supply Voltage (OUT) ................................. –0.3V to 5V

Input Voltages

Currents

DD

I

...................................................................10mA

VDD

OUT

...................................................................10mA

BASE................................................. –300µA to 10µA

SD.......................................................–10mA to 10µA

Operating Ambient Temperature Range (Note 4)

LTC4366C................................................ 0°C to 70°C

LTC4366I.............................................–40°C to 85°C

LTC4366H.......................................... –40°C to 125°C

LTC4366MP....................................... –55°C to 125°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec)

FB .............................................. –0.3V to OUT + 0.3V

TIMER................................................... –0.3V to 3.5V

SD.......................................................... –0.3V to 10V

Output Voltages

BASE.........................................................–1.5V to 4V

OUT – BASE ......................................... –0.3V to 5.5V

GATE (Note 3)........................................ –0.3V to 15V

GATE – OUT (Note 3)............................. –0.3V to 10V

TSOT-23 Package Only .................................... 300°C

PIN CONFIGURATION

TOP VIEW

V

1

2

3

4

8

7

6

5

BASE

FB

SS

V

1

8 GATE

7 OUT

6 FB

TIMER

DD

9

SD 2

TIMER 3

SD

OUT

GATE

V

DD

V

SS

4

5 BASE

TS8 PACKAGE

8-LEAD PLASTIC TSOT-23

= 150°C, θ = 195°C/W

DDB PACKAGE

8-LEAD (3mm × 2mm) PLASTIC DFN

= 150°C,

T

JMAX

JA

T

JMAX

θ

JA

= 75°C/W IF V IS SOLDERED TO PCB, θ = 135°C/W IF V IS NOT SOLDERED TO PCB

SS JA SS

EXPOSED PAD (PIN 9), PCB V CONNECTION OPTIONAL

SS

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LTC4366

ORDER INFORMATION

Lead Free Finish

TAPE AND REEL (MINI)

TAPE AND REEL

PART MARKING*

LTFMC

LFMD

PACKAGE DESCRIPTION

TEMPERATURE RANGE

0°C to 70°C

LTC4366CTS8-1#TRMPBF

LTC4366ITS8-1#TRMPBF

LTC4366HTS8-1#TRMPBF

LTC4366CDDB-1#TRMPBF

LTC4366IDDB-1#TRMPBF

LTC4366HDDB-1#TRMPBF

LTC4366CTS8-2#TRMPBF

LTC4366ITS8-2#TRMPBF

LTC4366HTS8-2#TRMPBF

LTC4366CDDB-2#TRMPBF

LTC4366IDDB-2#TRMPBF

LTC4366HDDB-2#TRMPBF

LTC4366CTS8-1#TRPBF

LTC4366ITS8-1#TRPBF

LTC4366HTS8-1#TRPBF

LTC4366CDDB-1#TRPBF

LTC4366IDDB-1#TRPBF

LTC4366HDDB-1#TRPBF

LTC4366CTS8-2#TRPBF

LTC4366ITS8-2#TRPBF

LTC4366HTS8-2#TRPBF

LTC4366CDDB-2#TRPBF

LTC4366IDDB-2#TRPBF

LTC4366HDDB-2#TRPBF

8-Lead Plastic TSOT-23

–40°C to 85°C

–40°C to 125°C

0°C to 70°C

8-Lead Plastic TSOT-23

8-Lead (3mm × 2mm) Plastic DFN

8-Lead Plastic TSOT-23

LFMD

–40°C to 85°C

–40°C to 125°C

0°C to 70°C

LFMD

LTFMF

8-Lead Plastic TSOT-23

–40°C to 85°C

–40°C to 125°C

0°C to 70°C

LTFMF

8-Lead Plastic TSOT-23

LFMG

8-Lead (3mm × 2mm) Plastic DFN

8-Lead Plastic TSOT-23

LFMG

–40°C to 85°C

–40°C to 125°C

–55°C to 125°C

LFMG

LTC4366MPTS8-1#TRMPBF LTC4366MPTS8-1#TRPBF LTFMC

LTC4366MPTS8-2#TRMPBF LTC4366MPTS8-2#TRPBF LTFMF

LTC4366MPDDB-1#TRMPBF LTC4366MPDDB-1#TRPBF LFMD

LTC4366MPDDB-2#TRMPBF LTC4366MPDDB-2#TRPBF LFMG

8-Lead Plastic TSOT-23

8-Lead (3mm × 2mm) Plastic DFN

TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container.

Consult LTC Marketing for parts specified with wider operating temperature ranges.

Consult LTC Marketing for information on lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

436612fe

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LTC4366

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. All voltages relative to V_SS, unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

DD

Regulator

l

V

Shunt Regulator Voltage

I = 1mA

11.5

12

12.5

V

Z(VDD)

DD

l

∆V

Shunt Regulator Load Regulation

I = 1mA to 5mA

LTC4366C/I/H

LTC4366MP

30

90

130

mV

Z(VDD)

l

V

Supply Voltage (Note 3)

4.5

V

µA

DD

Z(VDD)

I

Pin Current – Start-Up, Gate Low

Pin Current – Start-Up, Gate High

Pin Current – Shutdown

GATE = 0V, V = 7V, OUT = 0V

15

9

23

VDD(STLO)

VDD(STHI)

VDD(SD)

DD

GATE Open, V = 7V, OUT = 0V

13

8

DD

V

= 7V, OUT = 0V

5

DD

OUT Regulator

l

V

OUT Shunt Regulator Voltage

OUT Shunt Regulator Load Regulation

OUT Supply Voltage (Note 3)

OUT Undervoltage Lockout 1

I = 1mA, BASE = 0V

I = 1mA to 5mA

5.0

3.0

5.7

30

6.0

70

V

mV

V

Z(OUT)

∆V

Z(OUT)

OUT

V

Z(OUT)

l

V

Rising

LTC4366C/I/H

LTC4366MP

2.42

2.55

2.75

2.80

V

UVLO1

l

∆V

OUT Undervoltage Lockout 1 Hysteresis

OUT Undervoltage Lockout 2

0.2

4.5

0.3

0.28

4.75

0.4

37

0.4

4.9

0.5

54

V

UVH1

V

UVLO2

∆V

OUT Undervoltage Lockout 2 Hysteresis

OUT Pin Current – Regulation Amplifier On

OUT Pin Current – Charge Pump On

OUT Pin Current – Shutdown

V

UVH2

OUT(AMP)

OUT(CP)

OUT(SD)

I

µA

150

3

220

6

BASE, V

SS

l

V

BASE Shunt Regulator Voltage (OUT – BASE) I = –10µA, OUT = 4.5V

5.5

6.2

125

–0.8

–45

–160

–7

6.6

200

–5.5

–72

V

mV

µA

Z(BASE)

∆V

BASE Shunt Regulator Load Regulation

BASE Pin Leakage Current

I = –10µA to –80µA, OUT = 4.5V

OUT = 4.5V, BASE = –0.5V

Z(BASE)

I

–0.1

–30

BASE

V

Pin Current – Regulation Amplifier On

Pin Current – Charge Pump On

Pin Current – Shutdown

VSS(AMP)

VSS(CP)

VSS(SD)

SS

–108

–230

–12

GATE Drive

l

∆V

External N-Channel Gate Drive (GATE – OUT) OUT = 4.9V, I = 0, –1µA

11.2

12

12.5

V

GATE

l

I

GATE Pin Current – Start-Up

GATE = OUT = 0V

LTC4366C/I/H

LTC4366MP

–4.5

–3.2

–7.5

–11

µA

GATE(ST)

l

I

GATE Pin Current – Charge Pump On

GATE Pin Current – Fast Discharge

GATE Pin Current – Fault

GATE = 5V, OUT = 4.9V

GATE = 10V, OUT = 4.9V

–14

122

0.3

–20

200

0.7

–28

300

1.2

µA

mA

GATE(CP)

GATE(FD)

GATE(FLT)

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LTC4366

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. All voltages relative to V_SS, unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

1.193

1.0

TYP

MAX

UNITS

FB, SD, TIMER

l

V

3% FB pin Regulation Threshold (OUT – FB)

FB Pin Leakage Current

1.23

0

1.267

1

V

µA

V

FB(REG)

I

OUT – FB = 1.2V

Falling

FB

V

SD Pin Threshold Voltage (V – SD)

1.5

2.3

SD(TH)

DD

l

SD Pin Hysteresis

LTC4366C/I/H

LTC4366MP

147

129

280

530

mV

SD(HYST)

l

I

SD Pin Input Pull-Up Current

V

DD

– SD = 0.7V

LTC4366C/I/H

LTC4366MP

–0.7

–0.5

–1.6

–3.5

µA

SD

l

V

TIMER Pin Threshold

TIMER Rising, V = 7V, OUT = V

Z(OUT)

2.6

2.8

3.1

V

TIMER(H)

DD

l

I

TIMER Pin Pull-Up Current

TIMER = 1V

LTC4366C/I/H

LTC4366MP

–5.1

–4

–9

–13

µA

TIMER(UP)

l

TIMER Pin Pull-Down Current

TIMER = 1V

LTC4366C/I/H

LTC4366MP

0.9

0.7

1.8

2.8

µA

TIMER(DN)

l

TIMER Pin Current Ratio I

/I

15

20

25

%

TIMER(RATIO)

TIMER(DN) TIMER(UP)

AC Characteristics

l

t

–

SD Low to Gate Low Filter Time

Step V – SD from 0V to 3V

420

60

700

150

1200

300

µs

ns

DLY SD

DD

–

FB Low to Gate Low Delay Time

Cool-Down Timer (Internal)

Step OUT – FB from 0V to 1.3V

DLY FAST

l

V

DD

= V

Z(VDD)

LTC4366C/I/H

LTC4366MP

5.9

9

16

19

Seconds

D(COOL)

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 3: Limits on the maximum rating is defined as whichever limit occurs

first. An internal clamp limits the GATE pin to a maximum of 12V above

source. Driving this pin to voltages beyond the clamp may damage the

device.

Note 2: All currents into pins are positive.

Note 4: T is calculated from the ambient temperature, T , and power

J A

dissipation, P , according to the formula:

D

T = T + (P • θ )

JA

J

A

D

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LTC4366

TYPICAL PERFORMANCE CHARACTERISTICS

V_DDShunt Regulator vs

V_DDCurrent

V_DDShunt Regulator vs

Temperature

V_DDStart-Up Current vs

Temperature (Gate High)

13.0

12.5

12.0

11.5

13.0

12.5

12.0

11.5

11.0

15

12

9

6

3

0

5

10

(mA)

15

20

–50 –25

0

25

50

75 100 125

–50 –25

0

25

50

75 100 125

I

TEMPERATURE (°C)

VDD

436612 G01

436612 G02

436612 G03

OUT Shunt Regulator vs

OUT Current

OUT Shunt Regulator vs

Temperature

V_SSCurrent (Regulation AMP On)

vs Temperature

5.9

5.8

5.7

5.6

5.5

7

6

5

4

75

50

25

0

5

10

(mA)

15

20

–50 –25

0

25

50

75 100 125

–50 –25

0

25

50

75 100 125

I

TEMPERATURE (°C)

OUT

436612 G04

436612 G05

436612 G10

V_SSCurrent (Charge Pump On)

vs Temperature

Gate Drive vs Gate Pull-Up

Current

Gate Current (Charge Pump On)

vs Temperature

–300

–200

–100

0

16

12

8

–40

–30

–20

–10

0

4

0

–50 –25

0

25

50

75 100 125

0

–10

–20

–30

–50 –25

0

25

50

75 100 125

TEMPERATURE (°C)

I

(µA)

TEMPERATURE (°C)

GATE

436612 G11

436612 G12

436612 G14

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LTC4366

TYPICAL PERFORMANCE CHARACTERISTICS

Base Shunt Regulator vs

Base Current

Timer Pull-Up Current vs

Temperature

Gate Start-Up Current vs

Temperature

–12

–10

–8

7.0

6.5

6.0

5.5

–12

–10

–8

–6

–4

–50 –25

0

25

50

75 100 125

0

–100

–200

–300

(µA)

–400

–500

–50 –25

0

25

50

75 100 125

TEMPERATURE (°C)

I

TEMPERATURE (°C)

BASE

436612 G15

436612 G16

436612 G18

SD Pull-Up Current vs

FB Regulation Threshold vs

Temperature

Cool-Down Time vs Temperature

1.24

1.23

1.22

1.21

16

14

12

10

8

–3

–2

–1

0

6

–50 –25

0

25

50

75 100 125

–50 –25

0

25

50

75 100 125

–50 –25

0

25

50

75 100 125

TEMPERATURE (°C)

436612 G22

436612 G23

436612 G21

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LTC4366

PIN FUNCTIONS

BASE: Base Driver Output for External PNP Shunt Regula-

tor. This pin is connected to the anode of an internal 6.2V

Zener with the cathode tied to OUT. In cases where lower

SD: Shutdown Comparator Input. Tie to V if unused.

DD

Connectpintoalimitedcurrentpulldowncreatedbyadding

a resistor in series with an open-drain or open-collector

pull-down transistor. Activating the external pull down

overcomes the internal 1.6µA pull-up current source and

allows the SD pin to cross the shutdown threshold. This

Zener (Z3) clamp current is desired but a large V resis-

SS

tor is prohibited, connect an external PNP base to this pin

(PNP collector is grounded, emitter is tied to V ). Tie this

SS

pin to V if unused.

threshold is defined as 1.5V below V with a 280mV

SS

DD

hysteresis. To prevent false triggers this pin must stay

below the threshold for 700µs to activate the shutdown

state. The shutdown state lowers the total quiescent cur-

Exposed Pad: The exposed pad may be left open or con-

nected to V .

SS

FB: Overvoltage Regulation Amplifier Feedback Input.

Connect this pin to an external resistive divider from OUT

to ground. The overvoltage regulation amplifier controls

the gate of the external N-channel MOSFET to regulate

the FB pin voltage at 1.23V below OUT. The overvoltage

amplifier will activate a 200mA pull-down on the GATE pin

during a fast overvoltage event.

rent (I

plus I ) below 20µA. This quiescent current

VDD

OUT

does not include shunt current in the V , OUT and BASE

DD

regulators. After a fault on the LTC4366, putting the part

in shutdown will clear the fault and allow operation to

resume. Clearing the fault during the 9-second cool-down

period will shorten the timeout for the LTC4366-2 (auto-

retry) version.

GATE: Gate Drive for External N-Channel MOSFET. Dur-

TIMER:TimerInput.Leavethispinopenfora1µsovervolt-

age regulation period before fault off. Connect a capacitor

between this pin and V_SSto set a 311ms/µF duration for

overvoltage regulation before the switch is turned off.

The LTC4366-2 version will restart after a nine second

cool-down period.

ing start-up an internal 7.5µA current source charges the

gate of the external N-channel MOSFET from the V pin.

DD

Once the OUT voltage is above V by 4.75V, the charge

SS

pump will finish charging the GATE to 12V above OUT.

During a fast overvoltage event, a 200mA pull-down cur-

rent source between GATE and OUT is activated, followed

by regulation of the GATE pin voltage by the overvoltage

regulation amplifier.

V :Start-Up Supply. Supplyinput for 7.5µA start-upcur-

DD

rentsourcethatchargesthegateoftheexternalN-channel

MOSFET. Also provides supply for timer and logic circuits

activewhentheexternalMOSFETisoff.Thispinisclamped

OUT: Charge Pump and Overvoltage Regulation Amplifier

SupplyVoltage.Supplyinputforfloatingcircuitrypowered

from the MOSFET source. Once the OUT voltage is 4.75V

at 12V above V . Do not bypass this pin with a capacitor.

SS

V : Device Return and Substrate. The capacitors on the

SS

(UVLO2)aboveV ,thechargepumpwillturnonanddraw

SS

TIMER and OUT pins should be returned to this pin.

power from this pin. When OUT exceeds 2.55V (UVLO1)

it is used as a power supply and reference input for over-

voltage regulation amplifier. This pin is clamped at 5.7V

and requires a 0.22µF or greater bypass to the V pin.

SS

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LTC4366

SIMPLIFIED DIAGRAM

Start

Run

Regulate

R

IN

+

1.23V

–

7.5µA

20µA

Z3

5.7V

Z3

5.7V

–

+

R

CP

FB1

Z1

12V

FB2

436612 SD

R

SS

R

SS

R

SS

FUNCTIONAL DIAGRAM

M1

V

OUT

IN

R

G

R

IN

C

G

Z4

12V

V

GATE

OUT

DD

7.5µA

D1

OUT

20µA

CHARGE

PUMP

f = 2MHz

Z1

12V

UVLO2

4.75V

LOGIC

SUPPLY

V

CC

UVLO1

2.55V

V

DD

V

CC

C1

SHUTDOWN

+

1.23V

–

COMPARATOR

+

1.5V

–

1.6µA

9µA

LOGIC

AND

TIMER

+

–

+

R

FB1

SD

FB

FB2

OVERVOLTAGE

AMPLIFIER

CC

TIMER

COMPARATOR

TIMER

OUT

+

–

Z2

6.2V

Z3

5.7V

+

C

T

2.8V

–

1.8µA

V

BASE

SS

436612 FD

R

SS

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LTC4366

OPERATION

The Simplified Diagram shows three states of operation:

the start, run and regulate mode. Previous surge stopper

parts are powered off the input supply, therefore the surge

voltageislimitedtothebreakdownvoltageoftheinputpins

of the part. As demonstrated in run and regulate modes,

the majority of this part is powered off the output, so the

MOSFET isolates the surge from the power pins of the

part. This allows surge voltages up to the breakdown of

the external MOSFET.

Once the OUT to V voltage exceeds the 2.55V UVLO1

SS

threshold, the overvoltage amplifier is enabled. Next, the

UVLO2thresholdof4.75Viscrossedandthechargepump

turns on. The charge pump charges the GATE pin with

20µA to its final value 12V above OUT (clamped by Z4).

This allows the capacitor between OUT and V to charge

SS

until clamped by Z3 to 5.7V. In this run mode the MOSFET

is configured as a low resistance pass transistor with little

voltage drop and power dissipation in the MOSFET.

In the start mode a 15µA trickle current flows through R ,

The powered up LTC4366 is now ready to protect the load

against an overvoltage transient. The overvoltage regula-

tion amplifier monitors the load voltage between OUT and

ground by sensing the voltage on the FB pin with respect

IN

half is used to charge the gate with the other half used as

biascurrent.AstheGATEpincharges,theexternalMOSFET

brings up the OUT pin. This leads to the run mode where

the output is high enough to become a supply voltage for

the charge pump. The charge pump is then used to fully

charge the gate 12V above the source.

to the OUT pin (drop across R ). In an overvoltage

FB1

condition the OUT rises until the amplifier drives the M1

gate to regulate and limit the output voltage. This is the

regulate mode.

With the output voltage equal to the input voltage, it is

necessary to protect the load from an input supply over-

voltage. In the regulate mode, the overvoltage regulation

amplifier is referenced to the output through a 1.23V

reference. If the voltage drop across the upper feedback

Duringregulationtheexcessvoltageisdroppedacrossthe

MOSFET.TopreventoverheatingtheMOSFET,theLTC4366

limitstheovervoltageregulationtimeusingtheTIMERpin.

The TIMER pin is charged with 9µA until the pin exceeds

2.8V. At that point an overvoltage fault is set, the MOSFET

is turned off, and the part enters a cool-down period of

9 seconds. The logic and timer block are active during

cool down while the GATE pin is pulled to OUT.

resistor,R ,exceeds1.23Vtheregulationamplifierpulls

FB1

the gate down to regulate the R voltage back to 1.23V.

FB1

Therefore, the output voltage is clamped by setting the

proper ratio between R and R

.

FB1

FB2

Forexample,iftheoutputvoltageisregulatedat100Vthen

The latched-off version, LTC4366-1, will remain in fault

untiltheSDpinistoggledlowandthenhigh. Oncethefault

is cleared, the GATE is permitted to turn the MOSFET on

again.Theauto-retryversion,LTC4366-2,waits9seconds

then clears the fault and restarts.

the voltage drop across the R is 98.77V. If the Zener Z3

FB2

is 5.7V then the voltage drop across R is 94.3V. There-

SS

fore, when the output is at a high voltage, the majority of

the voltage is dropped across the two resistors R and

FB2

R . This demonstrates how the LTC4366 floats up with

SS

the supply. The adjustable 3-terminal regulators, such

as the LT^®1085 and LM117, are also based on this idea.

The Functional Diagram shows the actual circuits. An

external R resistor on the V pin powers up the 12V

IN

DD

shunt regulator which then powers up logic supply, V .

CC

After verifying that the shutdown input is not active, the

GATE pin is charged with a 7.5µA current from V . This

DD

is the start mode.

436612fe

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LTC4366

APPLICATIONS INFORMATION

The typical LTC4366 application is a protected system

that distributes power to loads safe from overvoltage

transients. External component selection is discussed in

the following sections.

voltage minus 5.7V is impressed on R . The R current

SS SS

is divided into three areas: the 5.7V shunt current, bias

current between OUT and V and finally the R current.

SS

IN

The 5.7V shunt current can be as high as 10mA which

greatly exceeds the typical OUT (160µA) bias current.

Dual Shunt Regulators

Turn-On Sequence

The LTC4366 uses two shunt regulators coupled with

the external voltage dropping resistors, R and R , to

The voltage between the V and V pins is shunt regu-

DD SS

SS

IN

generate internal supply rails at the V and OUT pins.

lated to 12V after ramping up the input supply. Next, the

DD

These shunt-regulated rails allow overvoltage protection

from unlimited high voltage transients irrespective of the

voltage rating of the LTC4366’s internal circuitry.

internally generated supply, V , produces a 30µs power-

CC

on-reset pulse which clears the fault latch and initializes

internallatches.Next,theshutdowncomparatordetermines

if the SD pin is externally pulled low, thereby requesting a

low bias current shutdown state. Otherwise the external

MOSFET, M1, is allowed to turn on.

At the beginning of start-up, during shutdown, or after an

overvoltage fault, the GATE pin is clamped to the OUT pin

thereby shutting off the MOSFET. This allows the V and

SS

OUT pins to be pulled to ground by output load and R .

Turningonthe7.5µAGATEpull-upcurrentsourcefromthe

SS

Under this condition the V pin is clamped with a 12V

V

pin begins what can be described as a“bootstrapped”

DD

shunt regulator to V . The full supply voltage minus 12V

method for powering up the MOSFET gate. Once the GATE

SS

is then impressed on the R resistor which sets the shunt

reaches the V pin voltage (minus a Schottky diode), the

IN

DD

current. The shunt current can be as high as 10mA which

7.5µA source loses voltage headroom and stops charging

theGATE(middleofwaveformsinFigure2.).Thebootstrap

method relies on charging C1 to a sufficient voltage after

GATE stops increasing. The voltage on C1 is then used

as a supply for a charge pump that charges the gate to

its final value 12V above OUT. C1 will discharge if the

charge pump current exceeds the C1 charging current.

If the voltage drops below 4.35V, the charge pump will

pause allowing C1 to recharge.

is several orders of magnitude higher than the typical 9µA

V

pin quiescent current.

DD

In normal operation the OUT voltage is equal to the input

supply.WithC1fullychargedI iszeroatthispoint.Under

C1

this condition the voltage between the OUT and V pins

SS

are clamped with a 5.7V shunt regulator. The input supply

M1

FQA62N25C

V

IN

OUT

28V

1.5A

(18V DC TO 250V DC)

(43V CLAMP)

C

G

R

G

10nF

V

10Ω

GATE

R

10V/DIV

C1

0.47µF

IN

324k

CHARGE

PUMP PAUSE

R

FB1

R1

V

GATE

LTC4366-2

OUT

FB

BASE

DD

12.4k

470k

R2

V

SD

OUT

10V/DIV

R

422k

100k

FB2

Q1

TIMER

V

SS

SD

MMBT3904

C1 RECHARGING

C

T

8.2nF

V

C1

436612 F01

CHARGE

PUMP STARTS

5V/DIV

R

SS

46.4k

C1 CHARGING

20ms/DIV

436612 TA01b

Figure 1. Typical Application

Figure 2. Turn-On Waveforms

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LTC4366

APPLICATIONS INFORMATION

Starting up with a supply voltage insufficient to charge

C1 with large load current may result in overheating the

MOSFET and subsequent damage. While the gate and

output are ramping the drop across the MOSFET is the

input supply minus the output. If the supply is lower than

necessarytochargeC1,thentheoutputfailstoramphigher

than the supply minus the threshold of the MOSFET. This

3V to 5V MOSFET drop with high load current will result in

power dissipation without any protection or timeout limit.

Depending on which version, the part will cool down and

self start (LTC4366-2), or remain latched off until the SD

pin activates a shutdown followed by a start-up command

(LTC4366-1).Thecool-downtimeistypicallynineseconds

which provides a very low pulsed power duty cycle.

Starting up with an input supply overvoltage and full

load current does increase the power dissipation in the

MOSFET well beyond the case for an overvoltage surge.

During the gate and output ramp up, the partial supply

voltage (at full current) is dropped across the MOSFET.

Afterstart-upthenormalovervoltagesurge(withtimeout)

occurs before the shutting off the MOSFET. The Design

Example section only considers the normal overvoltage

surge for safe operating area (SOA) calculations for the

MOSFET. Start-up into overvoltage will require additional

SOA considerations.

Overvoltage Fault

The LTC4366 prevents an overvoltage on the input supply

from reaching the load. Normally, the pass transistor is

fully on, powering the load with very little voltage drop. As

theinputvoltageincreasestheOUTvoltageincreasesuntil

it reaches the regulation point (V ). From that point any

REG

further voltage increase is dropped across the MOSFET.

Note the MOSFET is still on so the LTC4366 allows un-

interrupted operation during a short overvoltage event.

Shutdown

The LTC4366 has a low current (<20µA) shutdown state

that turns off the pass FET by tying the GATE and OUT pins

together with a switched resistor. In the normal operating

TheV pointisconfiguredwiththetwoFBresistors,R

REG

FB1

and R . The regulation amplifier compares the FB pin to

FB2

a threshold 1.23V below the OUT pin. During regulation

condition, the SD pin is pulled up to the V pin voltage

DD

the drop across R is 1.23V, while the remainder of the

with a 1.6µA current source. Tie the SD pin to V when

FB1

DD

V

voltage is dropped across R

.

the shutdown state is not used.

REG

FB2

Whentheoutputisattheregulationpointatimerisstarted

to prevent excessive power dissipation in the MOSFET.

Normally the TIMER pin is held low with a 1.8µA pull-

down current. During regulation the TIMER pin charges

with 9µA. If the regulation point is held long enough for

the TIMER pin to reach 2.8V then an overvoltage fault is

latched. The equation for setting the timer capacitor is:

Bringing the SD pin more than 1.5V below V pin volt-

DD

age for greater than the 700µs filter time activates the

shutdown state. This filter time prevents unwanted activa-

tion of shutdown during transients. The SD pin is diode

clamped 0.7V below V which requires current limiting

SS

(maximum 10mA) on the pull-down device. One way to

limit the current is to connect an external 470k resistor in

series with the open-collector pull-down device. Activat-

ing the external pull-down overcomes the internal 1.6µA

pull-up current source and allows the SD pin to cross the

shutdown threshold.

C = 3.2 • t nF /ms

[

]

T

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LTC4366

APPLICATIONS INFORMATION

Followinganovervoltagefault,puttingthepartinshutdown

will clear the fault, allowing operation to resume once the

LTC4366 leaves shutdown.

The full supply voltage minus 12V can appear across

IN

R

during the overvoltage cool-down period. Normally

the value for R is several times larger than R which

IN

SS

lowers the power and size requirements for this resistor.

Output Short

External PNP

A sudden short on the output can result in excessive cur-

rent into the LTC4366 GATE pin supplied from the gate

InsomecasesthepowerresistorforR maybephysically

SS

capacitor, C . The GATE pin is internally clamped to OUT

large. A large value R (with lower power and size) may

G

SS

with a 10V to 12V clamp. If the OUT pin is pulled low

be used in conjunction with a PNP as shown in Figure 4.

while the GATE pin is held up with C , then the clamp will

In addition to the 0.8µA sourced from the BASE pin, the

G

be damaged trying to discharge C when clamp voltage

base current from the PNP must flow through R which

SS

G

is exceeded. One solution is to add a 1k R resistor in

will limit the maximum R value. In some cases the

S

SS

series with C with a bypass diode as shown in Figure 3.

minimum PNP Beta is as low as 35. The base current

G

The diode allows the capacitor to function as a bypass for

energy coming from the MOSFET drain to gate capacitor

during an supply overvoltage.

becomes 10µA when the V current is 350µA. One can

SS

see this allows a 35 (Beta) times larger R than the ap-

SS

plication without the PNP.

M1

R

G

LTC4366

D

BYPASS

BASE

R

V

SS

R

S

LTC4366

1k

GATE

OUT

C

G

10V TO

12V

SS

436612 F04

436612 F03

Figure 4. External PNP Option

Figure 3. Output Short Protection

Minimum Supply Start-Up

Resistor Power Ratings

When designing for the minimum supply condition, it is

important that R and R are chosen to provide enough

The proper rating for the R resistor in Figure 1 must be

SS

considered. During an overvoltage event the OUT pin is

SS

IN

current to sufficiently charge C1 to 4.75V. The parameters

that determine the minimum supply voltage include: C1

voltage,MOSFETthresholdvoltage,aseriesSchottkydiode

voltage drop, resistance of R and R , current in the V

at regulation voltage (V ), so the voltage across R is

REG

SS

V

REG

minus5.7V.Asmallminimumsupplyvoltagereduces

the value of R . Therefore, large differences between

SS

minimum supply voltage and the regulation voltage may

SS

IN

DD

require a large power resistor for R .

SS

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LTC4366

APPLICATIONS INFORMATION

pin, and finally the current from the V pin (see Figure 5).

The last V

SS

equation sets the maximum value for

IN(MIN)

SS

R . After choosing R the maximum value for R (for

SS

IN

V

= (I

• R ) + V + V + V + (I

• R )

IN(MIN)

VDD

IN

D

TH

C1

VSS SS

that particular R ) is calculated from the first V

equation:

SS

IN(MIN)

Using the Electrical Characteristics table for above

parameters:

V_IN(MIN)– 5.7V

R_SS(MAX)

=

V

= V

= 4.75V (UVLO2 threshold)

C1

UVLO2

160µA

I

= I

= 9µA (I

VDD

start-up, gate high)

w/regulation amp)

VDD

VSS

VDD(STHI)

VSS(AMP)

V

_IN(MIN)– 4.75V – 0.58V – V_TH– 45µA •R

(

)

SS

R_IN(MAX)

=

= I

= 45µA (I

VSS

9µA

V = 0.58V

D

These two equations maximize the values of R and

IN

SS

V

=(9µA•R )+0.58V+V +4.75V+(45µA• R )

IN TH SS

IN(MIN)

R

(reducing power dissipation) while still providing

the necessary V voltage to turn the charge pump on.

C1

When the MOSFET gate is fully enhanced, the OUT pin

voltage is equal to the supply voltage. This places another

constraint on the minimum supply voltage because the

charge pump increases the V current to 160µA. The C1

voltage is assumed to be clamped at 5.7V. These values

are specified as V

in the table of Electrical Characteristics:

Increasing the supply voltage beyond the minimum sup-

ply voltage increases the current and power in R while

SS

reducing the time required to charge C1. Conditions that

SS

may require an even smaller R

will be discussed

SS(MAX)

in the Maximum Supply Start-Up section.

and I

(charge pump on)

Z(OUT)

VSS(CP)

Maximum Supply Start-Up

V

= V

+ (I

• R )

IN(MIN)

Z(OUT)

VSS(CP) SS

The maximum overvoltage supply may also exist during

start-up. The overvoltage protection circuitry has to wake

up before high voltage is passed to the load. Dynamically

the GATE is ramping up while C1 is charging. Capacitor

C1 must charge to the 2.55V UVLO1 threshold to turn on

the regulation amplifier and reference before the OUT pin

or

V

= 5.7V + (160µA • R )

IN(MIN)

SS

V

I

IN

voltage exceeds the overvoltage regulation point, V

.

RIN

R

REG

IN

7.5µA

D1

These conditions may reduce the value of R below the

V

DD

SS

GATE

G

M1

V

maximum value dictated by the minimum supply start-up

C

discussed above.

OUT

C1

OUT

When current in R exceeds the current sourced from

SS

R

LOAD

the V pin (essentially I ), the capacitor C1 begins to

SS

RIN

Z1

12V

Z3

5.7V

LOGIC

TIMER

CIRCUITS

charge. The voltage at the V pin when I = I

labeled V

voltage divider between R and R after the Zener clamp

voltage from V to V is subtracted from the supply.

is now

+

–

SS

RIN RSS

V

C1

. The V pin voltage is the center of a

SS(MATCH)

SS

I

9µA

I

C1

SHUNT1

SHUNT2

BIAS

IN

SS

V

SS

DD

SS

I

R

R_SS

R_SS+R_IN

RSS

SS

V_SS(MATCH)

=

• V_IN(MAX)– V_Z(VDD)

(

)

436612 F05

Figure 5. Simplified Block Diagram

As V increases the V

voltage increases. If the

IN

SS(MATCH)

match voltage exceeds the overvoltage regulation point

(V ), then load is unprotected. This is true because

REG

C1 will still need to charge to 2.55V while V already

SS

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LTC4366

APPLICATIONS INFORMATION

has exceeded V . Since the OUT pin voltage is at least

GATE Capacitor, C

G

REG

2.55V larger than V it exceeds the specified maximum.

SS

The gate capacitor is used for three functions. First, C

G

Choosing the match point (with supply at the maximum)

absorbs charge from the gate-to-drain capacitance of

the MOSFET during overvoltage transients. Second, the

capacitor also acts as a compensation element for the

overvoltage regulation amplifier. The minimum value for

sufficiently below V

(by at least 2.55V), allows C1 to

REG

charge up in time to protect the load from overvoltage.

In reality having V pin voltage 7V below V

provides

SS

REG

required margin for charging C1.

C to guarantee stability is 2nF. Finally, C sets the slew

G

V

= V

– 7V

rate of the GATE and OUT pins. The voltage at the GATE pin

SS(MATCH)(MAX)

REG

rises at a slope equal to 20µA/C . This slope determines

G

Increasing R increases the match point, so determin-

SS

the charging current into the load capacitor.

ing the maximum R value while still protecting from

SS

overvoltage is useful. Using I = I

:

C_LOAD

C_G

RIN

RSS

I

=

•I_G

INRUSH

V_RSS

V_RIN

R_SS=R_IN•

The voltage rating for C must be greater than the regula-

G

tion voltage (V ).

REG

Using:

V

= V

– 7V

REG

MOSFET Selection

RSS

RIN

SS(MATCH)(MAX)

= V – V

– V

RSS

The LTC4366 drives an N-channel MOSFET to conduct

the load current. The important features of the MOSFET

IN

Z(VDD)

Substituting:

are on-resistance, R

, the maximum drain-source

DS(ON)

R • V

– 7V

(

)

voltage, V , the threshold voltage, and the SOA.

(BR)DSS

IN

REG

R_SS(MAX)

=

V

– 12V – V

– 7V

(

)

IN(MAX)

REG

The maximum allowable drain-source voltage must be

higher than the supply voltage. If the output is shorted

to ground or during an overvoltage event, the full supply

voltage will appear across the MOSFET.

R • V

– 7V

(

)

IN

REG

R_SS(MAX)

V

_IN(MAX)– 5V – V_REG

The threshold voltage of the MOSFET is used in the mini-

mum supply start-up calculation. For applications with

supplies less than 12V, a logic-level MOSFET is required.

Above 12V a standard threshold N-channel MOSFET is

sufficient.

If we guarantee that R < R

then the following

SS

SS(MAX)

is true:

V

< V

SS(MATCH)(MAX)

SS(MATCH)

C1 bypasses the charge pump, and requires at least a

0.22µF. The size of C1 needs limits also. The gate capaci-

The SOA of the MOSFET must encompass all fault condi-

tions. In normal operation the pass transistor is fully on,

dissipatingverylittlepower.Butduringovervoltagefaults,

the GATE pin is servoed to regulate the output voltage

through the MOSFET. Large current and high voltage drop

across the MOSFET can coexist in these cases. The SOA

curves of the MOSFET must be considered carefully along

with the selection of the fault timer capacitor.

tor (C ) dictates the maximum output capacitor C1

G

(MAX)

that will charge to the 2.55V UVLO1 threshold (V

)

UVLO1

beforetheOUTvoltageexceedstheovervoltagethreshold.

–C • R +R_IN– V_SS(MATCH)

V

REG

(

)

(

)

G

SS

C1

=

(MAX )









2 • V_UVLO1

V_REG– V

I_G•R_SS•R •In 1–

IN





_SS(MATCH)



In most cases:

C1 = 10 • C to 100 • C

G

(MAX)

G

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LTC4366

APPLICATIONS INFORMATION

Layout Considerations

DESIGN EXAMPLE

Overview

Due to the high impedances on the SD, V , and GATE

DD

pins, these pins are susceptible to leakages to ground.

For example, a leakage to ground on SD will activate the

shutdown state if greater than 1.6µA. Providing adequate

spacingawayfromgroundedtracesandaddingconformal

coating on exposed pins lowers the risk that leakage cur-

rent will interrupt system operation.

The design process starts with minimum input voltage

start-up equations to calculate values for R and R .

These values need further refinement to meet two other

conditions: the maximum input voltage start-up condi-

tions and proper current for the charging of C1. The the

remaining element values are calculated based on the

input parameters.

SS

IN

It is important to put the bypass capacitor, C1, as close as

possible to the OUT and V pins. Place the 10Ω resistor

SS

Following are the input parameters for this example:

as close as possible to the MOSFET gate pin. This will

limit the parasitic trace capacitance that leads to MOSFET

self-oscillation.

V

= 18V, V

= 43V, V

= 250V, I

IN(MAX) LOAD

SUPPLY(MIN)

= 1.5A at start-up, I

REG

LOAD

= 3A after start-up, V = 5V

TH

The FB pin is sensitive to parasitic capacitance when the

regulation loop is closed. One result from this capacitive

loading is output oscillations during overvoltage regula-

tion. It is suggested that the resistors R and R be

ImportantElectricalCharacteristicstableparametersused

in this example are summarized in Table 1.

Step 1: Maximum R

FB1

FB2

SS

placed close to the pin and that the FB trace itself be

In this design example (Figure 6.) the component sizing

first considers the start-up phase after the charge pump

minimized in size.

is active. The goal is to maximize the resistance of R

SS

which still allows operation when the input voltage is at

the minimum value.

M1

FQA62N25C

V

OUT

IN

1.5A

28V

(43V CLAMP)

(18V DC TO 250V DC)

C

G

R

G

10nF

10Ω

C1

0.47µF

R

IN

324k

R

FB1

R1

V

GATE

LTC4366-2

OUT

FB

BASE

DD

12.4k

470k

R2

SD

R

422k

100k

FB2

Q1

TIMER

V

SS

SD

MMBT3904

C

T

8.2nF

436612 F06

R

SS

46.4k

Figure 6. Overvoltage Protected 28V, 1.5A Supply

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LTC4366

APPLICATIONS INFORMATION

Table 1. Electrical Parameters Used in Design Example

SYMBOL

PARAMETER

CONDITIONS

I = 1mA, BASE = 0V

Rising

TYP

MAX

6.0V

V

OUT Shunt Reg. Voltage

OUT Undervoltage Lockout 2

5.7V

4.75V

–160µA

–45µA

9µA

Z(OUT)

4.9V

UVLO2

I

V

Pin Current – Charge Pump On

Pin Current – Regulation Amplifier On

Pin Current – Start-Up, Gate High

–230µA

–72µA

13µA

VSS(CP)

VSS(AMP)

VDD(STHI)

GATE(ST)

SS

DD

GATE Open, V = 7V, OUT = 0V

DD

GATE Pin Current – Start-Up

OUT Undervoltage Lockout 1

GATE = OUT = 0V

Rising

–7.5µA

2.55V

–11µA

2.75V

V

UVLO1

After the charge pump is active the V current increases

Step 3: Find R

SS(MAX)

SS

to 160µA (worst-case 230µA, see Table 1) current while

thefinalvalueOUTvoltageisequaltotheminimumsupply

voltage. The C1 voltage is clamped at 5.7V (worst-case

6.0V):

In some cases this value for R is too large to charge C1

SS

and power the overvoltage amplifier before the maximum

input voltage passes to the output. The voltage at the V

SS

).

pinwhenI =I

iscalledthematchpoint(V

RIN RSS

SS(MATCH)

V_IN(MIN)– V_Z(OUT)

Choosing the match point (with supply at the maximum)

sufficientlybelowV (byatleast7V),allowsC1tocharge

R_SS(MAX)

=

REG

I_VSS(CP)

up in time to protect the load from overvoltage:

18V – 6V

230µA

R • V

_IN(MAX)−5V − V_REG

– 7V

(

)

R_SS(MAX)

=

= 52.3k

IN

REG

R_SS(MAX)

=

V

Step 2: Determine R

IN

287k • 43V – 7V

(

)

= 51.1k

R_SS(MAX)

ThevalueforresistorR iscalculatedusingthecalculated

250V – 5V – 43V

IN

R

value. R is chosen to provide enough headroom to

SS

IN

In this case the R value of 52.3k calculated in Step 1

SS

sufficiently charge C1 to 4.9V the maximum undervoltage

is too large.

lockout2threshold(V

)whichstartsthechargepump.

UVLO2

The parameters that determine R include: minimum

IN

Step 4: Iterate Smaller R

SS

supply voltage, the final C1 voltage, MOSFET threshold

voltage, R , 72µA maximum V pin current (regulation

Using 51.1k (R

) as the next guess for R , we can

SS(MAX) SS

SS

now calculate R and R

:

amplifier on, I

), and finally the 13µA maximum

VSS(AMP)

IN

SS(MAX)

start-up current in the V pin (I

):

DD

VDD(STHI)

18V – 4.9V −0.58V −5V − 72µA • 51.1k

(

)

R_IN=

V

_IN(MIN)– V_UVLO2− V_D− V_TH− I_SS(AMP)•R_SS

(

)

13µA

R_IN(MAX)

=

I_VDD(STHI)

R_IN= 294k

R_SS(MAX)

18V −4.9V −0.58V −5V − 72µA • 52.3k

(

)

R_IN(MAX)

294k • 43V – 7V

(

)

= 52.3k

13µA

250V – 5V −43V

R

_IN(MAX)= 287k

In this case the R value of 51.1k is less than R

SS

SS(MAX)

and the solution is acceptable.

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LTC4366

APPLICATIONS INFORMATION

threshold, 2.75V:

–10nF • 51.6k +291k 43V – 35.8V

Step 5: Determine C , C1

, Check R

G

(MAX)

SS

The gate capacitor (C ) determines the gate slew rate and

(

)(

)

G

C1

=

(MAX )

therefore the slew rate of the OUT pin since the output











2 • 2.75V

43V −35.8V

11µA • 51.6k • 291k •In 1–

voltage follows the GATE pin. The voltage at the GATE pin



riseswithaslopeequalto7.5µA/C atstartupand20µA/C

G

or

when the charge pump is on. Limiting this slope will limit

the inrush current charging the load capacitance where:

C1

= 0.1µF

(MAX)

C_LOAD

C_G

This limit on C1 does not meetthe shunt regulatorstability

requirements (C1 > 0.22µF).

I

=

•I_G

INRUSH

If we desire a larger value of C1 then a lower size of R

SS

In this example we choose C to be 10nF which limits the

G

is required. A lower value for R is 48.7k, which calls

SS

inrush current to be 660mA for a 330µF C

.

LOAD

out an R value of 309k and a max C1 value of 0.27µF.

IN

C1 is used as a bypass capacitor for the circuitry between

The next lower value of 46.4k with R of 324k, results

VIN

the OUT and V pins. C1 also stabilizes the shunt regula-

SS

in the worst-case maximum C1 value of 0.49µF. A larger

C1 increases circuit immunity to transients in exchange

for slightly higher current. Therefore, a selection of com-

ponents that allow a 0.47µF C1 is recommended.

tor that clamps the voltage between these pins where the

minimum value for regulator stability is 0.22µF. An even

greater 0.47µF value is desired for C1 to protect the OUT

to V circuitry from transients on the OUT pin.

SS

The lowered R value of 46.4k now considers the toler-

SS

The startup into an overvoltage creates an upper bound-

ances of all the components that set the C1 ramp rate to

guarantee it charges to the 2.55V UVLO1 threshold before

the OUT voltage exceeds the overvoltage threshold.

ary on the value of C1. The value of C , R and R

G

SS

VIN

determines a maximum C1 that will reach UVLO1 and

power the regulation amplifier before the OUT pin voltage

exceeds the overvoltage threshold. If our desired value

for C1 (0.47µF) exceeds the maximum allowed C1 then

Step 6: Determine R , R

FB1 FB2

The feedback resistors, R

and R , are chosen to

FB2

FB1

a smaller R must be used to iterate a new solution for

SS

regulatetheovervoltageat43V.Onewaytoquicklychoose

C1

. We start with calculating V

:

(MAX)

SS(MATCH)

these resistors is to assign 100µA or 1.2V across a 12.4k

R_SS

R_SS+R_VIN

R

. R would need to drop the remainder of the regu-

FB1 FB2

V_SS(MATCH)

=

• V – V

(

IN Z(VDD)

)

lated voltage. Dividing this remainder by 100µA yields the

value for R . In this example R drops 41.8V. When

FB2

If we use the worst-case 1% maximum value for R

SS

divided by 100µA it results in a 422k value.

(51.6k) and minimum value for R (291k):

VIN

Step 7: Determine C , R1

T

V

= 35.8V

SS(MATCH)

DuringanovervoltagethepowerdissipatedintheMOSFET

is dependent on the load current and the difference be-

tween the supply and regulated voltages. It is necessary

to keep the device power in a safe range. In the power

MOSFET data sheets there is a maximum safe operating

curve displaying current versus drain to source voltage

for a fixed pulsed time. Other pulsed time data from DC

to 10µs are plotted on the one graph. The different lines

of operation generally follow a constant power squared

–C • R +R

V_REG– V_SS(MATCH)

(

)

(

)

IN

G

SS

C1

=

(MAX)









2 • V_UVLO1

V_REG– V

I_G•R_SS•R •In 1–



IN



_SS(MATCH)



Usetheworst-casemaximumgatecurrentof11µAinstead

of the typical 7.5µA and the worst-case minimum UVLO1

436612fe

18

For more information www.linear.com/LTC4366

LTC4366

APPLICATIONS INFORMATION

2

times time or P t. Knowing the power we then adjust

In order to limit the SD pin current (10mA max) a collector

resistor, R1, in series with Q1 is required. The maximum

value for this resistor is around 5M. This requirement oc-

curs when the pull-down is required to sink 1.6µA from

2

the time using the timer capacitor to limit the P t during

overvoltage. In this example the MOSFET data sheet has

2

a 6400W s P t for a 10ms single pulse.

SD and V is clamped at 12V. High valued resistors are

DD

In this application 250V minus 43V is applied across the

MOSFETat3A. Ifthepowerisappliedforlessthan16.5ms

susceptibletoleakagecurrentssowechosea470kresistor

forR1.ResistorR2providesESDprotectionforQ1’sbase.

2

then MOSFET P t limit is not exceeded:

The gate resistor R limits the parasitic trace capacitance

G

P = (250V – 43V) • 3A = 621W

on M1’s gate node that could lead to parasitic MOSFET

2

P t = (621W) • 16.5ms = 6363W s

self-oscillation. The recommended value for R is 10Ω.

G

Prior to the moment when the output is regulated at 43V,

the output is ramping from 28V to 43V. This ramp time is

based on the 20µA gate current charging the 10nF capaci-

tor. Using the equation for ramp time:

High Voltage Application

In Figure 7 the circuit accepts 110V AC (rectified to 160V)

and protects the load from accidental connection to 220V

AC by limiting the output to less than 200V. The circuit

C_G• ∆V 10nF •15V

∆t =

=

= 7.5ms

has a 100V to 800V V operating range where the FET

IN

I_G

20µA

breakdown voltage limits the maximum input voltage. The

C1issetto0.47µFtoprovideabypassforthechargepump

that is large enough to provide good noise immunity from

outside voltage transients. The timer capacitor is sized to

To be safe we set the overvoltage time to 10ms. We set the

regulation time to be 2.5ms (the remainder of the 10ms

overvoltage time minus the ramp time). In this example

it is assumed the 250V overvoltage is a constant DC volt-

age for 10ms. This duration exceeds Mil-Std-1275 which

specifies a 70µs surge to 250V that decays in 1.6ms. Us-

ing the following equation (based on charging with 9µA)

2

give a 1ms overvoltage regulation time that keeps the P t

2

below the 640W s specified for this MOSFET.

to set the C :

T

∆t

∆V

2.5ms

2.8V

C_T=I_T•

= 9µA •

≈ 8.2nF

M1

IXTH12N100L

V

OUT

IN

160V (RECTIFIED 110V AC)

100V TO 800V

0.5A

(200V CLAMP)

C

G

R

G

2nF

10Ω

R

IN

C1

0.47µF

4.64M

R

FB1

R1

V

GATE

LTC4366-2

OUT

FB

BASE

DD

12.4k

470k

R2

SD

R

2M

100k

FB2

Q1

TIMER

V

SS

SD

BF722

C

T

3.3nF

436612 F07

R

SS

412k

DANGER! Lethal Voltages Present

Figure 7. Rectified 110V AC Supply Protected from 220V AC

436612fe

19

For more information www.linear.com/LTC4366

LTC4366

APPLICATIONS INFORMATION

28V Vehicle Application

During negative input voltages Q2 turns on when current

from R6 (via D4) develops a forward diode drop on R5.

Q2 then holds the gate of M2 at the input voltage which

turns M2 off. This blocks negative input voltages from

reaching M1 and the load. D2 prevents damage to the

LTC4366’s GATE pin by clamping it at ground when the

M2’s gate is negative.

The circuit in Figure 8 adds reverse voltage protection to

the standard 28V application shown in Figure 6. There are

three modes to this circuit: pass FET On when the input

is 18V to 41V, clamping the output to 43V when more

than 43V appears at the input and finally reverse voltage

protection when up to –250V DC is present at the input.

The reverse voltage protection consists of the circuitry

inside the dotted box in Figure 8. When a positive voltage

is first applied to the input, D3 and the forward biased

base-collector junction of Q2 allow the gate of M2 to

follow the input voltage minus a two diode drop. During

this condition the body diode of M2 is used to transmit

power to the LTC4366. Once the LTC4366 is powered up

it fully enhances the gate of M1 and M2 (via D1). The M1

and M2 pass FETs then provide a low impedance path to

the load. In an overvoltage condition, D1 blocks excessive

positivevoltagefromtheinputsupplypassingtotheGATE

pin of the LTC4366. D4 eliminates current flow through

R6 when the input is positive while D3 prevents emitter

base breakdown of Q2 when the input is powering up.

Low Voltage Application

The circuit on the last page (Surge Protected Automotive

Supply) starts up with minimum input voltage of 9V. In

order to successfully start up at 9V and clamp the output

voltage at 18V for input voltages up to 100V the value of

R

has to be small (1.91k). The FET used in this case has

SS

a3Vthresholdtoeasethestart-uprequirements.Thetimer

capacitor is sized to give a 2.5ms overvoltage regulation

time that keeps the P t below the 420W s specified for

this MOSFET.

2

REVERSE VOLTAGE

PROTECTION

M2

M1

V

OUT

FDB33N25

FQA62N25C

IN

18V TO 41V

( 250V DC)

1.5A

(43V CLAMP)

Q2

MMBT3904

C

G

R

G

10nF

10Ω

D1

R

D3

IN

R5

470k

R4

270k

C1

0.47µF

BAV3004W

324k

BAV3004W

D4

D2

BAV3004W

R

FB1

R1

R6

270k

V

GATE

LTC4366-2

OUT

FB

BASE

DD

12.4k

470k

SD

TIMER

R

422k

FB2

Q1

MMBT3904

V

SS

SD

R2

100k

C

T

8.2nF

436612 F08

R

SS

46.4k

Figure 8. 28V Vehicle Application with Reverse Voltage Protection

436612fe

20

For more information www.linear.com/LTC4366

LTC4366

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

TS8 Package

8-Lead Plastic TSOT-23

(Reference LTC DWG # 05-08-1637 Rev A)

2.90 BSC

(NOTE 4)

0.40

MAX

0.65

REF

1.22 REF

1.4 MIN

1.50 – 1.75

(NOTE 4)

2.80 BSC

3.85 MAX 2.62 REF

PIN ONE ID

RECOMMENDED SOLDER PAD LAYOUT

PER IPC CALCULATOR

0.22 – 0.36

8 PLCS (NOTE 3)

0.65 BSC

0.80 – 0.90

0.20 BSC

DATUM ‘A’

0.01 – 0.10

1.00 MAX

0.30 – 0.50 REF

1.95 BSC

TS8 TSOT-23 0710 REV A

0.09 – 0.20

(NOTE 3)

NOTE:

1. DIMENSIONS ARE IN MILLIMETERS

2. DRAWING NOT TO SCALE

3. DIMENSIONS ARE INCLUSIVE OF PLATING

4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR

5. MOLD FLASH SHALL NOT EXCEED 0.254mm

6. JEDEC PACKAGE REFERENCE IS MO-193

436612fe

21

For more information www.linear.com/LTC4366

LTC4366

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

DDB Package

8-Lead Plastic DFN (3mm × 2mm)

(Reference LTC DWG # 05-08-ꢀ702 Rev B)

0.6ꢀ 0.05

(2 SIDES)

0.70 0.05

2.55 0.05

ꢀ.ꢀ5 0.05

PACKAGE

OUTLINE

0.25 0.05

0.50 BSC

2.20 0.05

(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

R = 0.ꢀꢀ5

0.40 0.ꢀ0

3.00 0.ꢀ0

(2 SIDES)

TYP

5

R = 0.05

TYP

8

2.00 0.ꢀ0

(2 SIDES)

PIN ꢀ BAR

TOP MARK

PIN ꢀ

R = 0.20 OR

0.25 × 45°

(SEE NOTE 6)

0.56 0.05

(2 SIDES)

CHAMFER

4

ꢀ

(DDB8) DFN 0905 REV B

0.25 0.05

0.75 0.05

0.200 REF

0.50 BSC

2.ꢀ5 0.05

(2 SIDES)

0 – 0.05

BOTTOM VIEW—EXPOSED PAD

NOTE:

ꢀ. DRAWING CONFORMS TO VERSION (WECD-ꢀ) IN JEDEC PACKAGE OUTLINE M0-229

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.ꢀ5mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION ON THE TOP AND BOTTOM OF PACKAGE

436612fe

22

For more information www.linear.com/LTC4366

LTC4366

REVISION HISTORY

REV

DATE

DESCRIPTION

PAGE NUMBER

A

1/12

Added Patents Pending statement

1

Revised Figure 4 in Applications Information section

Removed reference to overcurrent faults under MOSFET Selection

Fixed orientation of M2 in Figure 8

11

B

C

2/12

8/12

13

18

Updated Shutdown current from <20µA to <14µA

Changed MOSFET part number and Gate Capacitor value used in the Typical Application

Added MP-grade order information and specifications

Added negative sign to graphs G12 x-axis and G18, G21 y-axis

Changed MOSFET part number in Figure 1 and Figure 6

1

2, 3, 4, 5

6, 7

11, 16

Added section GATE Capacitor, C

15

G

Changed I

current from 5A to 3A in Design Example

16

LOAD

Updated C1

values in Step 5 calculations to 0.27µF and worst case 0.49µF

18

(MAX)

Updated calculated values in Step 7, added supporting text

19

Changed MOSFET part number and GATE capacitor used in Figure 7

Simplified Diagram: Corrected amplifier’s input polarity in Regulate Diagram

Functional Diagram: Added switch in series with TIMER pull-down current

19

D

E

8/13

8/15

9

Clarified “Ambient” on Operating Temperature Range; raised T

TIMER Pin Function: Changed 278ms/µF to 311ms/µF

to 150°C

2

8

JMAX

Figures 1, 6, 8: Changed C to 8.2nF from 10nF

11, 16, 20

12, 19

T

In C equation, changed constant to 3.2 from 3.5; updated C calculation

T

436612fe

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

23

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

For more information www.linear.com/LTC4366

LTC4366

TYPICAL APPLICATION

Surge Protected Automotive 12V Supply

M1

HUF76639S3S

V

IN

OUT

12V

4A

(9V TO 100V)

(18V CLAMP)

C

G

R

G

2nF

10Ω

R

IN

C1

0.47µF

29.4k

R

FB1

R1

V

GATE

LTC4366-2

OUT

FB

BASE

DD

12.4k

470k

SD

R2

100k

R

169k

FB2

Q1

TIMER

V

SS

SD

MMBT3904

C

T

3.3nF

436612 TA02

R

SS

1.91k

RELATED PARTS

PART NUMBER

LTC1696

DESCRIPTION

COMMENTS

Overvoltage Protection Controller

ThinSOT™ Package, 2.7V to 28V

LTC2909

Triple/Dual Inputs UV/OV Negative Monitor

Single/Dual UV/OV Voltage Monitor

Quad UV/OV Monitor

Pin Selectable Input Polarity Allows Negative and OV Monitoring

Ads UV and OV Trip Values, 1.5% Threshold Accuracy

For Positive and Negative Supplies

LTC2912/LTC2913

LTC2914

LTC3827/LTC3827-1 Low I , Dual, Synchronous Controller

4V ≤ V ≤ 36V, 0.8V ≤ V

≤ 10V, 80µA Quiescent Current

Q

IN

OUT

LTC3835/LTC3835-1 Low I , Synchronous Step-Down Controller

Single Channel LTC3827/LTC3827-1

4V ≤ V ≤ 60V, 1.23V ≤ V ≤ 36V, 120µA Quiescent Current

Q

LT3845

Low I , Synchronous Step-Down Controller

Q

IN

OUT

LTC3850

Dual, 550kHz, 2-Phase Synchronous Step-Down Dual 180° Phased Controllers, V 4V to 24V, 97% Duty Cycle, 4mm × 4mm

IN

Controller

QFN-28, SSOP-28 Packages

LTC3890

LT4256

Low I , Dual 2-Phase, Synchronous Step-Down 4V ≤ V ≤ 60V, 0.8V ≤ V

≤ 24V, 50µA Quiescent Current

Q

IN

OUT

Controller

Positive 48V Hot Swap Controller with

Open-Circuit Detect

Foldback Current Limiting, Open-Circuit and Overcurrent Fault Output, Up to 80V

Supply

LTC4260

Positive High Voltage Hot Swap Controller with

Wide Operating Range 8.5V to 80V

2

8-Bit ADC and I C

LTC4352

LTC4354

LTC4355

LT4363

Ideal MOSFET ORing Diode

External N-Channel MOSFETs Replace ORing Diodes, 0V to 18V

Controls Two N-Channel MOSFETs, 1.2µs Turn-Off, –80V Operation

Controls Two N-Channel MOSFETs, 0.4µs Turn-Off, 80V Operation

100V Overvoltage and Overcurrent Protection, Latch-Off and Auto-Retry Options

2.5V to 34V Operation, Protects 60V to –40V

Negative Voltage Diode-OR Controller

Positive Voltage Diode-OR Controller

High Voltage Surge Stopper

LTC4365

Window Passer – OV, UV and Reverse Supply

Protection Controller

436612fe

LT 0815 REV E • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

24

For more information www.linear.com/LTC4366

●

 LINEAR TECHNOLOGY CORPORATION 2011

(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC4366


型号：	LTC4366ITS8-2#TRMPBF
厂家：	Linear
描述：	LTC4366 - High Voltage Surge Stopper; Package: SOT; Pins: 8; Temperature Range: -40°C to 85°C 光电二极管
文件：	总24页 (文件大小：287K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC4366ITS8-2#TRMPBF [Linear]

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