LTC4365HTS8#TRMPBF [Linear]
LTC4365 - Overvoltage, Undervoltage and Reverse Supply Protection Controller; Package: SOT; Pins: 8; Temperature Range: -40°C to 125°C;
| 型号： | LTC4365HTS8#TRMPBF |
| 厂家： | 
Linear |
| 描述： | LTC4365 - Overvoltage, Undervoltage and Reverse Supply Protection Controller; Package: SOT; Pins: 8; Temperature Range: -40°C to 125°C 光电二极管 |
| 文件： | 总20页 (文件大小：1045K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC4365
Overvoltage,
Undervoltage and Reverse
Supply Protection Controller
DESCRIPTION
FEATURES
The LTC®4365 protects applications where power supply
input voltages may be too high, too low or even negative.
It does this by controlling the gate voltages of a pair of
external N-channel MOSFETs to ensure that the output
stays within a safe operating range.The LTC4365 can
withstand voltages between –40V and 60V and has an
operating range of 2.5V to 34V, while consuming only
125µA in normal operation.
n
Wide Operating Voltage Range: 2.5V to 34V
n
Overvoltage Protection to 60V
n
Reverse Supply Protection to –40V
n
LTC4365: Blocks 50Hz and 60Hz AC Power
n
LTC4365-1: Fast (1ms) Recovery from Fault
n
No Input Capacitor or TVS Required for Most
Applications
n
Adjustable Undervoltage and Overvoltage
Protection Range
Two comparator inputs allow configuration of the over-
voltage (OV) and undervoltage (UV) set points using an
externalresistivedivider.Ashutdownpinprovidesexternal
control for enabling and disabling the MOSFETs as well
as placing the device in a low current shutdown state. A
fault output provides status of the gate pin pulling low. A
fault is indicated when the part is in shutdown or the input
voltage is outside the UV and OV set points.
n
Charge Pump Enhances External N-Channel MOSFET
n
Low Operating Current: 125µA
Low Shutdown Current: 10µA
Compact 8-Lead, 3mm × 2mm DFN and
TSOT-23 (ThinSOT™) Packages
n
n
n
AEC-Q100 Qualified for Automotive Applications
APPLICATIONS
The LTC4365 has a 36ms turn-on delay that debounces
live connections and blocks 50Hz to 60Hz AC power. For
fast recovery after faults, the LTC4365-1 has a reduced
1ms turn-on delay.
n
Portable Instrumentation
n
Industrial Automation
n
Laptops
n
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. patents, including XXXXX, XXXXX.
Automotive Surge Protection
TYPICAL APPLICATION
12V Automotive Application
Load Protected from Reverse and Overvoltage at VIN
ꢓꢔꢓBꢉꢋꢕꢂ
ꢀ
ꢀ
ꢁꢂ
ꢄꢃꢌ
ꢑꢃ ꢒ ꢌꢃ
ꢓꢃ ꢒ ꢇꢔꢃ
ꢆꢒꢀ
ꢊꢍ
ꢃ
ꢉꢅ
ꢁꢂꢃ
ꢐꢍꢌꢑ
ꢃꢎꢕꢉꢆ
ꢀ
ꢀ
ꢄꢃꢌ
ꢁꢂ
ꢖꢉꢅꢆꢓꢖ
ꢖꢌꢗꢉꢊꢋꢈ
ꢃ
ꢓꢑꢍ
ꢈꢆꢎꢘ
ꢄꢅꢆ
ꢃ
ꢓꢑꢍ
SHDN
ꢒꢙꢉꢎꢘ
ꢇꢂꢃꢈꢆꢉꢃ
ꢀꢁꢂꢃ
ꢃꢀ
FAULT
ꢃ
ꢉꢅ
ꢒꢆꢈꢘ
ꢄꢀ
ꢊꢁꢋꢌ ꢍꢎꢂꢇꢏ
ꢄꢀ ꢅ ꢆꢇꢀ
ꢃꢀ ꢅ ꢈꢀ
ꢇꢐꢈꢆꢉꢃ
ꢇꢉ.ꢈꢘ
ꢐꢂꢕ
ꢉꢊꢋꢈ ꢌꢍꢎꢆꢏ
Rev. B
1
Document Feedback
For more information www.analog.com
LTC4365
ABSOLUTE MAXIMUM RATINGS
Input Currents
UV, OV, SHDN....................................................–1mA
Operating Ambient Temperature Range
Supply Voltage (Note 1)
V .......................................................... –40V to 60V
IN
Input Voltages (Note 3)
LTC4365C................................................ 0°C to 70°C
LTC4365I.............................................–40°C to 85°C
LTC4365H.......................................... –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
UV, SHDN .............................................. –0.3V to 60V
OV............................................................ –0.3V to 6V
OUT
V
....................................................... –0.3V to 40V
Output Voltages (Note 4)
FAULT..................................................... –0.3V to 60V
GATE....................................................... –40V to 45V
for TSOT Only...................................................300°C
PIN CONFIGURATION
ꢀꢁꢂ ꢃꢄꢅꢆ
ꢈꢉꢊ ꢋꢌꢍꢎ
ꢈꢉꢊ
ꢁꢃ
ꢜ
ꢔ
ꢒ
ꢛ
ꢎ
ꢚ
ꢙ
ꢘ
SHDN
FAULT
ꢋ
ꢀ
ꢄ ꢓꢐꢈꢍ
ꢅ ꢋ
ꢌꢘ
ꢇ
ꢈꢉꢊ
ꢗꢋ ꢁ
ꢉꢋ ꢂ
ꢓꢘꢖ ꢃ
ꢉꢗꢈ
ꢝꢃ
ꢃ
ꢁꢝꢀ
ꢆ FAULT
ꢇ SHDN
ꢃ
ꢄꢉ
ꢈꢋꢀꢅ
ꢈꢏꢄ ꢊꢐꢑꢒꢐꢓꢍ
ꢄꢔꢕꢍꢐꢖ ꢊꢕꢐꢏꢈꢌꢑ ꢈꢏꢉꢈꢔꢁꢂ
ꢊꢊB ꢂꢋꢌꢍꢋꢈꢅ
ꢎꢏꢐꢅꢋꢊ ꢑꢒꢓꢓ × ꢔꢓꢓꢕ ꢂꢐꢋꢖꢀꢄꢌ ꢊꢗꢉ
= 150°C, θ = 76°C/W
T
= 150°C, θ = 195°C/W
JMAX
JA
T
JMAX
JA
EXPOSED PAD (PIN 9) PCB GROUND CONNECTION OPTIONAL
ORDER INFORMATION
Lead Free Finish
TAPE AND REEL (MINI)
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
0°C to 70°C
LTC4365CDDB#TRMPBF
LTC4365CDDB#TRPBF
LFKS
8-Lead (3mm × 2mm) Plastic DFN
8-Lead (3mm × 2mm) Plastic DFN
8-Lead (3mm × 2mm) Plastic DFN
8-Lead (3mm × 2mm) Plastic DFN
8-Lead (3mm × 2mm) Plastic DFN
8-Lead (3mm × 2mm) Plastic DFN
8-Lead Plastic TSOT-23
LTC4365CDDB-1#TRMPBF LTC4365CDDB-1#TRPBF LGMB
0°C to 70°C
LTC4365IDDB#TRMPBF
LTC4365IDDB-1#TRMPBF
LTC4365HDDB#TRMPBF
LTC4365IDDB#TRPBF
LTC4365IDDB-1#TRPBF LGMB
LTC4365HDDB#TRPBF LFKS
LFKS
–40°C to 85°C
–40°C to 85°C
–40°C to 125°C
–40°C to 125°C
0°C to 70°C
LTC4365HDDB-1#TRMPBF LTC4365HDDB-1#TRPBF LGMB
LTC4365CTS8#TRMPBF
LTC4365CTS8-1#TRMPBF
LTC4365ITS8#TRMPBF
LTC4365ITS8-1#TRMPBF
LTC4365HTS8#TRMPBF
LTC4365CTS8#TRPBF
LTFKT
LTC4365CTS8-1#TRPBF LTGKZ
8-Lead Plastic TSOT-23
0°C to 70°C
LTC4365ITS8#TRPBF
LTC4365ITS8-1#TRPBF
LTC4365HTS8#TRPBF
LTFKT
LTGKZ
LTFKT
8-Lead Plastic TSOT-23
–40°C to 85°C
–40°C to 85°C
–40°C to 125°C
–40°C to 125°C
8-Lead Plastic TSOT-23
8-Lead Plastic TSOT-23
LTC4365HTS8-1#TRMPBF LTC4365HTS8-1#TRPBF LTGKZ
8-Lead Plastic TSOT-23
Rev. B
2
For more information www.analog.com
LTC4365
ORDER INFORMATION
Lead Free Finish
AUTOMOTIVE PRODUCTS**
TAPE AND REEL (MINI)
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
8-Lead Plastic TSOT-23
8-Lead Plastic TSOT-23
8-Lead Plastic TSOT-23
8-Lead Plastic TSOT-23
TEMPERATURE RANGE
–40°C to 85°C
LTC4365ITS8#WTRMPBF
LTC4365ITS8#WTRPBF
LTFKT
LTC4365ITS8-1#WTRMPBF LTC4365ITS8-1#WTRPBF LTGKZ
LTC4365HTS8#WTRMPBF LTC4365HTS8#WTRPBF LTFKT
LTC4365HTS8-1#WTRMPBF LTC4365HTS8-1#WTRPBF LTGKZ
–40°C to 85°C
–40°C to 125°C
–40°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These
models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your
local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for
these models.
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 2.5V to 34V, unless otherwise noted. (Note 2)
SYMBOL
V , V
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
IN OUT
l
l
V
Input Voltage Range
Input Supply Current
Operating Range
Protection Range
2.5
–40
34
60
V
V
IN
l
l
l
I
SHDN = 0V, V = V , –40°C to 85°C
10
10
25
50
100
150
µA
µA
µA
VIN
IN
OUT
OUT
SHDN = 0V, V = V , –40°C to 125°C
IN
SHDN = 2.5V
l
l
I
Reverse Input Supply Current
V
= –40V, V
= 0V
–1.2
2.2
–1.8
2.4
mA
V
VIN(R)
IN
IN
OUT
V
Input Supply Undervoltage Lockout
V
Rising
1.8
IN(UVLO)
VOUT
l
l
l
I
V
Input Current
SHDN = 0V, V = V
OUT
6
100
20
30
250
50
µA
µA
µA
OUT
IN
SHDN = 2.5V, V = V
IN
OUT
= 0V
V
= –40V, V
IN
OUT
GATE
l
l
ΔV
N-Channel Gate Drive
(GATE-V
V
IN
V
IN
= V
= V
= 5.0V, I = –1µA
GATE
3
7.4
3.6
8.4
4.2
9.8
V
V
GATE
OUT
OUT
)
= 12V to 34V, I
= –1µA
OUT
GATE
l
l
l
l
l
I
I
I
t
t
t
N-Channel Gate Pull Up Current
N-Channel Gate Fast Pull Down Current
N-Channel Gate Gentle Pull Down Current
N-Channel Gate Fast Turn Off Delay
N-Channel Gentle Turn Off Delay
GATE Recovery Delay Time
GATE = V = V = 12V
OUT
–12
31
–20
50
–30
72
µA
mA
µA
µs
GATE(UP)
IN
Fast Shutdown, GATE = 20V, V = V = 12V
GATE(FAST)
GATE(SLOW)
GATE(FAST)
GATE(SLOW)
RECOVERY
IN
OUT
Gentle Shutdown, GATE = 20V, V = V = 12V
50
90
150
4
IN
OUT
C
C
V
= 2.2nF, UV or OV Fault
2
GATE
GATE
= 2.2nF, SHDN Falling, V = V
= 12V
150
250
350
µs
IN
OUT
= 12V, Power Good to ΔV
> 0V
IN
GATE
l
l
LTC4365, C
= 2.2nF
GATE
26
0.6
36
1
49
1.5
ms
ms
GATE
LTC4365-1, C
= 2.2nF
Rev. B
3
For more information www.analog.com
LTC4365
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 2.5V to 34V, unless otherwise noted. (Note 2)
SYMBOL
UV, OV
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
l
l
l
l
V
UV Input Threshold Voltage
OV Input Threshold Voltage
UV Input Hysteresis
492.5
492.5
20
500
500
25
507.5
507.5
32
mV
mV
mV
mV
nA
UV Falling → ΔV
OV Rising → ΔV
= 0V
= 0V
UV
GATE
V
OV
GATE
V
V
UVHYST
OVHYST
LEAK
OV Input Hysteresis
20
25
32
I
t
UV, OV Leakage Current
UV, OV Fault Propagation Delay
V = 0.5V, V = 34V
10
IN
Overdrive = 50mV
1
2
µs
FAULT
V
IN
= V
= 12V
OUT
SHDN
l
l
l
l
V
SHDN Input Threshold
SHDN Falling to ΔV
= 0V
0.4
0.75
1.2
10
V
nA
µs
µs
SHDN
GATE
I
t
t
t
SHDN Input Current
SHDN = 0.75V, V = 34V
IN
SHDN
Delay Coming Out of Shutdown Mode
SHDN to FAULT Asserted
SHDN Rising to ΔV
> 0V, V = V = 12V
OUT
400
800
1.5
1200
3
START
GATE
IN
V
V
= V
= V
= 12V
= 12V
SHDN(F)
LOWPWR
IN
OUT
Delay from Turn Off to Low Power Operation
IN
OUT
l
l
LTC4365
26
0.3
36
0.7
55
2
ms
ms
LTC4365-1
FAULT
l
l
V
FAULT Output Voltage Low
FAULT Leakage Current
I
= 500µA
0.15
0.4
20
V
OL
FAULT
I
FAULT = 5V, V = 34V
nA
FAULT
IN
Note 1. Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 3. These pins can be tied to voltages below –0.3V through a resistor
that limits the current below 1mA.
Note 4. The GATE pin is referenced to V
and does not exceed 44V for
OUT
the entire operating range.
Note 2. All currents into pins are positive; all voltages are referenced to
GND unless otherwise noted.
Rev. B
4
For more information www.analog.com
LTC4365
TYPICAL PERFORMANCE CHARACTERISTICS
VIN Operating Current vs
Temperature
VIN Shutdown Current vs VIN
VIN Current vs VIN (–40 to 60V)
ꢋꢅ
ꢊꢈ
ꢊꢅ
ꢉꢈ
ꢕꢌꢌ
ꢔꢌ
ꢓꢌ
ꢒꢌ
ꢑꢌ
ꢌ
ꢎꢇꢇ
ꢇ
ꢀ
ꢏ ꢀ
ꢐꢑꢒ
ꢁꢂ
SHDN ꢙ ꢑ.ꢋꢎ
SHDN ꢒ ꢓꢀ ꢒ ꢇꢀ
ꢌꢆꢔꢕ
SHDN ꢏ ꢅꢀ
ꢎ
ꢙ ꢎ
ꢚꢅꢀ
ꢍꢏ
ꢉꢊꢈꢓꢔ
ꢎ
ꢍꢏ
ꢙ ꢖꢒꢎ
ꢎ
ꢅꢎꢆꢔꢕ
ꢈꢌꢆꢔꢕ
ꢅꢎꢇꢇ
ꢅꢍꢇꢇ
ꢅꢈꢌꢇꢇ
ꢅꢈꢉꢇꢇ
ꢖꢅꢓꢔ
ꢙ ꢕꢑꢎ
ꢊꢈꢓꢔ
ꢍꢏ
ꢉꢅ
ꢈ
ꢕꢌꢈꢓꢔ
ꢌꢆꢔꢕ
ꢎ
ꢙ ꢑ.ꢋꢎ
ꢑꢋ
ꢍꢏ
ꢅ
ꢊꢈ
ꢋꢅ
ꢋꢈ
ꢘꢋ ꢕꢌꢌ
ꢅ
ꢈ
ꢉꢅ
ꢉꢈ
ꢀ
ꢊꢅ
ꢏꢆ
ꢊꢋꢌ ꢊꢑꢋ
ꢌ
ꢋꢌ
ꢕꢑꢋ
ꢅꢆꢇ
ꢅꢌꢆ
ꢇ
ꢌꢆ
ꢆꢇ
ꢃꢀꢄ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀ
ꢃꢀꢄ
ꢁꢂ
ꢁꢂ
ꢌꢋꢍꢈ ꢎꢅꢊ
ꢒꢖꢓꢋ ꢗꢌꢕ
ꢎꢐꢉꢆ ꢑꢇꢐ
VOUT Operating Current vs
Temperature
VOUT Shutdown Current vs
Temperature
VOUT Current vs Reverse VIN
ꢔꢌꢌ
ꢓꢕꢌ
ꢓꢔꢌ
ꢒꢌ
ꢒꢌ
ꢑꢋ
ꢑꢌ
ꢋ
ꢍꢋ
SHDN ꢙ ꢔ.ꢋꢎ
ꢀ
ꢕ ꢅꢀ
ꢆꢇꢈ
SHDN ꢘ ꢌꢎ
ꢎ
ꢙ ꢎ
ꢎ
ꢘ ꢎ
ꢍꢚ
ꢏꢅꢀ
ꢍꢙ
ꢏꢅꢀ
ꢍꢅ
ꢌꢋ
ꢌꢅ
ꢋ
ꢎ
ꢙ ꢗꢑꢎ
ꢏꢅꢀ
ꢎ
ꢎꢐꢋꢓꢔ
ꢎ
ꢘ ꢕꢔꢎ
ꢏꢅꢀ
ꢙ ꢓꢔꢎ
ꢏꢅꢀ
ꢍꢋꢓꢔ
ꢎ
ꢘ ꢑꢒꢎ
ꢏꢅꢀ
ꢌꢍꢋꢓꢔ
ꢎꢐꢅ
ꢑꢌ
ꢎ
ꢙ ꢔ.ꢋꢎ
ꢋꢌ
ꢏꢅꢀ
ꢎ
ꢘ ꢒ.ꢋꢎ
ꢏꢅꢀ
ꢌ
ꢌ
ꢅ
ꢓꢔꢋ
ꢊꢋꢌ ꢊꢔꢋ
ꢌ
ꢔꢋ
ꢖꢋ ꢓꢌꢌ
ꢑꢒꢋ
ꢎꢋꢅ
ꢊꢋꢌ ꢊꢒꢋ
ꢌ
ꢒꢋ
ꢋꢌ
ꢓꢋ ꢑꢌꢌ
ꢅ
ꢎꢌꢅ
ꢎꢍꢅ
ꢀ
ꢎꢏꢅ
ꢃꢀꢄ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢁꢂ
ꢑꢗꢕꢋ ꢘꢌꢑ
ꢔꢕꢖꢋ ꢗꢌꢋ
ꢐꢏꢑꢋ ꢒꢅꢑ
GATE Current vs GATE Drive
GATE Drive vs VIN
GATE Drive vs Temperature
12
10
8
10
8
–25
–20
–15
–10
–5
V
= V
OUT
= 12V
IN
V
IN
= V
= 34V
OUT
V
= 0V
= V
OUT
125°C
V
IN
= V
OUT
= 12V
I
= –1µA
GATE
V
OUT
IN
6
25°C
6
4
4
–45°C
V
IN
= V
= 2.5V
OUT
2
2
T = 25°C
I
= –1µA
GATE
0
0
0
25
30
35
0
5
10
15
V
20
(V)
75 100
TEMPERATURE (°C)
–50 –25
0
25
50
125
8
10
0
2
4
6
IN
∆V
(V)
GATE
4365 G07
4365 G08
4365 G09
Rev. B
5
For more information www.analog.com
LTC4365
TYPICAL PERFORMANCE CHARACTERISTICS
OV Threshold vs Temperature
UV/OV Leakage vs Temperature
UV Threshold vs Temperature
ꢋꢌꢒ.ꢋ
ꢋꢌꢓ.ꢋ
ꢗ.ꢍꢍ
ꢍ.ꢋꢌ
ꢐ
ꢙ ꢐ
ꢙ ꢓꢏꢐ
ꢚꢅꢀ
ꢐ
ꢚ ꢐ
ꢚ ꢔꢏꢐ
ꢘ
ꢘ
ꢛ ꢍ.ꢌꢘ
ꢅꢘꢙꢚꢘ
ꢎꢜ
ꢗꢘ
ꢘꢙ
ꢑꢅꢀ
ꢛ ꢗꢒꢘ
ꢋꢌꢋ.ꢌ
ꢋꢌꢏ.ꢋ
ꢋꢌꢌ.ꢌ
ꢍꢎꢒ.ꢋ
ꢍꢎꢋ.ꢌ
ꢍꢎꢏ.ꢋ
ꢋꢌꢋ.ꢌ
ꢋꢌꢏ.ꢋ
ꢋꢌꢌ.ꢌ
ꢍꢎꢓ.ꢋ
ꢍꢎꢋ.ꢌ
ꢍꢎꢏ.ꢋ
ꢍ.ꢌꢍ
ꢍ.ꢒꢌ
ꢍ
ꢅꢘ
ꢚꢘ
ꢗꢒꢌ
ꢒꢋ ꢓꢌꢌ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢊꢋꢌ ꢊꢏꢋ
ꢌ
ꢏꢋ
ꢋꢌ
ꢓꢏꢋ
ꢓꢋ ꢔꢌꢌ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢋꢌ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢊꢋꢌ ꢊꢏꢋ
ꢌ
ꢏꢋ
ꢋꢌ
ꢔꢏꢋ
ꢊꢋꢌ
ꢊꢒꢌ
ꢒꢌ
ꢗꢋꢌ
ꢍꢔꢕꢋ ꢖꢓꢌ
ꢍꢕꢖꢋ ꢗꢔꢔ
ꢓꢔꢕꢌ ꢖꢗꢒ
UV/OV Propagation Delay vs
Overdrive
Recovery Delay Time vs
Temperature
LTC4365 Recovery Delay Time
vs VIN
ꢔꢉ
ꢈꢕ
ꢈꢔ
ꢋꢌ
ꢖꢌ
ꢕꢌ
ꢔꢌ
ꢓꢌ
ꢌ
ꢑꢅ
ꢐꢅ
ꢏꢅ
ꢎꢅ
ꢍꢅ
ꢅ
ꢁ
ꢚ ꢁ
ꢚ ꢈꢔꢁ
ꢀꢍꢏ
ꢄꢙ
ꢕꢐꢑꢔꢈ
ꢍꢎꢑꢔꢈ
ꢏ ꢚ ꢔꢗꢛꢜ
ꢏ
ꢜ ꢕꢖꢏ
ꢚꢛ
ꢎꢑꢔꢈ
ꢏ
ꢜ ꢓꢔꢏ
ꢚꢛ
ꢒ
ꢓ
ꢉ
ꢏ
ꢜ ꢔ.ꢋꢏ
ꢚꢛ
ꢈꢉꢉꢉ
ꢈ
ꢈꢉ
ꢈꢉꢉ
ꢙꢋ ꢓꢌꢌ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢊꢋꢌ ꢊꢔꢋ
ꢌ
ꢔꢋ
ꢋꢌ
ꢓꢔꢋ
ꢎꢑ
ꢏꢅ
ꢏꢑ
ꢅ
ꢑ
ꢍꢅ
ꢍꢑ
ꢀ
ꢎꢅ
ꢃꢀꢄ
ꢀꢁꢂRꢃRꢄꢁꢂ ꢅꢆꢁꢇ
ꢁꢂ
ꢓꢖꢕꢗ ꢘꢈꢖ
ꢖꢕꢗꢋ ꢘꢓꢖ
ꢐꢏꢒꢑ ꢓꢍꢑ
LTC4365 AC Blocking
Turn-On Timing
Turn-Off Timing
100µF, 12Ω LOAD ON V
ꢌ
OUT
100µF, 12Ω LOAD ON V
OUT
60V SI9945 DUAL NCH MOSFET
ꢐꢑꢎ
GATE
GATE
ꢄꢒꢊ
ꢅꢌꢉꢊꢋꢌ
60V SI9945 DUAL NCH MOSFET
V
= 12V
IN
5V/DIV
3V/DIV
5V/DIV
3V/DIV
ꢌ
ꢋꢒ
V
OUT
V
OUT
ꢄꢒꢊ
ꢆꢓꢌꢉꢊꢋꢌ
ꢄꢍꢎꢏ
GND
GND
GND
GND
SHDN
SHDN
ꢅꢓꢔ ꢖ ꢅꢗ ꢘꢐꢍꢊ ꢐꢒ ꢌ
ꢐꢑꢎ
ꢂꢓꢌ ꢊꢑꢍꢘ ꢒꢙꢚ ꢛꢐꢜꢕꢏꢎ
ꢀꢁꢂꢃ ꢄꢅꢂ
4365 G18
4365 G17
ꢆ.ꢃꢇꢈꢉꢊꢋꢌ
250µs/DIV
250µs/DIV
Rev. B
6
For more information www.analog.com
LTC4365
PIN FUNCTIONS
Exposed Pad: Connect to device ground.
SHDN: Shutdown Control Input. SHDN high enables the
GATE charge pump which in turn enhances the gate of an
external N-channel MOSFET. A low on SHDN generates a
pull down on the GATE output with a 90µA current sink and
placestheLTC4365inlowcurrentmode(10µA).Ifunused,
FAULT: FaultIndicationOutput.Thishighvoltageopendrain
output is pulled low if UV is below its monitor threshold,
if OV is above its monitor threshold, if SHDN is low, or if
V has not risen above V
IN
.
IN(UVLO)
connect to V . If V goes below ground, or if V rings
IN
IN
IN
GATE:GateDriveOutputforExternalN-channelMOSFETs.
An internal charge pump provides 20µA of pull-up current
and up to 9.8V of enhancement to the gate of an external
N-channel MOSFET.
to 60V, use a current limiting resistor of at least 100k.
UV:UndervoltageComparatorInput.Connectthispintoan
external resistive divider to set the desired V undervolt-
IN
age fault threshold. The UV input connects to an accurate,
fast (1µs) comparator with a 0.5V falling threshold and
25mV of hysteresis. When UV falls below its threshold, a
50mA current sink pulls down on the GATE output. When
UV rises back above 0.525V, and after a 36ms recovery
delay waiting period (1ms for LTC4365-1), the GATE
charge pump is enabled. The low leakage current of the
UV input allows the use of large valued resistors for the
When turned off, GATE is pulled just below the lower of
V or V . When V goes negative, GATE is automati-
IN
OUT
IN
cally connected to V .
IN
GND: Device Ground.
OV: Overvoltage Comparator Input. Connect this pin to an
externalresistivedividertosetthedesiredV overvoltage
IN
fault threshold. The OV input connects to an accurate, fast
(1µs) comparator with a 0.5V rising threshold and 25mV
of hysteresis. When OV rises above its threshold, a 50mA
current sink pulls down on the GATE output. When OV
falls back below 0.475V, and after a 36ms recovery delay
waiting period (1ms for LTC4365-1), the GATE charge
pump is enabled. The low leakage current of the OV input
allows the use of large valued resistors for the external
resistive divider. Connect to GND if unused.
external resistive divider. If unused, connect to V . While
IN
connected to V , if V goes below ground, or if V rings
IN
IN
IN
to 60V, use a current limiting resistor of at least 100k.
V : Power Supply Input. Maximum protection range:
IN
–40V to 60V. Operating range: 2.5V to 34V.
V
:OutputVoltageSenseInput.Thispinsensesthevolt-
OUT
age at the output side of the external N-channel MOSFET.
The GATE charge pump voltage is referenced to V . It
is used as the charge pump input when V
than approximately 6.5V.
OUT
is greater
OUT
Rev. B
7
For more information www.analog.com
LTC4365
BLOCK DIAGRAM
RꢊꢀꢊRꢍꢊ
ꢏRꢇꢆꢊꢗꢆꢁꢇꢂ
ꢀ
ꢁꢂ
ꢓꢋꢆꢊ
ꢃꢄꢅꢀ ꢆꢇ ꢈꢅꢀ
–
+
ꢗꢌꢇꢍꢊꢍ ꢍꢘꢁꢆꢗꢕ
ꢘꢕꢊꢂ ꢀ ꢁꢍ ꢂꢊꢓꢋꢆꢁꢀꢊ
ꢉꢀ ꢁꢂꢆꢊRꢂꢋꢌ
ꢍꢎꢏꢏꢌꢐ
ꢁꢂ
ꢌꢑꢇ
ꢈ.ꢉꢀ ꢁꢂꢆꢊRꢂꢋꢌ
ꢍꢎꢏꢏꢌꢐ
ꢓꢋꢆꢊ
ꢗꢕꢋRꢓꢊ
ꢏꢎꢜꢏ
ꢁ
ꢓꢋꢆꢊ
ꢀ
ꢇꢎꢆ
ꢝ ꢞ ꢄꢅꢅꢟꢕꢠ
ꢊꢂꢋBꢌꢊ
ꢒ.ꢒꢀ
ꢎꢀꢌꢇ
ꢙꢋꢎꢌꢆ
ꢇꢙꢙ
ꢆꢎRꢂ
ꢇꢙꢙ
ꢑꢊꢌꢋꢐ ꢆꢁꢜꢊRꢍ
ꢌꢇꢓꢁꢗ
SHDN
FAULT
SHDN
ꢎꢀ
ꢇꢀ
–
+
ꢉꢅꢔꢋ
ꢚꢅꢛꢋ
ꢒꢉꢔꢀ
ꢕꢐꢍꢆꢊRꢊꢍꢁꢍ
ꢓꢋꢆꢊ ꢏꢎꢌꢌꢑꢇꢘꢂ
+
–
ꢅ.ꢉꢀ
ꢓꢂꢑ
ꢄꢖꢈꢉ Bꢑ
OPERATION
Many of today’s electronic systems get their power from
external sources such as wall wart adapters, batteries and
custom power supplies. A typical supply arrangement for
a portable product is shown by the operational diagram
in Figure 1. Power is supplied by an AC adaptor or, if the
plug is withdrawn, by a removable battery. Trouble arises
when any of the following occurs:
directly to the electronic systems, the systems could be
subject to damage. The LTC4365 is an input voltage fault
protectionN-channelMOSFETcontroller.Thepartisolates
an input supply from its load to protect the load from
unexpected supply voltage conditions, while providing a
low loss path for qualified power.
To protect electronic systems from improperly connected
power supplies, system designers will often add discrete
diodes,transistorsandhighvoltagecomparators.Thehigh
voltagecomparatorsenablesystempoweronlyiftheinput
supply falls within a desired voltage window. A Schottky
diode or P-channel MOSFET typically added in series with
the supply protects against reverse supply connections.
• The battery is installed backwards
• An AC adaptor of opposite polarity is attached
• An AC adaptor of excessive voltage is attached
• The battery is discharged below a safe level
This can lead to supply voltages that are too high, too
low, or even negative. If these power sources are applied
The LTC4365 provides accurate overvoltage and under-
voltage comparators to ensure that power is applied to
Rev. B
8
For more information www.analog.com
LTC4365
OPERATION
the system only if the input supply meets the user select-
able voltage window. Reverse supply protection circuits
automaticallyisolatetheloadfromnegativeinputvoltages.
During normal operation, a high voltage charge pump
enhances the gate of external N-channel power MOSFETs.
Power consumption is 10µA during shutdown and 125µA
while operating. The LTC4365 integrates all these func-
tions in tiny TSOT-23 and 3mm × 2mm DFN packages.
ꢖꢉꢐꢀ ꢇꢄ ꢎꢐꢀ ꢊRꢄꢇꢋꢔꢇꢁꢄꢂ Rꢌꢂꢍꢋ
ꢚꢑ
ꢚꢅ
+
ꢌꢔ
ꢌꢒꢌꢊꢇꢄR
ꢁꢂꢊꢃꢇ
–
ꢓꢄꢌꢒ
ꢔꢁRꢔꢃꢁꢇ
ꢍꢌꢇꢋ
BꢌꢇꢇꢋRꢕ
ꢀ
ꢀ
ꢄꢃꢇ
ꢁꢂ
ꢓꢇꢔꢉꢈꢎꢆ
Rꢆ
SHDN
Rꢈ
ꢃꢀ
FAULT
ꢄꢀꢗ ꢃꢀ ꢊRꢄꢇꢋꢔꢇꢁꢄꢂ
ꢇꢘRꢋꢙꢘꢄꢓꢒꢙ ꢙꢋꢇ ꢇꢄ
ꢙꢌꢇꢁꢙꢏꢕ ꢓꢄꢌꢒ ꢔꢁRꢔꢃꢁꢇ
Rꢅ
Rꢑ
ꢄꢀ
ꢅ.ꢆꢀ ꢇꢄ ꢈꢉꢀ
ꢄꢊꢋRꢌꢇꢁꢂꢍ Rꢌꢂꢍꢋ
ꢍꢂꢒ
ꢉꢈꢎꢆ ꢏꢐꢑ
Figure 1. Operational Diagram Common to Many Portable Products
APPLICATIONS INFORMATION
The LTC4365 is an N-channel MOSFET controller that
protects a load from faulty supply connections. A basic
application circuit using the LTC4365 is shown in Figure 2
18V. Voltages at V outside of the 5V to 18V range are
IN
prevented from getting to the load and can be as high as
40V and as low as –40V. The circuit of Figure 2 protects
The circuit provides a low loss connection from V to
againstnegativevoltagesatV asshown.Nootherexternal
IN
IN
V
as long as the voltage at V is between 5V and
components are needed.
OUT
IN
During normal operation, the LTC4365 provides up to
9.8V of gate enhancement to the external back-to-back
N-channel MOSFETs. This turns on the MOSFET, thus
ꢕꢖꢕBꢉꢋꢗꢂ
ꢉꢍꢀ ꢗꢃꢑꢔ
ꢀ
ꢀ
ꢄꢃꢏ
ꢁꢂ
ꢆꢎꢀ ꢂꢄꢓꢁꢂꢑꢔ
ꢈꢀ ꢏꢄ ꢆꢇꢀ
+
ꢓꢆ
ꢓꢎ
ꢘ
ꢄꢃꢏ
ꢆꢍꢍꢚꢌ
connecting the load at V
to the supply at V .
OUT
IN
ꢐꢑꢏꢒ
ꢀ
ꢀ
ꢄꢃꢏ
ꢁꢂ
GATE Drive
Rꢈ
ꢆꢍꢍꢙ
ꢔꢏꢘꢉꢊꢋꢈ
SHDN
TheLTC4365turnsontheexternalN-channelMOSFETsby
Rꢊ
ꢎꢛꢉꢍꢙ
driving the GATE pin above V . The voltage difference
OUT
ꢃꢀ
FAULT
between the GATE and V
pins (gate drive) is a function
OUT
Rꢎ
ꢎꢆꢈꢙ
of V and V
.
IN
OUT
ꢄꢀ
ꢄꢀ ꢅ ꢆꢇꢀ
ꢃꢀ ꢅ ꢈꢀ
Rꢆ
ꢇꢉ.ꢈꢙ
ꢐꢂꢗ
ꢉꢊꢋꢈ ꢌꢍꢎ
Figure 2. LTC4365 Protects Load from –40V
to 40V VIN Faults
Rev. B
9
For more information www.analog.com
LTC4365
APPLICATIONS INFORMATION
Figure3highlightsthedependenceofthegatedriveonV
Overvoltage and Undervoltage Protection
IN
and V . When system power is first turned on (SHDN
OUT
low to high, V
TheLTC4365providestwoaccuratecomparatorstomoni-
torforovervoltage(OV)andundervoltage(UV)conditions
= 0V), gate drive is at a maximum for all
OUT
values of V . This helps prevent start-up problems into
IN
at V . If the input supply rises above the user adjustable
IN
heavy loads by ensuring that there is enough gate drive
OV threshold, the gate of the external MOSFET is quickly
turned off, thus disconnecting the load from the input.
Similarly, if the input supply falls below the user adjust-
able UV threshold, the gate of the external MOSFET also
is quickly turned off. Figure 4 shows a UV/OV application
for an input supply of 12V.
to support the load.
As V
ramps up from 0V, the absolute value of the GATE
OUT
voltage remains fixed until V
is greater than the lower
OUT
crosses this threshold,
OUT
of (V –1V) or 6V. Once V
IN
gate drive begins to increase up to a maximum of 9.8V
(for V ≥ 12V). The curves of Figure 3 were taken with
IN
a GATE load of –1µA. If there were no load on GATE, the
ꢚꢆꢓꢌꢍꢎꢉ
gate drive for each V would be slightly higher.
ꢃꢄꢀ
ꢀ
ꢁꢂ
IN
ꢅꢀ
Rꢍ
Note that when V is at the lower end of the operating
IN
ꢓꢊꢛꢜꢔRꢔꢆꢊR
–
ꢄꢌꢝꢐꢞ
range, the external N-channel MOSFET must be selected
ꢅꢀ
ꢅꢀ ꢈ ꢉꢀ
ꢆꢇ
with a corresponding lower threshold voltage.
ꢄꢉꢘꢀ
ꢊꢀ
+
Rꢄ
ꢄꢃꢉꢞ
ꢐ.ꢉꢀ
ꢑꢁꢒꢓꢇꢔRꢕꢖ ꢕꢔꢆꢖ
ꢗꢁꢆꢇ ꢉꢐꢘꢔ ꢒꢁꢂꢙ
12
T = 25°C
GATE
ꢓꢊꢛꢜꢔRꢔꢆꢊR
I
= –1µA
ꢊꢀ
10
8
ꢊꢀ ꢈ ꢃꢋꢀ
ꢆꢇ
+
V
= 30V
IN
ꢄꢉꢘꢀ
Rꢃ
ꢋꢌ.ꢉꢞ
ꢐ.ꢉꢀ
–
6
ꢌꢍꢎꢉ ꢏꢐꢌ
V
= 12V
IN
4
V
= 5V
IN
Figure 4. UV, OV Comparators Monitor 12V Supply
2
V
= 3.3V
IN
V
= 2.5V
IN
3
0
12
15
The external resistive divider allows the user to select
an input supply range that is compatible with the load at
OUT
0
6
V
9
(V)
OUT
4365 F03
V
. Furthermore, the UV and OV inputs have very low
Figure 3. Gate Drive (GATE – VOUT) vs VOUT
leakage currents (typically < 1nA at 100°C), allowing for
largevaluesintheexternalresistivedivider. Intheapplica-
tion of Figure 4, the load is connected to the supply only
if V lies between 5V and 18V. In the event that V goes
Table 1 lists some external MOSFETs compatible with
different V supply voltages.
IN
IN
IN
above 18V or below 5V, the gate of the external N-channel
MOSFET is immediately discharged with a 50mA current
sink, thus isolating the load from the supply.
Table 1. Dual MOSFETs for Various Supply Ranges
V
MOSFET
SiB914
Si5920
Si7940
Si4214
Si9945
V
V
V
DS(MAX)
IN
TH(MAX)
GS(MAX)
2.5V
3.3V
5V
0.8V
5V
8V
1.0V
1.5V
3.0V
3.0V
5V
8V
8V
12V
30V
60V
≤30V
≤60V
20V
20V
Rev. B
10
For more information www.analog.com
LTC4365
APPLICATIONS INFORMATION
Figure 5 shows the timing associated with the UV pin.
Once a UV fault propagates through the UV comparator
Procedure for Selecting UV/OV External Resistor Values
The following 3-step procedure helps select the resistor
values for the resistive divider of Figure 4. This procedure
minimizes UV and OV offset errors caused by leakage
currents at the respective pins.
(t
), the FAULT output is asserted low and a 50mA
FAULT
current sink discharges the GATE pin. As V
falls, the
OUT
GATE pin tracks V
.
OUT
1. Choose maximum tolerable offset at the UV pin,
ꢐ
ꢋꢐ
ꢐ
ꢑ ꢐ
ꢋꢐ ꢋꢐꢒꢓꢎꢈ
ꢋꢐ
V
. Divide by the worst case leakage current at
OS(UV)
the UV pin, I (10nA). Set the sum of R1 + R2 equal
ꢊ
ꢊ
ꢄꢇꢋꢌꢈ
ꢄꢇꢋꢌꢈ
UV
to V
divided by 10nA. Note that due to the
presence of R3, the actual offset at UV will be slightly
OS(UV)
FAULT
ꢊ
ꢊ
RꢉꢔꢕꢐꢉRꢓ
ꢆꢇꢈꢉꢍꢄꢇꢎꢈꢏ
lower:
ꢉꢖꢈꢉRꢗꢇꢌ ꢗꢘꢔꢒꢇꢗꢗꢉꢌ ꢙꢕꢎꢄꢉꢈ
ꢈꢋRꢗꢎ ꢕꢄꢄ
ꢆꢇꢈꢉ
V
OS(UV)
ꢀꢁꢂꢃ ꢄꢅꢃ
R1+ R2 =
I
UV
Figure 5. UV Timing (OV < (VOV – VOVHYST), SHDN > 1.2V)
2. Select the desired V UV trip threshold, UV . Find
IN
TH
the value of R3:
Figure 6 shows the timing associated with the OV pin.
Once an OV fault propagates through the OV comparator
V
UV – 0.5V
⎛
⎞
OS(UV)
TH
R3 =
•
⎜
⎟
(t
), the FAULT output is asserted low and a 50mA
FAULT
I
0.5V
⎝
⎠
UV
current sink discharges the GATE pin. As V
falls, the
OUT
GATE pin tracks V
.
3. Select the desired V OV trip threshold, OV . Find
OUT
IN
TH
the values of R1 and R2:
ꢐ
ꢑꢐ
ꢐ
ꢒ ꢐ
ꢑꢐ ꢑꢐꢓꢔꢎꢈ
ꢑꢐ
⎛
⎞
V
OS(UV)
ꢊ
ꢊ
+ R3
ꢄꢇꢋꢌꢈ
ꢄꢇꢋꢌꢈ
⎜
⎟
I
⎝
UV
⎠
R1 =
R2 =
• 0.5V
FAULT
OV
TH
ꢊ
ꢊ
RꢉꢕꢑꢐꢉRꢔ
ꢆꢇꢈꢉꢍꢄꢇꢎꢈꢏ
V
ꢉꢖꢈꢉRꢗꢇꢌ ꢗꢘꢕꢓꢇꢗꢗꢉꢌ ꢙꢑꢎꢄꢉꢈ
ꢈꢋRꢗꢎ ꢑꢄꢄ
OS(UV)
ꢆꢇꢈꢉ
– R1
ꢀꢁꢂꢃ ꢄꢅꢂ
I
UV
Figure 6. OV Timing (UV > (VUV + VUVHYST), SHDN > 1.2V)
TheexampleofFigure4usesstandard1%resistorvalues.
The following parameters were selected:
When both the UV and OV faults are removed, the external
MOSFET is not immediately turned on. The input supply
must remain within the user selected power good window
V
= 3mV
OS(UV)
I
= 10nA
UV
for at least 36ms (t ) before the load is again
RECOVERY
UV = 5V
TH
connected to the supply. This recovery timeout period
filters noise (including line noise) at the input supply and
prevents chattering of power at the load. For applications
that require faster turn-on after a fault, the LTC4365-1
provides a 1ms recovery timeout period.
OV = 18V
TH
Rev. B
11
For more information www.analog.com
LTC4365
APPLICATIONS INFORMATION
The resistor values can then be solved:
As shown in Figure 7, external back-to-back N-channel
MOSFETsarerequiredforreversesupplyprotection.When
3mV
V goes negative, the reverse V comparator closes the
IN
IN
1. R1+ R2 =
= 300k
internal switch, which in turn connects the gates of the
10nA
external MOSFETs to the negative V voltage. The body
IN
diode (D1) of M1 turns on, but the body diode (D2) of
M2 remains in reverse blocking mode. This means that
the common source connection of M1 and M2 remains
3mV
2.
R3 = 2•
• 5V − 0.5V = 2.7M
(
)
10nA
about a diode drop higher than V . Since the gate voltage
The closest 1% value: R3 = 2.74M:
IN
of M2 is shorted to V , M2 will be turned off and no cur-
IN
rent can flow from V to the load at V . Note that the
300k + 1.82M
IN
OUT
3. R1=
= 84.4k
voltage rating of M2 must withstand the reverse voltage
2•18V
excursion at V .
IN
The closest 1% value: R1 = 84.5k:
R2 = 300k – 84.5k = 215.5k
Figure 8 illustrates the waveforms that result when V
IN
is hot plugged to –20V. V , GATE and V
start out at
IN
OUT
ground just before the connection is made. Due to the
The closest 1% value: R2 = 215k
Therefore: OV = 17.99V, UV = 5.07V.
parasitic inductance of the V and GATE connections, the
IN
voltage at the V and GATE pins ring significantly below
IN
–20V. Therefore, a 40V N-channel MOSFET was selected
Reverse V Protection
to survive the overshoot.
IN
The LTC4365’s rugged and hot-swappable V input helps
The speed of the LTC4365 reverse protection circuits is
IN
protect the more sensitive circuits at the output load. If
the input supply is plugged in backwards, or a negative
supply is inadvertently connected, the LTC4365 prevents
this negative voltage from passing to the output load.
evident by how closely the GATE pin follows V during
IN
the negative transients. The two waveforms are almost
indistinguishable on the scale shown.
The trace at V , on the other hand, does not respond
OUT
The LTC4365 employs a novel, high speed reverse supply
to the negative voltage at V , demonstrating the desired
IN
voltagemonitor.WhenthenegativeV voltageisdetected,
reversesupplyprotection.ThewaveformsofFigure8were
IN
an internal switch connects the gates of the external back-
captured using a 40V dual N-channel MOSFET, a 10µF
to-back N-channel MOSFETs to the negative input supply.
ceramic output capacitor and no load current on V
.
OUT
ꢙꢚ
ꢙꢛ
ꢌꢊ ꢖꢊꢎꢙ
ꢀ
ꢁꢂ
ꢐ ꢑꢃꢈꢀ
+
ꢃ
ꢔꢕꢒ
ꢓ
ꢔꢚ
ꢔꢛ
ꢈꢉꢆ
ꢄꢃꢅꢆꢇꢃ
ꢀꢁꢂꢃ
ꢊꢋꢌ
ꢀ
ꢍꢎꢌꢏ
ꢀ
ꢊꢋꢌ
ꢁꢂ
ꢖꢌꢓꢃꢄꢅꢆ
RꢏꢀꢏRꢒꢏ ꢀ
ꢁꢂ
ꢃ
ꢇꢉ
ꢓꢊꢔꢕꢎRꢎꢌꢊR
ꢈꢑꢒꢓ
+
–
ꢓꢖꢊꢒꢏꢒ ꢒꢗꢁꢌꢓꢘ
ꢗꢘꢏꢂ ꢀ ꢁꢒ ꢂꢏꢍꢎꢌꢁꢀꢏ
ꢍꢂꢙ
ꢁꢂ
ꢃꢄꢅꢆ ꢇꢈꢉ
ꢊꢋꢌꢄ ꢍꢂꢎ
ꢄꢂꢂꢏꢐꢅꢆꢇꢃ
Figure 7. Reverse VIN Protection Circuits
Figure 8. Hot Swapping VIN to –20V
Rev. B
12
For more information www.analog.com
LTC4365
APPLICATIONS INFORMATION
Recovery Timer
further decrease GATE pin slew rate, place a capacitor
across the gate and source terminals of the external MOS-
FETs. The waveforms of Figure 10 were captured using
the Si4214 dual N-channel MOSFETs, and a 2A load with
100µF output capacitor.
The LTC4365 has a recovery delay timer that filters noise
at V and helps prevent chatter at V . After either an
IN
OUT
OV or UV fault has occurred, the input supply must return
to the desired operating voltage window for at least 36ms
(t
) in order to turn the external MOSFET back on
RECOVERY
ꢁ
ꢔ ꢉꢕꢁ
ꢄꢓ
as illustrated in Figure 5 and Figure 6. For applications
that require faster turn-on after a fault, the LTC4365-1
provides a 1ms recovery timeout period.
ꢏ ꢔ ꢕꢀꢖꢗ
ꢍꢎꢏꢐ
ꢁ
ꢑꢒꢏ
Going out of and then back into fault in less than t
RECOVERY
ꢀꢁꢂꢃꢄꢁ
ꢍꢓꢃ
will keep the MOSFET off continuously. Similarly, coming
out of shutdown (SHDN low to high) triggers an 800µs
start-up delay timer (see Figure 11).
SHDN
The recovery timer is also active while the part is power-
ꢅꢆꢇꢀ ꢈꢉꢊ
ꢉꢊꢊꢋꢌꢂꢃꢄꢁ
ing up. The recovery timer starts once V rises above
IN
V
and V lies within the user selectable UV/OV
Figure 10. Gentle Shutdown: GATE Tracks VOUT as VOUT Decays
IN(UVLO)
IN
power good window. See Figure 9.
FAULT Status
ꢏ
ꢏ
ꢐꢎꢑꢒꢏꢓꢌꢔ
ꢐꢎ
The FAULT high voltage open drain output is driven low if
SHDN is asserted low, if V is outside the desired UV/OV
IN
ꢕ
voltage window, or if V has not risen above V
.
RꢊꢖꢌꢏꢊRꢗ
IN
IN(UVLO)
Figure 5, Figure 6 and Figure 11 show the FAULT output
timing.
ꢇꢈꢉꢊ
ꢋꢌꢍꢄꢊꢉ ꢌꢄꢄ
ꢋꢌꢍꢄꢊꢉ ꢌꢎ
ꢀꢁꢂꢃ ꢄꢅꢆ
SHDN
Figure 9. Recovery Timing During Power-On (OV
= GND, UV = SHDN = VIN)
ꢇ
ꢇ
ꢉꢂꢁRꢂ
ꢀꢁꢂꢃꢈꢉꢊꢅꢋꢌ
ꢀꢁꢂꢃ
∆ꢄ
ꢀꢁꢂꢃ
Gentle Shutdown
ꢀꢁꢂꢃ ꢍ ꢄ
ꢅꢆꢂ
ꢄ
ꢅꢆꢂ
TheSHDNinputturnsofftheexternalMOSFETsinagentle,
controlled manner. When SHDN is asserted low, a 90µA
currentsinkslowlybeginstoturnofftheexternalMOSFETs.
ꢇ
ꢉꢎꢏꢐꢈꢑꢌ
FAULT
ꢒꢓꢔꢕ ꢑꢖꢖ
Once the voltage at the GATE pin falls below the voltage
at the V
pin, the current sink is throttled back and a
OUT
Figure 11. Gentle Shutdown Timing
feedbacklooptakesover.ThisloopforcestheGATEvoltage
to track V , thus keeping the external MOSFETs off as
OUT
Select Between Two Input Supplies
With the part in shutdown, the V and V
V
OUT
decays. Note that when V
is pulled to within 400mV of ground.
< 4.5V, the GATE pin
OUT
pins can be
OUT
IN
driven by separate power supplies. The LTC4365 then
automatically drives the GATE pin just below the lower of
Rev. B
Gentle gate turn off reduces load current slew rates and
mitigates voltage spikes due to parasitic inductances. To
13
For more information www.analog.com
LTC4365
APPLICATIONS INFORMATION
thetwosupplies,thusturningofftheexternalback-to-back
MOSFETs.TheapplicationofFigure12usestwoLTC4365s
toselectbetweentwopowersupplies.Careshouldbetaken
to ensure that only one of the two LTC4365s is enabled
at any given time.
Limiting Inrush Current During Turn-On
The LTC4365 turns on the external N-channel MOSFET
with a 20µA current source. The maximum slew rate at
the GATE pin can be reduced by adding a capacitor on
the GATE pin:
ꢀꢉ
20µA
ꢔꢉ
ꢔꢃ
Slew Rate =
C
GATE
ꢍꢎꢌꢏ
ꢀ
ꢀ
ꢊꢋꢌ
ꢁꢂ
Since the MOSFET acts like a source follower, the slew
rate at V equals the slew rate at GATE.
ꢐꢌꢑꢄꢅꢆꢇ
ꢊꢋꢌ
OUT
SHDN
Therefore, inrush current is given by:
ꢒꢏꢐ ꢊꢋꢌ
ꢓ
ꢉ
ꢀꢉ
ꢀꢃ
C
OUT
I
=
• 20µA
ꢀꢃ
INRUSH
C
GATE
ꢔꢉ
ꢔꢃ
For example, a 1A inrush current to a 330µF output
capacitance requires a GATE capacitance of:
ꢍꢎꢌꢏ
ꢀ
ꢀ
ꢊꢋꢌ
ꢁꢂ
ꢐꢌꢑꢄꢅꢆꢇ
SHDN
ꢒꢏꢐ
20µA • C
OUT
C
=
ꢄꢅꢆꢇ ꢈꢉꢃ
GATE
I
INRUSH
Figure 12. Selecting One of Two Supplies
20µA • 330µF
1A
C
=
= 6.6nF
GATE
Single MOSFET Application
When reverse V protection is not needed, only a single
IN
The 6.8nF C
capacitor in the application circuit of
GATE
external N-channel MOSFET is necessary. The applica-
Figure 14 limits the inrush current to approximately 1A.
tion circuit of Figure 13 connects the load to V when
IN
R
makes sure that C
does not affect the fast GATE
GATE
GATE
V is less than 30V, and uses the minimal set of external
IN
turn off characteristics during UV/OV faults, or during
components.
reverse V connection. R4A and R4B help prevent high
IN
frequencyoscillationswiththeexternalN-channelMOSFET
ꢒꢁꢓꢌꢑꢇꢔꢂ
ꢉꢇꢀ
ꢀ
and related board parasitics.
ꢁꢂ
ꢀ
ꢄꢃꢍ
ꢑꢈꢀ
+
ꢖ
ꢄꢃꢍ
ꢌꢇꢇꢘꢋ
V
IN
V
OUT
ꢎꢏꢍꢐ
ꢀ
ꢀ
ꢄꢃꢍ
+
ꢁꢂ
M1
M2
C
OUT
Rꢊ
ꢌꢇꢇꢗ
ꢕꢍꢖꢈꢆꢉꢊ
R4A
10Ω
R4B
10Ω
330µF
SHDN
R
GATE
FAULT
ꢃꢀ
V
IN
GATE
LTC4365
V
OUT
Rꢑ
5.1k
ꢑꢆꢓꢇꢗ
C
GATE
ꢄꢀ
6.8nF
ꢄꢀ ꢅ ꢆꢇꢀ
Rꢌ
ꢈꢇ.ꢑꢗ
ꢎꢂꢔ
4365 F14
ꢈꢆꢉꢊ ꢋꢌꢆ
Figure 14. Limiting Inrush Current with CGATE
Figure 13. Small Footprint Single MOSFET Application
Protects Against 60V
Rev. B
14
For more information www.analog.com
LTC4365
APPLICATIONS INFORMATION
Transients During OV Fault
pacitance at the V node. D1 is an optional power clamp
IN
(TVS, Tranzorb) recommended for applications where
The circuit of Figure 15 was used to display transients
duringanovervoltagecondition.Thenominalinputsupply
is 24V and it has an overvoltage threshold of 30V. The
parasiticinductanceisthatofa1footwire(roughly300nH).
Figure 16 shows the waveforms during an overvoltage
the DC input voltage can exceed 24V and with large V
IN
parasitic inductance. No clamp was used to capture the
waveforms of Figure 16. In order to maintain reverse sup-
ply protection, D1 must be a bi-directional clamp rated for
at least 225W peak pulse power dissipation.
condition at V . These transients depend on the parasitic
IN
inductance and resistance of the wire along with the ca-
12 INCH WIRE
LENGTH
SI9945
60V
V
OUT
V
IN
24V
+
+
C
IN
C
OUT
100µF
M1
M2
1000µF
9Ω
GATE
V
IN
V
OUT
R3
100k
LTC4365
D1
OPTIONAL
SHDN
UV
FAULT
R2
2370k
OV
OV = 30V
R1
GND
40.2k
4365 F15
Figure 15. OV Fault with Large VIN Inductance
ꢆꢁꢑꢒ
ꢓꢔꢑ
ꢅ
ꢓꢔꢑ
ꢅ
ꢆꢁꢑꢒ
ꢀꢈꢅꢂꢃꢄꢅ
ꢆꢇꢃ
ꢅ
ꢄꢇ
ꢀꢈꢅꢂꢃꢄꢅ
ꢆꢇꢃ
ꢈꢁ
ꢄ
ꢄꢇ
ꢀꢁꢂꢃꢄꢅ
ꢉꢊꢋꢌ ꢍꢎꢋ
ꢀꢌꢈꢏꢐꢂꢃꢄꢅ
Figure 16. Transients During OV Fault When No
Tranzorb (TVS) Is Used
Rev. B
15
For more information www.analog.com
LTC4365
APPLICATIONS INFORMATION
REGULATOR APPLICATIONS
and duty cycle of the V glitch must not exceed the SOA
IN
rating of the external MOSFETs.
Hysteretic Regulator
Solar Charger
Built-in hysteresis and the availability of both inverting
and noninverting control inputs (OV and UV) facilitate the
design of hysteretic regulators. Figure 17 shows how the
LTC4365-1 can protect a load from OV transients, while
regulatingtheoutputvoltageatauser-definedlevel. When
the output voltage reaches its OV limit, the LTC4365-1
turns off the external MOSFETs. The load current then
discharges the output capacitance until OV falls below the
hysteresis voltage. The external MOSFETs are turned back
on after a 1ms delay. Figure 18 shows the waveforms for
the circuit of Figure 17. Note that the duration, magnitude
Figure 19 shows a series regulator for a solar charger.
The LTC4365-1 connects the solar charger to the battery
when the battery voltage falls below 13.9V (after a 1ms
delay). Conversely, when the battery reaches 14.6V, the
LTC4365-1 immediately (2µs) opens the charging path.
Regulation of the battery voltage is achieved by connect-
ing a resistive divider from the battery to the accurate OV
comparator input (with 5% hysteresis). The fast rising
responseoftheOVcomparatorpreventsthebatteryvoltage
from rising above the user-selected threshold.
Si4946
DUAL NCH
V
IN
V
OUT
12V
+
R7
1Ω
R
C
LOAD
LOAD
100Ω
47µF
OPTIONAL
SNUBBER
ꢍ
ꢌꢏ
1µF
GATE
R5
510k
V
V
OUT
IN
LTC4365-1
ꢃꢍꢊꢋꢌꢍ
ꢎꢏꢋ
UV
R2
ꢍ
1820k
ꢐꢑꢒ
SHDN
FAULT
OV
C
R1
59k
OV
GND
220pF
4365 F17
ꢀꢁꢂꢃ ꢄꢅꢆ
ꢇ.ꢃꢈꢉꢊꢋꢌꢍ
Figure 17. Hysteretic Regulation of VOUT During OV Transients
Figure 18. VOUT Regulates at 16V When VIN
Glitches Above Desired Level
ꢈꢐꢑ ꢊꢇ ꢒꢓꢃꢑꢈꢃ
ꢈꢐꢑ ꢊꢇ ꢒꢓꢃꢑꢈꢃ
ꢔꢑ
ꢔꢈ
ꢔꢃ
Bꢈꢄꢙ
ꢘꢈ
ꢘꢑ
ꢌꢊ ꢕꢊꢎꢔ
+
ꢖ
Bꢛꢜ
ꢖ
Bꢎꢌꢌ
ꢈꢆꢞ
ꢒꢊꢕꢎR
ꢜꢎꢂꢏꢕ
ꢈꢙꢙꢝꢇ
ꢈꢙꢙꢚꢇ
ꢈꢑꢀꢡ ꢢꢎꢣ
ꢍꢏꢕꢖꢏꢕꢕ
SHDN ꢋꢀ ꢀ
ꢍꢎꢌꢏ
ꢀ
ꢊꢋꢌ
ꢁꢂ
Rꢑ
ꢕꢌꢖꢃꢄꢅꢆꢗꢈ
ꢍꢂꢔ
ꢄ.ꢑꢃꢘ
ꢊꢀ
ꢖ
Rꢈ
ꢈꢈꢆꢟ
ꢊꢀ
ꢑꢑꢙꢠꢇ
ꢈꢃ.ꢅꢀ ꢊꢇꢇ
ꢈꢄ.ꢉꢀ ꢊꢂ
ꢃꢄꢅꢆ ꢇꢈꢉ
Figure 19. Series Hysteretic Solar Charger with Reverse-Battery and Solar Panel Protection
Rev. B
16
For more information www.analog.com
LTC4365
APPLICATIONS INFORMATION
Note that during initial start-up, the LTC4365-1 will not handling capability, drain and gate breakdown voltages,
and threshold voltage.
turn on the external MOSFETs until a battery is first con-
nected to the V pin. To begin operation, V must initially
rise above the 2.2V UVLO lockout voltage. Connecting the
battery ensures that the LTC4365-1 comes out of UVLO.
IN
IN
The drain to source breakdown voltage must be higher
thanthemaximumvoltageexpectedbetweenV andV
Notethatifanapplicationgenerateshighenergytransients
duringnormaloperationorduringHotSwap™,theexternal
MOSFET must be able to withstand this transient voltage.
.
IN
OUT
12V Application with 150V Transient Protection
Figure 20 shows a 12V application that withstands input
supply transients up to 150V. When the input voltage ex-
ceeds 17.9V, the OV resistive divider turns off the external
Due to the high impedance nature of the charge pump that
drivestheGATEpin,thetotalleakageontheGATEpinmust
bekeptlow.ThegatedrivecurvesofFigure2weremeasured
with a 1µA load on the GATE pin. Therefore, the leakage on
theGATEpinmustbenogreaterthan1µAinordertomatch
the curves of Figure 2. Higher leakage currents will result
in lower gate drive. The dual N-channel MOSFETs shown
in Table 1 all have a maximum GATE leakage current of
100nA. Additionally, Table 1 lists representative MOSFETs
MOSFETs. As V rises to 150V, the gate of transistor M1
IN
remains in the Off condition, thus preventing conduction
from V to V . Note that M1 must have an operating
IN
OUT
range above 150V.
Resistor R6 and diode D3 clamp the LTC4365 supply volt-
age to 50V. To prevent R6 from interfering with reverse
operation, the recommended value is 1k or less. Note that
the power handling capability of R6 must be considered in
order to avoid overheating during transients. D3 is shown
asabidirectionalclampinordertoachievereverse-polarity
that would work at different values of V .
IN
Layout Considerations
The trace length between the V pin and the drain of the
IN
protection at V . M2 is also required in order to protect
IN
externalMOSFETshouldbeminimized,aswellasthetrace
length between the GATE pin of the LTC4365 and the gates
of the external MOSFETs.
V
OUT
from negative voltages at V and should have an
IN
operating range beyond the breakdown of D3. If reverse
protection is not desired remove M2 and connect the
source of M1 directly to V
.
Place the bypass capacitors at V
as close as possible
OUT
OUT
to the external MOSFET. Use high frequency ceramic
capacitors in addition to bulk capacitors to mitigate Hot
Swap ringing. Place the high frequency capacitors closest
to the MOSFET. Note that bulk capacitors mitigate ringing
by virtue of their ESR. Ceramic capacitors have low ESR
and can thus ring near their resonant frequency.
MOSFET Selection
To protect against a negative voltage at V , the external
IN
N-channel MOSFETs must be configured in a back-to-
back arrangement. Dual N-channel packages are thus the
best choice. The MOSFET is selected based on its power
ꢘꢉBꢊꢊꢂꢙꢗ
ꢍꢆ ꢍꢙ
ꢀ
ꢁꢂ
ꢀ
ꢄꢃꢔ
ꢆꢙꢀ
Rꢖ
ꢆꢜ
ꢛꢎꢔꢓ
ꢀ
ꢁꢂ
ꢀ
ꢄꢃꢔ
Rꢊ
ꢗꢆꢚꢜ
ꢕꢔꢑꢐꢊꢖꢗ
ꢉꢊ
SHDN
ꢃꢀ
Rꢙ
ꢙꢚꢗꢚꢜ
FAULT
ꢄꢀ ꢅ ꢆꢇ.ꢈꢀ
ꢄꢀ
Rꢆ
ꢗꢈꢜ
ꢛꢂꢉ
ꢉꢊꢋ ꢌꢍꢎꢏꢐꢊꢑꢎ BꢁꢒꢉꢁRꢓꢑꢔꢁꢄꢂꢎꢕ
ꢐꢊꢖꢗ ꢘꢙꢚ
Figure 20. 12V Application Protected from 150V Transients
Rev. B
17
For more information www.analog.com
LTC4365
PACKAGE DESCRIPTION
TS8 Package
8-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1637 Rev A)
ꢌ.ꢚꢂ Bꢎꢏ
ꢅꢆꢇꢈꢉ ꢊꢋ
ꢂ.ꢊꢂ
ꢗꢕꢝ
ꢂ.ꢑꢁ
Rꢉꢞ
ꢀ.ꢌꢌ Rꢉꢞ
ꢀ.ꢁꢂ ꢃ ꢀ.ꢄꢁ
ꢅꢆꢇꢈꢉ ꢊꢋ
ꢌ.ꢍꢂ Bꢎꢏ
ꢀ.ꢊ ꢗꢟꢆ
ꢐ.ꢍꢁ ꢗꢕꢝ ꢌ.ꢑꢌ Rꢉꢞ
ꢒꢟꢆ ꢇꢆꢉ ꢟꢔ
Rꢉꢏꢇꢗꢗꢉꢆꢔꢉꢔ ꢎꢇꢓꢔꢉR ꢒꢕꢔ ꢓꢕꢧꢇꢖꢈ
ꢒꢉR ꢟꢒꢏ ꢏꢕꢓꢏꢖꢓꢕꢈꢇR
ꢂ.ꢌꢌ ꢃ ꢂ.ꢐꢑ
ꢍ ꢒꢓꢏꢎ ꢅꢆꢇꢈꢉ ꢐꢋ
ꢂ.ꢑꢁ Bꢎꢏ
ꢂ.ꢍꢂ ꢃ ꢂ.ꢚꢂ
ꢂ.ꢌꢂ Bꢎꢏ
ꢔꢕꢈꢖꢗ ꢘꢕꢙ
ꢂ.ꢂꢀ ꢃ ꢂ.ꢀꢂ
ꢀ.ꢂꢂ ꢗꢕꢝ
ꢂ.ꢐꢂ ꢃ ꢂ.ꢁꢂ Rꢉꢞ
ꢀ.ꢚꢁ Bꢎꢏ
ꢈꢎꢍ ꢈꢎꢇꢈꢛꢌꢐ ꢂꢄꢀꢂ Rꢉꢜ ꢕ
ꢂ.ꢂꢚ ꢃ ꢂ.ꢌꢂ
ꢅꢆꢇꢈꢉ ꢐꢋ
ꢆꢇꢈꢉꢠ
ꢀ. ꢔꢟꢗꢉꢆꢎꢟꢇꢆꢎ ꢕRꢉ ꢟꢆ ꢗꢟꢓꢓꢟꢗꢉꢈꢉRꢎ
ꢌ. ꢔRꢕꢡꢟꢆꢢ ꢆꢇꢈ ꢈꢇ ꢎꢏꢕꢓꢉ
ꢐ. ꢔꢟꢗꢉꢆꢎꢟꢇꢆꢎ ꢕRꢉ ꢟꢆꢏꢓꢖꢎꢟꢜꢉ ꢇꢞ ꢒꢓꢕꢈꢟꢆꢢ
ꢊ. ꢔꢟꢗꢉꢆꢎꢟꢇꢆꢎ ꢕRꢉ ꢉꢝꢏꢓꢖꢎꢟꢜꢉ ꢇꢞ ꢗꢇꢓꢔ ꢞꢓꢕꢎꢣ ꢕꢆꢔ ꢗꢉꢈꢕꢓ BꢖRR
ꢁ. ꢗꢇꢓꢔ ꢞꢓꢕꢎꢣ ꢎꢣꢕꢓꢓ ꢆꢇꢈ ꢉꢝꢏꢉꢉꢔ ꢂ.ꢌꢁꢊꢤꢤ
ꢑ. ꢥꢉꢔꢉꢏ ꢒꢕꢏꢦꢕꢢꢉ RꢉꢞꢉRꢉꢆꢏꢉ ꢟꢎ ꢗꢇꢛꢀꢚꢐ
DDB Package
8-Lead Plastic DFN (3mm × 2mm)
(Reference LTC DWG # 05-08-1702 Rev B)
0.61 0.05
(2 SIDES)
R = 0.115
0.40 ± 0.10
3.00 0.10
(2 SIDES)
TYP
5
R = 0.05
8
TYP
0.70 0.05
2.55 0.05
1.15 0.05
2.00 ±0.10
PIN 1 BAR
(2 SIDES)
TOP MARK
PIN 1
R = 0.20 OR
(SEE NOTE 6)
0.25 × 45°
PACKAGE
OUTLINE
0.56 ± 0.05
CHAMFER
(2 SIDES)
4
1
(DDB8) DFN 0905 REV B
0.25 0.05
0.25 0.05
0.75 ±0.05
0.200 REF
0.50 BSC
2.20 0.05
(2 SIDES)
0.50 BSC
2.15 ±0.05
(2 SIDES)
0 – 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING CONFORMS TO VERSION (WECD-1) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
Rev. B
18
For more information www.analog.com
LTC4365
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
09/13 Added LTC4365-1 Information
Multiple
8, 9
Operation section: Rewritten with new Figure 1
Table 1: MOSFET for ≤30V changed to Si4214 from Si4230
Figure 13: Inserted R5, 100k resistor to SHDN pin
Added "Regulator Applications" with three subsections and Figures 17 to 20
Updated Typical Application
10
14
16, 17
20
B
09/19 Added AEC-Q100 qualification and "W” part numbers
1, 3
Revised application examples (Figures 2 and 4) to support V
= 5V to 18V
9-12
OUT
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
19
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
LTC4365
TYPICAL APPLICATION
LTC4365 Protects Step Down Regulator from –40V to 40V VIN Faults
ꢒꢓꢒBꢊꢈꢔꢂ
ꢔꢃꢍꢕ ꢂꢖꢗꢘꢍꢂꢂꢑꢕ
ꢀ
ꢄꢃꢌ
ꢄꢃꢌꢙꢃꢌ
ꢉꢀ
ꢋ.ꢉꢍ
ꢀ
ꢁꢂ
ꢆꢏꢀ ꢂꢄꢛꢁꢂꢍꢕ
ꢆꢎꢞꢚ
ꢀ
ꢙRꢄꢌꢑꢗꢌꢑꢔ
ꢄꢃꢌ
ꢀ
Bꢔ
ꢁꢂ
ꢚRꢄꢛ ꢜꢊꢎꢀ ꢌꢄ ꢊꢎꢀ
Rꢃꢂꢢꢒꢒ Bꢄꢄꢒꢌ
ꢕꢌꢆꢟꢆꢋ
ꢎ.ꢊꢠꢞꢚ
ꢊ.ꢠꢞꢘ
ꢐꢍꢌꢑ
ꢀ
ꢀ
ꢄꢃꢌ
ꢁꢂ
ꢆꢉꢝ
ꢈꢇꢎꢤꢚ
ꢕꢌꢗꢊꢋꢈꢉ
ꢀ
ꢒꢡ
ꢗ
ꢉꢆꢎꢝ
SHDN
Rꢌ
ꢙꢐ
ꢆꢇꢏꢎꢝ
ꢉꢋꢈꢝ
ꢆꢎꢎꢝ
ꢚB
ꢃꢀ
FAULT
ꢐꢂꢔ
ꢒꢣꢂꢗ
ꢈꢋ.ꢊꢝ
ꢊꢠꢞꢚ
ꢟꢠ.ꢈꢝ
ꢉꢊ.ꢟꢝ
ꢄꢀ
ꢄꢀ ꢅ ꢆꢇꢀ
ꢃꢀ ꢅ ꢈ.ꢉꢀ
ꢊꢋꢈꢉ ꢌꢍꢎꢏ
ꢐꢂꢔ
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
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Regulator
Wide Operating Range: 4V to 80V, Reverse Protection to –60V, Adjustable
Output Clamp Voltage
LTC4364
Surge Stopper with Ideal Diode
Floating Surge Stopper
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Pin Selectable Input Polarity Allows Negative and OV Monitoring
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For Positive and Negative Supplies
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Triple/Dual Inputs UV/OV Negative Monitor
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2
ADC and I C
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LT1913
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External N-Channel MOSFETs Replace ORing Diodes, 0V to 18V
Controls Two N-Channel MOSFETs, 1.2µs Turn-Off, –80V Operation
Controls Two N-Channel MOSFETs, 0.4µs Turn-Off, 80V Operation
3.6V to 25V Input, 3.5A Maximum Current, 200kHz to 2.4MHz
Negative Voltage Diode-OR Controller
Positive Voltage Diode-OR Controller
Step-Down Switching Regulator
Rev. B
09/19
www.analog.com
20
ANALOG DEVICES, INC. 2013–2019
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