LTC4301CMS8#PBF_技术文档

LTC4301

Supply Independent Hot

Swappable 2-Wire Bus Buffer

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FEATURES

DESCRIPTIO

TheLTC^®4301supplyindependent,hotswappable,2-wire

bus buffer allows I/O card insertion into a live backplane

without corruption of the data and clock busses. In addi-

tion, the LTC4301 allows the V_CC, SDAIN and SCLIN pull-

up voltage and the SDAOUT and SCLOUT pull-up voltage

to be independent from each other. Control circuitry

prevents the backplane from being connected to the card

until a stop bit or a bus idle is present. When the connec-

tion is made, the LTC4301 provides bidirectional buffer-

ing,keepingthebackplaneandcardcapacitancesisolated.

■

Allows Bus Pull-Up Voltages Above or Below V_CC

■

Bidirectional Buffer* for SDA and SCL Lines

Increases Fanout

■

Prevents SDA and SCL Corruption During Live Board

Insertion and Removal from Backplane

■

Isolates Input SDA and SCL Line from Output

■

10kV Human Body Model ESD Protection

■

1V Precharge On All SDA and SCL Lines

■

Supports Clock Stretching, Arbitration and

Synchronization

■

High Impedance SDA, SCL Pins for V_CC= 0V

During insertion, the SDA and SCL lines are precharged to

1Vtominimizebusdisturbances. Whendrivenlow, theCS

input pin allows the part to connect after a stop bit or bus

idle occurs. Driving CS high breaks the connection be-

tween SCLIN and SCLOUT and between SDAIN and

SDAOUT. The READY output pin indicates that the back-

plane and card sides are connected together.

■

CS Gates Connection from Input to Output

Compatible with I²C^TM, I²C Fast Mode and SMBus

■

Standards (Up to 400kHz Operation)

■

^{Small 8-Pin MSO}U^{P and DFN (3mm × 3mm) Packages}

APPLICATIO S

■

Hot Board Insertion

Servers

The LTC4301 is offered in 8-pin DFN (3mm × 3mm) and

MSOP packages.

■

Capacitance Buffer/Bus Extender

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

Protected by U.S. Patents including 7032051.

■

Desktop Computers

CompactPCI^TMand ATCA Systems

■

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TYPICAL APPLICATIO

Input-Output Connection

3.3V 5V

0.01µF

10k 10k

V

CC

10k 10k

LTC4301

SCLIN

SDAIN

CS

SCLOUT

SDAOUT

BACK_SCL

BACK_SDA

CARD_SCL

INPUT

SIDE

55pF

OUTPUT

SIDE

20pF

CARD_SDA

1V/DIV

5V

10k

READY

GND

4301 TA01b

1µs/DIV

4301 TA01

BACKPLANE

CONNECTOR

CARD

4301fb

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LTC4301

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ABSOLUTE MAXIMUM RATINGS ^{(Note 1)}

V_CCto GND ................................................. –0.3V to 7V

SDAIN, SCLIN, SDAOUT, SCLOUT, CS ........ –0.3V to 7V

READY ........................................................ –0.3V to 6V

Operating Temperature Range

Storage Temperature Range

MSOP ............................................... –65°C to 150°C

DFN .................................................. –65°C to 125°C

Lead Temperature (Soldering, 10 sec).................. 300°C

LTC4301C ............................................... 0°C to 70°C

LTC4301I............................................ – 40°C to 85°C

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PACKAGE/ORDER INFORMATION

TOP VIEW

ORDER PART

NUMBER

CS

SCLOUT

SCLIN

GND

1

2

3

4

8

7

6

5

V

CC

TOP VIEW

LTC4301CDD

LTC4301IDD

LTC4301CMS8

LTC4301IMS8

SDAOUT

SDAIN

CS

SCLOUT

SCLIN

GND

1

2

3

4

8 V

CC

9

7 SDAOUT

6 SDAIN

5 READY

READY

DD PART

MARKING*

MS8 PART

MARKING*

MS8 PACKAGE

8-LEAD PLASTIC MSOP

T_JMAX= 125°C, θ_JA= 200°C/W

DD PACKAGE

8-LEAD (3mm × 3mm) PLASTIC DFN

T_JMAX= 125°C, θ_JA= 43°C/W

LBBY

LTBBW

EXPOSED PAD (PIN 9)

PCB CONNECTION OPTIONAL

Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF

Lead Free Part Marking: http://www.linear.com/leadfree/

*The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS ^The

●

indicates specifications which apply over the full operating

temperature range, otherwise specifications are at T = 25°C. V = 2.7V to 5.5V, unless otherwise noted.

A

CC

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Power Supply

V

Positive Supply Voltage

Supply Current

●

2.7

5.5

6.2

V

CC

I

V

= 5.5V, V

= 5.5V, CS = 5.5V

= V = 0V

SCLIN

4.5

300

mA

µA

CC

SDAIN

Start-Up Circuitry

V

Precharge Voltage

SDA, SCL Floating

●

0.85

60

1.05

95

1.25

175

0.4

2

V

µs

V

PRE

t

Bus Idle Time

IDLE

RDY

READY Output Low Voltage

Connection Sense Threshold

CS Input Current

I

= 3mA

PULLUP

VOL

V

0.8

1.4

±0.1

1.8

V

THRCS

I

CS from 0V to V

Rising Edge

(Note 3)

±1

µA

V

CS

CC

V

SDA, SCL Logic Input Threshold Voltage

1.55

2.0

THR

HYS

SDA, SCL Logic Input Threshold Voltage

Hysteresis

50

mV

t

I

CS Delay On-Off

READY Delay Off-On

10

ns

PLH

PHL

OFF

CS Delay Off-On

READY Delay On-Off

95

10

µs

ns

Ready Off Leakage Current

±0.1

µA

4301fb

2

LTC4301

The

●

indicates specifications which apply over the full operating

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T = 25°C. V = 2.7V to 5.5V, unless otherwise noted.

A

CC

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Input-Output Connection

V

C

Input-Output Offset Voltage

10k to V on SDA, SCL, V = 3.3V,

SDA or SCL = 0.2V (Note 2)

●

0

100

175

10

mV

pF

OS

IN

CC

Digital Input Capacitance SDAIN, SDAOUT,

SCLIN, SCLOUT

(Note 3)

I

Input Leakage Current

SDA, SCL Pins

±5

µA

LEAK

V

Output Low Voltage, Input = 0V

SDA, SCL Pins, I

= 3mA, V = 2.7V

0

0.4

V

OL

SINK

CC

Timing Characteristics

2

f

t

I C Maximum Operating Frequency

(Note 3)

400

600

kHz

I2C,MAX

BUF

Bus Free Time Between Stop and Start

Condition

1.3

µs

t

Hold Time After (Repeated) Start Condition (Note 3)

100

0

ns

HD,STA

SU,STA

SU,STO

HD,DATI

SU,DAT

Repeated Start Condition Set-Up Time

Stop Condition Set-Up Time

Data Hold Time Input

(Note 3)

0

Data Set-Up Time

100

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The connection circuitry always regulates its output to a higher

voltage than its input. The magnitude of this offset voltage as a function of

the pull-up resistor and V voltage is shown in the Typical Performance

CC

Characteristics section.

Note 3: Determined by design, not tested in production.

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TYPICAL PERFOR A CE CHARACTERISTICS

Input – Output High to Low

Propagation Delay vs Temperature

I

CC

vs Temperature

Connection Circuitry V – V

OUT IN

4.9

4.8

4.7

4.6

4.5

4.4

4.3

4.2

4.1

4.0

3.9

300

250

200

150

100

50

100

80

60

40

20

0

T

= 25°C

IN

A

V

= 2.7V

= 3.3V

CC

= 0V

V

= 5.5V

CC

V

= 3.3V

= 2.7V

CC

V

= 5V

CC

V

= 5.5V

CC

V

= 3.3V

CC

C

= C

PULLUPIN

= 100pF

OUT

IN

R

= R

= 10k

PULLUPOUT

0

–80 –60 –40 –20

0

20 40 60 80 100

0

10,000

20,000

(Ω)

30,000

40,000

–50

–25

0

25

50

75

100

TEMPERATURE (°C)

R

TEMPERATURE (°C)

PULLUP

4301 G01

4301 G03

4301 G02

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LTC4301

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PI FU CTIO S

CS (Pin 1): The connection sense pin is a 1.4V threshold

digital input pin. For normal operation CS is grounded.

Driving CS above the 1.4V threshold isolates SDAIN from

SDAOUT and SCLIN from SCLOUT and asserts READY

low.

when the start-up sequence described in the Operation

section has not been completed. READY goes high when

CS is low and a start-up is complete.

SDAIN (Pin 6): Serial Data Input. Connect this pin to the

SDA bus on the backplane.

SCLOUT (Pin 2): Serial Clock Output. Connect this pin to

the SCL bus on the card.

SDAOUT (Pin 7): Serial Data Output. Connect this pin to

the SDA bus on the card.

SCLIN (Pin 3): Serial Clock Input. Connect this pin to SCL

on the bus backplane.

V

_CC(Pin 8): Main Input Supply. Place a bypass capacitor

of at least 0.01µF close to V_CCfor best results.

GND (Pin 4): Ground. Connect this pin to a ground plane

for best results.

Exposed Pad (Pin 9): Exposed pad may be left open or

connected to device ground.

READY(Pin5):TheREADYpinisanopendrainN-channel

MOSFET output which pulls down when CS is high or

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BLOCK DIAGRA

LTC4301 Supply Independent 2-Wire Bus Buffer

PRECHARGE

CONNECT

V

8

7

CC

PRECHARGE

CONNECT

PRECHARGE

CONNECT

R1

R2

R3

200k

R4

200k

200k 200k

SDAOUT

SCLOUT

SDAIN

SCLIN

6

3

CONNECT

2

PRECHARGE

CONNECT

LOGIC

1.8V

READY

CONNECT

CS

5

1

95µs

DELAY

UVLO

1.4V

GND

4

4301 BD

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LTC4301

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OPERATIO

Start-Up

and card capacitances isolated. Because of this isolation,

the waveforms on the backplane busses look slightly

different than the corresponding card bus waveforms as

described here.

When the LTC4301 first receives power on its V_CCpin,

either during power-up or live insertion, it starts in an

undervoltage lockout (UVLO) state, ignoring any activity

ontheSDAorSCLpinsuntilV_CCrisesabove2.5V(typical).

This is to ensure that the part does not try to function until

it has enough voltage to do so.

Input-to-Output Offset Voltage

When a logic low voltage, V_LOW1, is driven on any of the

LTC4301’s data or clock pins, the LTC4301 regulates the

voltage on the other side of the device (call it V_LOW2) at a

slightly higher voltage, as directed by the following

equation:

During this time, the 1V precharge circuitry is active and

forces 1V through 200k nominal resistors to the SDA and

SCL pins. Because the I/O card is being plugged into a live

backplane, the voltage on the backplane SDA and SCL

bussesmaybeanywherebetween0VandV_CC.Precharging

the SCL and SDA pins to 1V minimizes the worst-case

voltage differential these pins will see at the moment of

connection, therefore minimizing the amount of distur-

bance caused by the I/O card.

V_LOW2= V_LOW1+ 75mV + (V_CC/R) • 70Ω (typical)

where R is the bus pull-up resistance in ohms. For ex-

ample, if a device is forcing SDAOUT to 10mV where V_CC

= 3.3V and the pull-up resistor R on SDAIN is 10k, then the

voltage on SDAIN = 10mV + 75mV + (3.3/10000) • 70 =

108mV (typical). See the Typical Performance Character-

istics section for curves showing the offset voltage as a

function of V_CCand R.

Once the LTC4301 comes out of UVLO, it assumes that

SDAIN and SCLIN have been inserted into a live system

and that SDAOUT and SCLOUT are being powered up at

the same time as itself. Therefore, it looks for either a stop

bit or bus idle condition on the backplane side to indicate

the completion of a data transaction. When either one

occurs, the part also verifies that both the SDAOUT and

SCLOUT voltages are high. When all of these conditions

are met, the input-to-output connection circuitry is acti-

vated, joiningtheSDAandSCLbussesontheI/Ocardwith

those on the backplane.

Propagation Delays

During a rising edge, the rise time on each side is deter-

mined by the bus pull-up resistor and the equivalent

capacitance on the line. If the pull-up resistors are the

same, a difference in rise time occurs which is directly

proportional to the difference in capacitance between

the two sides. This effect is displayed in Figure 1 for

V_CC= 5V and a 10k pull-up resistor on each side (55pF on

one side and 20pF on the other). SDAIN and SCLIN are

pulled-up to 3.3V, and SDAOUT and SCLOUT are pulled-

up to 5V. Since the output side has less capacitance than

the input, it rises faster and the effective low to high

propagation delay is negative.

Connection Circuitry

Once the connection circuitry is activated, the functional-

ity of the SDAIN and SDAOUT pins is identical. A low

forced on either pin at any time results in both pin voltages

being low. For proper operation, logic low input voltages

should be no higher than 0.4V with respect to the ground

pin voltage of the LTC4301. SDAIN and SDAOUT enter a

logic high state only when all devices on both SDAIN and

SDAOUT release high. The same is true for SCLIN and

SCLOUT.Thisimportantfeatureensuresthatclockstretch-

ing, clock synchronization, arbitration and the acknowl-

edge protocol always work, regardless of how the devices

in the system are tied to the LTC4301.

INPUT

SIDE

55pF

OUTPUT

SIDE

20pF

1V/DIV

4301 F01

1µs/DIV

Another key feature of the connection circuitry is that it

provides bidirectional buffering, keeping the backplane

Figure 1. Input-Output Connection

4301fb

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LTC4301

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OPERATIO

There is a finite high to low propagation delay through the

connectioncircuitryforfallingwaveforms. Figure2shows

the falling edge waveforms for the same pull-up resistors

and equivalent capacitance conditions as used in Figure 1.

An external N-channel MOSFET device pulls down the

voltage on the side with 55pF capacitance; LTC4301 pulls

downthevoltageontheoppositesidewithadelayof60ns.

This delay is always positive and is a function of supply

voltage, temperatureandthepull-upresistorsandequiva-

lentbuscapacitancesonbothsidesofthebus. TheTypical

Performance Characteristics section shows high to low

propagation delay as a function of temperature and volt-

age for 10k pull-up resistors pulled-up to V_CCand 100pF

equivalent capacitance on both sides of the part. Larger

output capacitances translate to longer delays (up to

150ns). Users must quantify the difference in propagation

times for a rising edge versus a falling edge in their

systems and adjust setup and hold times accordingly.

Ready Digital Output

This pin provides a digital flag which is low when either CS

is high or the start-up sequence described earlier in this

section has not been completed. READY goes high when

CS is low and start-up is complete. The pin is driven by an

open-drain pull-down capable of sinking 3mA while hold-

ing 0.4V on the pin. Connect a resistor of 10k to V_CCto

provide the pull-up.

Connection Sense

When the CS pin is driven above 1.4V with respect to the

LTC4301’s ground, the backplane side is disconnected

from the card side and the READY pin is internally pulled

low. When the pin voltage is low, the part waits for data

transactions on both the backplane and card sides to be

complete (as described in the Start-Up section) before

reconnecting the two sides. At this time the internal

pulldown on READY releases.

OUTPUT

SIDE

20pF

INPUT

SIDE

55pF

1V/DIV

4301 F02

20ns/DIV

Figure 2. Input-Output Connection

High to Low Propagation Delay

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LTC4301

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APPLICATIO S I FOR ATIO

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Live Insertion and Capacitance Buffering Application

on the edge of each card, however, isolates the card

capacitance from the backplane. For a given I/O card, the

LTC4301 drives the capacitance of everything on the card

and the backplane must drive only the capacitance of the

LTC4301, which is less than 10pF.

Figures 3 illustrates applications of the LTC4301 with

different bus pull-up and V_CCvoltages, demonstrating its

ability to recognize and buffer bus data levels that are

above or below its V_CCsupply. All of these applications

take advantage of the LTC4301’s Hot Swap^TMcontrolling,

capacitance buffering and precharge features. If the I/O

cardswerepluggeddirectlyintothebackplanewithoutthe

LTC4301 buffer, all of the backplane and card capaci-

tances would add directly together, making rise- and fall-

time requirements difficult to meet. Placing an LTC4301

In most applications the LTC4301 will be used with a

staggeredconnectorwhereV_CCandGNDwillbelongpins.

SDA and SCL are medium length pins to ensure that the

V_CCand GND pins make contact first. This will allow the

precharge circuitry to be activated on SDA and SCL before

Hot Swap is a trademark of Linear Technology Corporation.

5V

0.01µF

10k 10k

10k

3.3V

10k 10k

V

CC

SDAOUT

SCLOUT

READY

CARD_SDA

CARD_SCL

CS

SDA

SCL

LTC4301

GND

SDAIN

SCLIN

BACKPLANE

CONNECTOR

CARD

3.3V

0.01µF

10k 10k

10k

5V

10k 10k

V

CC

SDAOUT

SCLOUT

READY

CARD_SDA

CARD_SCL

CS

SDA

SCL

LTC4301

GND

SDAIN

SCLIN

BACKPLANE

CONNECTOR

CARD

2.5V

3.3V

0.01µF

10k 10k

10k

5V

10k 10k

V

CC

SDAOUT

SCLOUT

CARD_SDA

CARD_SCL

CS

SDA

SCL

LTC4301

GND

SDAIN

SCLIN

READY

4301 F03

BACKPLANE

CONNECTOR

CARD

Figure 3. Typical Supply Independent Applications

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LTC4301

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APPLICATIO S I FOR ATIO

they make contact. CS is a short pin that is pulled up when

not connected. This is to ensure that the connection

between the backplane and the cards data and clock

busses is not enabled until the transients associated with

live insertion have settled.

Figure 4 shows the LTC4301 in a CompactPCI^TMconfigu-

ration. The LTC4301 receives its V_CCvoltage from one of

the long “early power” pins. Because this power is not

switched, add a 5Ω to 10Ω resistor between V_CCof the

LTC4301 and the connector V_CCpin. Establishing early

power V_CCensures that the 1V precharge voltage is

present at SDAIN and SCLIN before they make contact.

The CS pin is driven by the CompactPCI’s BD_SEL# pin

using a short pin. This is to ensure that a connection is not

enabled until the transients associated with live insertion

have settled.

Figure 5 shows the LTC4301 in a PCI application where all

of the pins have the same length. In this case, an RC filter

circuit on the I/O card with a product of 10ms provides a

CompactPCI is a trademark of the PCI Industrial Computer Manufacturers Group.

BACKPLANE

CONNECTOR

BACKPLANE

I/O PERIPHERAL CARD 1

5.1Ω

V

CC

0.01µF

R4

10k

R5

10k

R6

10k

V

CC2

R3

10k

R1

10k

R2

10k

V

CC

SDAOUT

SCLOUT

READY

CARD_SDA

CARD_SCL

BD_SEL

SDA

CS

SDAIN

SCLIN

LTC4301

GND

SCL

I/O PERIPHERAL CARD 2

0.01µF

5.1Ω

R8

10k

R9

10k

R10

10k

R7

10k

V

CC

SDAOUT

SCLOUT

READY

CARD2_SDA

CARD2_SCL

CS

LTC4301

GND

SDAIN

SCLIN

I/O PERIPHERAL CARD N

0.01µF

5.1Ω

R12

10k

R13

10k

R14

10k

R11

10k

V

CC

SDAOUT

SCLOUT

READY

CARDN_SDA

CARDN_SCL

CS

LTC4301

GND

SDAIN

SCLIN

4301 F03

Figure 4. Inserting Multiple I/O Cards into a Live Backplane Using the LTC4301 in a CompactPCI System

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LTC4301

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APPLICATIO S I FOR ATIO

BACKPLANE

CONNECTOR

BACKPLANE

I/O PERIPHERAL CARD 1

V

CC

0.01µF

R4

10k

R5

10k

R6

10k

0.1µF

V

CC2

V

R1

10k

R2

10k

R3

100k

CC

SDAOUT

SCLOUT

READY

CARD_SDA

CARD_SCL

CS

SDAIN

SCLIN

LTC4301

GND

SDA

SCL

I/O PERIPHERAL CARD 2

0.01µF

R8

10k

R9

10k

R10

10k

0.1µF

V

CC

R7

100k

SDAOUT

SCLOUT

READY

CARD2_SDA

CARD2_SCL

CS

SDAIN

SCLIN

LTC4301

GND

4301 F05

•

Figure 5. Inserting Multiple I/O Cards into a Live Backplane Using the LTC4301 in a PCI System

system to meet rise- and fall-time requirements. In this

situation, the differential ground voltage between the two

systems may limit the allowed distance, because valid

logic low voltage with respect to the ground at one end of

the system may violate the allowed V_OLspecification with

respect to the ground at the other end. In addition, the

connection circuitry offset voltages of the back-to-back

LTC4301s add together, directly contributing to the same

problem.

filter to prevent the LTC4301 from becoming activated

until the transients associated with live insertion have

settled. Connect the capacitor between V_CCand CS, and

the resistor from CS to GND.

Repeater/Bus Extender Application

Users who wish to connect two 2-wire systems separated

by a distance can do so by connecting two LTC4301s

back-to-back as shown in Figure 6. The I²C specification

allows for 400pF maximum bus capacitance, severely

limiting the length of the bus. The SMBus specification

places no restriction on bus capacitance, but the limited

impedances of devices connected to the bus require

systems to remain small if rise- and fall-time specifica-

tions are to be met. Using the LTC4301 allows the capaci-

tance to be isolated into smaller sections, enabling the

Systems with Supply Voltage Droop

In large 2-wire systems, the V_CCvoltages seen by devices

at various points in the system can differ by a few hundred

millivoltsormore.Thissituationiswellmodelledbyaseries

resistor in the V_CCline as shown in Figure 7. For proper

operation, make sure that the V_CC(LTC4301)is ≥ 2.7V.

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LTC4301

APPLICATIO S I FOR ATIO

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V

CC3

V

CC1

CC4

CC2

CC5

0.01µF

R5

10k

R2

R3

R6

10k

R1

10k

R4

10k

R7

10k

R8

10k

LTC4301

5.1k 5.1k

V

CC

V

CC

CS

SDAOUT

SCLOUT

READY

SDAOUT

SDAIN

SCLIN

SCLOUT

READY

SDAIN

SCLIN

SDA1

SDA2

SCL1

TO OTHER

SYSTEM 1

DEVICES

SCL2

TO OTHER

SYSTEM 2

DEVICES

GND

LONG

DISTANCE

BUS

4301 F07

Figure 6. Repeater/Bus Extender Application

R

DROP

V

CC

V

CC

(BUS)

0.01µF

R1

10k

R2

10k

R3

10k

R4

10k

R5

10k

V

CC

CS

SDAOUT

SCLOUT

READY

SDA2

SCL2

SDAIN

SCLIN

LTC4301

GND

SDA

SCL

4301 F06

Figure 7. System with V Voltage Droop

CC

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LTC4301

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PACKAGE DESCRIPTIO

DD Package

8-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1698)

R = 0.115

0.38 ± 0.10

TYP

5

8

0.675 ±0.05

3.5 ±0.05

2.15 ±0.05 (2 SIDES)

1.65 ±0.05

3.00 ±0.10 1.65 ± 0.10

(4 SIDES)

(2 SIDES)

PIN 1

TOP MARK

(NOTE 6)

(DD8) DFN 1203

4

1

PACKAGE

OUTLINE

0.25 ± 0.05

0.75 ±0.05

0.200 REF

0.25 ± 0.05

0.50 BSC

0.50

BSC

2.38 ±0.05

(2 SIDES)

2.38 ±0.10

(2 SIDES)

0.00 – 0.05

BOTTOM VIEW—EXPOSED PAD

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

NOTE:

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON TOP AND BOTTOM OF PACKAGE

MS8 Package

8-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1660)

3.00 ± 0.102

(.118 ± .004)

(NOTE 3)

0.52

(.0205)

REF

8

7 6

5

3.00 ± 0.102

(.118 ± .004)

(NOTE 4)

4.90 ± 0.152

(.193 ± .006)

DETAIL “A”

0° – 6° TYP

0.889 ± 0.127

(.035 ± .005)

0.254

(.010)

GAUGE PLANE

1

2

3

4

5.23

(.206)

MIN

3.20 – 3.45

(.126 – .136)

0.53 ± 0.152

(.021 ± .006)

1.10

(.043)

MAX

0.86

(.034)

REF

DETAIL “A”

0.18

(.007)

0.65

(.0256)

BSC

0.42 ± 0.038

(.0165 ± .0015)

SEATING

PLANE

TYP

0.22 – 0.38

0.127 ± 0.076

(.009 – .015)

RECOMMENDED SOLDER PAD LAYOUT

(.005 ± .003)

0.65

(.0256)

BSC

TYP

MSOP (MS8) 0204

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

4301fb

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

11

LTC4301

U

TYPICAL APPLICATIO

3.3V 5V

0.01µF

10k 10k

V

CC

10k 10k

LTC4301

SCLIN

SCLOUT

SDAOUT

BACK_SCL

CARD_SCL

SDAIN

CS

BACK_SDA

CARD_SDA

5V

10k

FROM

MICROPROCESSOR

READY

GND

4301 TA01

BACKPLANE

CONNECTOR

CARD

Figure 8. System with Active Connection Control

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LTC1380/LTC1393

Single-Ended 8-Channel/Differential 4-Channel Analog Low R : 35Ω Single-Ended/70Ω Differential,

ON

Mux with SMBus Interface

Expandable to 32 Single or 16 Differential Channels

LTC1427-50

Micropower, 10-Bit Current Output DAC

with SMBus Interface

Precision 50µA ± 2.5% Tolerance Over Temperature,

4 Selectable SMBus Addresses, DAC Powers up at Zero or Midscale

LTC1623

Dual High Side Switch Controller with SMBus Interface 8 Selectable Addresses/16-Channel Capability

LTC1663

SMBus Interface 10-Bit Rail-to-Rail Micropower DAC

SMBus Accelerator

DNL < 0.75LSB Max, 5-Lead SOT-23 Package

2

LTC1694/LTC1694-1

Improved SMBus/I C Rise-Time,

Ensures Data Integrity with Multiple SMBus/I C Devices

2

LT1786F

LTC1695

LTC1840

SMBus Controlled CCFL Switching Regulator

1.25A, 200kHz, Floating or Grounded Lamp Configurations

0.75Ω PMOS 180mA Regulator, 6-Bit DAC

TM

2

SMBus/I C Fan Speed Controller in ThinSOT

2

Dual I C Fan Speed Controller

Two 100µA 8-Bit DACs, Two Tach Inputs, Four GPI0

Isolates Backplane and Card Capacitances

LTC4300A-1/LTC4300A-2 Hot Swappable 2-Wire Bus Buffer

LTC4301L

Hot Swappable 2-Wire Bus Buffer

with Low Voltage Level Translation

Allows Bus Pull-Up Voltages as Low as 1V on SDAIN and SCLIN

LTC4302-1/LTC4302-2

Addressable 2-Wire Bus Buffer

Address Expansion, GPIO, Software Controlled

ThinSOT is a trademark of Linear Technology Corporation.

4301fb

LT 0806 REV B • PRINTED IN THE USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

12

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC4301CMS8#PBF
厂家：	Linear
描述：	LTC4301 - Supply Independent Hot Swappable 2-Wire Bus Buffer; Package: MSOP; Pins: 8; Temperature Range: 0°C to 70°C 光电二极管
文件：	总12页 (文件大小：201K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC4301CMS8#PBF [Linear]

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