LTC4301LCDD8#PBF_技术文档

LTC4301L

Hot Swappable 2-Wire

Bus Buffer with Low Voltage

Level Translation

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FEATURES

DESCRIPTIO

The LTC^®4301L hot swappable, 2-wire bus buffer allows

I/O card insertion into a live backplane without corruption

of the data and clock busses. In addition, the LTC4301L

SDAIN and SCLIN pins are compatible with systems with

pull-up voltages as low as 1V. Control circuitry prevents

the backplane from being connected to the card until a

stop bit or a bus idle is present. When the connection is

made, the LTC4301L provides bidirectional buffering,

keeping the backplane and card capacitances isolated.

■

Level Translates 1V Signals to Standard 3.3V and

5V Logic Rails

■

Allows Bus Pull-Up Voltages as Low as 1V on

SDAIN and SCLIN

■

Bidirectional Buffer* for SDA and SCL Lines

Increases Fanout

■

Prevents SDA and SCL Corruption During Live Board

Insertion and Removal from Backplane

■

Isolates Input SDA and SCL Line from Output

■

10kV Human Body Model ESD Protection

When driven low, the CS input pin allows the part to

connect after a stop bit or bus idle occurs. Driving CS high

breaks the connection between SCLIN and SCLOUT and

between SDAIN and SDAOUT. A logic high on READY

indicates that the backplane and card sides are connected

together.

■

Supports Clock Stretching, Arbitration and

Synchronization

■

High Impedance SDA, SCL Pins for V_CC= 0V

■

CS Gates Connection from Input to Output

Compatible with I²C^TM, I²C Fast Mode and SMBus

■

Standards (Up to 400kHz Operation)

^{Small 8-Pin MSO}U^{P and DFN (3mm × 3mm) Packages}

The LTC4301L is offered in 8-pin DFN (3mm × 3mm) and

MSOP packages.

, LTC and LT are registered trademarks of Linear Technology Corporation.

I²C is a trademark of Philips Electronics N.V.

*Patent Pending

■

APPLICATIO S

■

Hot Board Insertion

Servers

Capacitance Buffer/Bus Extender

Desktop Computers

■

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TYPICAL APPLICATIO

Input-Output Connection

1.2V

3.3V

0.01µF

2k

10k 10k

SDA

V

CC

SDA

SCL

SDAIN

SDAOUT

INPUT

SIDE

55pF

OUTPUT

SIDE

µP

LTC4301L

20pF

SCL

SCLIN

SCLOUT

0.5V/DIV

CS

READY

GND

4301l TA01a

4301 TA01b

1µs/DIV

4301lf

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LTC4301L

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ABSOLUTE MAXIMUM RATINGS ^{(Note 1)}

V_CCto GND ................................................. –0.3V to 7V

SDAIN, SCLIN, SDAOUT, SCLOUT, CS ........ –0.3V to 7V

READY ........................................................ –0.3V to 6V

Operating Temperature Range

Storage Temperature Range

MSOP ............................................... –65°C to 150°C

DFN .................................................. –65°C to 125°C

Lead Temperature (Soldering, 10 sec).................. 300°C

LTC4301LC ............................................. 0°C to 70°C

LTC4301LI.......................................... – 40°C to 85°C

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PACKAGE/ORDER INFORMATION

TOP VIEW

ORDER PART

NUMBER

CS

SCLOUT

SCLIN

GND

1

2

3

4

8

7

6

5

V

CC

TOP VIEW

LTC4301LCDD8

LTC4301LIDD8

LTC4301LCMS8

LTC4301LIMS8

SDAOUT

SDAIN

CS

SCLOUT

SCLIN

GND

1

2

3

4

8 V

CC

9

7 SDAOUT

6 SDAIN

5 READY

READY

DD8 PART

MARKING

MS8 PART

MARKING

MS8 PACKAGE

8-LEAD PLASTIC MSOP

T_JMAX= 125°C, θ_JA= 200°C/W

DD8 PACKAGE

8-LEAD (3mm × 3mm) PLASTIC DFN

T_JMAX= 125°C, θ_JA= 43°C/W

EXPOSED PAD (PIN 9) IS GND

PCB CONNECTION OPTIONAL

LBHS

LTBHQ

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS ^The● indicates specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_CC= 2.7V to 5.5V, unless otherwise noted.

SYMBOL PARAMETER

Power Supply

CONDITIONS

MIN

TYP

MAX

UNITS

V

Positive Supply Voltage

Supply Current

●

2.7

5.5

6.2

V

CC

I

V

= 5.5V, V

= 5.5V, CS = 5.5V

= V = 0V

SCLIN

4.5

300

mA

µA

CC

SDAIN

Start-Up Circuitry

V

Precharge Voltage

SDAOUT, SCLOUT Floating

●

0.85

60

1.05

95

1.25

175

0.4

2

V

µs

V

PRE

t

Bus Idle Time

IDLE

RDY

READY Output Low Voltage

Connection Sense Threshold

CS Input Current

I

= 3mA

PULLUP

VOL

V

0.8

1.4

V

THRCS

I

CS from 0V to V

±0.1

±1

µA

CS

CC

V

SDAIN, SCLIN Logic Input Threshold Voltage

SDAOUT, SCLOUT Logic Input Threshold Voltage

Rising Edge

0.45

1.55

0.6

1.8

0.75

2.0

V

THR

HYS

PLH

PHL

OFF

V

SDAIN, SCLIN Logic Input Threshold Hysteresis

SDAOUT, SCLOUT Logic Input Threshold Hysteresis (Note 3)

(Note 3)

85

50

mV

t

I

CS Delay On-Off

READY Delay Off-On

10

ns

CS Delay Off-On

READY Delay On-Off

95

10

µs

ns

Ready Off Leakage Current

±0.1

µA

4301lf

2

LTC4301L

The ● indicates specifications which apply over the full operating

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T_A= 25°C. V_CC= 2.7V to 5.5V, unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Input-Output Connection

V

C

Input-Output Offset Voltage

10k to V on SDA, SCL, V = 3.3V,

SDA or SCL = 0.2V (Note 2)

●

0

100

175

10

mV

pF

OS

IN

CC

Digital Input Capacitance SDAIN, SDAOUT,

SCLIN, SCLOUT

(Note 3)

I

Input Leakage Current

SDA, SCL Pins

±5

µA

LEAK

V

Output Low Voltage, Input = 0V

SDA, SCL Pins, I

= 3mA, V = 2.7V

0

0.4

0.2

V

OL

SINK

CC

= 1mA, V = 2.7V

CC

Timing Characteristics

2

f

t

I C Maximum Operating Frequency

(Note 3)

400

600

kHz

I2C,MAX

BUF

Bus Free Time Between Stop and Start

Condition

1.3

µs

t

Hold Time After (Repeated) Start Condition (Note 3)

100

0

ns

HD,STA

SU,STA

SU,STO

HD,DATI

SU,DAT

Repeated Start Condition Set-Up Time

Stop Condition Set-Up Time

Data Hold Time Input

(Note 3)

0

Data Set-Up Time

100

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

the pull-up resistor and V voltage is shown in the Typical Performance

Characteristics section.

CC

Note 2: The connection circuitry always regulates its output to a higher

Note 3: Determined by design, not tested in production.

voltage than its input. The magnitude of this offset voltage as a function of

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3

LTC4301L

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TYPICAL PERFOR A CE CHARACTERISTICS

Input – Output High to Low

Propagation Delay vs

Temperature

I_CCvs Temperature

Connection Circuitry V_OUT– V_IN

4.9

4.8

4.7

4.6

4.5

4.4

4.3

4.2

4.1

4.0

3.9

100

80

60

40

20

0

300

250

200

150

100

50

T

= 25°C

A

V

= 2.7V

= 3.3V

CC

V = 0V

IN

V

= 5.5V

CC

V

= 3.3V

= 2.7V

CC

V

= 5V

CC

V

= 5.5V

CC

V

= 3.3V

CC

C

= C

PULLUPIN

= 100pF

= R

IN

OUT

R

= 10k

PULLUPOUT

0

–50

–25

0

25

50

75

100

–80 –60 –40 –20

0

20 40 60 80 100

0

10,000

20,000

(Ω)

30,000

40,000

TEMPERATURE (°C)

R

PULLUP

4301 G02

4301 G01

4301 G03

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PI FU CTIO S

CS (Pin 1): The connection sense pin is a 1.4V threshold

digital input pin. For normal operation CS is grounded.

Driving CS above the 1.4V threshold isolates SDAIN from

SDAOUT and SCLIN from SCLOUT and asserts READY

low.

READY(Pin5):TheREADYpinisanopendrainN-channel

MOSFET output which pulls down when CS is high or

when the start-up sequence described in the Operation

section has not been completed. READY goes high when

CS is low and a start-up is complete.

SCLOUT (Pin 2): Serial Clock Output. Connect this pin to

the SCL bus on the card.

SDAIN (Pin 6): Serial Data Input. Connect this pin to the

SDA bus on the backplane.

SCLIN (Pin 3): Serial Clock Input. Connect this pin to SCL

on the bus backplane.

SDAOUT (Pin 7): Serial Data Output. Connect this pin to

the SDA bus on the card.

GND(Pin4,9):Ground.Connectthispintoagroundplane

for best results. Exposed pad (DFN package) is ground.

V_CC(Pin 8): Main Input Supply. Place a bypass capacitor

of at least 0.01µF close to V_CCfor best results.

4301lf

4

LTC4301L

W

BLOCK DIAGRA

LTC4301L Supply Independent 2-Wire Bus Buffer

PRECHARGE

V

8

7

CC

CONNECT

PRECHARGE

CONNECT

R1

200k

R2

200k

SDAOUT

SCLOUT

SDAIN

6

SCLIN

3

2

PRECHARGE

CONNECT

LOGIC

0.6V

1.8V

READY

CONNECT

CS

1

5

4

95µs

DELAY

UVLO

1.4V

GND

4301l BD

4301lf

5

LTC4301L

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OPERATIO

Start-Up

Input-to-Output Offset Voltage

When the LTC4301L first receives power on its V_CCpin,

either during power-up or live insertion, it starts in an

undervoltage lockout (UVLO) state, ignoring any activity

on the SDA or SCL pins until V_CCrises above 2.5V. This is

to ensure that the part does not try to function until it has

enough voltage to do so.

When a logic low voltage, V_LOW1, is driven on any of the

LTC4301L’s data or clock pins, the LTC4301L regulates

the voltage on the other side of the device (call it V_LOW2

)

at a slightly higher voltage, as directed by the following

equation:

V_LOW2= V_LOW1+ 75mV + (V_CC/R) • 70Ω (typical)

During this time, the 1V precharge circuitry is active and

forces 1V through 200k nominal resistors to the SDAOUT

andSCLOUTpins. PrechargingtheSCLOUTandSDAOUT

pins to 1V minimizes the worst-case voltage differential

these pins will see at the moment of connection, therefore

minimizing bus disturbances.

where R is the bus pull-up resistance in ohms. For ex-

ample, if a device is forcing SDAOUT to 10mV where V_CC

= 3.3V and the pull-up resistor R on SDAIN is 10k, then the

voltage on SDAIN = 10mV + 75mV + (3.3/10000) • 70 =

108mV(typical). See the Typical Performance Character-

istics section for curves showing the offset voltage as a

function of V_CCand R.

Once the LTC4301L comes out of UVLO, it assumes that

SDAIN and SCLIN have been inserted into a live system

and that SDAOUT and SCLOUT are being powered up at

the same time as itself. Therefore, it looks for either a stop

bit or bus idle condition on the backplane side to indicate

the completion of a data transaction. When either one

occurs, the part also verifies that both the SDAOUT and

SCLOUT voltages are high. When all of these conditions

are met, the input-to-output connection circuitry is acti-

vated, joiningtheSDAandSCLbussesontheI/Ocardwith

those on the backplane.

Propagation Delays

During a rising edge, the rise time on each side is deter-

mined by the bus pull-up resistor and the equivalent

capacitance on the line. In Figure 1, V_CC= 3.3V, SDAOUT

and SCLOUT are pulled-up to 3.3V with 10k resistor (20pF

on this side) and SDAIN and SCLIN are pulled-up to 1.2V

with a 2k resistor (55pF on this side). Lower pull-up

resistor values are used on the input side to allow the

output side to be released sooner.

Connection Circuitry

Once the connection circuitry is activated, the functional-

ity of the SDAIN and SDAOUT pins is identical. A low

forced on either pin at any time results in both pin voltages

being low. For proper operation, logic low input voltages

should be no higher than 0.4V with respect to the ground

pin voltage of the LTC4301L. SDAIN and SDAOUT enter a

logic high state only when all devices on both SDAIN and

SDAOUT release high. The same is true for SCLIN and

SCLOUT.Thisimportantfeatureensuresthatclockstretch-

ing, clock synchronization, arbitration and the acknowl-

edge protocol always work, regardless of how the devices

in the system are tied to the LTC4301L.

INPUT

SIDE

55pF

OUTPUT

SIDE

20pF

0.5V/DIV

4301 TA01b

1µs/DIV

Figure 1. Input-Output Connection

There is a finite high to low propagation delay through the

connectioncircuitryforfallingwaveforms. Figure2shows

the falling edge waveforms for the same pull-up resistors

and equivalent capacitance conditions as used in Figure 1.

An external N-channel MOSFET device pulls down the

voltageonthesidewith55pFcapacitance;LTC4301Lpulls

downthevoltageontheoppositesidewithadelayof60ns.

Another key feature of the connection circuitry is that it

provides bidirectional buffering, keeping the backplane

and card capacitances isolated. Because of this isolation,

the waveforms on the backplane busses look slightly

different than the corresponding card bus waveforms as

described here.

4301lf

6

LTC4301L

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OPERATIO

This delay is always positive and is a function of supply

voltage, temperatureandthepull-upresistorsandequiva-

lentbuscapacitancesonbothsidesofthebus. TheTypical

Performance Characteristics section shows the high to

low propagation delay as a function of temperature and

voltage for 10k pull-up resistors pulled-up to V_CCand

100pF equivalent capacitance on both sides of the part.

Larger output capacitances translate to longer delays (up

to 150ns). Users must quantify the difference in propaga-

tion times for a rising edge versus a falling edge in their

systems and adjust setup and hold times accordingly.

Ready Digital Output

This pin provides a digital flag which is low when either CS

is high or the start-up sequence described earlier in this

section has not been completed. READY goes high when

CS is low and start-up is complete. The pin is driven by an

open-drain pull-down capable of sinking 3mA while hold-

ing 0.4V on the pin. Connect a resistor of 10k to V_CCto

provide the pull-up.

Connection Sense

OUTPUT

SIDE

20pF

INPUT

SIDE

55pF

When the CS pin is driven above 1.4V with respect to the

LTC4301L’s ground, the backplane side is disconnected

from the card side and the READY pin is internally pulled

low. When the pin voltage is low, the part waits for data

transactions on both the backplane and card sides to be

complete (as described in the Start-Up section) before

reconnecting the two sides. At this time the internal

pulldown on READY releases.

0.5V/DIV

4301 F02

20ns/DIV

Figure 2. Input-Output Connection

High to Low Propagation Delay

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APPLICATIO S I FOR ATIO

Live Insertion and Capacitance Buffering Application

In most applications the LTC4301L will be used with a

staggeredconnectorwhereV_CCandGNDwillbelongpins.

SDA and SCL are medium length pins to ensure that the

V_CCand GND pins make contact first. This will allow the

precharge circuitry to be activated on SDA and SCL before

they make contact. CS is a short pin that is pulled up when

not connected. This is to ensure that the connection

between the backplane and the cards data and clock

busses is not enabled until the transients associated with

live insertion have settled.

Figure 3 illustrates applications of the LTC4301L with

different bus pull-up and V_CCvoltages, demonstrating its

ability to recognize and buffer bus data levels that are

above or below its V_CCsupply. All of these applications

take advantage of theLTC4301L’s HotSwap^TMcontrolling,

capacitance buffering and precharge features. If the I/O

cardswerepluggeddirectlyintothebackplanewithoutthe

LTC4301L buffer, all of the backplane and card capaci-

tances would add directly together, making rise- and fall-

time requirements difficult to meet. Placing an LTC4301L

on the edge of each card, however, isolates the card

capacitance from the backplane. For a given I/O card, the

LTC4301Ldrivesthecapacitanceofeverythingonthecard

and the backplane must drive only the capacitance of the

LTC4301L, which is less than 10pF.

Figure 4 shows the LTC4301L in an application where all

of the pins have the same length. In this case, an RC filter

circuit on the I/O card with a product of 10ms provides a

filter to prevent the LTC4301L from becoming activated

until the transients associated with live insertion have

settled. Connect the capacitor between V_CCand CS, and

the resistor from CS to GND.

Hot Swap is a trademark of Linear Technology Corporation.

4301lf

7

LTC4301L

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APPLICATIO S I FOR ATIO

5V

0.01µF

10k 10k

10k

1.2V

2k

V

CC

SDAOUT

SCLOUT

READY

CARD_SDA

CARD_SCL

CS

SDA

SCL

LTC4301L

GND

SDAIN

SCLIN

BACKPLANE

CONNECTOR

CARD

3.3V

2k

0.01µF

10k 10k

1.2V

V

CC

SDAOUT

SCLOUT

READY

CARD_SDA

CARD_SCL

CS

SDA

SCL

LTC4301L

GND

SDAIN

SCLIN

BACKPLANE

CONNECTOR

CARD

3V

3.3V

2k

0.01µF

10k 10k

1V

V

CC

SDAOUT

SCLOUT

CARD_SDA

CARD_SCL

CS

SDA

SCL

LTC4301L

GND

SDAIN

SCLIN

READY

4301l F03

BACKPLANE

CONNECTOR

CARD

Figure 3. Typical Supply Independent Applications

4301lf

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LTC4301L

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APPLICATIO S I FOR ATIO

U

1.2V 3.3V

0.01µF

10k 10k

V

CC

2k

LTC4301L

SCLIN

SCLOUT

SDAOUT

BACK_SCL

BACK_SDA

CARD_SCL

SDAIN

CS

CARD_SDA

3.3V

10k

FROM

MICROPROCESSOR

READY

GND

4301l F05

BACKPLANE

CONNECTOR

CARD

Figure 4. Inserting Multiple I/O Cards into a Live Backplane Using a Connector with All the Pins the Same Length

4301lf

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LTC4301L

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PACKAGE DESCRIPTIO

DD Package

8-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1698)

R = 0.115

0.38 ± 0.10

TYP

5

8

0.675 ±0.05

3.5 ±0.05

2.15 ±0.05 (2 SIDES)

1.65 ±0.05

3.00 ±0.10

(4 SIDES)

1.65 ± 0.10

(2 SIDES)

PIN 1

TOP MARK

(NOTE 6)

PACKAGE

OUTLINE

(DD8) DFN 1203

4

1

0.25 ± 0.05

0.75 ±0.05

0.200 REF

0.25 ± 0.05

0.50 BSC

0.50

BSC

2.38 ±0.05

(2 SIDES)

2.38 ±0.10

(2 SIDES)

0.00 – 0.05

BOTTOM VIEW—EXPOSED PAD

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

NOTE:

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON TOP AND BOTTOM OF PACKAGE

4301lf

10

LTC4301L

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PACKAGE DESCRIPTIO

MS8 Package

8-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1660)

0.889 ± 0.127

(.035 ± .005)

5.23

(.206)

MIN

3.20 – 3.45

(.126 – .136)

3.00 ± 0.102

(.118 ± .004)

(NOTE 3)

0.52

(.0205)

REF

0.65

(.0256)

BSC

0.42 ± 0.038

(.0165 ± .0015)

TYP

8

7 6 5

RECOMMENDED SOLDER PAD LAYOUT

3.00 ± 0.102

(.118 ± .004)

(NOTE 4)

4.90 ± 0.152

(.193 ± .006)

DETAIL “A”

0.254

(.010)

0° – 6° TYP

GAUGE PLANE

1

2

3

4

0.53 ± 0.152

(.021 ± .006)

1.10

(.043)

MAX

0.86

(.034)

REF

DETAIL “A”

0.18

(.007)

SEATING

PLANE

0.22 – 0.38

0.127 ± 0.076

(.009 – .015)

(.005 ± .003)

0.65

(.0256)

BSC

TYP

MSOP (MS8) 0204

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

4301lf

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

11

LTC4301L

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TYPICAL APPLICATIO

System with Active Connection Control

1.2V 3.3V

0.01µF

10k 10k

V

CC

2k

LTC4301L

SCLIN

SCLOUT

SDAOUT

BACK_SCL

BACK_SDA

CARD_SCL

SDAIN

3.3V

CARD_SDA

10k

CS

FROM

MICROPROCESSOR

READY

GND

4301l F05

BACKPLANE

CONNECTOR

CARD

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Supply Independent Hot Swappable 2-Wire Bus Buffer Supply Independent

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4301lf

LT/TP 0304 1K • PRINTED IN THE USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

12

●

LINEAR TECHNOLOGY CORPORATION 2003

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC4301LCDD8#PBF
厂家：	Linear
描述：	IC SPECIALTY INTERFACE CIRCUIT, DSO8, 3 X 3 MM, PLASTIC, MO-229WEED-1, DFN-8, Interface IC:Other 接口集成电路
文件：	总12页 (文件大小：220K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC4301LCDD8#PBF [Linear]

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