LTC4088EDE-1#TRPBF [Linear]
LTC4088-1/-2 - High Efficiency Battery Charger/USB Power Manager with Regulated Output Voltage; Package: DFN; Pins: 14; Temperature Range: -40°C to 85°C;
| 型号： | LTC4088EDE-1#TRPBF |
| 厂家： | 
Linear |
| 描述： | LTC4088-1/-2 - High Efficiency Battery Charger/USB Power Manager with Regulated Output Voltage; Package: DFN; Pins: 14; Temperature Range: -40°C to 85°C 电池 |
| 文件： | 总24页 (文件大小：303K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC4088-1/LTC4088-2
High Efficiency Battery
Charger/USB Power Manager
with Regulated Output Voltage
U
FEATURES
DESCRIPTIO
The LTC®4088-1/LTC4088-2 is a high efficiency USB
PowerPathTM controller and Li-Ion/Polymer battery
charger. It includes a synchronous switching input regu-
lator, a full-featured battery charger and an ideal diode.
Designed specifically for USB applications, the
LTC4088-1/LTC4088-2’s switching regulator auto-
matically limits its input current to either 100mA, 500mA
or 1A via logic control. The LTC4088-1 powers-up with the
charger off; the LTC4088-2 powers-up with the charger on.
n
Switching Regulator Makes Optimal Use of Limited
Power Available from USB Port to Charge Battery
and Power Application
180mΩ Internal Ideal Diode Plus External Ideal Diode
Controller Seamlessly Provide Low Loss Power Path
When Input Power is Limited or Unavailable
Automatic Charge Current Reduction Maintains
n
n
3.6V Minimum V
Full Featured Li-Ion/Polymer Battery Charger
OUT
n
n
V
Operating Range: 4.25V to 5.5V (7V Absolute
BUS
The switching input stage provides power to V
where
OUT
Maximum—Transient)
power sharing between the application circuit and the
n
n
n
n
n
1.2A Maximum Input Current Limit
battery charger is managed. Charge current is automati-
1.5A Maximum Charge Current with Thermal Limiting
cally reduced to maintain a regulated 3.6V V
during
OUT
Bat-TrackTM Adaptive Output Control
low-battery conditions. As the battery is charged, V
OUT
Slew Control Reduces Switching EMI
Low Profile (0.75mm)14-Lead 4mm× 3mm DFN Package
tracks V
for high efficiency charging. This feature al-
BAT
lows the LTC4088-1/LTC4088-2 to provide more power to
the application and eases thermal issues in constrained
applications.
U
APPLICATIO S
n
Media Players
An ideal diode ensures that system power is available
from the battery when the input current limit is reached
or if the USB or wall supply is removed.
n
Digital Cameras
n
GPS
PDAs
Smart Phones
n
The LTC4088-1/LTC4088-2 is available in the low profile
14-Lead 4mm × 3mm × 0.75mm DFN surface mount
package.
n
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
PowerPath and Bat-Track are trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 6522118
U
TYPICAL APPLICATIO
Switching Regulator Efficiency to
System Load (P /P
)
OUT BUS
High Efficiency Battery Charger/USB Power Manager
100
90
80
70
60
50
40
30
20
10
3.3µH
WALL
SYSTEM
LOAD
USB
V
D0
D1
D2
SW
V
OUT
V
OUTS
GATE
BAT = 4.2V
BUS
10µF
BAT = 3.3V
LTC4088-1/LTC4088-2
CHRG
BAT
CLPROG
PROG C/X GND NTC
10µF
+
8.2Ω
0.1µF
Li-Ion
V
I
= 5V
BUS
= 0mA
2.94k
499Ω
BAT
408812 TA01a
10x MODE
0
0.01
0.1
(A)
1
I
408812 TA01b
OUT
40881fb
1
LTC4088-1/LTC4088-2
W W U W
ABSOLUTE AXI U RATI GS
PIN CONFIGURATION
(Note 1)
V
V
(Transient) t < 1ms, Duty Cycle < 1%.. –0.3V to 7V
BUS
BUS
TOP VIEW
(Static), BAT, CHRG, NTC, D0,
NTC
1
2
3
4
5
6
7
14 D1
13 D0
12 SW
D1, D2.......................................................... –0.3V to 6V
CLPROG
I
I
I
I
I
I
....................................................................3mA
V
CLPROG
PROG C/X
CHRG
OUT
SW
BAT
OUTS
15
D2
C/X
11
10
9
V
V
, I ................................................................2mA
BUS
OUT
......................................................................75mA
PROG
CHRG
BAT
.............................................................................2A
8
GATE
..............................................................................2A
.............................................................................2A
DE PACKAGE
14-LEAD (4mm × 3mm) PLASTIC DFN
Maximum Operating Junction Temperature .......... 125°C
Operating Temperature Range.................. –40°C to 85°C
Storage Temperature Range................... –65°C to 125°C
T
= 125°C, θ = 37°C/W
JA
JMAX
EXPOSED PAD (PIN 15) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
LTC4088EDE-1#PBF
LTC4088EDE-2#PBF
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC4088EDE-1#TRPBF 40881
LTC4088EDE-2#TRPBF 40882
–40°C to 85°C
–40°C to 85°C
14-Lead (4mm × 3mm × 0.75mm) Plastic DFN
14-Lead (4mm × 3mm) Plastic DFN
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS The
l
denotes the specifications which apply over the full operating
= 5V, BAT = 3.8V, R = 2.94k, unless otherwise noted.
temperature range, otherwise specifications are at T = 25°C. V
A
BUS
CONDITIONS
CLPROG
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
Input Power Supply
l
V
Input Supply Voltage
Total Input Current
4.35
5.5
V
BUS
l
l
l
l
l
I
1x Mode
5x Mode
10x Mode
Low Power Suspend Mode
High Power Suspend Mode
92
445
815
0.32
1.6
97
100
500
1000
0.5
mA
mA
mA
mA
mA
BUS(LIM)
470
877
0.39
2.05
2.5
I
(Note 4)
Input Quiescent Current
1x Mode
6
mA
mA
mA
mA
mA
BUSQ
5x Mode
14
10x Mode
Low Power Suspend Mode
High Power Suspend Mode
14
0.038
0.038
h
(Note 4) Ratio of Measured V
Current to
1x Mode
224
1133
2140
11.3
59.4
mA/mA
mA/mA
mA/mA
mA/mA
mA/mA
CLPROG
BUS
CLPROG Program Current
5x Mode
10x Mode
Low Power Suspend Mode
High Power Suspend Mode
40881fb
2
LTC4088-1/LTC4088-2
ELECTRICAL CHARACTERISTICS The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. V
= 5V, BAT = 3.8V, R
= 2.94k, unless otherwise noted.
CLPROG
A
BUS
SYMBOL
PARAMETER
Current Available Before
CONDITIONS
MIN
TYP
MAX
UNITS
I
V
1x Mode, BAT = 3.3V
5x Mode, BAT = 3.3V
10x Mode, BAT = 3.3V
Low Power Suspend Mode
High Power Suspend Mode
135
672
1251
0.32
2.04
mA
mA
mA
mA
mA
OUT
OUT
Discharging Battery
0.26
1.6
0.41
2.46
V
V
V
V
CLPROG Servo Voltage in Current Limit 1x, 5x, 10x Modes
Suspend Modes
1.188
100
V
CLPROG
mV
V
Undervoltage Lockout
Rising Threshold
Falling Threshold
4.30
4.00
4.35
V
V
UVLO
BUS
3.95
3.5
V
to BAT Differential Undervoltage
Rising Threshold
Falling Threshold
200
50
mV
mV
DUVLO
OUT
BUS
Lockout
V
Voltage
1x, 5x, 10x Modes, 0V < BAT ≤ 4.2V,
OUT
BAT + 0.3
4.7
V
OUT
I
= 0mA, Battery Charger Off
USB Suspend Modes, I
= 250µA
4.5
1.8
4.6
4.7
2.7
V
MHz
Ω
OUT
f
Switching Frequency
2.25
0.18
0.30
OSC
R
R
PMOS On Resistance
NMOS On Resistance
Peak Inductor Current Clamp
PMOS
NMOS
PEAK
Ω
I
1x, 5x Modes
10x Mode
2
3
A
A
R
Suspend LDO Output Resistance
15
Ω
SUSP
Battery Charger
V
BAT Regulated Output Voltage
Constant-Current Mode Charge Current
Battery Drain Current
4.179
4.165
4.200
4.200
4.221
4.235
V
V
FLOAT
0°C ≤ T ≤ 85°C
A
I
I
R
PROG
R
PROG
= 1k
= 5k
980
196
1030
206
1080
220
mA
mA
CHG
V
> V , PowerPath Switching
UVLO
3.5
5
µA
BAT
BUS
Regulator On, Battery Charger Off,
I
= 0µA
OUT
V
= 0V, I
= 0µA (Ideal Diode Mode)
OUT
23
35
µA
V
BUS
V
V
PROG Pin Servo Voltage
1.000
0.100
PROG
PROG Pin Servo Voltage in Trickle
Charge
BAT < V
V
PROG,TRKL
TRKL
h
Ratio of I to PROG Pin Current
1031
2.85
135
–100
4.0
mA/mA
V
PROG
BAT
V
Trickle Charge Threshold Voltage
Trickle Charge Hysteresis Voltage
Recharge Battery Threshold Voltage
Safety Timer Termination Period
Bad Battery Termination Time
BAT Rising
2.7
3.0
TRKL
mV
∆V
TRKL
RECHRG
TERM
V
Threshold Voltage Relative to V
–80
3.2
0.4
85
–120
4.8
mV
FLOAT
t
t
I
Timer Starts when V = V
Hour
Hour
BAT
FLOAT
BAT < V
0.5
0.6
BADBAT
C/X
TRKL
Battery Charge Current at Programmed
End of Charge Indication
R
C/X
R
C/X
= 1k
= 5k
100
20
115
mA
mA
V
C/X Threshold Voltage
100
1031
65
mV
mA/mA
mV
C/X
h
Battery Charge Current Ratio to C/X
CHRG Pin Output Low Voltage
CHRG Pin Input Current
C/X
V
I
= 5mA
100
1
CHRG
CHRG
CHRG
I
BAT = 4.5V, V
= 5V
0
µA
CHRG
40881fb
3
LTC4088-1/LTC4088-2
ELECTRICAL CHARACTERISTICS The
l
denotes the specifications which apply over the full operating
= 5V, BAT = 3.8V, R = 2.94k, unless otherwise noted.
temperature range, otherwise specifications are at T = 25°C. V
A
BUS
CLPROG
SYMBOL
PARAMETER
CONDITIONS
= 200mA
MIN
TYP
MAX
UNITS
R
Battery Charger Power FET
On-Resistance (Between V
I
0.18
Ω
ON_CHG
BAT
and BAT)
OUT
T
Junction Temperature in Constant
Temperature Mode
110
°C
LIM
NTC
V
V
V
Cold Temperature Fault Threshold
Voltage
Rising Threshold
Hysteresis
75.0
33.4
0.7
76.5
1.5
78.0
36.4
2.7
%V
%V
COLD
HOT
DIS
BUS
BUS
Hot Temperature Fault Threshold
Voltage
Falling Threshold
Hysteresis
34.9
1.5
%V
%V
BUS
BUS
NTC Disable Threshold Voltage
Falling Threshold
Hysteresis
1.7
50
%V
BUS
mV
I
NTC Leakage Current
V
NTC
= V = 5V
BUS
–50
50
nA
NTC
Ideal Diode
V
FWD
Forward Voltage Detection
I
= 10mA
= 0V, I
15
2
mV
mV
OUT
BUS
V
= 10mA
OUT
R
Internal Diode On-Resistance, Dropout
Diode Current Limit
I
= 200mA
0.18
Ω
DROPOUT
OUT
I
2
A
MAX
Logic (D0, D1, D2)
V
V
Input Low Voltage
0.4
V
V
IL
IH
Input High Voltage
1.2
I
Static Pull-Down Current
V
PIN
= 1V
2
µA
PD
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC4088E-1/ LTC4088E-2 is guaranteed to meet performance
specifications from 0°C to 85°C. Specifications over the –40°C to 85°C
operating temperature range are assured by design, characterization and
correlation with statistical process controls.
Note 3: The LTC4088E-1/ LTC4088E-2 includes overtemperature protection
that is intended to protect the device during momentary overload
conditions. Junction temperature will exceed 125°C when overtemperature
protection is active. Continuous operation above the specified maximum
operating junction temperature may impair device reliability.
Note 4: Total input current is the sum of quiescent current, I
, and
BUSQ
measured current given by V
/R
• (h
+ 1).
CLPROG CLPROG
CLPROG
40881fb
4
LTC4088-1/LTC4088-2
U W
T = 25°C unless otherwise noted.
A
TYPICAL PERFOR A CE CHARACTERISTICS
Ideal Diode Resistance
Output Voltage vs Output Current
(Battery Charger Disabled)
4.50
vs Battery Voltage
Ideal Diode V-I Characteristics
1.0
0.8
0.6
0.4
0.2
0
0.25
0.20
0.15
0.10
0.05
0
V
= 5V
INTERNAL IDEAL DIODE
WITH SUPPLEMENTAL
EXTERNAL VISHAY
Si2333 PMOS
BUS
V
= 4V
BAT
5x MODE
4.25
4.00
3.75
3.50
3.25
INTERNAL IDEAL
DIODE
INTERNAL IDEAL
DIODE ONLY
V
= 3.4V
BAT
INTERNAL IDEAL DIODE
WITH SUPPLEMENTAL
EXTERNAL VISHAY
Si2333 PMOS
V
V
= 0V
= 5V
BUS
BUS
0
0.04
0.08
0.12
0.16
0.20
0
200
400
600
800
1000
2.7
3.0
3.3
3.6
3.9
4.2
FORWARD VOLTAGE (V)
OUTPUT CURRENT (mA)
BATTERY VOLTAGE (V)
408812 G01
408812 G03
408812 G02
USB Limited Battery Charge
Current vs Battery Voltage
USB Limited Battery Charge
Current vs Battery Voltage
Battery Drain Current
vs Battery Voltage
700
600
150
125
25
20
15
10
5
I
= 0µA
OUT
V
= 0V
BUS
V
R
R
= 5V
BUS
500
400
300
200
100
0
V
R
R
= 5V
= 1k
BUS
PROG
CLPROG
100
75
= 1k
= 2.94k
PROG
CLPROG
= 2.94k
50
25
0
V
= 5V
BUS
(SUSPEND MODE)
5x USB SETTING,
BATTERY CHARGER SET FOR 1A
1x USB SETTING,
BATTERY CHARGER SET FOR 1A
0
3.0
3.3
3.6
4.2
2.7
3.9
2.7 3.0 3.3 3.6
BATTERY VOLTAGE (V)
3.9
4.2
2.7
3.0
3.3
3.6
3.9
4.2
BATTERY VOLTAGE (V)
BATTERY VOLTAGE (V)
408812 G04
408812 G05
408812 G06
Battery Charging Efficiency vs
Battery Voltage with No External
PowerPath Switching Regulator
Efficiency vs Output Current
V
Current vs V
Voltage
BUS
BUS
(Suspend)
Load (P /P
)
BAT BUS
100
90
80
70
60
50
40
90
88
86
84
82
80
50
40
30
20
10
0
V
= 3.8V
BAT
I
= 0mA
R
R
OUT
= 2.94k
OUT
CLPROG
PROG
5x, 10x MODE
= 1k
1x MODE
I
= 0mA
5x CHARGING
EFFICIENCY
1x CHARGING
EFFICIENCY
0.01
0.1
OUTPUT CURRENT (A)
1
2.7
3.0
3.3
3.6
3.9
4.2
1
2
3
4
5
6
BATTERY VOLTAGE (V)
V
VOLTAGE (V)
BUS
408812 G07
408812 G08
408812 G09
40881fb
5
LTC4088-1/LTC4088-2
U W
T = 25°C unless otherwise noted.
A
TYPICAL PERFOR A CE CHARACTERISTICS
Output Voltage vs Output Current
in Suspend
V
Current vs Output Current
BUS
in Suspend
Battery Charge Current vs V
OUT
2.5
2.0
1.5
1.0
0.5
0
5.0
4.5
4.0
3.5
3.0
2.5
600
500
V
V
R
= 5V
= 3.3V
R
= 2k
BUS
BAT
PROG
5x MODE
= 2.94k
CLPROG
5x MODE
400
300
1x MODE
200
100
0
V
V
R
= 5V
BUS
BAT
1x MODE
1.5
= 3.3V
= 2.94k
CLPROG
0
0.5
1
2
2.5
0
0.5
1
1.5
2
2.5
3.1
3.2
3.3
V
OUT
3.4
(V)
3.5
3.6
OUTPUT LOAD CURRENT (mA)
OUTPUT CURRENT (mA)
408812 G11
408812 G10
408812 G12
Battery Charge Current
vs Temperature
Battery Charger Float Voltage
vs Temperature
Low-Battery (Instant-On) Output
Voltage vs Temperature
4.21
4.20
4.19
4.18
4.17
3.68
3.66
3.64
3.62
3.60
600
500
400
300
200
100
0
R
= 2k
V
= 2.7V
PROG
BAT
I
= 100mA
OUT
5x MODE
THERMAL REGULATION
–40
–15
10
35
60
85
–40
–15
10
35
60
85
60 80
20 40
TEMPERATURE (oC)
–40 –20
0
100 120
TEMPERATURE (°C)
TEMPERATURE (°C)
408812 G14
408812 G15
408812 G13
Oscillator Frequency
vs Temperature
V
Quiescent Current
Quiescent Current in Suspend
vs Temperature
BUS
vs Temperature
15
12
9
2.35
2.30
2.25
2.20
2.15
2.10
46
44
V
= 5V
= 0µA
V
= 5V
BUS
OUT
BUS
OUT
5x MODE
I
I
= 0mA
SUSP HI
42
40
38
36
34
1x MODE
6
3
–40
–15
10
35
60
85
–40
–15
10
35
60
85
–40
–15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
408812 G17
408812 G18
408812 G16
40881fb
6
LTC4088-1/LTC4088-2
U W
T = 25°C unless otherwise noted.
A
TYPICAL PERFOR A CE CHARACTERISTICS
CHRG Pin Current vs Voltage
(Pull-Down State)
Suspend LDO Transient Response
(500µA to 1mA)
100
V
V
= 5V
= 3.8V
BUS
BAT
I
OUT
80
60
40
20
0
500MA/DIV
0mA
V
OUT
20mV/DIV
AC COUPLED
408812 G21
500µs/DIV
0
1
2
3
4
5
CHRG PIN VOLTAGE (V)
408812 G19
U
U
U
PI FU CTIO S
NTC (Pin 1): Input to the NTC Thermistor Monitoring
Circuits. The NTC pin connects to a negative temperature
coefficient thermistor which is typically co-packaged with
the battery pack to determine if the battery is too hot or
too cold to charge. If the battery’s temperature is out of
range, chargingispauseduntilthebatterytemperaturere-
enters the valid range. A low drift bias resistor is required
V
(Pin 3): Output Voltage Sense. The V
pin is
OUTS
OUTS
used to sense the voltage at V
when the PowerPath
OUT
switching regulator is in operation. V
be connected directly to V
should always
OUTS
.
OUT
D2 (Pin 4): Mode Select Input Pin. D2, in combination
with the D0 pin and D1 pin, controls the current limit and
batterychargerfunctionsoftheLTC4088-1/LTC4088-2.The
LTC4088-1 and LTC4088-2 differ only in the functionality
of the D2 pin default (0, 0, 0) state (see Table 1). This pin
is pulled low by a weak current sink.
from V
to NTC and a thermistor is required from NTC
BUS
to ground. If the NTC function is not desired, the NTC pin
should be grounded.
CLPROG (Pin 2): USB Current Limit Program and Monitor
Pin. A 1% resistor from CLPROG to ground determines
C/X(Pin5):EndofChargeIndicationProgramPin.Thispin
is used to program the current level at which a completed
charge cycle is indicated by the CHRG pin.
the upper limit of the current drawn from the V
pin.
BUS
, is sent
A precise fraction of the input current, h
CLPROG
PROG (Pin 6): Charge Current Program and Charge Cur-
rent Monitor Pin. Connecting a 1% resistor from PROG
to ground programs the charge current. If sufficient input
powerisavailableinconstant-currentmode,thispinservos
to 1V. The voltage on this pin always represents the actual
charge current by using the following formula:
to the CLPROG pin when the high side switch is on. The
switching regulator delivers power until the CLPROG
pin reaches 1.188V. Therefore, the current drawn from
V
will be limited to an amount given by h
and
BUS
CLPROG
R
. There are several ratios for h
available,
CLPROG
CLPROG
two of which correspond to the 500mA and 100mA USB
specifications. A multilayer ceramic averaging capacitor
is also required at CLPROG for filtering.
VPROG
IBAT
=
•1031
RPROG
40881fb
7
LTC4088-1/LTC4088-2
U
U
U
PI FU CTIO S
if the load exceeds the allotted power from V
or if the
CHRG (Pin 7): Open-Drain Charge Status Output. The
CHRG pin indicates the status of the battery charger. Four
possible states are represented by CHRG: charging, not
charging (or float charge current less than programmed
endofchargeindicationcurrent),unresponsivebatteryand
battery temperature out of range. CHRG is modulated at
35kHz and switches between a low and a high duty cycle
foreasyrecognitionbyeitherhumansormicroprocessors.
CHRG requires a pull-up resistor and/or LED to provide
indication.
BUS
V
power source is removed. V
should be bypassed
BUS
OUT
with a low impedance multilayer ceramic capacitor.
V
(Pin 11): Input voltage for the switching PowerPath
BUS
controller. V
will usually be connected to the USB port
BUS
of a computer or a DC output wall adapter. V
should
BUS
be bypassed with a low impedance multilayer ceramic
capacitor.
SW (Pin 12): The SW pin delivers power from V
to
BUS
V
via the step-down switching regulator. An inductor
OUT
GATE(Pin8):IdealDiodeAmplifierOutput.Thispincontrols
the gate of an external P-channel MOSFET transistor used
to supplement the internal ideal diode. The source of the
should be connected from SW to V . See the Applica-
OUT
tions Information section for a discussion of inductance
value and current rating.
P-channel MOSFET should be connected to V
drain should be connected to BAT.
and the
OUT
D0 (Pin 13): Mode Select Input Pin. D0, in combina-
tion with the D1 pin and the D2 pin, controls the current
limit and battery charger functions of the LTC4088-1/
LTC4088-2 (see Table 1). This pin is pulled low by a weak
current sink.
BAT (Pin 9): Single Cell Li-Ion Battery Pin. Depending on
availablepowerandload,aLi-IonbatteryonBATwilleither
deliver system power to V
through the ideal diode or
OUT
be charged from the battery charger.
D1 (Pin 14): Mode Select Input Pin. D1, in combination
with the D0 pin and the D2 pin, controls the current limit
and battery charger functions of the LTC4088-1/LTC4088-
2 (see Table 1). This pin is pulled low by a weak current
sink.
V
(Pin 10): Output voltage of the switching PowerPath
OUT
controller and input voltage of the battery charger. The
majority of the portable product should be powered from
V
.TheLTC4088-1/LTC4088-2willpartitiontheavailable
OUT
power between the external load on V
and the internal
OUT
Exposed Pad (Pin 15): GND. Must be soldered to the
PCB to provide a low electrical and thermal impedance
connection to ground.
battery charger. Priority is given to the external load and
any extra power is used to charge the battery. An ideal
diodefromBATtoV
ensuresthatV
ispoweredeven
OUT
OUT
40881fb
8
LTC4088-1/LTC4088-2
W
BLOCK DIAGRA
40881fb
9
LTC4088-1/LTC4088-2
U
OPERATIO
Introduction
regulator. To meet the USB maximum load specification,
the switching regulator contains a measurement and
control system that ensures that the average input cur-
rent remains below the level programmed at CLPROG.
TheLTC4088-1/LTC4088-2includesaPowerPathcontroller,
battery charger, internal ideal diode, external ideal diode
controller and a SUSPEND LDO. Designed specifically for
USBapplications,thePowerPathcontrollerincorporatesa
precisionaverageinputcurrentlimitedstep-downswitch-
ing regulator to make maximum use of the allowable USB
power. Because power is conserved, the LTC4088-1/
V
drives the combination of the external load and the
OUT
battery charger.
If the combined load does not cause the switching power
supply to reach the programmed input current limit, V
OUT
will track approximately 0.3V above the battery voltage.
By keeping the voltage across the battery charger at this
low level, power lost to the battery charger is minimized.
Figure 1 shows the power path components.
LTC4088-2 allows the load current on V
to exceed the
OUT
current drawn by the USB port without exceeding the USB
load specifications.
Theswitchingregulatorandbatterychargercommunicate
to ensure that the average input current never exceeds the
USB specifications.
Ifthecombinedexternalloadplusbatterychargecurrentis
largeenoughtocausetheswitchingpowersupplytoreach
the programmed input current limit, the battery charger
will reduce its charge current by precisely the amount
necessary to enable the external load to be satisfied. Even
if the battery charge current is programmed to exceed the
allowable USB current, the USB specification for average
input current will not be violated; the battery charger will
reduce its current as needed. Furthermore, if the load cur-
The ideal diodes from BAT to V
guarantee that ample
even if there is insuf-
OUT
OUT
power is always available to V
ficient or absent power at V
.
BUS
Finally, to prevent battery drain when a device is con-
nected to a suspended USB port, an LDO from V to
BUS
V
OUT
provides either low power or high power suspend
rent at V
exceeds the programmed power from V
,
current to the application.
Input Current Limited Step Down Switching Regulator
The power delivered from V to V is controlled
OUT
BUS
load current will be drawn from the battery via the ideal
diodes even when the battery charger is enabled.
The current at CLPROG is a precise fraction of the V
BUS
BUS
OUT
current. When a programming resistor and an averaging
by a 2.25MHz constant frequency step-down switching
SYSTEM LOAD
SW
TO USB
OR WALL
ADAPTER
V
BUS
3.5V TO
11
12
3
(BAT + 0.3V)
V
OUTS
I
/N
SWITCH
V
OUT
PWM AND
GATE DRIVE
10
8
IDEAL
DIODE
EXTERNAL
IDEAL DIODE
PMOS
+
–
GATE
BAT
CONSTANT CURRENT
CONSTANT VOLTAGE
BATTERY CHARGER
OV
–
+
15mV
–
+
–
+
+
0.3V
CLPROG
1.188V
2
+
–
9
3.6V
AVERAGE INPUT
CURRENT LIMIT
CONTROLLER
AVERAGE OUTPUT
VOLTAGE LIMIT
CONTROLLER
+
SINGLE CELL
Li-Ion
408812 F01
Figure 1
40881fb
10
LTC4088-1/LTC4088-2
U
OPERATIO
capacitorareconnectedfromCLPROGtoGND,thevoltage
on CLPROG represents the average input current of the
switching regulator. As the input current approaches the
programmed limit, CLPROG reaches 1.188V and power
delivered by the switching regulator is held constant.
Several ratios of current are available which can be set
to correspond to USB low and high power modes with a
single programming resistor.
typically be used when there is line power available from
a wall adapter.
While not in current limit, the switching regulator’s Bat-
Track feature will set V
to approximately 300mV above
OUT
the voltage at BAT. However, if the voltage at BAT is below
3.3V,andtheloadrequirementdoesnotcausetheswitching
regulator to exceed its current limit, V
will regulate at a
OUT
fixed 3.6V as shown in Figure 2. This will allow a portable
producttorunimmediatelywhenpowerisappliedwithout
waiting for the battery to charge.
The input current limit is programmed by various com-
binations of the D0, D1 and D2 pins as shown in Table 1.
The switching input regulator can also be deactivated
(USB Suspend).
If the load does exceed the current limit at V , V
BUS OUT
will range between the no-load voltage and slightly below
TheaverageinputcurrentwillbelimitedbytheCLPROGpro-
grammingresistoraccordingtothefollowingexpression:
the battery voltage, indicated by the shaded region of
Figure 2.
4.5
VCLPROG
RCLPROG
IVBUS = IBUSQ
+
• h
(
+ 1
)
CLPROG
4.2
3.9
where I
is the quiescent current of the LTC4088-
BUSQ
NO LOAD
3.6
1/LTC4088-2, V
current limit, R
is the CLPROG servo voltage in
is the value of the programming
CLPROG
CLPROG
300mV
3.3
resistor and h
is the ratio of the measured current
CLPROG
3.0
2.7
2.4
at V
to the sample current delivered to CLPROG. Refer
BUS
totheElectricalCharacteristicstableforvaluesofh
,
CLPROG
V
and I
. Given worst-case circuit tolerances,
CLPROG
BUSQ
3.6
4.2
2.4
2.7
3.0
3.3
3.9
the USB specification for the average input current in 1x
BAT (V)
or 5x mode will not be violated, provided that R
2.94k or greater.
is
408812 F02
CLPROG
Figure 2. V
vs BAT
OUT
Table 1 shows the available settings for the D0, D1 and
D2 pins.
For very low-battery voltages, the battery charger acts like
a load and, due to limited input power, its current will tend
Table 1. Controlled Input Current Limit
4088-1 4088-2 CHARGER
topullV belowthe3.6V“InstantOn”voltage.Toprevent
OUT
D0
0
D1
0
D2
0
D2
1
STATUS
Off
On
Off
On
Off
On
Off
Off
I
BUS(LIM)
100mA (1x)
100mA (1x)
500mA (5x)
500mA (5x)
V
from falling below this level, an undervoltage circuit
OUT
automatically detects that V
is falling and reduces the
OUT
0
0
1
0
battery charge current as needed. This reduction ensures
that load current and voltage are always prioritized and yet
delivers as much battery charge current as possible. (See
OverProgrammingtheBatteryChargerintheApplications
Information section).
0
1
0
1
0
1
1
0
1
0
0
1
1A (10x)
1A (10x)
1
0
1
0
1
1
0
1
2.5mA (Susp High)
500µA (Susp Low)
1
1
1
0
The voltage regulation loop compensation is controlled by
the capacitance on V . An MLCC capacitor of 10µF is
Notice that when D0 is high and D1 is low, the switching
regulator is set to a higher current limit for increased
charging and power availability at V . These modes will
OUT
required for loop stability. Additional capacitance beyond
this value will improve transient response.
OUT
40881fb
11
LTC4088-1/LTC4088-2
U
OPERATIO
Ideal Diode from BAT to V
drain should be connected to BAT. Capable of driving a
1nF load, the GATE pin can control an external P-channel
MOSFET transistor having an on-resistance of 30mΩ or
OUT
The LTC4088-1/LTC4088-2 has an internal ideal diode as
well as a controller for an external ideal diode. Both the
internal and the external ideal diodes are always on and
lower. When V
is unavailable, the forward voltage of
BUS
the ideal diode amplifier will be reduced from 15mV to
nearly zero.
will respond quickly whenever V
drops below BAT.
OUT
If the load current increases beyond the power allowed
from the switching regulator, additional power will be
pulled from the battery via the ideal diodes. Furthermore,
Suspend LDO
The LTC4088-1/LTC4088-2 provides a small amount of
if power to V
(USB or wall power) is removed, then
BUS
power to V
in SUSPEND mode by including an LDO
OUT
OUT
all of the application power will be provided by the bat-
tery via the ideal diodes. The ideal diodes will be fast
from V
to V . This LDO will prevent the battery from
BUS
running down when the portable product has access to
a suspended USB port. Regulating at 4.6V, this LDO only
becomes active when the switching converter is disabled.
To remain compliant with the USB specification, the input
to the LDO is current limited so that it will not exceed the
lowpowerorhighpowersuspendspecification. Iftheload
enough to keep V
from drooping with only the stor-
OUT
age capacitance required for the switching regulator. The
internal ideal diode consists of a precision amplifier that
activates a large on-chip MOSFET transistor whenever
the voltage at V
is approximately 15mV (V ) below
OUT
FWD
the voltage at BAT. Within the amplifier’s linear range, the
small-signal resistance of the ideal diode will be quite low,
keeping the forward drop near 15mV. At higher current
levels, the MOSFET will be in full conduction. An external
P-channel MOSFET transistor should be added from BAT
on V
exceeds the suspend current limit, the additional
OUT
currentwillcomefromthebatteryviatheidealdiodes. The
suspend LDO sends a scaled copy of the V current to
BUS
theCLPROGpin,whichwillservotoapproximately100mV
inthismode.Thus,thehighpowerandlowpowersuspend
settings are related to the levels programmed by the same
resistor for 1x and 5x modes.
to V . The GATE pin of the LTC4088-1/LTC4088-2 drives
OUT
the gate of the external P-channel MOSFET transistor for
automatic ideal diode control. The source of the external
P-channel MOSFET should be connected to V
and the
OUT
V
BUS
Undervoltage Lockout (UVLO)
AninternalundervoltagelockoutcircuitmonitorsV and
BUS
2200
VISHAY Si2333
keepstheswitchingregulatoroffuntilV
risesabovethe
2000
BUS
EXTERNAL
1800
IDEAL DIODE
risingUVLOthreshold(4.3V).IfV
fallsbelowthefalling
BUS
1600
UVLO threshold (4V), system power at V
will be drawn
OUT
1400
1200
1000
800
600
400
200
0
LTC4088-1/
LTC4088-2
IDEAL DIODE
from the battery via the ideal diodes. The voltage at V
BUS
must also be higher than the voltage at BAT by approxi-
mately170mVfortheswitchingregulatortooperate.
ON
SEMICONDUCTOR
MBRM120LT3
Battery Charger
V
= 5V
The LTC4088-1/LTC4088-2 includes a constant-current/
constant-voltagebatterychargerwithautomaticrecharge,
automatic termination by safety timer, low voltage trickle
charging, bad cell detection and thermistor sensor input
for out of temperature charge pausing.
BUS
0
120 180 240 300 360 420 480
FORWARD VOLTAGE (mV) (BAT – V
60
)
OUT
408812 F03
Figure 3. Ideal Diode V-I Characteristics
40881fb
12
LTC4088-1/LTC4088-2
U
OPERATIO
When a battery charge cycle begins, the battery charger
cycles low and then high (e.g., V
replaced) or if the charger is momentarily disabled using
the D2 pin.
is removed and then
BUS
first determines if the battery is deeply discharged. If the
batteryvoltageisbelowV ,typically2.85V,anautomatic
TRKL
trickle charge feature sets the battery charge current to
10% of the programmed value. If the low voltage persists
for more than 1/2 hour, the battery charger automatically
terminates and indicates, via the CHRG pin, that the bat-
tery was unresponsive.
Charge Current
The charge current is programmed using a single resistor
from PROG to ground. 1/1031th of the battery charge cur-
rent is delivered to PROG, which will attempt to servo to
1.000V. Thus, the battery charge current will try to reach
1031 times the current in the PROG pin. The program
resistor and the charge current are calculated using the
following equations:
OncethebatteryvoltageisaboveV ,thechargerbegins
TRKL
charginginfullpowerconstant-currentmode. Thecurrent
delivered to the battery will try to reach 1031V/R
.
PROG
Depending on available input power and external load
conditions, the battery charger may or may not be able to
charge at the full programmed rate. The external load will
always be prioritized over the battery charge current. The
USB current limit programming will always be observed
and only additional power will be available to charge the
battery. When system loads are light, battery charge cur-
rent will be maximized.
1031V
ICHG
1031V
RPROG
RPROG
=
, ICHG =
Ineithertheconstant-currentorconstant-voltagecharging
modes, the voltage at the PROG pin will be proportional
to the actual charge current delivered to the battery. The
chargecurrentcanbedeterminedatanytimebymonitoring
the PROG pin voltage and using the following equation:
Charge Termination
The battery charger has a built-in safety timer. Once the
voltage on the battery reaches the pre-programmed float
voltageof4.200V,thechargerwillregulatethebatteryvolt-
age there and the charge current will decrease naturally.
Once the charger detects that the battery has reached
4.200V, the 4-hour safety timer is started. After the safety
timer expires, charging of the battery will discontinue and
no more current will be delivered.
VPROG
RPROG
IBAT
=
•1031
In many cases, the actual battery charge current, I , will
BAT
belowerthantheprogrammedcurrent,I ,duetolimited
CHG
input power available and prioritization to the system load
drawn from V
.
OUT
Charge Status Indication
Automatic Recharge
The CHRG pin indicates the status of the battery charger.
FourpossiblestatesarerepresentedbyCHRGwhichinclude
charging, not charging (or float charge current less than
programmedendofchargeindicationcurrent),unrespon-
sive battery and battery temperature out of range.
Once the battery charger terminates, it will remain off
drawing only microamperes of current from the battery.
If the portable product remains in this state long enough,
the battery will eventually self discharge. To ensure that
the battery is always topped off, a charge cycle will au-
tomatically begin when the battery voltage falls below
The signal at the CHRG pin can be easily recognized as
one of the above four states by either a human or a mi-
croprocessor. An open-drain output, the CHRG pin can
drive an indicator LED through a current limiting resistor
for human interfacing or simply a pull-up resistor for
microprocessor interfacing.
V
(typically 4.1V). In the event that the safety timer
RECHRG
is running when the battery voltage falls below V
, it
RECHRG
will reset back to zero. To prevent brief excursions below
fromresettingthesafetytimer,thebatteryvoltage
V
RECHRG
must be below V
for more than 1.5ms. The charge
RECHRG
cycle and safety timer will also restart if the V
UVLO
BUS
40881fb
13
LTC4088-1/LTC4088-2
U
OPERATIO
pingivesthebatteryfaultindication.Forthisfault,ahuman
would easily recognize the frantic 6.1Hz “fast” blink of the
LEDwhileamicroprocessorwouldbeabletodecodeeither
the 12.5% or 87.5% duty cycles as a bad cell fault.
To make the CHRG pin easily recognized by both humans
and microprocessors, the pin is either a DC signal of ON
for charging, OFF for not charging or it is switched at high
frequency(35kHz)toindicatethetwopossiblefaults.While
switching at 35kHz, its duty cycle is modulated at a slow
rate that can be recognized by a human.
BecausetheLTC4088-1/LTC4088-2isa3-terminalPower-
Pathproduct,systemloadisalwaysprioritizedoverbattery
charging. Due to excessive system load, there may not
be sufficient power to charge the battery beyond the bad
cell threshold voltage within the bad cell timeout period.
In this case the battery charger will falsely indicate a bad
cell. System software may then reduce the load and reset
the battery charger to try again.
When charging begins, CHRG is pulled low and remains
lowforthedurationofanormalchargecycle.Whencharg-
ing is complete, as determined by the criteria set by the
C/X pin, the CHRG pin is released (Hi-Z). The CHRG pin
does not respond to the C/X threshold if the LTC4088-1/
LTC4088-2 is in V
current limit. This prevents false end
BUS
of charge indications due to insufficient power available
to the battery charger. If a fault occurs while charging, the
pin is switched at 35kHz. While switching, its duty cycle
is modulated between a high and low value at a very low
frequency. The low and high duty cycles are disparate
enough to make an LED appear to be on or off thus giving
the appearance of “blinking”. Each of the two faults has
its own unique “blink” rate for human recognition as well
as two unique duty cycles for machine recognition.
Although very improbable, it is possible that a duty cycle
reading could be taken at the bright-dim transition (low
duty cycle to high duty cycle). When this happens the
duty cycle reading will be precisely 50%. If the duty cycle
reading is 50%, system software should disqualify it and
take a new duty cycle reading.
C/X Determination
The current exiting the C/X pin represents 1/1031th of
the battery charge current. With a resistor from C/X to
ground that is X/10 times the resistor at the PROG pin,
the CHRG pin releases when the battery current drops to
Table 2 illustrates the four possible states of the CHRG
pin when the battery charger is active.
Table 2. CHRG Signal
C/X. For example, if C/10 detection is desired, R should
MODULATION
FREQUENCY (BLINK) FREQUENCY
DUTY
CYCLES
C/X
STATUS
be made equal to R
PROG
state is given by:
. For C/20, R would be twice
. The current threshold at which CHRG will change
PROG
C/X
Charging
0Hz
0Hz
0Hz (Low Z)
0Hz (Hi-Z)
100%
0%
R
I
< C/X
BAT
NTC Fault
35kHz
35kHz
1.5Hz at 50%
6.1Hz at 50%
6.25% or 93.75%
12.5% or 87.5%
VC/X
RC/X
Bad Battery
IBAT
=
•1031
Notice that an NTC fault is represented by a 35kHz pulse
trainwhosedutycycletogglesbetween6.25%and93.75%
at a 1.5Hz rate. A human will easily recognize the 1.5Hz
rate as a “slow” blinking which indicates the out of range
battery temperature while a microprocessor will be able
to decode either the 6.25% or 93.75% duty cycles as an
NTC fault.
With this design, C/10 detection can be achieved with only
one resistor rather than a resistor for both the C/X pin and
the PROG pin. Since both of these pins have 1/1031 of the
battery charge current in them, their voltages will be equal
when they have the same resistor value. Therefore, rather
thanusingtworesistors, theC/XpinandthePROGpincan
be connected together and the resistors can be paralleled
to a single resistor of 1/2 of the program resistor.
If a battery is found to be unresponsive to charging (i.e.,
its voltage remains below 2.85V for 1/2 hour), the CHRG
40881fb
14
LTC4088-1/LTC4088-2
U
OPERATIO
NTC Thermistor
Thermal Regulation
The battery temperature is measured by placing a nega- To prevent thermal damage to the IC or surrounding
tive temperature coefficient (NTC) thermistor close to components, an internal thermal feedback loop will
the battery pack. The NTC circuitry is shown in the Block automatically decrease the programmed charge current
Diagram.
if the die temperature rises to approximately 110°C.
Thermal regulation protects the LTC4088-1/LTC4088-2
from excessive temperature due to high power operation
or high ambient thermal conditions, and allows the user
to push the limits of the power handling capability with a
given circuit board design without risk of damaging the
LTC4088-1/LTC4088-2orexternalcomponents.Thebenefit
oftheLTC4088-1/LTC4088-2thermalregulationloopisthat
charge current can be set according to actual conditions
rather than worst-case conditions for a given application
with the assurance that the charger will automatically
reduce the current in worst-case conditions.
To use this feature, connect the NTC thermistor, R
,
,
NTC
NOM
betweentheNTCpinandgroundandabiasresistor, R
fromV toNTC.R
shouldbea1%resistorwithavalue
BUS
NOM
equal to the value of the chosen NTC thermistor at 25°C
(R25).A100kthermistorisrecommendedsincethermistor
currentisnotmeasuredbytheLTC4088-1/LTC4088-2and
will have to be considered for USB compliance.
The LTC4088-1/LTC4088-2 will pause charging when the
resistance of the NTC thermistor drops to 0.54 times the
value of R25 or approximately 54k (for a Vishay “Curve
1” thermistor, this corresponds to approximately 40°C).
If the battery charger is in constant voltage (float) mode, Shutdown Mode
the safety timer also pauses until the thermistor indicates
a return to a valid temperature. As the temperature drops,
theresistanceoftheNTCthermistorrises.TheLTC4088-1/
LTC4088-2 is also designed to pause charging when the
valueoftheNTCthermistorincreasesto3.25timesthevalue
of R25. For a Vishay “Curve 1” thermistor, this resistance,
325k, correspondstoapproximately0°C. Thehotandcold
comparators each have approximately 3°C of hysteresis
to prevent oscillation about the trip point. Grounding the
NTC pin disables all NTC functionality.
The input switching regulator is enabled whenever V
BUS
is above the UVLO voltage and the LTC4088-1/LTC4088-2
is not in one of the two USB suspend modes (500µA or
2.5mA).
The ideal diode is enabled at all times and cannot be
disabled.
40881fb
15
LTC4088-1/LTC4088-2
U
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APPLICATIO S I FOR ATIO
CLPROG Resistor and Capacitor
ables the synchronous rectifier as current approaches
zero. This comparator will minimize the effect of current
reversal on the average input current measurement.
For some low inductance values, however, the inductor
current may reverse slightly. This value depends on the
speed of the comparator in relation to the slope of the
As described in the Step-Down Input Regulator section,
the resistor on the CLPROG pin determines the average
input current limit in each of the six current limit modes.
The input current will be comprised of two components,
the current that is used to drive V
and the quiescent
OUT
current waveform, given by V /L, where V is the voltage
L
L
current of the switching regulator. To ensure that the USB
specificationisstrictlymet, bothcomponentsofinputcur-
rent should be considered. The Electrical Characteristics
table gives the typical values for quiescent currents in all
settings as well as current limit programming accuracy.
To get as close to the 500mA or 100mA specifications as
possible, a precision resistor should be used.
across the inductor (approximately –V ) and L is the
OUT
inductance value.
An inductance value of 3.3µH is a good starting value. The
ripple will be small enough for the regulator to remain in
continuousconductionat100mAaverageV
current.At
BUS
lighter loads the current-reversal comparator will disable
thesynchronousrectifieratacurrentslightlyabove0mA.As
theinductanceisreducedfromthisvalue,thepartwillenter
discontinuous conduction mode at progressively higher
An averaging capacitor is required in parallel with the
resistor so that the switching regulator can determine
the average input current. This capacitor also provides
the dominant pole for the feedback loop when current
limit is reached. To ensure stability, the capacitor on
CLPROG should be 0.47µF or larger. Alternatively, faster
transient response may be obtained with 0.1µF in series
with 8.2Ω.
loads. Ripple at V
will increase, directly proportionally
OUT
to the magnitude of inductor ripple. Transient response,
however, will be improved. The current mode controller
controls inductor current to exactly the amount required
by the load to keep V
in regulation. A transient load
OUT
steprequirestheinductorcurrenttochangetoanewlevel.
Sinceinductorcurrentcannotchangeinstantaneously,the
Choosing the Inductor
capacitance on V
delivers or absorbs the difference in
Becausetheaverageinputcurrentcircuitdoesnotmeasure
OUT
current until the inductor current can change to meet the
new load demand. A smaller inductor changes its current
morequicklyforagivenvoltagedrivethanalargerinductor,
resultinginfastertransientresponse.Alargerinductorwill
reduce output ripple and current ripple, but at the expense
reverse current (i.e., current from V
to V ), cur-
OUT
BUS
rent reversal in the inductor at light loads will contribute
an error to the V current measurement. The error is
BUS
conservative in that if the current reverses, the voltage
at CLPROG will be higher than what would represent the
actual average input current drawn. The current available
for charging and the system load is thus reduced. The
USB specification will not be violated.
ofreducedtransientperformance(ormoreC
required)
VOUT
and a physically larger inductor package size.
The input regulator has an instantaneous peak current
clamp to prevent the inductor from saturating during tran-
sient load or start-up conditions. The clamp is designed
so that it does not interfere with normal operation at
highloadswithreasonableinductorripple.Itwillprevent
inductor current runaway in case of a shorted output.
This reduction in available V
current will happen when
BUS
the peak-peak inductor ripple is greater than twice the
average current limit setting. For example, if the average
current limit is set to 100mA, the peak-peak ripple should
notexceed200mA. Iftheinputcurrentislessthan100mA,
the measurement accuracy may be reduced, but it does
not affect the average current loop since it will not be in
regulation.
The DC winding resistance and AC core losses of the
inductor will affect efficiency, and therefore available
output power. These effects are difficult to characterize
and vary by application. Some inductors which may be
suitable for this application are listed in Table 3.
The LTC4088-1/LTC4088-2 includes a current-reversal
comparator which monitors inductor current and dis-
40881fb
16
LTC4088-1/LTC4088-2
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APPLICATIO S I FOR ATIO
Table 3. Recommended Inductors for the LTC4088-1/LTC4088-2
L
(µH)
MAX I
(A)
MAX DCR
SIZE IN mm
(L × W × H)
DC
INDUCTOR TYPE
(Ω)
MANUFACTURER
LPS4018
3.3
2.2
0.08
Coilcraft
www.coilcraft.com
3.9 × 3.9 × 1.7
D53LC
DB318C
3.3
3.3
2.26
1.55
0.034
0.070
Toko
www.toko.com
5 × 5 × 3
3.8 × 3.8 × 1.8
WE-TPC Type M1
3.3
1.95
0.065
Würth Elektronik
www.we-online.com
4.8 × 4.8 × 1.8
CDRH6D12
CDRH6D38
3.3
3.3
2.2
3.5
0.0625
0.020
Sumida
www.sumida.com
6.7 × 6.7 × 1.5
7 × 7 × 4
VBUS and VOUT Bypass Capacitors
There are several types of ceramic capacitors avail-
able each having considerably different characteristics.
Forexample,X7Rceramiccapacitorshavethebestvoltage
and temperature stability. X5R ceramic capacitors have
apparentlyhigherpackingdensitybutpoorerperformance
over their rated voltage and temperature ranges. Y5V
ceramic capacitors have the highest packing density,
but must be used with caution, because of their extreme
nonlinearcharacteristicofcapacitanceversusvoltage.The
actualin-circuitcapacitanceofaceramiccapacitorshould
be measured with a small AC signal and DC bias as is
expectedin-circuit.Manyvendorsspecifythecapacitance
verse voltage with a 1VRMS AC test signal and, as a result,
over state the capacitance that the capacitor will present
in the application. Using similar operating conditions as
the application, the user must measure or request from
the vendor the actual capacitance to determine if the
selected capacitor meets the minimum capacitance that
the application requires.
The style and value of capacitors used with the
LTC4088-1/LTC4088-2 determine several important
parameters such as regulator control-loop stability and
inputvoltageripple.BecausetheLTC4088-1/LTC4088-2
uses a step-down switching power supply from VBUS
to VOUT, its input current waveform contains high fre-
quency components. It is strongly recommended that
a low equivalent series resistance (ESR) multilayer ce-
ramic capacitor be used to bypass VBUS. Tantalum and
aluminum capacitors are not recommended because
of their high ESR. The value of the capacitor on VBUS
directly controls the amount of input ripple for a given
load current. Increasing the size of this capacitor will
reduce the input ripple. The USB specification allows a
maximum of 10µF to be connected directly across the
USB power bus. If additional capacitance is required
for noise performance, a soft-connect circuit may be
required to limit inrush current and avoid excessive
transient voltage drops on the bus (see Figure 5).
Overprogramming the Battery Charger
To prevent large VOUT voltage steps during transient
load conditions, it is also recommended that a ceramic
capacitorbeusedtobypassVOUT.Theoutputcapacitoris
used in the compensation of the switching regulator. At
least10µFwithlowESRarerequiredonVOUT.Additional
capacitance will improve load transient performance
and stability.
The USB high power specification allows for up to 2.5W
to be drawn from the USB port. The switching regulator
transforms the voltage at VBUS to just above the voltage
at BAT with high efficiency, while limiting power to less
than the amount programmed at CLPROG. The charger
should be programmed (with the PROG pin) to deliver the
maximumsafechargingcurrentwithoutregardtotheUSB
specifications. If there is insufficient current available to
charge the battery at the programmed rate, it will reduce
charge current until the system load on VOUT is satisfied
and the VBUS current limit is satisfied. Programming the
Multilayer ceramic chip capacitors typically have excep-
tional ESR performance. MLCCs combined with a tight
boardlayoutandanunbrokengroundplanewillyieldvery
good performance and low EMI emissions.
40881fb
17
LTC4088-1/LTC4088-2
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APPLICATIO S I FOR ATIO
charger for more current than is available will not cause
theaverageinputcurrentlimittobeviolated. Itwillmerely
allow the battery charger to make use of all available
power to charge the battery as quickly as possible, and
with minimal power dissipation within the charger.
R1 = Optional temperature range adjustment resistor
(see Figure 4b)
The trip points for the LTC4088-1/LTC4088-2’s tempera-
ture qualification are internally programmed at 0.349 •
V
for the hot threshold and 0.765 • V
for the cold
BUS
threshold.
BUS
Alternate NTC Thermistors and Biasing
Therefore, the hot trip point is set when:
TheLTC4088-1/LTC4088-2providestemperaturequalified
charging if a grounded thermistor and a bias resistor are
connected to NTC. By using a bias resistor whose value is
equal to the room temperature resistance of the thermis-
tor (R25) the upper and lower temperatures are pre-pro-
grammed to approximately 40°C and 0°C, respectively
(assuming a Vishay “Curve 1” thermistor).
RNTC|HOT
• VBUS = 0.349 • VBUS
RNOM + RNTC|HOT
and the cold trip point is set when:
RNTC|COLD
• VBUS = 0.765 • VBUS
RNOM + RNTC|COLD
The upper and lower temperature thresholds can be ad-
justed by either a modification of the bias resistor value
or by adding a second adjustment resistor to the circuit.
If only the bias resistor is adjusted, then either the upper
or the lower threshold can be modified but not both. The
other trip point will be determined by the characteristics
of the thermistor. Using the bias resistor in addition to an
adjustmentresistor,boththeupperandthelowertempera-
ture trip points can be independently programmed with
the constraint that the difference between the upper and
lower temperature thresholds cannot decrease. Examples
of each technique are given below.
Solving these equations for R
results in the following:
and R
NTC|HOT
NTC|COLD
R
= 0.536 • R
NTC|HOT
NOM
and
R
= 3.25 • R
NTC|COLD
NOM
By setting R
equal to R25, the above equations result
NOM
= 0.536 and r
in r
= 3.25. Referencing these ratios
HOT
COLD
to the Vishay Resistance-Temperature Curve 1 chart gives
a hot trip point of about 40°C and a cold trip point of about
0°C. The difference between the hot and cold trip points
is approximately 40°C.
NTC thermistors have temperature characteristics which
areindicatedonresistance-temperatureconversiontables.
TheVishay-DalethermistorNTHS0603N011-N1003F,used
in the following examples, has a nominal value of 100k
and follows the Vishay “Curve 1” resistance-temperature
characteristic.
By using a bias resistor, R , different in value from R25,
NOM
the hot and cold trip points can be moved in either direc-
tion. The temperature span will change somewhat due to
the non-linear behavior of the thermistor. The following
equations can be used to easily calculate a new value for
the bias resistor:
In the explanation below, the following notation is used.
R25 = Value of the Thermistor at 25°C
rHOT
0.536
RNOM
=
=
•R25
R
= Value of thermistor at the cold trip point
= Value of the thermistor at the hot trip
NTC|COLD
R
point
NTC|HOT
rCOLD
3.25
RNOM
•R25
r
r
= Ratio of R
to R25
COLD
NTC|COLD
where r
and r
are the resistance ratios at the
COLD
desiredHhOoTtandcoldtrippoints. Notethattheseequations
are linked. Therefore, only one of the two trip points can
40881fb
= Ratio of R
to R25
HOT
NTC|COLD
R
=Primarythermistorbiasresistor(seeFigure4a)
NOM
18
LTC4088-1/LTC4088-2
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APPLICATIO S I FOR ATIO
be chosen, the other is determined by the default ratios
designed in the IC. Consider an example where a 60°C
hot trip point is desired.
the nearest 1% value is 105k:
R1 = 0.536 • 105k – 0.4368 • 100k = 12.6k
the nearest 1% value is 12.7k. The final solution is shown
in Figure 4b and results in an upper trip point of 45°C and
a lower trip point of 0°C.
FromtheVishayCurve1R-Tcharacteristics,r is0.2488
HOT
at 60°C. Using the above equation, R
should be set
NOM
to 46.4k. With this value of R
, the cold trip point is
NOM
about 16°C. Notice that the span is now 44°C rather than
the previous 40°C. This is due to the decrease in “tem-
perature gain” of the thermistor as absolute temperature
increases.
USB Inrush Limiting
TheUSBspecificationallowsatmost10µFofdownstream
capacitance to be hot-plugged into a USB hub. In most
LTC4088-1/LTC4088-2 applications, 10µF should be
The upper and lower temperature trip points can be inde-
pendentlyprogrammedbyusinganadditionalbiasresistor
asshowninFigure4b. Thefollowingformulascanbeused
enough to provide adequate filtering on V . If more
BUS
capacitance is required, the following circuit can be used
to soft-connect additional capacitance.
to compute the values of R
and R1:
NOM
MP1
Si2333
rCOLD –rHOT
RNOM
=
•R25
V
BUS
2.714
C1
100nF
5V USB
INPUT
R1= 0.536 •RNOM –rHOT •R25
LTC4088-1/
LTC4088-2
USB CABLE
C2
R1
40k
For example, to set the trip points to 0°C and 45°C with
a Vishay Curve 1 thermistor choose:
GND
408812 F05
3.266 – 0.4368
Figure 5. USB Soft-Connect Circuit
RNOM
=
•100k = 104.2k
2.714
LTC4088-1/LTC4088-2
NTC BLOCK
V
V
BUS
LTC4088-1/LTC4088-2
NTC BLOCK
V
V
BUS
BUS
BUS
0.765 • V
0.765 • V
BUS
BUS
R
R
NOM
105k
NTC
NOM
–
–
+
100k
TOO_COLD
TOO_COLD
TOO_HOT
NTC
1
+
1
R
R1
12.7k
NTC
T
100k
–
+
–
+
TOO_HOT
0.349 • V
0.349 • V
BUS
BUS
R
NTC
T
100k
+
–
+
–
NTC_ENABLE
NTC_ENABLE
0.1V
0.1V
408812 F04a
408812 F04b
(4a)
(4b)
Figure 4. NTC Circuits
40881fb
19
LTC4088-1/LTC4088-2
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APPLICATIO S I FOR ATIO
put capacitor be as close to the LTC4088-1/LTC4088-2
as possible and that there be an unbroken ground plane
under the LTC4088-1/LTC4088-2 and all of its external
high frequency components. High frequency currents,
such as the input current on the LTC4088-1/LTC4088-2,
tend to find their way on the ground plane along a mirror
path directly beneath the incident path on the top of the
board. If there are slits or cuts in the ground plane due to
other traces on that layer, the current will be forced to go
aroundtheslits. Ifhighfrequencycurrentsarenotallowed
to flow back through their natural least-area path, exces-
sivevoltagewillbuildupandradiatedemissionswilloccur
(see Figure 6). There should be a group of vias directly
under the grounded backside leading directly down to an
internal ground plane. To minimize parasitic inductance,
the ground plane should be as close as possible to the
top plane of the PC board (layer 2).
In this circuit, capacitor C1 holds MP1 off when the cable
is first connected. Eventually the bottom plate of C1 dis-
chargestoGND, applyingincreasinggatesupporttoMP1.
The long time constant of R1 and C1 prevent the current
from building up in the cable too fast, thus dampening
out any resonant overshoot.
Voltage overshoot on V
may sometimes be observed
BUS
whenconnectingtheLTC4088-1/LTC4088-2toalabpower
supply. This overshoot is caused by long leads from the
power supply to V . Twisting the wires together from
BUS
the supply to V
can greatly reduce the parasitic induc-
BUS
tance of these long leads, and keep the voltage at V
to
BUS
safe levels. USB cables are generally manufactured with
the power leads in close proximity, and thus fairly low
parasitic inductance.
Board Layout Considerations
The GATE pin for the external ideal diode controller has
extremely limited drive current. Care must be taken to
minimize leakage to adjacent PC board traces. 100nA of
leakage from this pin will introduce an additional offset to
theidealdiodeofapproximately10mV.Tominimizeleakage,
the trace can be guarded on the PC board by surrounding
The Exposed Pad on the backside of the LTC4088-1/
LTC4088-2 package must be securely soldered to the PC
board ground. This is the only ground pin in the package,
anditservesasthereturnpathforboththecontrolcircuitry
and the synchronous rectifier.
Furthermore, duetoitshighfrequencyswitchingcircuitry,
it is imperative that the input capacitor, inductor, and out-
it with V
connected metal, which should generally be
OUT
less than one volt higher than GATE.
408812 F06
Figure 6. Ground Currents Follow Their Incident Path
at High Speed. Slices in the Ground Plane Cause High
Voltage and Increased Emissions
40881fb
20
LTC4088-1/LTC4088-2
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APPLICATIO S I FOR ATIO
In constant-current mode, the PROG pin is in the feed-
back loop rather than the battery voltage. Because of the
additional pole created by any PROG pin capacitance,
capacitance on this pin must be kept to a minimum. With
no additional capacitance on the PROG pin, the charger
is stable with program resistor values as high as 25k.
However, additional capacitance on this node reduces the
maximumallowedprogramresistor.Thepolefrequencyat
the PROG pin should be kept above 100kHz. Therefore, if
Battery Charger Stability Considerations
TheLTC4088-1/LTC4088-2’sbatterychargercontainsboth
aconstant-voltageandaconstant-currentcontrolloop.The
constant-voltage loop is stable without any compensation
when a battery is connected with low impedance leads.
Excessive lead length, however, may add enough series
inductance to require a bypass capacitor of at least 1µF
from BAT to GND.
High value, low ESR multilayer ceramic chip capacitors
reduce the constant-voltage loop phase margin, possibly
resulting in instability. Ceramic capacitors up to 22µF may
beusedinparallelwithabattery,butlargerceramicsshould
be decoupled with 0.2Ω to 1Ω of series resistance.
the PROG pin has a parasitic capacitance, C
, the fol-
PROG
lowing equation should be used to calculate the maximum
resistance value for R
:
PROG
1
RPROG
≤
2π •100kHz •CPROG
Furthermore, a4.7µFcapacitorinserieswitha0.2Ωto1Ω
resistor from BAT to GND is required to prevent oscillation
when the battery is disconnected.
40881fb
21
LTC4088-1/LTC4088-2
U
TYPICAL APPLICATIO S
High Efficiency Battery Charger/USB Power Manager
with NTC Qualified Charging and Reverse Input Protection
L1
WALL
USB
3.3µH
M2
V
SW
V
LOAD
BUS
OUT
D0
D1
D2
CHRG
V
OUTS
R1
100k
LTC4088-1/
LTC4088-2
GATE
M1
µC
C1
10µF
0805
C3
10µF
0805
BAT
NTC
CLPROG PROG C/X GND
+
Li-Ion
R2
T
C2
0.1µF
0603
R5
8.2Ω
R3
2.94k
100k
R4
499Ω
408812 TA02
C1, C3: MURATA GRM21BR61A106KE19
C2: MURATA GRM188R71C104KA01
L1: COILCRAFT LPS4018-332MLC
M1, M2: SILICONIX Si2333
R2: VISHAY-DALE NTHS0603N011-N1003F
40881fb
22
LTC4088-1/LTC4088-2
U
PACKAGE DESCRIPTIO
DE Package
14-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1708 Rev B)
0.70 ±0.05
3.30 ±0.05
1.70 ± 0.05
3.60 ±0.05
2.20 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
3.00 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
R = 0.115
TYP
0.40 ± 0.10
4.00 ±0.10
(2 SIDES)
8
14
R = 0.05
TYP
3.30 ±0.10
3.00 ±0.10
(2 SIDES)
1.70 ± 0.10
PIN 1 NOTCH
R = 0.20 OR
PIN 1
TOP MARK
(SEE NOTE 6)
0.35 × 45°
CHAMFER
(DE14) DFN 0806 REV B
7
1
0.25 ± 0.05
0.75 ±0.05
0.200 REF
0.50 BSC
3.00 REF
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
40881fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC4088-1/LTC4088-2
RELATED PARTS
PART NUMBER
Battery Chargers
LTC4057
DESCRIPTION
COMMENTS
Lithium-Ion Linear Battery Charger
Up to 800mA Charge Current, Thermal Regulation, ThinSOTTM Package
LTC4058
Standalone 950mA Lithium-Ion Charger in DFN C/10 Charge Termination, Battery Kelvin Sensing, 7ꢀ Charge
Accuracy
LTC4065/LTC4065A 750mA Linear Lithium-Ion Battery Charger
2mm × 2mm DFN Package, Thermal Regulation, Standalone Operation
LTC4411/LTC4412
Low Loss Single PowerPath Controllers in
ThinSOT
Automatic Switching Between DC Sources, Load Sharing,
Replaces ORing Diodes
LTC4413
Dual Ideal Diodes
3mm × 3mm DFN Package, Low Loss Replacement for ORing Diodes
Power Management
LTC3406/LTC3406A 600mA (IOUT), 1.5MHz, Synchronous
Step-Down DC/DC Converter
95ꢀ Efficiency, VIN: 2.5V to 5.5V, VOUT = 0.6V, IQ = 20µA, ISD < 1µA,
ThinSOT Package
LTC3411
1.25A (IOUT), 4MHz, Synchronous Step-Down
DC/DC Converter
95ꢀ Efficiency, VIN: 2.5V to 5.5V, VOUT = 0.8V, IQ = 60µA, ISD < 1µA,
MS10 Package
LTC3455
Dual DC/DC Converter with USB Power Manager Seamless Transition Between Power Sources: USB, Wall Adapter and
and Li-Ion Battery Charger
Battery; 95ꢀ Efficient DC/DC Conversion
LTC3557/LTC3557-1 USB Power Manager with Li-Ion/Polymer
Charger, Triple Synchronous Buck Converter
+ LDO
Complete Multi-Function PMIC: Linear Power Manager and Three
Buck Regulators, Charge Current Programmable Up to 1.5A from Wall
Adapter Input, Thermal Regulation, Synchronous Buck Converters
Efficiency: >95ꢀ, ADJ Outputs: 0.8V to 3.6V at 400mA/400mA/600mA,
Bat-Track Adaptive Output Control, 200mΩ Ideal Diode, 4mm × 4mm
QFN-28 Package.
LTC4055
LTC4066
LTC4085
USB Power Controller and Battery Charger
USB Power Controller and Battery Charger
Charges Single-Cell Li-Ion Batteries Directly from a USB Port, Thermal
Regulation, 200mΩ Ideal Diode, 4mm × 4mm QFN-16 Package
Charges Single-Cell Li-Ion Batteries Directly from a USB Port, Thermal
Regulation, 50mΩ Ideal Diode, 4mm × 4mm QFN-24 Package
USB Power Manager with Ideal Diode Controller Charges Single-Cell Li-Ion Batteries Directly from a USB Port, Thermal
and Li-Ion Charger
Regulation, 200mΩ Ideal Diode with <50mΩ Option, 4mm × 3mm
DFN-14 Package
LTC4088
High Efficiency USB Power Manager and Battery Maximizes Available Power from USB Port, Bat-Track, “Instant-On”
Charger
Operation, 1.5A Max Charge Current, 180mΩ Ideal Diode with <50mΩ
Option, 3.3V/25mA Always-On LDO, 4mm × 3mm DFN-14 Package
LTC4089/LTC4089-5 USB Power Manager with Ideal Diode Controller High Efficiency 1.2A Charger from 6V to 36V (40V Max) Input. Charges
and High Efficiency Li-Ion Battery Charger
Single-Cell Li-Ion/Polymer Batteries Directly from a USB Port, Thermal
Regulation, 200mΩ Ideal Diode with <50mΩ Option, 4mm × 3mm
DFN-14 Package. Bat-Track Adaptive Output Control (LTC4089), Fixed
5V Output (LTC4089-5)
ThinSOT is a trademark of Linear Technology Corporation.
40881fb
LT 0907 REV B • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
●
●
© LINEAR TECHNOLOGY CORPORATION 2007
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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