LTC3850-2 [Linear]
Dual, 2-Phase Synchronous Step-Down Switching Controller; 双通道，两相同步降压型开关控制器
| 型号： | LTC3850-2 |
| 厂家： | 
Linear |
| 描述： | Dual, 2-Phase Synchronous Step-Down Switching Controller |
| 文件： | 总36页 (文件大小：402K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3850-2
Dual, 2-Phase
Synchronous Step-Down
Switching Controller
DESCRIPTION
The LTC®3850-2 is a high performance dual synchronous
step-down switching regulator controller that drives all
N-channel power MOSFET stages. A constant-frequency
current mode architecture allows a phase-lockable
frequency of up to 780kHz. Power loss and supply noise
are minimized by operating the two controller output
stages out of phase.
OPTI-LOOP® compensation allows the transient response
to be optimized over a wide range of output capacitance
and ESR values. The LTC3850-2 features a precision 0.8V
reference and a power good output indicator. A wide 4V
to 30V input supply range encompasses most battery
chemistries and intermediate bus voltages.
FEATURES
n
Dual, 180° Phased Controllers Reduce Required
Input Capacitance and Power Supply Induced Noise
n
High Efficiency: Up to 95%
n
R
or DCR Current Sensing
SENSE
n
n
n
n
n
n
n
n
n
n
1% 0.8V Output Voltage Accuracy
Phase-Lockable Fixed Frequency 250kHz to 780kHz
Supports Pre-Biased Output
Dual N-Channel MOSFET Synchronous Drive
Wide V Range: 4V to 30V Operation
IN
Adjustable Soft-Start Current Ramping or Tracking
Foldback Output Current Limiting
Output Overvoltage Protection
Power Good Output Voltage Monitor
28-Pin Narrow SSOP Package
Independent TK/SS pins for each controller ramp the
output voltages during start-up. Current foldback limits
MOSFET heat dissipation during short-circuit condi-
tions. The MODE/PLLIN pin selects among Burst Mode®
operation, pulse-skipping mode, or continuous inductor
current mode and allows the IC to be synchronized to an
external clock.
APPLICATIONS
n
Notebook and Palmtop Computers
n
Portable Instruments
n
Battery-Operated Digital Devices
DC Power Distribution Systems
n
L, LT, LTC, LTM, OPTI-LOOP and Burst Mode are registered trademarks of Linear Technology
Corporation. All other trademarks are the property of their respective owners. Protected by U.S.
Patents, including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 6304066, 6580258.
The LTC3850-2 is identical to the LTC3850-1, except they
have different pin assignments.
TYPICAL APPLICATION
High Efficiency Dual 3.3V/2.5V Step-Down Converter
Efficiency
V
IN
100
95
10000
1000
100
7V TO
26V
22μF
50V
V
V
= 12V
IN
OUT
4.7μF
= 3.3V
EFFICIENCY
V
PGOOD INTV
IN
CC
90
TG1
TG2
0.1μF
0.1μF
85
BOOST1
SW1
BOOST2
SW2
2.2μH
2.2μH
80
75
LTC3850-2
2.2k
BG2
PGND
BG1
70
65
60
55
50
2.2k
500kHz
MODE/PLLIN
EXT
FREQ/PLLFLTR
POWER LOSS
1000
VCC
+
+
SENSE1
RUN1
SENSE2
0.1μF
0.1μF
RUN2
–
–
V
SENSE1
SENSE2
OUT1
3.3V
5A
V
OUT2
10
10000
V
FB1
V
FB2
2.5V
10
100
5A
63.4k
43.2k
I
I
LOAD CURRENT (mA)
TH1
TH2
10nF
10k
220pF
15k
220pF
15k
38502 TA01b
TK/SS1 SGND TK/SS2
100μF
6V
100μF
6V
20k
20k
0.1μF
0.1μF
38502 TA01
38502f
1
LTC3850-2
ABSOLUTE MAXIMUM RATINGS
(Note 1)
PIN CONFIGURATION
TOP VIEW
Input Supply Voltage (V ).........................30V to –0.3V
IN
Input Supply Transient Voltage (V ) < 500ms, with
1
2
FREQ/PLLFLTR
MODE/PLLIN
SW1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RUN1
IN
+
INTV ≥ 5V...........................................34V to –0.3V
SENSE1
CC
–
3
SENSE1
Top Side Driver Voltages
4
TG1
V
BOOST1, BOOST2..................................34V to –0.3V
Switch Voltage (SW1, SW2) .........................30V to –5V
FB1
5
BOOST1
BG1
TK/SS1
6
I
TH1
INTV , RUN1, RUN2, PGOOD, EXTV ,
CC
CC
7
V
SGND
IN
(BOOST1-SW1), (BOOST2-SW2).................6V to –0.3V
8
INTV
CC
I
+
–
+
–
TH2
SENSE1 , SENSE2 , SENSE1 ,
9
BG2
TK/SS2
SENSE2 Voltages.....................................5.5V to –0.3V
10
11
12
13
14
PGND
BOOST2
TG2
V
FB2
–
MODE/PLLIN, TK/SS1,TK/SS2, FREQ/PLLFLTR
SENSE2
SENSE2
Voltages................................................INTV to –0.3V
+
CC
I
, I , V , V Voltages..................2.7V to –0.3V
TH1 TH2 FB1 FB2
SW2
RUN2
EXTV
INTV Peak Output Current ................................100mA
PGOOD
CC
CC
Operating Temperature Range (Note 2)....–40°C to 85°C
Junction Temperature (Note 3) ............................. 125°C
Storage Temperature Range...................–65°C to 125°C
Lead Temperature (Soldering, 10 sec)
GN PACKAGE
28-LEAD NARROW PLASTIC SSOP
T
= 125°C, θ = 95°C/W
JA
JMAX
(GN Package).................................................... 300°C
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
28-Lead Narrow Plastic SSOP
TEMPERATURE RANGE
LTC3850IGN-2#PBF
LTC3850IGN-2#TRPBF
LTC3850GN-2
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
38502f
2
LTC3850-2
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VIN = 15V, VRUN1,2 = 5V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Main Control Loops
l
V
Regulated Feedback Voltage
Feedback Current
I
Voltage = 1.2V; (Note 4)
0.792
0.800
–10
0.808
–50
V
nA
FB1,2
TH1,2
I
(Note 4)
= 6V to 24V (Note 4)
FB1,2
V
V
Reference Voltage Line Regulation
Output Voltage Load Regulation
V
0.002
0.02
%/V
REFLNREG
IN
(Note 4)
Measured in Servo Loop; ΔI Voltage = 1.2V to 0.7V
Measured in Servo Loop; ΔI Voltage = 1.2V to 1.6V
LOADREG
l
l
0.01
–0.01
0.1
–0.1
%
%
TH
TH
g
Transconductance Amplifier g
I = 1.2V; Sink/Source 5μA; (Note 4)
TH1,2
2.2
mmho
m1,2
m
I
Q
Input DC Supply Current
Normal Mode
Shutdown
(Note 5)
IN
RUN1,2
V
V
= 15V; EXTV Tied to V ; V = 5V
850
30
μA
μA
CC
OUT1 OUT1
= 0V
50
UVLO
UVLO
Undervoltage Lockout on INTV
V
Ramping Down
3
V
V
CC
INTVCC
UVLO Hysteresis
0.5
97.2
0.86
1
HYS
DF
Maximum Duty Factor
In Dropout
96
%
V
MAX
l
V
OVL
Feedback Overvoltage Lockout
Sense Pin Bias Current
Soft-Start Charge Current
RUN Pin ON Threshold
RUN Pin ON Hysteresis
Measured at V
0.84
0.88
2
FB1,2
I
I
(Each Channel) V
= 3.3V
μA
μA
V
SENSE
SENSE1,2
V
= 0V
0.9
1.1
1.3
1.22
80
1.7
1.35
TK/SS1,2
TK/SS1,2
l
l
V
V
V
V
, V
Rising
RUN1,2
RUN1 RUN2
mV
mV
Ω
RUN1,2HYS
SENSE(MAX)
Maximum Current Sense Threshold
TG Driver Pull-Up On-Resistance
TG Driver Pulldown On-Resistance
BG Driver Pull-Up On-Resistance
BG Driver Pulldown On-Resistance
V
= 0.7V, V
= 3.3V
SENSE1,2
40
50
60
FB1,2
TG R
TG R
BG R
BG R
TG High
TG Low
BG High
BG Low
(Note 6)
2.6
1.5
2.4
1.1
UP
Ω
DOWN
UP
Ω
Ω
DOWN
TG Transition Time:
Rise Time
Fall Time
TG1,2 t
TG1,2 t
C
C
= 3300pF
= 3300pF
25
25
ns
ns
r
f
LOAD
LOAD
BG Transition Time:
Rise Time
Fall Time
(Note 6)
LOAD
LOAD
BG1,2 t
BG1,2 t
C
C
= 3300pF
= 3300pF
25
25
ns
ns
r
f
TG/BG t
Top Gate Off to Bottom Gate On Delay
Synchronous Switch-On Delay Time
1D
C
C
= 3300pF Each Driver
30
ns
LOAD
BG/TG t
Bottom Gate Off to Top Gate On Delay
Top Switch-On Delay Time
2D
= 3300pF Each Driver
30
90
ns
ns
LOAD
t
Minimum On-Time
(Note 7)
ON(MIN)
INTV Linear Regulator
CC
V
V
V
V
V
Internal V Voltage
7V < V < 24V
4.8
4.5
5
5.2
2
V
%
INTVCC
CC
IN
INT
INTV Load Regulation
I = 0mA to 50mA
CC
0.5
4.7
50
LDO
CC
l
EXTV Switchover Voltage
EXTV Ramping Positive
V
EXTVCC
CC
CC
EXT
EXTV Voltage Drop
I
= 20mA, V = 5V
EXTVCC
100
mV
mV
LDO
CC
CC
EXTV Hysteresis
200
LDOHYS
CC
38502f
3
LTC3850-2
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VIN = 15V, VRUN1,2 = 5V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Oscillator and Phase-Locked Loop
f
f
f
Nominal Frequency
V
V
V
= 1.2V
= 0V
450
210
700
500
250
780
250
550
290
860
kHz
kHz
kHz
kΩ
NOM
LOW
HIGH
FREQ
FREQ
FREQ
Lowest Frequency
Highest Frequency
≥ 2.4V
R
MODE/PLLIN Input Resistance
MODE/PLLIN
FREQ
I
Phase Detector Output Current
Sinking Capability
Sourcing Capability
f
f
< f
> f
–13
13
μA
μA
MODE
MODE
OSC
OSC
PGOOD Output
V
PGOOD Voltage Low
PGOOD Leakage Current
PGOOD Trip Level
I
= 2mA
= 5V
0.1
0.3
2
V
PGL
PGOOD
I
V
V
μA
PGOOD
PGOOD
V
with Respect to Set Regulated Voltage
FB
PG
V
V
Ramping Negative
Ramping Positive
–5
5
–7.5
7.5
–10
10
%
%
FB
FB
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 4: The LTC3850I-2 is tested in a feedback loop that servos V
to
ITH1,2
a specified voltage and measures the resultant V
.
FB1,2
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.
Note 6: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 2: The LTC3850I-2 is guaranteed to meet performance specifications
over the –40°C to 85°C operating temperature range.
Note 7: The minimum on-time condition is specified for an inductor
Note 3: T is calculated from the ambient temperature T and power
J
A
peak-to-peak ripple current ≥40% of I
(see Minimum On-Time
MAX
dissipation P according to the following formulas:
D
Considerations in the Applications Information section).
LTC3850IGN-2: T = T + (P • 95°C/W)
J
A
D
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Output Current
and Mode
Efficiency vs Output Current
and Mode
Efficiency and Power Loss
vs Input Voltage
100
90
100
90
100
95
90
85
80
2000
1500
1000
500
0
V
V
= 12V
V
I
= 3.3V
= 2A
IN
OUT
OUT
OUT
BURST
DCM
= 1.8V
BURST
80
80
70
70
EFFICIENCY
DCM
60
50
60
50
40
30
20
10
0
40
30
20
10
0
POWER LOSS
CCM
CCM
V
V
= 12V
OUT
IN
= 3.3V
10
100
LOAD CURRENT (mA)
CIRCUIT OF FIGURE 14
1000
10000
10
100
LOAD CURRENT (mA)
CIRCUIT OF FIGURE 14
1000
10000
15
5
10
20
25
INPUT VOLTAGE (V)
38502 G03
38502 G01
38502 G02
CIRCUIT OF FIGURE 14
38502f
4
LTC3850-2
TYPICAL PERFORMANCE CHARACTERISTICS
Load Step
(Burst Mode Operation)
Load Step
(Forced Continuous Mode)
I
LOAD
I
LOAD
2A/DIV
2A/DIV
200mA TO 2.5A
200mA TO 2.5A
I
I
L
L
2A/DIV
2A/DIV
V
V
OUT
OUT
100mV/DIV
100mV/DIV
AC COUPLED
AC COUPLED
38502 G04
38502 G05
40μs/DIV
CIRCUIT OF FIGURE 14
= 12V, V = 1.8V
40μs/DIV
CIRCUIT OF FIGURE 14
V
V
IN
= 12V, V
= 1.8V
IN
OUT
OUT
Load Step
(Pulse-Skipping Mode)
Inductor Current at Light Load
FORCED
CONTINUOUS
MODE
I
LOAD
2A/DIV
200mA TO 2.5A
2A/DIV
I
L
2A/DIV
Burst Mode
OPERATION
2A/DIV
V
OUT
100mV/DIV
AC COUPLED
PULSE-SKIPPING
MODE
2A/DIV
38502 G07
38502 G06
1μs/DIV
40μs/DIV
CIRCUIT OF FIGURE 14
CIRCUIT OF FIGURE 14
V
= 12V, V
= 1.8V
V
= 12V, V
= 1.8V
IN
OUT
= 100μA
IN
OUT
I
LOAD
Prebiased Output at 2V
Coincident Tracking
RUN1
2V/DIV
V
, 3.3V
OUT1
V
OUT
V
TK/SS
3ꢀ LOAD, 1V/DIV
2V/DIV
500mV/DIV
V
, 1.8V
OUT2
V
FB
1.5ꢀ LOAD
500mV/DIV
1V/DIV
38502 G09
38502 G08
1ms/DIV
2.5ms/DIV
38502f
5
LTC3850-2
TYPICAL PERFORMANCE CHARACTERISTICS
Tracking Up and Down
with External Ramp
Quiescent Current
vs Input Voltage without EXTVCC
INTVCC Line Regulation
5.25
5.00
5
4
3
2
1
0
TK/SS1
TK/SS2
2V/DIV
4.75
4.50
4.25
4.00
3.75
3.50
V
OUT1
3.3V
3ꢀ LOAD
1V/DIV
V
OUT2
1.8V
1.5ꢀ LOAD
1V/DIV
38502 G10
10ms/DIV
5
10
15
20
5
10
15
25
25
0
20
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
38502 G11
38502 G12
Current Sense Threshold
vs ITH Voltage
Maximum Current Sense Threshold
vs Common Mode Voltage
Maximum Current Sense
Threshold vs Duty Cycle
80
60
80
70
60
50
100
90
80
70
60
50
40
30
20
10
0
40
20
40
30
0
–20
–40
20
10
0
0
0.5
1
1.5
2
1
2
4
0
5
3
20
40
DUTY CYCLE (%)
80
0
100
60
V
(V)
V
COMMON MODE VOLTAGE (V)
ITH
SENSE
38502 G13
38502 G14
38502 G15
TK/SS Pull-Up Current
vs Temperature
Maximum Current Sense Voltage vs
Feedback Voltage (Current Foldback)
2.00
1.75
1.50
1.25
1.00
80
70
60
50
40
30
20
10
0
50
TEMPERATURE (°C)
100
–50 –25
0
25
75
0.4 0.5
0.6 0.7 0.8 0.9
0
0.1 0.2 0.3
FEEDBACK VOLTAGE (V)
38502 G17
38502 G16
38502f
6
LTC3850-2
TYPICAL PERFORMANCE CHARACTERISTICS
Regulated Feedback Voltage
vs Temperature
Shutdown (RUN) Threshold
vs Temperature
Oscillator Frequency
vs Temperature
900
800
700
600
500
400
300
200
1.5
1.4
1.3
1.2
1.1
1.0
806
804
802
800
798
796
794
V
= INTV
CC
FREQ
ON
V
= 1.2V
FREQ
OFF
V
= 0V
FREQ
50
TEMPERATURE (°C)
100
50
TEMPERATURE (°C)
100
50
TEMPERATURE (°C)
100
–50 –25
0
25
75
–50 –25
0
25
75
–50 –25
0
25
75
38502 G20
38502 G18
38502 G19
Oscillator Frequency
vs Input Voltage
Undervoltage Lockout Threshold
(INTVCC) vs Temperature
Shutdown Current
vs Input Voltage
420
410
400
390
380
5
4
3
2
1
0
50
40
30
20
10
0
RISING
FALLING
10
15
20
25
5
10
15
20
25
50
TEMPERATURE (°C)
100
5
–50 –25
0
25
75
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
38502 G22
38502 G21
38502 G23
Quiescent Current
vs Temperature without EXTVCC
Shutdown Current
vs Temperature
50
40
30
20
10
0
5
4
3
2
1
0
V
= 15V
IN
50
TEMPERATURE (°C)
100
–50 –25
0
25
75
50
TEMPERATURE (°C)
100
–50 –25
0
25
75
38502 G24
38502 G25
38502f
7
LTC3850-2
PIN FUNCTIONS
RUN1,RUN2(Pin1,Pin13):RunControlInputs.Avoltage
above 1.2V on either pin turns on the IC. However, forcing
either of these pins below 1.2V causes the IC to shut down
that particular channel. There are 0.5μA pull-up currents
for these pins. Once the RUN pin rises above 1.2V, an
additional 4.5μA pull-up current is added to the pin.
PGOOD(Pin15):PowerGoodIndicatorOutput.Open-drain
logic out that is pulled to ground when either channel
output exceeds the 7.5% regulation window, after the
internal 17μs power bad mask timer expires.
PGND(Pin19):PowerGroundPin.Connectthispinclosely
to the sources of the bottom N-channel MOSFETs, the (–)
+
+
SENSE1 , SENSE2 (Pin 2, Pin 12): Current Sense
Comparator Inputs. The (+) inputs to the current
comparators are normally connected to DCR sensing
networks or current sensing resistors.
terminal of CV and the (–) terminal of C .
CC IN
INTV (Pin 21): Internal 5V Regulator Output. The con-
CC
trol circuits are powered from this voltage. Decouple this
pin to PGND with a 4.7μF low ESR tantalum or ceramic
capacitor.
–
–
SENSE1 , SENSE2 (Pin 3, Pin 11): Current Sense
Comparator Inputs. The (–) inputs to the current
comparators are connected to the outputs.
V
(Pin 22): Main Input Supply. Decouple this pin to
IN
PGND with a capacitor (0.1μF to 1μF). For applications
TK/SS1, TK/SS2 (Pin 5, Pin 9): Output Voltage Tracking
and Soft-Start Inputs. When one channel is configured to
be master of the two channels, a capacitor to ground at
this pin sets the ramp rate for the master channel’s output
voltage. When the channel is configured to be the slave
where the main input power is 5V, tie the V and INTV
pins together.
IN
CC
BG1,BG2(Pins23,20):BottomGateDriverOutputs.These
pins drive the gates of the bottom N-Channel MOSFETs
and swings between PGND and INTV .
CC
of two channels, the V voltage of the master channel is
FB
BOOST1, BOOST2 (Pins 24, 18): Boosted Floating Driver
Supplies. The (+) terminal of the boost-strap capacitors
connect to these pins. These pins swing from a diode
reproduced by a resistor divider and applied to this pin.
Internal soft-start currents of 1.3μA charge the soft-start
capacitors.
voltage drop below INTV up to V + INTV .
CC
IN
CC
I
, I
(Pin 6, Pin 8): Current Control Thresholds and
TH1 TH2
TG1,TG2(Pins25,17):TopGateDriverOutputs.Theseare
Error Amplifier Compensation Points. Each associated
channels’currentcomparatortrippingthresholdincreases
the outputs of floating drivers with a voltage swing equal
to INTV superimposed on the switch nodes voltages.
CC
with its I control voltage.
TH
SW1, SW2 (Pins 26, 16): Switch Node Connections to
V
, V
(Pin 4, Pin 10): Error Amplifier Feedback
FB1
FB2
Inductors. Voltage swing at these pins are from a body
Inputs. These pins receive the remotely sensed feedback
voltages for each channel from external resistive dividers
across the outputs.
diode voltage drop below ground to V .
IN
MODE/PLLIN (Pin 27): Force Continuous Mode, Burst
Mode, or Pulse-Skipping Mode Selection Pin and
External Synchronization Input to Phase Detector Pin.
Connect this pin to SGND to force both channels into
SGND(Pin7):SignalGround.Allsmall-signalcomponents
and compensation components should connect to this
ground, which in turn connects to PGND at one point.
the continuous mode of operation. Connect to INTV
CC
EXTV (Pin14):ExternalPowerInputtoanInternalSwitch
Connected to INTV . This switch closes and supplies the
IC power, bypassing the internal low dropout regulator,
whenever EXTV is higher than 4.7V. Do not exceed 6V
CC
to enable pulse-skipping mode of operation. Leaving the
pin floating will enable Burst Mode operation. A clock on
the pin will force the controller into continuous mode of
operation and synchronize the internal oscillator.
CC
CC
on this pin and ensure V > V
at all times.
IN
EXTVCC
FREQ/PLLFLTR (Pin 28): The Phase-Locked Loop’s
Low-Pass Filter is Tied to This Pin. Alternatively, this pin
can be driven with a DC voltage to vary the frequency of
the internal oscillator.
38502f
8
LTC3850-2
FUNCTIONAL DIAGRAM
FREQ/PLLFLTR
MODE/PLLIN
EXTV
V
IN
CC
V
IN
4.7V
+
C
IN
–
+
F
0.8V
5V
REG
MODE/SYNC
DETECT
INTV
CC
PLL-SYNC
–
+
INTV
CC
F
BOOST
BURSTEN
OSC
S
R
C
B
TG
FCNT
ON
Q
I
M1
SW
L1
SWITCH
LOGIC
AND
ANTI-
SHOOT
THROUGH
V
OUT
3k
+
–
–
+
+
D
SENSE
B
I
CMP
REV
–
SENSE
+
C
OUT
RUN
OV
BG
M2
C
VCC
SLOPE COMPENSATION
PGND
PGOOD
INTV
CC
UVLO
+
–
0.74V
R2
SLOPE RECOVERY
ACTIVE CLAMP
1
UV
OV
V
FB
51k
I
THB
+
–
V
IN
SLEEP
R1
0.86V
SGND
SS
RUN
–
–
+
+
0.8V
REF
1.3μA
EA
+ –
–
+
+
0.64V
1.2V
0.5μA
0.55V
38502 FD
C
C
SS
C1
I
RUN
TK/SS
TH
R
C
38502f
9
LTC3850-2
OPERATION
Main Control Loop
Shutdown and Start-Up (RUN1, RUN2 and TK/SS1,
TK/SS2 Pins)
The LTC3850-2 is a constant-frequency, current mode
step-down controller with two channels operating 180
degrees out-of-phase. During normal operation, each
top MOSFET is turned on when the clock for that channel
sets the RS latch, and turned off when the main current
The two channels of the LTC3850-2 can be independently
shut down using the RUN1 and RUN2 pins. Pulling either
of these pins below 1.2V shuts down the main control
loopforthatcontroller. Pullingbothpinslowdisablesboth
comparator, I
, resets the RS latch. The peak inductor
CMP
TH
FB
controllersandmostinternalcircuits,includingtheINTV
CMP
CC
current at which I
resets the RS latch is controlled by
regulator. Releasing either RUN pin allows an internal
0.5μA current to pull up the pin and enable that control-
ler. Alternatively, the RUN pin may be externally pulled up
or driven directly by logic. Be careful not to exceed the
Absolute Maximum Rating of 6V on this pin.
the voltage on the I pin, which is the output of each error
amplifier EA. The V pin receives the voltage feedback
signal, whichiscomparedtotheinternalreferencevoltage
by the EA. When the load current increases, it causes a
slight decrease in V relative to the 0.8V reference, which
FB
TH
The start-up of each controller’s output voltage V
is
OUT
in turn causes the I voltage to increase until the average
controlled by the voltage on the TK/SS1 and TK/SS2 pins.
When the voltage on the TK/SS pin is less than the 0.8V
inductor current matches the new load current. After the
top MOSFET has turned off, the bottom MOSFET is turned
on until either the inductor current starts to reverse, as
indicated by the reverse current comparator I , or the
beginning of the next cycle.
internalreference, theLTC3850-2regulatestheV voltage
FB
to the TK/SS pin voltage instead of the 0.8V reference. This
allows the TK/SS pin to be used to program a soft-start
by connecting an external capacitor from the TK/SS pin
to SGND. An internal 1.3μA pull-up current charges this
capacitor, creating a voltage ramp on the TK/SS pin. As the
TK/SS voltage rises linearly from 0V to 0.8V (and beyond),
REV
INTV /EXTV Power
CC
CC
Power for the top and bottom MOSFET drivers and most
otherinternalcircuitryisderivedfromtheINTV pin.When
theoutputvoltageV risessmoothlyfromzerotoitsfinal
CC
OUT
the EXTV pin is left open or tied to a voltage less than
value. Alternatively the TK/SS pin can be used to cause the
CC
4.7V,aninternal5VlinearregulatorsuppliesINTV power
start-up of V
to “track” that of another supply. Typically,
CC
OUT
from V . If EXTV is taken above 4.7V, the 5V regulator is
thisrequiresconnectingtotheTK/SSpinanexternalresistor
divider from the other supply to ground (see the Applica-
tions Information section). When the corresponding RUN
IN
CC
turned off and an internal switch is turned on connecting
EXTV . Using the EXTV pin allows the INTV power
CC
CC
CC
to be derived from a high efficiency external source such
as one of the LTC3850-2 switching regulator outputs.
pin is pulled low to disable a controller, or when INTV
CC
drops below its undervoltage lockout threshold of 3V, the
TK/SS pin is pulled low by an internal MOSFET. When in
undervoltage lockout, both controllers are disabled and
the external MOSFETs are held off.
Each top MOSFET driver is biased from the floating boot-
strap capacitor C , which normally recharges during each
B
off cycle through an external diode when the top MOSFET
turns off. If the input voltage V decreases to a voltage
IN
Light Load Current Operation (Burst Mode Operation,
Pulse-Skipping, or Continuous Conduction)
close to V , the loop may enter dropout and attempt
OUT
to turn on the top MOSFET continuously. The dropout
detector detects this and forces the top MOSFET off for
about one-twelfth of the clock period every third cycle to
TheLTC3850-2canbeenabledtoenterhighefficiencyBurst
Modeoperation,constant-frequencypulse-skippingmode,
or forced continuous conduction mode. To select forced
continuous operation, tie the MODE/PLLIN pin to a DC
voltage below 0.8V (e.g., SGND). To select pulse-skipping
allow C to recharge. However, it is recommended that a
B
load be present during the drop-out transition to ensure
C is recharged.
B
38502f
10
LTC3850-2
OPERATION
mode of operation, tie the MODE/PLLIN pin to INTV . To
Frequency Selection and Phase-Locked Loop
CC
select Burst Mode operation, float the MODE/PLLIN pin.
When a controller is enabled for Burst Mode operation,
the peak current in the inductor is set to approximately
one-third of the maximum sense voltage even though
(FREQ/PLLFLTR and MODE/PLLIN Pins)
Theselectionofswitchingfrequencyisatrade-offbetween
efficiency and component size. Low frequency operation
increasesefficiencybyreducingMOSFETswitchinglosses,
butrequireslargerinductanceand/orcapacitancetomain-
tain low output ripple voltage. The switching frequency
of the LTC3850-2’s controllers can be selected using the
FREQ/PLLFLTR pin. If the MODE/PLLIN pin is not being
driven by an external clock source, the FREQ/PLLFLTR
pin can be used to program the controller’s operating
frequency from 250kHz to 780kHz.
the voltage on the I pin indicates a lower value. If the
TH
average inductor current is higher than the load current,
the error amplifier EA will decrease the voltage on the I
TH
pin. When the I voltage drops below 0.5V, the internal
TH
sleep signal goes high (enabling “sleep” mode) and both
external MOSFETs are turned off.
In sleep mode, the load current is supplied by the output
capacitor. As the output voltage decreases, the EA’s output
begins to rise. When the output voltage drops enough, the
sleep signal goes low, and the controller resumes normal
operation by turning on the top external MOSFET on the
next cycle of the internal oscillator. When a controller is
enabled for Burst Mode operation, the inductor current is
not allowed to reverse. The reverse current comparator
A phase-locked loop (PLL) is available on the LTC3850-2
to synchronize the internal oscillator to an external clock
source that is connected to the MODE/PLLIN pin. The
controller is operating in forced continuous mode when
it is synchronized. A series R-C should be connected
between the FREQ/PLLFLTR pin and SGND to serve as
the PLL’s loop filter.
(I )turnsoffthebottomexternalMOSFETjustbeforethe
REV
inductor current reaches zero, preventing it from revers-
ing and going negative. Thus, the controller operates in
discontinuous operation. In forced continuous operation,
the inductor current is allowed to reverse at light loads or
underlargetransientconditions.Thepeakinductorcurrent
Power Good (PGOOD Pin)
ThePGOODpinisconnectedtoanopendrainofaninternal
N-channel MOSFET. The MOSFET turns on and pulls the
PGOOD pin low when either V pin voltage is not within
FB
7.5% of the 0.8V reference voltage. The PGOOD pin is
alsopulledlowwheneitherRUNpinisbelow1.2Vorwhen
the LTC3850-2 is in the soft-start or tracking phase. When
is determined by the voltage on the I pin, just as in nor-
TH
mal operation. In this mode, the efficiency at light loads is
lower than in Burst Mode operation. However, continuous
mode has the advantages of lower output ripple and less
interference with audio circuitry.
the V pin voltage is within the 7.5% requirement, the
FB
MOSFET is turned off and the pin is allowed to be pulled
up by an external resistor to a source of up to 6V. The
PGOOD pin will flag power good immediately when both
When the MODE/PLLIN pin is connected to INTV , the
CC
LTC3850-2 operates in PWM pulse-skipping mode at
V
pins are within the 7.5% window. However, there is
FB
light loads. At very light loads, the current comparator
an internal 17μs power bad mask when either V goes
FB
I
may remain tripped for several cycles and force the
CMP
out of the 7.5% window.
external top MOSFET to stay off for the same number of
cycles (i.e., skipping pulses). The inductor current is not
allowed to reverse (discontinuous operation). This mode,
likeforcedcontinuousoperation,exhibitslowoutputripple
as well as low audio noise and reduced RF interference
as compared to Burst Mode operation. It provides higher
low current efficiency than forced continuous mode, but
not nearly as high as Burst Mode operation.
Output Overvoltage Protection
An overvoltage comparator, OV, guards against transient
overshoots (> 7.5%) as well as other more serious con-
ditions that may overvoltage the output. In such cases,
the top MOSFET is turned off and the bottom MOSFET is
turned on until the overvoltage condition is cleared.
38502f
11
LTC3850-2
APPLICATIONS INFORMATION
TheTypicalApplicationonthefirstpageisabasicLTC3850-
2 application circuit. LTC3850-2 can be configured to use
eitherDCR(inductorresistance)sensingorlowvalueresis-
tor sensing. The choice between the two current sensing
schemes is largely a design trade-off between cost, power
consumption, and accuracy. DCR sensing is becoming
popular because it saves expensive current sensing resis-
tors and is more power efficient, especially in high current
applications. However, current sensing resistors provide
the most accurate current limits for the controller. Other
externalcomponentselectionisdrivenbytheloadrequire-
Filter components mutual to the sense lines should be placed
close to the LTC3850-2, and the sense lines should run close
together to a Kelvin connection underneath the current sense
element (shown in Figure 1). Sensing current elsewhere can
effectively add parasitic inductance and capacitance to the
currentsenseelement,degradingtheinformationatthesense
terminals and making the programmed current limit unpre-
dictable. If DCR sensing is used (Figure 2b), sense resistor
R1 should be placed close to the switching node, to prevent
noise from coupling into sensitive small-signal nodes. The
capacitor C1 should be placed close to the IC pins.
ment, and begins with the selection of R
(if R
is
SENSE
SENSE
Low Value Resistors Current Sensing
used)andinductorvalue.Next,thepowerMOSFETsarese-
lected. Finally, input and output capacitors are selected.
A typical sensing circuit using a discrete resistor is shown
in Figure 2a. R
output current.
is chosen based on the required
SENSE
+
–
SENSE and SENSE Pins
+
–
The SENSE and SENSE pins are the inputs to the current
comparators. The common mode input voltage range of
the current comparators is 0V to 5V. Both SENSE pins
are high impedance inputs with small base currents of
less than 1μA. When the SENSE pins ramp up from 0V
to 1.4V, the small base currents flow out of the SENSE
pins. When the SENSE pins ramp down from 5V to 1.1V,
the small base currents flow into the SENSE pins. The
high impedance inputs to the current comparators allow
accurate DCR sensing. However, care must be taken not
to float these pins during normal operation.
The current comparator has a maximum threshold
V
.Theinputcommonmoderangeofthecurrent
SENSE(MAX)
comparator is 0V to 5V. The current comparator threshold
TO SENSE FILTER,
NEXT TO THE CONTROLLER
C
OUT
INDUCTOR OR R
SENSE
38502 F01
Figure 1. Sense Lines Placement
with Inductor or Sense Resistor
V
V
IN
V
V
IN
IN
IN
INTV
CC
INTV
CC
BOOST
TG
SENSE RESISTOR
PLUS PARASITIC
INDUCTANCE
INDUCTOR
BOOST
TG
V
OUT
L
DCR
SW
LTC3850-2
R
ESL
V
OUT
SW
S
LTC3850-2
BG
BG
C
• 2 ≤ ESL/R
RF
F
S
PGND
POLE-ZERO
PGND
R1
CANCELLATION
+
R
R
F
SENSE
+
SENSE
C1*
R2
C
F
–
–
SENSE
SENSE
SGND
SGND
F
38502 F02b
38502 F02a
L
DCR
R2
R1 + R2
+
FILTER COMPONENTS
PLACED NEAR SENSE PINS
||
R1 R2 × C1 =
R
= DCR
*PLACE C1 NEAR SENSE ,
SENSE(EQ)
–
SENSE PINS
(2a) Using a Resistor to Sense Current
(2b) Using the Inductor DCR to Sense Current
Figure 2. Two Different Methods of Sensing Current
38502f
12
LTC3850-2
APPLICATIONS INFORMATION
sets the peak of the inductor current, yielding a maximum
purely inductive component. It was measured using two
scope probes and waveform math to obtain a differential
measurement. Based on additional measurements of the
inductor ripple current and the on-time and off-time of
the top switch, the value of the parasitic inductance was
determined to be 0.5nH using the equation:
average output current I
equal to the peak value less
MAX
half the peak-to-peak ripple current, ΔI . To calculate the
L
sense resistor value, use the equation:
VSENSE(MAX)
RSENSE
=
ΔIL
I(MAX)
+
VESL(STEP)
t
ON • tOFF
2
ESL =
ΔIL
tON + tOFF
BecauseofpossiblePCBnoiseinthecurrentsensingloop,
the AC current sensing ripple of ΔV = ΔI • R
SENSE
L
SENSE
IftheRCtimeconstantischosentobeclosetotheparasitic
inductance divided by the sense resistor (L/R), the result-
ing waveform looks resistive again, as shown in Figure
4. For applications using low maximum sense voltages,
check the sense resistor manufacturer’s data sheet for
information about parasitic inductance. In the absence of
data, measure the voltage drop directly across the sense
resistor to extract the magnitude of the ESL step and use
the equation above to determine the ESL. However, do not
over-filter. Keep the RC time constant less than or equal
to the inductor time constant to maintain a high enough
also needs to be checked in the design to get a good
signal-to-noise ratio. In general, for a reasonably good
PCB layout, a 15mV ΔV
voltage is recommended as
SENSE
a conservative number to start with, either for R
DCR sensing applications.
or
SENSE
For previous generation current mode controllers, the
maximum sense voltage was high enough (e.g., 75mV for
theLTC1628/LTC3728family)thatthevoltagedropacross
the parasitic inductance of the sense resistor represented
a relatively small error. For today’s highest current density
solutions, however, the value of the sense resistor can
be less than 1mꢀ and the peak sense voltage can be as
low as 20mV. In addition, inductor ripple currents greater
than 50% with operation up to 1MHz are becoming more
common. Under these conditions the voltage drop across
the sense resistor’s parasitic inductance is no longer neg-
ligible. A typical sensing circuit using a discrete resistor is
showninFigure2a. Inpreviousgenerationsofcontrollers,
a small RC filter placed near the IC was commonly used to
reducetheeffectsofcapacitiveandinductivenoisecoupled
inthe sense traces on the PCB. A typical filter consists of
two series 10ꢀ resistors connected to a parallel 1000pF
capacitor, resulting in a time constant of 20ns.
ripple voltage on V
.
RSENSE
The above generally applies to high density / high current
applicationswhereI >10Aandlowvaluesofinductors
(MAX)
areused. ForapplicationswhereI
and C to 1000pF. This will provide a good starting point.
<10A, setR to10Ω
(MAX)
F
F
The filter components need to be placed close to the IC. The
positive and negative sense traces need to be routed as a
differential pair and Kelvin connected to the sense resistor.
Inductor DCR Sensing
Forapplicationsrequiringthehighestpossibleefficiencyat
highloadcurrents,theLTC3850-2iscapableofsensingthe
voltage drop across the inductor DCR, as shown in Figure
2b. The DCR of the inductor represents the small amount
of DC winding resistance of the copper, which can be less
than 1mꢀ for today’s low value, high current inductors.
In a high current application requiring such an inductor,
conductionlossthroughasenseresistorwouldcostseveral
points of efficiency compared to DCR sensing.
ThissameRCfilter,withminormodifications,canbeusedto
extracttheresistivecomponentofthecurrentsensesignal
inthepresenceofparasiticinductance.Forexample,Figure
3 illustrates the voltage waveform across a 2mꢀ sense
resistor with a 2010 footprint for the 1.2V/15A converter
showninFigure18operatingat100%load. Thewaveform
is the superposition of a purely resistive component and a
38502f
13
LTC3850-2
APPLICATIONS INFORMATION
To ensure that the application will deliver full load cur-
rent over the full operating temperature range, choose
the minimum value for the Maximum Current Sense
Threshold (V
table (40mV).
) in the Electrical Characteristics
SENSE(MAX)
V
ESL(STEP)
V
SENSE
Next, determine the DCR of the inductor. Where provided,
use the manufacturer’s maximum value, usually given
at 20°C. Increase this value to account for the tempera-
ture coefficient of resistance, which is approximately
20mV/DIV
38502 F03
500ns/DIV
Figure 3. Voltage Waveform Measured
Directly Across the Sense Resistor.
0.4%/°C. A conservative value for T
is 100°C.
L(MAX)
To scale the maximum inductor DCR to the desired sense
resistor value, use the divider ratio:
RSENSE(EQUIV)
RD =
DCR(MAX) at TL(MAX)
V
C1 is usually selected to be in the range of 0.047μF to
0.47μF. This forces R1||R2 to around 2kꢀ, reducing
error that might have been caused by the SENSE pins’
1μA current.
SENSE
20mV/DIV
38502 F04
500ns/DIV
Figure 4. Voltage Waveform Measured After the
Sense Resistor Filter. CF = 1000pF, RF = 100Ω.
The equivalent resistance R1||R2 is scaled to the room
temperature inductance and maximum DCR:
If the external R1||R2 • C1 time constant is chosen to be
exactly equal to the L/DCR time constant, the voltage drop
across the external capacitor is equal to the drop across
theinductorDCRmultipliedbyR2/(R1+R2).R2scalesthe
voltage across the sense terminals for applications where
the DCR is greater than the target sense resistor value.
To properly dimension the external filter components, the
DCR of the inductor must be known. It can be measured
using a good RLC meter, but the DCR tolerance is not
always the same and varies with temperature; consult the
manufacturers’ datasheets for detailed information.
L
R1||R2 =
(DCR at 20°C) • C1
The sense resistor values are:
R1||R2
RD
R1• RD
1−RD
R1=
; R2=
The maximum power loss in R1 is related to duty cycle,
and will occur in continuous mode at the maximum input
voltage:
V
IN(MAX) − VOUT • V
(
)
OUT
Using the inductor ripple current value from the Inductor
Value Calculation section, the target sense resistor value is:
PLOSS R1=
R1
VSENSE(MAX)
Ensure that R1 has a power rating higher than this value.
If high efficiency is necessary at light loads, consider this
power loss when deciding whether to use DCR sensing or
RSENSE(EQUIV)
=
ΔIL
I(MAX)
+
2
38502f
14
LTC3850-2
APPLICATIONS INFORMATION
sense resistors. Light load power loss can be modestly
higher with a DCR network than with a sense resistor, due
totheextraswitchinglossesincurredthroughR1.However,
DCR sensing eliminates a sense resistor, reduces conduc-
tion losses and provides higher efficiency at heavy loads.
Peak efficiency is about the same with either method.
A reasonable starting point is to choose a ripple current
that is about 40% of I
. Note that the largest ripple
OUT(MAX)
current occurs at the highest input voltage. To guarantee
that ripple current does not exceed a specified maximum,
the inductor should be chosen according to:
VIN – VOUT VOUT
fOSC •IRIPPLE VIN
L ≥
•
To maintain a good signal to noise ratio for the current
sense signal, use a minimum ΔV
of 10mV to 15mV.
SENSE
For a DCR sensing application, the actual ripple voltage
will be determined by the equation:
Inductor Core Selection
Once the inductance value is determined, the type of in-
ductor must be selected. Core loss is independent of core
size for a fixed inductor value, but it is very dependent
on inductance selected. As inductance increases, core
losses go down. Unfortunately, increased inductance
requires more turns of wire and therefore copper losses
will increase.
V − VOUT VOUT
IN
ΔVSENSE
=
R1•C1 V • fOSC
IN
Slope Compensation and Inductor Peak Current
Slope compensation provides stability in constant-
frequency architectures by preventing subharmonic
oscillations at high duty cycles. It is accomplished inter-
nally by adding a compensating ramp to the inductor
current signal at duty cycles in excess of 40%. Normally,
this results in a reduction of maximum inductor peak cur-
rent for duty cycles >40%. However, the LTC3850-2 uses
a patented scheme that counteracts this compensating
ramp, which allows the maximum inductor peak current
to remain unaffected throughout all duty cycles.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Power MOSFET and Schottky Diode
(Optional) Selection
Inductor Value Calculation
Given the desired input and output voltages, the inductor
value and operating frequency f
inductor’s peak-to-peak ripple current:
Two external power MOSFETs must be selected for each
controller in the LTC3850-2: one N-channel MOSFET for
the top (main) switch, and one N-channel MOSFET for the
bottom (synchronous) switch.
directly determine the
OSC
⎛
⎞
VOUT V – VOUT
IN
IRIPPLE
=
⎜
⎟
V
fOSC •L
⎝
⎠
IN
Thepeak-to-peakdrivelevelsaresetbytheINTV voltage.
CC
Thisvoltageistypically5Vduringstart-up(seeEXTV Pin
CC
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors, and output voltage
ripple. Thus, highest efficiency operation is obtained at
low frequency with a small ripple current. Achieving this,
however, requires a large inductor.
Connection).Consequently,logic-levelthresholdMOSFETs
must be used in most applications. The only exception is if
low input voltage is expected (V < 5V); then, sub-logic level
IN
thresholdMOSFETs(V
<3V)shouldbeused.Payclose
GS(TH)
attention to the BV specification for the MOSFETs as well;
DSS
most of the logic level MOSFETs are limited to 30V or less.
38502f
15
LTC3850-2
APPLICATIONS INFORMATION
Selection criteria for the power MOSFETs include the
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
on-resistance R
, Miller capacitance C
, input
DS(ON)
MILLER
voltage and maximum output current. Miller capacitance,
C
, can be approximated from the gate charge curve
MILLER
usually provided on the MOSFET manufacturers’ data
sheet. C is equal to the increase in gate charge
The term (1 + δ) is generally given for a MOSFET in the
MILLER
form of a normalized R
vs Temperature curve, but
DS(ON)
along the horizontal axis while the curve is approximately
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
flat divided by the specified change in V . This result is
DS
then multiplied by the ratio of the application applied V
DS
to the gate charge curve specified V . When the IC is
TheoptionalSchottkydiodesconductduringthedeadtime
betweentheconductionofthetwopowerMOSFETs.These
preventthebodydiodesofthebottomMOSFETsfromturn-
ing on, storing charge during the dead time and requiring
a reverse recovery period that could cost as much as 3%
DS
operating in continuous mode the duty cycles for the top
and bottom MOSFETs are given by:
VOUT
Main Switch Duty Cycle =
VIN
in efficiency at high V . A 1A to 3A Schottky is generally
IN
VIN – VOUT
Synchronous SwitchDuty Cycle=
VIN
a good compromise for both regions of operation due to
the relatively small average current. Larger diodes result
in additional transition losses due to their larger junction
capacitance.
The MOSFET power dissipations at maximum output
current are given by:
Soft-Start and Tracking
VOUT
VIN
2
PMAIN
=
I
1+δ R
+
)
(
)
)
(
MAX
DS(ON)
The LTC3850-2 has the ability to either soft-start by itself
with a capacitor or track the output of another channel or
externalsupply.Whenoneparticularchannelisconfigured
to soft-start by itself, a capacitor should be connected to
its TK/SS pin. This channel is in the shutdown state if its
RUN pin voltage is below 1.2V. Its TK/SS pin is actively
pulled to ground in this shutdown state.
I
⎛
⎝
⎞
2
MAX
V
R
DR )(
C
•
(
)
(
IN ⎜
⎟
MILLER
⎠
2
⎡
⎤
⎥
⎦
1
1
+
• f
⎢
OSC
⎢ VINTVCC – VTH(MIN) VTH(MIN) ⎥
⎣
Once the RUN pin voltage is above 1.2V, the channel pow-
ers up. A soft-start current of 1.3μA then starts to charge
its soft-start capacitor. Note that soft-start or tracking is
achieved not by limiting the maximum output current of
the controller but by controlling the output ramp voltage
according to the ramp rate on the TK/SS pin. Current
foldback is disabled during this phase to ensure smooth
soft-start or tracking. The soft-start or tracking range is
defined to be the voltage range from 0V to 0.8V on the
TK/SS pin. The total soft-start time can be calculated as:
VIN – VOUT
VIN
2
PSYNC
=
I
(
1+δ R
DS(ON)
(
)
)
MAX
where δ is the temperature dependency of R
and
DS(ON)
R
(approximately 2ꢀ) is the effective driver resistance
DR
at the MOSFET’s Miller threshold voltage. V
typical MOSFET minimum threshold voltage.
is the
TH(MIN)
2
BothMOSFETshaveI RlosseswhilethetopsideN-channel
equation includes an additional term for transition losses,
which are highest at high input voltages. For V < 20V
the high current efficiency generally improves with larger
IN
CSS
tSOFTSTART = 0.8•
1.3µA
MOSFETs, while for V > 20V the transition losses rapidly
IN
Regardless of the mode selected by the MODE/PLLIN pin,
the regulator will always start in pulse-skipping mode up
increasetothepointthattheuseofahigherR
device
DS(ON)
withlowerC
actuallyprovideshigherefficiency. The
MILLER
38502f
16
LTC3850-2
APPLICATIONS INFORMATION
to TK/SS = 0.64V. Between TK/SS = 0.64V and 0.74V, it
will operate in forced continuous mode and revert to the
selected mode once TK/SS > 0.74V. The output ripple is
minimized during the 100mV forced continuous mode
window ensuring a clean PGOOD signal.
So which mode should be programmed? While either
mode in Figure 5 satisfies most practical applications,
some tradeoffs exist. The ratiometric mode saves a pair
of resistors, but the coincident mode offers better output
regulation. This can be better understood with the help
of Figure 7. At the input stage of the slave channel’s error
amplifier, two common anode diodes are used to clamp
the equivalent reference voltage and an additional diode
is used to match the shifted common mode voltage. The
top two current sources are of the same amplitude. In the
coincidentmode, theTK/SSvoltageissubstantiallyhigher
than 0.8V at steady state and effectively turns off D1. D2
and D3 will therefore conduct the same current and offer
When the channel is configured to track another supply,
the feedback voltage of the other supply is duplicated by
a resistor divider and applied to the TK/SS pin. Therefore,
the voltage ramp rate on this pin is determined by the
ramp rate of the other supply’s voltage. Note that the
small soft-start capacitor charging current is always
flowing, producing a small offset error. To minimize this
error, select the tracking resistive divider value to be small
enough to make this error negligible.
tight matching between V
and the internal precision
FB2
0.8V reference. In the ratiometric mode, however, TK/SS
equals 0.8V at steady state. D1 will divert part of the bias
In order to track down another channel or supply after
the soft-start phase expires, the LTC3850-2 is forced into
current to make V slightly lower than 0.8V.
FB2
continuous mode of operation as soon as V is below the
FB
Although this error is minimized by the exponential I-V
characteristic of the diode, it does impose a finite amount
ofoutputvoltagedeviation.Furthermore,whenthemaster
channel’s output experiences dynamic excursion (under
load transient, for example), the slave channel output will
be affected as well. For better output regulation, use the
coincident tracking mode instead of ratiometric.
undervoltage threshold of 0.74V regardless of the setting
on the MODE/PLLIN pin. However, the LTC3850-2 should
always be set in force continuous mode tracking down
when there is no load. After TK/SS drops below 0.1V, its
channel will operate in discontinuous mode.
Output Voltage Tracking
The LTC3850-2 allows the user to program how its out-
put ramps up and down by means of the TK/SS pins.
Through these pins, the output can be set up to ei-
ther coincidentally or ratiometrically track another
supply’s output, as shown in Figure 5. In the following
INTV Regulators and EXTV
CC
CC
The LTC3850-2 features an NPN linear regulator that sup-
plies power to INTV from the V supply. INTV powers
CC
IN
CC
the gate drivers and much of the LTC3850-2’s internal
circuitry. The linear regulator regulates the voltage at the
discussions, V
referstotheLTC3850-2’soutput1asa
OUT1
INTV pin to 5V when V is greater than 6.5V. EXTV
CC
CC
IN
masterchannelandV
referstotheLTC3850-2’soutput
OUT2
connects to INTV through a P-channel MOSFET and can
CC
2 as a slave channel. In practice, though, either phase can
be used as the master. To implement the coincident track-
ing in Figure 5a, connect an additional resistive divider to
supply the needed power when its voltage is higher than
4.7V. Each of these can supply a peak current of 100mA
and must be bypassed to ground with a minimum of 1μF
ceramiccapacitororlowESRelectrolyticcapacitor.Nomat-
ter what type of bulk capacitor is used, an additional 0.1μF
V
and connect its midpoint to the TK/SS pin of the
OUT1
slave channel. The ratio of this divider should be the same
as that of the slave channel’s feedback divider shown in
ceramic capacitor placed directly adjacent to the INTV
CC
Figure 6a. In this tracking mode, V
thanV
of the V
must be set higher
OUT1
and PGND pins is highly recommended. Good bypassing
is needed to supply the high transient currents required
by the MOSFET gate drivers and to prevent interaction
between the channels.
.Toimplementtheratiometrictracking,theratio
OUT2
OUT2
divider should be exactly the same as the
master channel’s feedback divider. By selecting different
resistors, the LTC3850-2 can achieve different modes of
tracking including the two in Figure 5.
38502f
17
LTC3850-2
APPLICATIONS INFORMATION
V
V
V
OUT1
OUT1
OUT2
V
OUT2
TIME
38502 F03a
38502 F03b
TIME
(5a) Coincident Tracking
(5b) Ratiometric Tracking
Figure 5. Two Different Modes of Output Voltage Tracking
V
OUT1
V
OUT1
V
V
OUT2
OUT2
R3
R4
R1
R2
R3
R4
R1
R2
R3
TO
TK/SS2
PIN
TO
TK/SS2
PIN
TO
FB1
PIN
TO
FB2
PIN
TO
TO
V
V
V
FB2
V
FB1
PIN
PIN
R4
38502 F06
(6a) Coincident Tracking Setup
(6b) Ratiometric Tracking Setup
Figure 6. Setup for Coincident and Ratiometric Tracking
I
I
+
–
D1
D2
EA2
TK/SS2
0.8V
D3
V
FB2
38502 F07
Figure 7. Equivalent Input Circuit of Error Amplifier
38502f
18
LTC3850-2
APPLICATIONS INFORMATION
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maxi-
mum junction temperature rating for the LTC3850-2 to
However, for 3.3V and other low voltage outputs, addi-
tional circuitry is required to derive INTV power from
CC
the output.
be exceeded. The INTV current, which is dominated
CC
The following list summarizes the four possible connec-
by the gate charge current, may be supplied by either
tions for EXTV :
CC
the 5V linear regulator or EXTV . When the voltage on
CC
1. EXTV left open (or grounded). This will cause
the EXTV pin is less than 4.7V, the linear regulator is
CC
CC
INTV to be powered from the internal 5V regulator
enabled. Power dissipation for the IC in this case is high-
CC
resulting in an efficiency penalty of up to 10% at high
input voltages.
est and is equal to V • I
. The gate charge current
IN INTVCC
is dependent on operating frequency as discussed in the
Efficiency Considerations section. The junction tempera-
ture can be estimated by using the equations given in
Note 3 of the Electrical Characteristics. For example, the
2. EXTV connected directly to V . This is the
CC
OUT
normal connection for a 5V regulator and provides
the highest efficiency.
LTC3850-2 INTV current is limited to less than 24mA
CC
3. EXTV connected to an external supply. If a 5V
CC
from a 24V supply in the GN package and not using the
external supply is available, it may be used to power
EXTV supply:
CC
EXTV providing it is compatible with the MOSFET
CC
T = 70°C + (24mA)(24V)(95°C/W) = 125°C
J
gate drive requirements.
To prevent the maximum junction temperature from being
exceeded, the input supply current must be checked while
operating in continuous conduction mode (MODE/PLLIN
4. EXTV connected to an output-derived boost net-
CC
work. For 3.3V and other low voltage regulators,
efficiency gains can still be realized by connecting
= SGND) at maximum V . When the voltage applied to
IN
EXTV to an output-derived voltage that has been
CC
EXTV rises above 4.7V, the INTV linear regulator is
CC
CC
boosted to greater than 4.7V.
turned off and the EXTV is connected to the INTV .
CC
CC
For applications where the main input power is 5V, tie
The EXTV remains on as long as the voltage applied
CC
the V and INTV pins together and tie the combined
IN
CC
to EXTV remains above 4.5V. Using the EXTV allows
CC
CC
pins to the 5V input with a 1ꢀ or 2.2ꢀ resistor as shown
the MOSFET driver and control power to be derived from
in Figure 8 to minimize the voltage drop caused by the
oneoftheLTC3850-2’sswitchingregulatoroutputsduring
gate charge current. This will override the INTV linear
CC
normal operation and from the INTV when the output
CC
regulator and will prevent INTV from dropping too low
CC
is out of regulation(e.g., start-up, short-circuit). If more
due to the dropout voltage. Make sure the INTV voltage
CC
current is required through the EXTV than is specified,
CC
is at or exceeds the R
test voltage for the MOSFET
DS(ON)
an external Schottky diode can be added between the
which is typically 4.5V for logic level devices.
EXTV and INTV pins. Do not apply more than 6V to
CC
CC
the EXTV pin and make sure that EXTV < V .
CC
CC
IN
Significant efficiency and thermal gains can be realized by
powering INTV from the output, since the V current
resultingfromthedriverandcontrolcurrentswillbescaled
by a factor of (Duty Cycle)/(Switcher Efficiency).
V
IN
CC
IN
LTC3850-2
R
VIN
INTV
5V
CC
1ꢀ
C
+
INTVCC
4.7μF
C
IN
Tying the EXTV pin to a 5V supply reduces the junction
CC
temperature in the previous example from 125°C to:
38502 F08
T = 70°C + (24mA)(5V)(95°C/W) = 81°C
J
Figure 8. Setup for a 5V Input
38502f
19
LTC3850-2
APPLICATIONS INFORMATION
Topside MOSFET Driver Supply (C , DB)
C and C
Selection
B
IN
OUT
External bootstrap capacitors C connected to the BOOST
The selection of C is simplified by the 2-phase architec-
B
IN
pinssupplythegatedrivevoltagesforthetopsideMOSFETs.
ture and its impact on the worst-case RMS current drawn
throughtheinputnetwork(battery/fuse/capacitor).Itcanbe
shown that the worst-case capacitor RMS current occurs
when only one controller is operating. The controller with
Capacitor C in the Functional Diagram is charged though
B
external diode DB from INTV when the SW pin is low.
CC
When one of the topside MOSFETs is to be turned on,
the driver places the C voltage across the gate source
the highest (V )(I ) product needs to be used in the
B
OUT OUT
of the desired MOSFET. This enhances the MOSFET and
formula below to determine the maximum RMS capacitor
current requirement. Increasing the output current drawn
from the other controller will actually decrease the input
RMS ripple current from its maximum value. The out-of-
phasetechniquetypicallyreducestheinputcapacitor’sRMS
ripple current by a factor of 30% to 70% when compared
to a single phase power supply solution.
turns on the topside switch. The switch node voltage, SW,
rises to V and the BOOST pin follows. With the topside
IN
MOSFET on, the boost voltage is above the input supply:
V
= V + V
. The value of the boost capacitor
BOOST
IN
INTVCC
C needs to be 100 times that of the total input capa-
B
citance of the topside MOSFET(s). The reverse break-
down of the external Schottky diode must be greater
Incontinuousmode,thesourcecurrentofthetopMOSFET
than V
. When adjusting the gate drive level, the
IN(MAX)
is a square wave of duty cycle (V )/(V ). To prevent
OUT
IN
final arbiter is the total input current for the regulator. If
a change is made and the input current decreases, then
the efficiency has improved. If there is no change in input
current, then there is no change in efficiency.
large voltage transients, a low ESR capacitor sized for the
maximum RMS current of one channel must be used. The
maximum RMS capacitor current is given by:
1/2
IMAX
VIN
⎡
⎤
CIN Required IRMS
≈
V
OUT )(
V – V
IN OUT
(
)
⎣
⎦
Undervoltage Lockout
The LTC3850-2 has two functions that help protect the
controller in case of undervoltage conditions. A precision
This formula has a maximum at V = 2V , where I
RMS
IN
OUT
= I /2. This simple worst-case condition is commonly
OUT
UVLOcomparatorconstantlymonitorstheINTV voltage
CC
usedfordesignbecauseevensignificantdeviationsdonot
offermuchrelief.Notethatcapacitormanufacturers’ripple
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may be paralleled to meet
size or height requirements in the design. Due to the high
operatingfrequencyoftheLTC3850-2, ceramiccapacitors
to ensure that an adequate gate-drive voltage is present.
It locks out the switching action when INTV is below
CC
3V. To prevent oscillation when there is a disturbance on
the INTV , the UVLO comparator has 500mV of preci-
CC
sion hysteresis.
Another way to detect an undervoltage condition is to
monitor the V supply. Because the RUN pins have a
IN
precision turn-on reference of 1.2V, one can use a resistor
can also be used for C . Always consult the manufacturer
IN
divider to V to turn on the IC when V is high enough.
IN
IN
if there is any question.
An extra 4.5μA of current flows out of the RUN pin once
the RUN pin voltage passes 1.2V. One can program the
hysteresis of the run comparator by adjusting the values
The benefit of the LTC3850-2 2-phase operation can be
calculated by using the equation above for the higher
power controller and then calculating the loss that would
have resulted if both controller channels switched on at
the same time. The total RMS power lost is lower when
of the resistive divider. For accurate V undervoltage
IN
detection, V needs to be higher than 4V.
IN
38502f
20
LTC3850-2
APPLICATIONS INFORMATION
V
bothcontrollersareoperatingduetothereducedoverlapof
current pulses required through the input capacitor’s ESR.
This is why the input capacitor’s requirement calculated
abovefortheworst-casecontrollerisadequateforthedual
controllerdesign.Also,theinputprotectionfuseresistance,
battery resistance, and PC board trace resistance losses
are also reduced due to the reduced peak currents in a 2-
phase system. The overall benefit of a multiphase design
willonlybefullyrealizedwhenthesourceimpedanceofthe
power supply/battery is included in the efficiency testing.
The sources of the top MOSFETs should be placed within
OUT
R
C
FF
B
A
1/2 LTC3850-2
V
FB
R
38502 F09
Figure 9. Setting Output Voltage
To improve the frequency response, a feed-forward ca-
pacitor, C , may be used. Great care should be taken to
FF
route the V line away from noise sources, such as the
FB
1cm of each other and share a common C (s). Separating
IN
inductor or the SW line.
the sources and C may produce undesirable voltage and
IN
current resonances at V .
IN
Fault Conditions: Current Limit and Current Foldback
A small (0.1μF to 1μF) bypass capacitor between the chip
IN
The LTC3850-2 includes current foldback to help limit
load current when the output is shorted to ground. If the
output falls below 50% of its nominal output level, then
themaximumsensevoltageisprogressivelyloweredfrom
its maximum programmed value to one-third of the maxi-
mum value. Foldback current limiting is disabled during
the soft-start or tracking up. Under short-circuit condi-
tions with very low duty cycles, the LTC3850-2 will begin
cycle skipping in order to limit the short-circuit current.
In this situation the bottom MOSFET will be dissipating
most of the power but less than in normal operation. The
short-circuit ripple current is determined by the minimum
V pin and ground, placed close to the LTC3850-2, is also
suggested. A 2.2ꢀ – 10ꢀ resistor placed between C
IN
(C1) and the V pin provides further isolation between
IN
the two channels.
The selection of C
is driven by the effective series
OUT
resistance (ESR). Typically, once the ESR requirement
is satisfied, the capacitance is adequate for filtering. The
output ripple (ΔV ) is approximated by:
OUT
⎛
⎜
⎝
⎞
1
ΔVOUT ≈IRIPPLE ESR+
⎟
8fCOUT
⎠
on-time t
of the LTC3850-2 (≈ 90ns), the input
ON(MIN)
voltage and inductor value:
where f is the operating frequency, C
is the output
OUT
capacitance and I
is the ripple current in the induc-
RIPPLE
VIN
L
ΔIL(SC) = tON(MIN)
•
tor. The output ripple is highest at maximum input voltage
since I increases with input voltage.
RIPPLE
The resulting short-circuit current is:
Setting Output Voltage
1/3 V
1
2
ISC =
SENSE(MAX) – ΔIL(SC)
The LTC3850-2 output voltages are each set by an exter-
nal feedback resistive divider carefully placed across the
output, as shown in Figure 9. The regulated output voltage
is determined by:
RSENSE
Phase-Locked Loop and Frequency Synchronization
TheLTC3850-2hasaphase-lockedloop(PLL)comprisedof
⎛
⎞
RB
RA
an internal voltage-controlled oscillator (V ) and a phase
VOUT = 0.8V • 1+
CO
⎜
⎝
⎟
⎠
detector. This allows the turn-on of the top MOSFET of
controller 1 to be locked to the rising edge of an external
clock signal applied to the MODE/PLLIN pin. The turn-on
38502f
21
LTC3850-2
APPLICATIONS INFORMATION
of controller 2’s top MOSFET is thus 180 degrees out-
of-phase with the external clock. The phase detector is
an edge sensitive digital type that provides zero degrees
phase shift between the external and internal oscillators.
This type of phase detector does not exhibit false lock to
harmonics of the external clock.
If no clock is applied to MODE/PLLIN pin, the FREQ/
PLLFLTR pin will be high impedance.
If the external clock frequency is greater than the internal
oscillator’s frequency, f , then current is sourced con-
OSC
tinuously from the phase detector output, pulling up the
FREQ/PLLFLTR pin. When the external clock frequency is
less than f , current is sunk continuously, pulling down
The output of the phase detector is a pair of complemen-
tary current sources that charge or discharge the external
filter network connected to the FREQ/PLLFLTR pin. The
relationship between the voltage on the FREQ/PLLFLTR
pin and operating frequency is shown in Figure 10 and
specifiedintheElectricalCharacteristicstable.Notethatthe
LTC3850-2 can only be synchronized to an external clock
whosefrequencyiswithinrangeoftheLTC3850-2’sinternal
OSC
theFREQ/PLLFLTRpin.Iftheexternalandinternalfrequen-
ciesarethesamebutexhibitaphasedifference,thecurrent
sourcesturnonforanamountoftimecorrespondingtothe
phase difference. The voltage on the FREQ/PLLFLTR pin is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
the filter capacitor C holds the voltage.
LP
V . This is guaranteed to be between 250kHz and 780kHz.
CO
A simplified block diagram is shown in Figure 11.
The loop filter components, C and R , smooth out the
LP
LP
currentpulsesfromthephasedetectorandprovideastable
900
800
700
600
500
400
300
200
100
0
input to the voltage-controlled oscillator. The filter compo-
nents C and R determine how fast the loop acquires
LP
LP
lock. Typically R = 10k and C is 2200pF to 0.01μF.
LP
LP
Typically,theexternalclock(onMODE/PLLINpin)inputhigh
threshold is 1.6V, while the input low thres-hold is 1V.
Minimum On-Time Considerations
Minimumon-timet
isthesmallesttimedurationthat
ON(MIN)
the LTC3850-2 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that
0
0.5
1
1.5
2
2.5
FREQ/PLLFLTR PIN VOLTAGE (V)
38502 F10
Figure 10. Relationship Between Oscillator
Frequency and Voltage at the FREQ/PLLFLTR Pin
VOUT
VIN(f)
2.4V
tON(MIN)
<
R
LP
C
LP
FREQ/
PLLFLTR
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
MODE/
PLLIN
DIGITAL
PHASE/
FREQUENCY
DETECTOR
EXTERNAL
OSCILLATOR
VCO
The minimum on-time for the LTC3850-2 is approximately
90ns, with reasonably good PCB layout, minimum 30%
inductor current ripple and at least 10mV – 15mV ripple
38502 F11
Figure 11. Phase-Locked Loop Block Diagram
38502f
22
LTC3850-2
APPLICATIONS INFORMATION
on the current sense signal. The minimum on-time can be
affected by PCB switching noise in the voltage and current
loop. As the peak sense voltage decreases the minimum
on-time gradually increases to 130ns. This is of particular
concern in forced continuous applications with low ripple
current at light loads. If the duty cycle drops below the
minimum on-time limit in this situation, a significant
amount of cycle skipping can occur with correspondingly
larger current and voltage ripple.
Supplying INTV power through EXTV from an out-
CC CC
put-derived source will scale the V current required
IN
for the driver and control circuits by a factor of (Duty
Cycle)/(Efficiency).Forexample,ina20Vto5Vapplica-
tion, 10mA of INTV current results in approximately
CC
2.5mAofV current.Thisreducesthemid-currentloss
IN
from 10% or more (if the driver was powered directly
from V ) to only a few percent.
IN
2
3. I R losses are predicted from the DC resistances of the
fuse(ifused), MOSFET, inductor, currentsenseresistor.
In continuous mode, the average output current flows
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
through L and R
, but is “chopped” between the
SENSE
topside MOSFET and the synchronous MOSFET. If the
two MOSFETs have approximately the same R
,
DS(ON)
then the resistance of one MOSFET can simply be
summed with the resistances of L and R
to obtain
SENSE
= 10mꢀ, R
2
I R losses. For example, if each R
DS(ON)
L
= 10mꢀ, R
= 5mꢀ, then the total resistance is
SENSE
%Efficiency = 100% – (L1 + L2 + L3 + ...)
25mꢀ. This results in losses ranging from 2% to 8%
as the output current increases from 3A to 15A for
a 5V output, or a 3% to 12% loss for a 3.3V output.
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Efficiency varies as the inverse square of V
for the
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
OUT
sameexternalcomponentsandoutputpowerlevel.The
combined effects of increasingly lower output voltages
andhighercurrentsrequiredbyhighperformancedigital
systemsisnotdoublingbutquadruplingtheimportance
of loss terms in the switching regulator system!
losses in LTC3850-2 circuits: 1) IC V current, 2) INTV
IN
CC
2
regulator current, 3) I R losses, 4) Topside MOSFET
transition losses.
1. The V current is the DC supply current given in
IN
4. Transition losses apply only to the topside MOSFET(s),
and become significant only when operating at high
input voltages (typically 15V or greater). Transition
losses can be estimated from:
the Electrical Characteristics table, which excludes
MOSFET driver and control currents. V current typi-
IN
cally results in a small (<0.1%) loss.
2. INTV current is the sum of the MOSFET driver and
CC
2
Transition Loss = (1.7) V
I
C
f
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge dQ moves
IN O(MAX) RSS
Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is
very important to include these “system” level losses
during the design phase. The internal battery and fuse
resistance losses can be minimized by making sure that
from INTV to ground. The resulting dQ/dt is a cur-
CC
rent out of INTV that is typically much larger than the
CC
control circuit current. In continuous mode, I
GATECHG
= f(Q + Q ), where Q and Q are the gate charges of
C has adequate charge storage and very low ESR at the
T
B
T
B
IN
the topside and bottom side MOSFETs.
switching frequency. A 25W supply will typically require
38502f
23
LTC3850-2
APPLICATIONS INFORMATION
a minimum of 20μF to 40μF of capacitance having a
maximum of 20mꢀ to 50mꢀ of ESR. The LTC3850-2
2-phasearchitecturetypicallyhalvesthisinputcapacitance
requirement over competing solutions. Other losses
including Schottky conduction losses during dead time
and inductor core losses generally account for less than
2% total additional loss.
determined. The output capacitors need to be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 80%
of full-load current having a rise time of 1μs to 10μs will
produce output voltage and I pin waveforms that will
TH
give a sense of the overall loop stability without break-
ing the feedback loop. Placing a power MOSFET directly
across the output capacitor and driving the gate with an
appropriate signal generator is a practical way to produce
a realistic load step condition. The initial output voltage
step resulting from the step change in output current may
not be within the bandwidth of the feedback loop, so this
signal cannot be used to determine phase margin. This
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V
shifts by an
OUT
is why it is better to look at the I pin signal which is in
TH
amount equal to ΔI
(ESR), where ESR is the effective
LOAD
the feedback loop and is the filtered and compensated
control loop response. The gain of the loop will be in-
series resistance of C . ΔI
also begins to charge or
OUT
LOAD
discharge C
generating the feedback error signal that
OUT
creased by increasing R and the bandwidth of the loop
forces the regulator to adapt to the current change and
C
will be increased by decreasing C . If R is increased by
return V
time V
to its steady-state value. During this recovery
can be monitored for excessive overshoot or
C
C
OUT
the same factor that C is decreased, the zero frequency
C
OUT
will be kept the same, thereby keeping the phase shift the
same in the most critical frequency range of the feedback
loop. The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance.
ringing, which would indicate a stability problem. The
availability of the I pin not only allows optimization of
TH
control loop behavior but also provides a DC coupled and
AC filtered closed loop response test point. The DC step,
rise time and settling at this test point truly reflects the
closed loop response. Assuming a predominantly second
ordersystem, phasemarginand/ordampingfactorcanbe
estimated using the percentage of overshoot seen at this
pin.Thebandwidthcanalsobeestimatedbyexaminingthe
A second, more severe transient is caused by switching
in loads with large (>1μF) supply bypass capacitors. The
dischargedbypasscapacitorsareeffectivelyputinparallel
with C , causing a rapid drop in V . No regulator can
OUT
OUT
rise time at the pin. The I external components shown
TH
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
in the Typical Application circuit will provide an adequate
starting point for most applications.
The I series R -C filter sets the dominant pole-zero
C
to C
is greater than 1:50, the switch rise time
TH
C
C
LOAD
OUT
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and
the particular output capacitor type and value have been
should be controlled so that the load rise time is limited
to approximately 25 • C . Thus a 10μF capacitor would
LOAD
require a 250μs rise time, limiting the charging current
to about 200mA.
38502f
24
LTC3850-2
APPLICATIONS INFORMATION
PC Board Layout Checklist
5. Is the INTV decoupling capacitor connected close to
CC
theIC, betweentheINTV andthepowergroundpins?
CC
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layoutdiagramofFigure12.Figure13illustratesthecurrent
waveformspresentinthevariousbranchesofthe2-phase
synchronousregulatorsoperatinginthecontinuousmode.
Check the following in your layout:
ThiscapacitorcarriestheMOSFETdriverscurrentpeaks.
Anadditional1μFceramiccapacitorplacedimmediately
next to the INTV and PGND pins can help improve
CC
noise performance substantially.
6. Keep the switching nodes (SW1, SW2), top gate nodes
(TG1, TG2), andboostnodes(BOOST1, BOOST2)away
from sensitive small-signal nodes, especially from the
oppositechannel’svoltageandcurrentsensingfeedback
pins. All of these nodes have very large and fast moving
signals and therefore should be kept on the “output
side” of the LTC3850-2 and occupy minimum PC trace
area. If DCR sensing is used, place the top resistor
(Figure 2b, R1) close to the switching node.
1. ArethetopN-channelMOSFETsM1andM3locatedwithin
1 cm of each other with a common drain connection at
C ? Do not attempt to split the input decoupling for the
IN
two channels as it can cause a large resonant loop.
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return
of C
must return to the combined C
(–)
INTVCC
OUT
7. Use a modified “star ground” technique: a low imped-
ance, large copper area central grounding point on
the same side of the PC board as the input and output
terminals. The V and I traces should be as short
FB
TH
as possible. The path formed by the top N-channel
MOSFET, Schottky diode and the C capacitor should
IN
capacitors with tie-ins for the bottom of the INTV
CC
have short leads and PC trace lengths. The output
capacitor (–) terminals should be connected as close
as possible to the (–) terminals of the input capacitor
by placing the capacitors next to each other and away
from the Schottky loop described above.
decouplingcapacitor,thebottomofthevoltagefeedback
resistive divider and the SGND pin of the IC.
PC Board Layout Debugging
Start with one controller at a time. It is helpful to use a
DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output
switching node (SW pin) to synchronize the oscilloscope
totheinternaloscillatorandprobetheactualoutputvoltage
as well. Check for proper performance over the operating
voltage and current range expected in the application. The
frequencyofoperationshouldbemaintainedovertheinput
voltage range down to dropout and until the output load
dropsbelowthelowcurrentoperationthreshold—typically
10% of the maximum designed current level in Burst
Mode operation.
3. DotheLTC3850-2V pins’resistivedividersconnectto
FB
the (+) terminals of C ? The resistive divider must be
OUT
connected between the (+) terminal of C
and signal
OUT
ground. The feedback resistor connections should not
be along the high current input feeds from the input
capacitor(s).
+
–
4. AretheSENSE andSENSE leadsroutedtogetherwith
minimumPCtracespacing?Thefiltercapacitorbetween
+
–
SENSE and SENSE should be as close as possible
to the IC. Ensure accurate current sensing with Kelvin
connectionsatthesenseresistororinductor,whichever
is used for current sensing.
38502f
25
LTC3850-2
APPLICATIONS INFORMATION
R
TK/SS1
PU2
V
PULL-UP
PGOOD
I
PGOOD
TH1
V
FB1
L1
R
SENSE
+
–
V
OUT1
SENSE1
SENSE1
PLLLPF
TG1
SW1
C
B1
M1
M2
D1
BOOST1
LTC3850-2
MODE/PLLIN
BG1
1μF
CERAMIC
f
IN
C
C
OUT1
V
IN
R
C
IN
VIN
RUN1
RUN2
PGND
V
GND
IN
EXTV
CC
CC
C
IN
SGND
C
INTVCC
–
+
INTV
SENSE2
OUT2
D2
1μF
CERAMIC
BG2
SENSE2
M4
M3
BOOST2
V
FB2
TH2
C
B2
SW2
TG2
I
R
SENSE
V
OUT2
TK/SS2
L2
38502 F12
Figure 12. Recommended Printed Circuit Layout Diagram
SW1
L1
R
SENSE1
V
OUT1
D1
C
R
L1
OUT1
V
IN
R
IN
C
IN
SW2
L2
R
SENSE2
V
OUT2
D2
C
R
L2
OUT2
BOLD LINES INDICATE
HIGH SWITCHING
CURRENT. KEEP LINES
TO A MINIMUM LENGTH.
38502 F13
Figure 13. Branch Current Waveforms
38502f
26
LTC3850-2
APPLICATIONS INFORMATION
V
IN
7V TO
20V
22μF
50V
1μF
2.2ꢀ
4.7μF
D3
D4
V
PGOOD EXTV INTV
CC CC
IN
M2
M1
TG1
TG2
0.1μF
0.1μF
L1
L2
BOOST1
SW1
BOOST2
SW2
3.3μH
2.2μH
LTC3850-2
BG2
4.12k
1%
BG1
10k, 1%
6.19k
1%
MODE/PLLIN
PGND
FREQ/PLLFLTR
+
+
SENSE1
SENSE2
1.5k
1%
1.33k
1%
0.1μF
0.1μF
–
–
SENSE1
SENSE2
33pF
33pF
RUN1
RUN2
V
OUT1
3.3V
5A
V
OUT2
V
TH1
V
TH2
1.8V
FB1
FB2
I
I
5A
63.4k
1%
25.5k
1%
2200pF
5.49k
1%
1800pF
TK/SS1
TK/SS2
0.1μF
SGND
100pF
100pF
0.1μF
C
C
OUT1
100μF
X2
20k
1%
4.75k
1%
3.16k
1%
20k
1%
OUT2
100μF
X2
38502 F14
L1, L2: COILTRONICS HCP0703
M1, M2: VISHAY SILICONIX Si4816BDY
C
, C
: TAIYO YUDEN JMK325BJ107MM
OUT1 OUT2
Figure 14. High Efficiency Dual 500kHz 3.3V/1.8V Step-Down Converter
Thedutycyclepercentageshouldbemaintainedfromcycle
tocycleinawell-designed,lownoisePCBimplementation.
Variationinthedutycycleatasubharmonicratecansuggest
noise pickup at the current or voltage sensing inputs or
inadequate loop compensation. Overcompensation of the
loop can be used to tame a poor PC layout if regulator
bandwidth optimization is not required. Only after each
controllerischeckedforitsindividualperformanceshould
bothcontrollersbeturnedonatthesametime.Aparticularly
difficultregionofoperationiswhenonecontrollerchannel
is nearing its current comparator trip point when the other
channel is turning on its top MOSFET. This occurs around
50% duty cycle on either channel due to the phasing of the
internal clocks and may cause minor duty cycle jitter.
Investigate whether any problems exist only at higher out-
put currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG,
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
sensing pins needs to be placed immediately adjacent to
the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
capacitive coupling. If problems are encountered with
high current output loading at lower input voltages, look
for inductive coupling between C , Schottky and the top
IN
MOSFET components to the sensitive current and voltage
sensing traces. In addition, investigate common ground
path voltage pickup between these components and the
SGND pin of the IC.
Reduce V from its nominal level to verify operation
IN
of the regulator in dropout. Check the operation of the
undervoltage lockout circuit by further lowering V while
IN
monitoring the outputs to verify operation.
38502f
27
LTC3850-2
APPLICATIONS INFORMATION
Design Example
Theminimumon-timeoccursonChannel1atthemaximum
V , and should not be less than 90ns:
IN
Asadesignexampleforatwochannelmediumcurrentregu-
lator, assume V = 12V(nominal), V = 20V(maximum),
VOUT
1.8V
IN
IN
tON(MIN)
=
=
=180ns
V
= 3.3V, V
= 1.8V, I = 5A, and f = 500kHz
OUT1
OUT2
MAX1,2
VIN(MAX)
ƒ
20V(500kHz)
(see Figure 14).
The equivalent R
using the minimum value for the maximum current sense
threshold (40mV).
resistor value can be calculated by
SENSE
The regulated output voltages are determined by:
⎛
⎞
RB
RA
VOUT = 0.8V • 1+
⎜
⎝
⎟
⎠
VSENSE(MIN)
RSENSE(EQUIV)
=
=
ΔIL(NOM)
Using 20k 1% resistors from both V nodes to ground,
FB
ILOAD(MAX)
+
2
the top feedback resistors are (to the nearest 1% standard
value) 63.4k and 25.5k.
40mV
≅ 7mΩ
1.5A
The frequency is set by biasing the FREQ/PLLFLTR pin to
5A +
2
1.2V (see Figure 10), using a divider from INTV . This
CC
voltage will decrease as V approaches 5V, lowering the
The equivalent R
is the same for Channel 2.
IN
SENSE
switchingfrequency.Ifaseparate5Vsupplyisconnectedto
The Coiltronics (Cooper) HCP0703-2R2 (20mΩ DCR
at 20°C) and HCP0703-3R3 (30mꢀ DCR
MAX
EXTV , INTV will remain at 5V even if V decreases.
CC
CC
IN
at 20°C) are
MAX
The inductance values are based on a 35% maximum
ripple current assumption (1.75A for each channel). The
highest value of ripple current occurs at the maximum
input voltage:
chosen.At100°C,theestimatedmaximumDCRvaluesare
26.4mꢀ and 39.6mꢀ. The divider ratios are:
RSENSE(EQUIV)
7mΩ
RD =
=
= 0.26;
DCRMAX at TL(MAX) 26.4mΩ
⎛
⎞
⎟
VOUT
VOUT
7mΩ
≅ 0.18
L =
1−
⎜
and
ƒ • ΔIL(MAX)
VIN(MAX)
⎝
⎠
39.6mΩ
Channel 1 will require 3.2μH, and Channel 2 will require
1.9μH.Thenexthigheststandardvaluesare3.3μHand2.2μH.
At the nominal input voltage (12V), the ripple will be:
For each channel, 0.1μF is selected for C1.
2.2µH
L
R1||R2 =
=
(DCRMAX at 20°C)•C1 20mΩ•0.1µF
⎛
⎞
⎟
VOUT
VOUT
3.3µH
30mΩ•0.1µF
ΔIL(NOM)
=
1−
⎜
=1.1k ; and
= 1.1k
ƒ • L
V
IN(NOM)
⎝
⎠
Channel 1 will have 1.45A (29%) ripple, and Channel 2 will
have 1.4A (28%) ripple. The peak inductor current will be
the maximum DC value plus one-half the ripple current,
or 5.725A for Channel 1 and 5.7A for Channel 2.
For channel 1, the DCR
filter/divider values are:
SENSE
1.1k
0.18
R1||R2
RD
R1=
R2=
=
≅ 6.19k;
R1• RD 6.19k • 0.18
=
≅1.33k
1−RD
1− 0.18
38502f
28
LTC3850-2
APPLICATIONS INFORMATION
The power loss in R1 at the maximum input voltage is:
(VIN(MAX) − VOUT)• VOUT
ThepowerdissipationonthetopsideMOSFETcanbeeasily
estimated. Choosing a Siliconix Si4816BDY dual MOSFET
results in: R
= 0.023ꢀ/0.016ꢀ, C
≅ 100pF.
DS(ON)
MILLER
PLOSSR1=
=
R1
At maximum input voltage with T(estimated) = 50°C:
(20V −3.3V)•3.3V
= 9mW
3.3V
2
PMAIN
=
5
1+(0.005)(50°C–25°C) •
( )
6.19k
[
]
20V
0.023Ω + 20V
The respective values for Channel 2 are R1 = 4.12k, R2 =
1.5k; and P R1 = 8mW.
5A
2
⎛
⎞
2
2Ω 100pF •
)(
(
) (
)
(
)
⎜
⎝
⎟
⎠
LOSS
BurstModeoperationischosenforhighlightloadefficiency
(Figure 15) by floating the MODE/PLLIN pin. Power loss
due to the DCR sensing network is slightly higher at light
loads than would have been the case with a suitable sense
resistor (7mꢀ). At heavier loads, DCR sensing provides
higher efficiency.
1
1
⎡
⎤
+
500kHz =186mW
(
)
⎢
⎣
⎥
⎦
5–2.3 2.3
A short-circuit to ground will result in a folded back cur-
rent of:
⎛
⎞
1/ 3 50mV
0.007Ω
90ns(20V)
3.3µH
(
)
1
2
ISC =
–
= 2.1A
⎜
⎟
⎝
⎠
100
90
80
70
60
50
40
10
DCR
with a typical value of R
and δ = (0.005/°C)(20)
DS(ON)
= 0.1. The resulting power dissipated in the bottom
7mꢀ
1
MOSFET is:
DCR
20V – 3.3V
20V
= 66mW
2
PSYNC
=
2.1A 1.125 0.016Ω
(
) (
)(
)
0.1
0.01
EFFICIENCY
POWER LOSS
which is less than under full-load conditions.
C is chosen for an RMS current rating of at least 2A at
temperature assuming only channel 1 or 2 is on. C
0.01
0.1
1
10
IN
LOAD CURRENT (mA)
is
38502 F15
OUT
chosen with an ESR of 0.02ꢀ for low output ripple. The
output ripple in continuous mode will be highest at the
maximum input voltage. The output voltage ripple due to
ESR is approximately:
Figure 15. Design Example Efficiency vs Load
V
= R (ΔI ) = 0.02ꢀ(1.5A) = 30mV
ESR L P–P
ORIPPLE
38502f
29
LTC3850-2
TYPICAL APPLICATIONS
V
IN
7V TO
24V
22μF
50V
2.2ꢀ
1μF
4.7μF
D3
D4
V
PGOOD INTV
IN
CC
M1
M2
TG1
TG2
0.1μF
0.1μF
L2
2.2μH
L2
3.3μH
BOOST1
SW1
BOOST2
SW2
LTC3850-2
BG2
BG1
10k
1%
MODE/PLLIN
PGND
FREQ/PLLFLTR
10ꢀ
1000pF
10ꢀ
10ꢀ
+
+
SENSE1
SENSE2
1000pF
6mꢀ
15pF
6mꢀ
10pF
–
–
SENSE1
SENSE2
10ꢀ
RUN1
RUN2
V
EXTV
V
OUT1
3.3V
5A
CC
V
OUT2
V
5V
FB1
FB2
TH2
105k
1%
5A
63.4k
1%
I
I
TH1
1000pF
100pF
1000pF
TK/SS1
TK/SS2
SGND
+
+
20k
1%
C
10k
1%
20k
1%
C
OUT2
150μF
15k
1%
3.16k
1%
OUT1
220μF
100pF
0.1μF
0.1μF
38502 F16
L1: TDK RLF 7030T-2R2M5R4
L2: TDK ULF10045T-3R3N6R9
C
C
: SANYO 4TPE220MF
OUT1
: SANYO 6TPE150MI
OUT2
Figure 16. 3.3V/5A, 5V/5A Converter Using Sense Resistors
38502f
30
LTC3850-2
TYPICAL APPLICATIONS
38502f
31
LTC3850-2
TYPICAL APPLICATIONS
38502f
32
LTC3850-2
TYPICAL APPLICATIONS
5V 0.5V
4.7μF
6.3V
2x
1ꢀ
4.7μF
D3
D4
V
PGOOD EXTV INTV
CC
IN
CC
M2
M1
TG1
TG2
0.1μF
0.1μF
L1
L2
BOOST1
SW1
BOOST2
SW2
0.75μH
0.75μH
LTC3850-2
BG2
1.2k
1%
BG1
1.2k
1%
PLLIN
750kHz
MODE/PLLIN
PGND
FREQ/PLLFLTR
+
+
SENSE1
SENSE2
4.99k
1%
2.94k
1%
0.047μF
0.047μF
–
–
SENSE1
SENSE2
47pF
100pF
RUN1
RUN2
V
OUT1
1.8V
5A
V
1.2V
5A
OUT2
V
TH1
V
TH2
FB1
FB2
I
I
25.5k
1%
10k
1%
2200pF
14k
1%
100pF
1nF
2200pF
TK/SS1
TK/SS2
0.1μF
10nF
SGND
100pF
0.1μF
C
C
OUT1
100μF
X2
OUT2
100μF
X2
20k
1%
20k
1%
10k
1%
14k
1%
38502 F19
L1, L2: TOKO FDV0630 0.75μH
M1, M2: VISHAY SILICONIX Si4816BDY
, C : TAIYO YUDEN JMK325BJ107MM
C
OUT1 OUT2
Figure 19. 1.8V/5A, 1.2V/5A Core-I/O Converter with a 5V Input Synchronized at 750kHz
38502f
33
LTC3850-2
TYPICAL APPLICATIONS
2.2ꢀ
V
V
IN2
3.3V
IN1
12V
1μF
13.0k
10k
4.7μF
2x
4.7μF
M1
4.7μF
D3
D4
V
PGOOD EXTV INTV
CC CC
IN
M2
TG1
TG2
0.1μF
0.1μF
L1
L2
0.75μH
BOOST1
SW1
BOOST2
SW2
2.2μH
LTC3850-2
BG2
1.2k
1%
BG1
10k
1%
3.74k
1%
MODE/PLLIN
PGND
FREQ/PLLFLTR
+
+
SENSE1
SENSE2
4.32k
1%
1.40k
1%
0.1μF
0.1μF
–
–
SENSE1
SENSE2
47pF
100pF
RUN1
RUN2
V
OUT1
2.5V
5A
V
1.2V
5A
OUT2
V
TH1
V
TH2
FB1
FB2
I
I
43.2k
1%
10k
1%
2200pF
10k
1%
100pF
2200pF
6.04k
1%
TK/SS1
TK/SS2
0.1μF
SGND
100pF
0.1μF
C
C
OUT1
100μF
X2
OUT2
100μF
X2
20k
1%
20k
1%
3.16k
1%
38502 F20
L1: TOKO FDV0630 2.2μH
L2: TOKO FDV0630 0.75μH
M1, M2: VISHAY SILICONIX Si4816BDY
, C : TAIYO YUDEN JMK325BJ107MM
C
OUT1 OUT2
Figure 20. 2.5V/5A, 1.2V/5A Core-I/O Converter with Dual Inputs
38502f
34
LTC3850-2
PACKAGE DESCRIPTION
GN Package
28-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.386 – .393*
(9.804 – 9.982)
.045 p.005
.033
(0.838)
REF
28 27 26 25 24 23 22 21 20 19 18 17 1615
.254 MIN
.150 – .165
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.0165 p.0015
.0250 BSC
1
2
3
4
5
6
7
8
9 10 11 12 13 14
RECOMMENDED SOLDER PAD LAYOUT
.015 p .004
(0.38 p 0.10)
.0532 – .0688
(1.35 – 1.75)
s 45o
.004 – .0098
(0.102 – 0.249)
.0075 – .0098
(0.19 – 0.25)
0o – 8o TYP
.016 – .050
(0.406 – 1.270)
.008 – .012
.0250
(0.635)
BSC
GN28 (SSOP) 0204
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
38502f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
35
LTC3850-2
TYPICAL APPLICATION
V
IN
7V TO 14V
20k
2.55k
10k
+
2.21k
10μF
2x
RUN
180μF
L1
RJK0305DPB
RJK0301DPB
1nF
0.1μF
–
0.56μH
7.5k
0.1μF
0.1μF
+
SENSE1 SENSE1 RUN1 FREQ MODE SW1 TG1
CMDSH-3
220pF
TK/SS1
BOOST1
BG1
2.2nF
I
TH1
2.74k
20k
2.2Ω
1μF
V
V
V
IN
FB1
FB2
TH2
LTC3850-2
INTV
CC
V
OUT
1.1V/30A
4.7μF
I
BG2
+
PGND
C
OUT1
100μF
2x
TK/SS2
SENSE2
330μF
2.5V
4x
CMDSH-3
0.1μF
–
BOOST2
L2
0.56μH
RJK0305DPB
RJK0301DPB
+
SENSE2 SGND RUN2 EXTV
PGOOD SW2 TG2
CC
0.1μF
2.21k
PGOOD
20k
100k
38502 TA02
RUN
L1, L2: VISHAY IHLP4040DZ-01 0.56μH
C
: SANYO 2R5TPE330M9
OUT
FOR SINGLE OUTPUT, DUAL PHASE OPERATION, TIE THE FOLLOWING PINS TOGETHER:
V
TO V
TK/SS1 TO TK/SS2
RUN1 TO RUN2
FB1
FB1
ITH1 TO ITH2
Figure 21. 1.1V/30A Dual Phase Core Converter, FSW = 400kHz
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PolyPhase is a registered trademark of Linear Technology Corporation. No R
is a trademark of Linear Technology Corporation.
SENSE
38502f
LT 0908 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
36
●
●
© LINEAR TECHNOLOGY CORPORATION 2007
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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