LTC3850EGN_技术文档

LTC3735

2-Phase, High Efficiency

DC/DC Controller for

Intel Mobile CPUs

FEATURES

DESCRIPTION

The LTC^®3735 is a 2-phase synchronous step-down

switching regulator controller that drives all N-channel

power MOSFETs in a constant frequency architecture. The

output voltage is programmable by six VID bits during

normal operation and by external resistors during initial

boot-upanddeepersleepstate.TheLTC3735drivesitstwo

output stages out-of-phase at frequencies up to 550kHz

to minimize the RMS ripple currents in both input and

output capacitors. This antiphase technique also doubles

the apparent switching frequency, improving the transient

response while operating each phase at an optimum fre-

quency for efficiency. Thermal design is further simplified

bycycle-by-cyclecurrentsharingbetweenthetwophases.

n

Output Stages Operate Antiphase

n

1ꢀ Output ꢁoltage Accuracy

n

6-Bit IMꢁP-Iꢁ ꢁID Code: ꢁ

= 0.7ꢁ to 1.708ꢁ

OUT

n

Intel Compatible Power Saving Mode (PSIB)

Stage Shedding Improves Low Current Efficiency

Power Good Output with Adaptive Masking

Lossless ꢁoltage Positioning

Dual Input Supply Capability for Load Sharing

Resistor Programmable V

Sleep State

at Boot-Up and Deeper

OUT

n

Resistor Programmable Deep Sleep Offset

Programmable Fixed Frequency: 210kHz to 550kHz

Adjustable Soft-Start Current Ramping

Foldback Output Current Limit

Short-Circuit Shutdown Timer with Defeat Option

Overvoltage Protection

AnIntelcompatiblePSIBinputisprovidedtoselectbetween

two modes of operation. Fully enhanced synchronous

mode achieves a very small output ripple and very fast

transient response while power saving mode realizes

very high efficiency. OPTI-LOOP^®compensation allows

the transient response to be optimized for a wide range

of output capacitance and ESR values.

Available in 36-Lead SSOP (0.209 Wide) and 38-Lead

(5mm × 7mm) Packages

APPLICATIONS

n

Mobile and Desktop Computers

Internet Servers

L, LT, LTC, LTM, OPTI-LOOP, PolyPhase, Linear Technology and the Linear logo are registered

trademarks of Linear Technology Corporation. All other trademarks are the property of their

respective owners.

n

TYPICAL APPLICATION

M1

M2

MCH_PG

DPRSLPVR

STP_CPUB

PSIB

TG1

SW1

1µH

D1

0.002Ω

V

IN

5V TO 24V

BG1

FREQSET

PGND

VID5-VID0

V

OUT

+

–

0.7V TO 1.708V

40A

PGOOD SENSE1

SENSE1

C

IN

OUT

+

I

TH

330µF

2V

10µF

35V

×4

R

C

100pF

RUN/SS

M3

M4

TG2

SW2

BG2

4.74k

1µH

D2

×5

232k

C

0.1µF

470pF

SGND

+

V

OA

LTC3735

+

–

SENSE2

4.5V TO 7V

PV

CC

13.3k

V

4.7µF

12.7k

RBOOT

BAT54A

56.2k

13.3k

BOOST1 RDPRSLP

1.27M

549k

BOOST2

RDPSLP

+

0.47µF

+

V

OA

OAOUT

–

SW2

SW1

V

OA

3735 F01

Figure 1. High Current 2-Phase Step-Down Converter

3735fa

1

LTC3735

ABSOLUTE MAXIMUM RATINGS ^{(Note 1)}

Input Supply Voltage (PV )....................... 7V to –0.3V

Peak Gate Drive Current <1µs

(TG1, TG2, BG1, BG2).................................................5A

Operating Ambient Temperature Range

(Note 2) ................................................... –40°C to 85°C

Junction Temperature (Note 3) ............................. 125°C

Storage Temperature Range

CC

Topside Driver Voltages (BOOST1,2) ......... 38V to –0.3V

Switch Voltage (SW1, 2)............................... 32V to –5V

Boosted Driver Voltages

(BOOST1-SW1, BOOST2-SW2) ............... 7V to –0.3V

DPRSLPVR, STP_CPUB, MCH_PG, PGOOD,

RDPRSLP, RDPSLP, RBOOT Voltages ......... 5V to –0.3V

RUN/SS, PSIB, FREQSET Voltages .............7V to –0.3V

VID0-VID5 Voltages ....................................5V to –0.3V

SSOP ................................................. –65°C to 150°C

QFN.................................................... –65°C to 125°C

QFN Reﬂow Peak Body Temperature.................... 260°C

Lead Temperature (Soldering, 10 sec) .................. 300°C

V , Voltage ................................................ 2V to –0.3V

FB

V

+

–

, V

............................................... 3.6V to –0.3V

OA

PIN CONFIGURATION

TOP VIEW

1

MCH_PG

PGOOD

BOOST1

TG1

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

V

FB

2

3

DPRSLPVR

FREQSET

38 37 36 35 34 33 32

4

PSIB

+

FREQSET

1

2

3

4

5

6

7

8

9

31 NC

5

SW1

V

PSIB

+

30 BOOST2

OA

–

V

TG2

6

BOOST2

TG2

29

28

OA

–

V

SW2

7

OAOUT

STP_CPUB

SGND

OA

OAOUT

STP_CPUB

SGND

27 PV

CC

8

SW2

BG1

26

9

PV

CC

39

25 PGND

24 BG2

23 VID5

22 VID4

21 VID3

+

10

11

12

13

14

15

16

17

18

BG1

SENSE1

+

SENSE1

–

PGND

BG2

SENSE1

–

SENSE1

+

SENSE2

+

SENSE2 10

–

VID5

VID4

VID3

VID2

VID1

VID0

SENSE2

–

SENSE2 11

RDPRSLP

RDPSLP

RUN/SS

20

RDPRSLP 12

VID2

13 14 15 16 17 18 19

UHF PACKAGE

I

TH

RBOOT

38-LEAD (7mm × 5mm) PLASTIC QFN

= 125°C, θ = 34°C/W

G PACKAGE

36-LEAD PLASTIC SSOP

= 125°C, θ = 85°C/W

T

JMAX

JA

EXPOSED PAD (PIN 39) IS SIGNAL GROUND, MUST BE CONNECTED TO PCB AND SGND

T

JMAX

JA

ORDER INFORMATION

LEAD FREE FINISH

TAPE AND REEL

PART MARKING*

PACKAGE DESCRIPTION

TEMPERATURE RANGE

LTC3735EG#PBF

LTC3735EG#TRPBF

LTC3735

36-Lead Plastic SSOP

–40°C to 85°C

LTC3735EUHF#PBF

LTC3735EUHF#TRPBF

–40°C to 85°C

38-Lead (7mm × 5mm) Plastic QFN

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

3735fa

2

LTC3735

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. ꢁ_PꢁCC= 5ꢁ, ꢁ_RUN/SS= 5ꢁ unless otherwise noted.

SYMBOL

Main Control Loop

Reference Regulated Feedback Voltage

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

I

Voltage = 0.5V; Measured at V (Note 4)

0.600

72

V

TH

FB

l

V

Maximum Current Sense Threshold

Output Voltage Load Regulation

Voltage = Max; V = 1.7V

59

85

mV

SENSEMAX

LOADREG

TH

CM

(Note 4)

Measured in Servo Loop, ∆I Voltage: 1.2V to 0.7V

Measured in Servo Loop, ∆I Voltage: 1.2V to 2V

l

0.1

–0.1

0.5

–0.5

%

TH

V

Reference Voltage Line Regulation

Forced Continuous Threshold

Forced Continuous Current

V

= 4.5V to 7V

0.02

0.6

–0.5

0.66

6

0.1

0.63

–1

%/V

V

REFLNREG

PSIB

PVCC

0.57

I

V

PSIB

= 0V

µA

PSIB

V

Output Overvoltage Threshold

Measured with Respect to V = 0.6V

0.64

4.5

0.68

7.5

V

OVL

m

FB

l

g

Transconductance Amplifier g

I

TH

I

TH

= 1.2V, Sink/Source 25µA (Note 4)

mmho

V/mV

m

Transconductance Amplifier Gain

Output Voltage in Active Mode

= 1.2V, (g • Z ; No Ext Load) (Note 4)

3

mOL

m

L

V

VID = 010110, I = 0.5V (0°C to 85°C)

VID = 010110, I = 0.5V (Note 2)

1.342

1.336

1.356

1.370

1.376

V

ACTIVE

TH

I

Input DC Supply Current

Normal Mode

Shutdown

(Note 5)

Q

2

20

3

100

mA

µA

V

= 0V

RUN/SS

UVR

Undervoltage RUN/SS Reset

Soft-Start Charge Current

PV Lowered Until the RUN/SS Pin is Pulled Low

3.2

–2.3

1.0

3.7

–1.5

1.5

4.2

–0.8

1.9

V

µA

V

CC

I

V

= 1.9V

RUN/SS

VRUN/SS

RUN/SS Pin ON Threshold

RUN/SS Pin Latchoff Arming

RUN/SS Pin Latchoff Threshold

RUN/SS Discharge Current

Shutdown Latch Disable Current

Total Sense Pins Source Current

Maximum Duty Factor

Rising

V

Rising from 3V

, Ramping Negative

3.9

V

RUN/SSARM

RUN/SSLO

SCL

3.2

V

I

Soft-Short Condition V = 0.375V, V

= 4.5V

RUN/SS

–5

–1.5

1.5

µA

%

FB

V

FB

= 0.375V, V = 4.5V

RUN/SS

5

SDLHO

–

+

Each Channel: V

= V

= 0V

–85

95

–60

98.5

SENSE

SENSE1 , 2

DF

In Dropout, V ≤ 45mV

SENSEMAX

MAX

Top Gate Transition Time:

Rise Time

Fall Time

(Note 6)

TG1, 2 t

C

= 3300pF

30

40

90

ns

r

f

LOAD

= 3300pF

Bottom Gate Transition Time:

Rise Time

Fall Time

(Note 6)

LOAD

BG1, 2 t

C

= 3300pF

60

50

90

ns

r

f

TG/BG t

Top Gate Off to Bottom Gate On Delay C

Synchronous Switch-On Delay Time

= 3300pF Each Driver (Note 6)

50

ns

1D

LOAD

BG/TG t

Bottom Gate Off to Top Gate On Delay C

Top Switch-On Delay Time

= 3300pF Each Driver (Note 6)

60

2D

LOAD

t

Minimum On-Time

Tested with a Square Wave (Note 7)

100

ON(MIN)

ꢁID Parameters

R

VID Top Resistance

5.33

kΩ

%

V

ATTEN

l

ATTEN

Resistive Divider Error

(Note 8)

–0.25

0.7

0.25

0.3

ERR

THLOW

THHIGH

LEAK

VID

VID0 to VID5 Logic Threshold Low

VID0 to VID5 Logic Threshold High

VID0 to VID5 Leakage

V

1

µA

3735fa

3

LTC3735

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. ꢁ_PꢁCC= 5ꢁ, ꢁ_RUN/SS= 5ꢁ unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Oscillator

I

f

FREQSET Input Current

Nominal Frequency

Lowest Frequency

Highest Frequency

V

= 0V

–2

–1

µA

kHz

FREQSET

NOM

FREQSET

= 1.2V

= 0V

320

190

490

355

210

550

390

240

610

LOW

≥ 2.4V

HIGH

PGOOD Output

V

PGOOD Voltage Low

I

= 2mA

0.1

0.3

1

V

PGL

PGOOD

I

PGOOD Leakage Current

PGOOD Trip Thresholds

V

= 5V

PGOOD

µA

PGOOD

V

with Respect to Set Output Voltage

Ramping Negative

Ramping Positive

PG

FB

V

–7

7

–10

11

–13

13

%

FB

t

PGOOD Mask Timer

MCH_PG Delay Time

100

110

15

120

µs

MASK

cycles

DELAY

Operational Amplifier

I

Input Bias Current

15

200

5

nA

mV

V

B

V

Input Offset Voltage Magnitude

Common Mode Input Voltage Range

Common Mode Rejection Ratio

Output Source Current

V

+ = V – 1.2V, I = 1mA

OUT

0.8

OS

OA

CM

0

P

– 1.4

VCC

CMRR

I

= 1mA

46

10

70

35

30

2

dB

OUT

I

mA

V/mV

MHz

V/µs

V

CL

A

Open-Loop DC Gain

I

= 1mA

VOL

OUT

GBP

SR

Gain-Bandwidth Product

Slew Rate

OUT

R = 2k

5

L

V

Maximum High Output Voltage

I

= 1mA

P

– 1.2 P

– 0.9

O(MAX)

OUT

VCC

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The LTC3735E is guaranteed to meet performance speciﬁcations

from 0°C to 70°C. Speciﬁcations over the –40°C to 85°C operating

Note 4: The LTC3735 is tested in a feedback loop that servos V to a

ITH

speciﬁed voltage and measures the resultant V

.

FB

Note 5: Dynamic supply current is higher due to the gate charge being

delivered at the switching frequency. See Applications Information.

Note 6: Rise and fall times are measured using 10% and 90% levels. Delay

times are measured using 50% levels.

temperature range are assured by design, characterization and correlation

with statistical process controls.

Note 7: The minimum on-time condition corresponds to the on inductor

peak-to-peak ripple current ≥40% I

(see Minimum On-Time

Considerations in the Applications Information section).

MAX

Note 3: T is calculated from the ambient temperature T and power

J

A

dissipation P according to the following formula:

D

Note 8: The ATTEN speciﬁcation is in addition to the output voltage

ERR

LTC3735EG: T = T + (P • 85°C/W)

J

A

D

accuracy speciﬁed at VID code = 010110.

LTC3735EUHF: T = T + (P • 34°C/W)

J

A

D

3735fa

4

LTC3735

TYPICAL PERFORMANCE CHARACTERISTICS

Active Mode Efficiency

(Figure 14)

Deeper Sleep Mode Efficiency

Efficiency vs Input ꢁoltage

(Figure 14)

100

90

80

70

60

90

80

70

60

100

90

80

70

60

50

I

= 20A

OUT

V

= 1.468V

PSI = 0

OUT

ID

V

= 1.6V

PSI = 0

V

= 7.5V

IN

V

= 7.5V

IN

V

= 20V

IN

V

= 20V

IN

0

5

10

15

20

25

30

0.01

0.1

1

10

5

10

15

INPUT VOLTAGE (V)

20

LOAD CURRENT (A)

3735 G01

3735 G02

3735 G03

Maximum Current Sense

Threshold vs Percent of Nominal

Output ꢁoltage (Foldback)

Supply Current vs Pꢁ_CCꢁoltage

and Mode

Maximum Current Sense

Threshold vs Duty Factor

2500

2000

1500

1000

500

75

50

25

0

80

70

60

50

40

30

20

10

0

ON

SHUTDOWN

0

20

40

60

80

100

50

4

5

6

7

0

25

75

100

DUTY FACTOR (%)

PV VOLTAGE (V)

CC

PERCENT OF NOMINAL OUTPUT VOLTAGE (%)

3735 G05

3735 G06

3735 G04

Maximum Current Sense

Threshold vs ꢁ_RUN/SS(Soft-Start)

Maximum Current Sense Threshold

vs Sense Common Mode ꢁoltage

Current Sense Threshold

vs I_THVoltage

76

72

90

80

V

= 1.25V

SENSE(CM)

70

60

70

60

50

40

68

64

60

30

20

30

20

10

0

–10

–20

–30

10

0

1

2

3

4

5

0

1

2

3

4

5

0

0.5

1.5

(V)

1

2

2.5

V

(V)

COMMON MODE VOLTAGE (V)

V

RUN/SS

ITH

3735 G08

3735 G07

3735 G09

3735fa

5

LTC3735

TYPICAL PERFORMANCE CHARACTERISTICS

Load Regulation (Without AꢁP)

SENSE Pins Total Source Current

100

0.0

–0.1

–0.2

–0.3

–0.4

V

= 5V

PSIB

IN

= 15V

FIGURE 1

50

0

–50

–100

2

4

0

6

0

5

10

15

20

25

V

COMMON MODE VOLTAGE (V)

LOAD CURRENT (A)

SENSE

3735 G12

3735 G10

Maximum Current Sense

Threshold vs Temperature

Current Sense Pin Input Current

vs Temperature

RUN/SS Current vs Temperature

78

76

74

72

70

68

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

–12

–11

–10

–9

V

= 1.6V

OUT

–8

–7

0

–50 –25

0

25

50

75 100 125

–50 –25

0

25

50

75 100 125

–50 –25

0

25

125

50

75 100

TEMPERATURE (°C)

3735 G13

3735 G18

3735 G14

Oscillator Frequency

vs Temperature

Constant Frequency Low Current

Mode (Figure 14)

Start-Up Sequence (Figure 14)

700

600

500

400

300

200

100

V

= 15V, V

= 1.6V, I

= 400mA

LOAD

IN

OUT

V

RON

C1 MAX

3.28V

V

OUT(AC)

2V/DIV

V

= 1.37V

BOOT

20mV/DIV

V

= 1.228V

ID

V

= 2.4V

FREQSET

V

CC – CORE

500mV/DIV

I

L1

C2 MAX

1.37V

1A/DIV

C3 MAX

3.24V

PGOOD

2V/DIV

= 1.2V

= 0V

I

L2

1A/DIV

C4 MAX

3.20V

MCH –PGOOD

2V/DIV

V

= 0V

PSIB

V

FREQSET

3735 G17

2µs/DIV

3735 G16

500µs/DIV

50

100 125

–50 –25

0

25

75

TEMPERATURE (°C)

3735 G19

3735fa

6

LTC3735

TYPICAL PERFORMANCE CHARACTERISTICS

ꢁ_RUN/SSShutdown Latch

Thresholds vs Temperature

Load Step (Figure 14)

ꢁID Transition (Figure 14)

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

1

0

VIDs

LATCH ARMING

32A

OUT

1.356V

I

V

OUT

200mV

/DIV

10A/DIV

LATCHOFF

THRESHOLD

7.2A

0.844V

1.364V

V

OUT

PGOOD

2V/DIV

100mV/DIV

1.230V

3735 G22

3735 G23

20s/DIV

50s/DIV

0

–50 –25

0

25

125

50

75 100

TEMPERATURE (°C)

3735 G21

PIN FUNCTIONS ^(G/UHF)

FB

pares the feedback voltage to the internal 0.6V reference

voltage.

ꢁ

(Pin 1/Pin 37): Input to the error amplifier that com-

STP_CPUB(Pin8/Pin6):DeepSleepStateInput.Whenthe

signal to this pin is low, the voltage regulator enters deep

sleep state and its output voltage is a certain percentage

lower than the VID commands. This offset percentage is

set by the resistor connected to the RDPSLP pin. When

the signal to this pin is high, the voltage regulator exits

deep sleep state.

DPRSLPꢁR (Pin 2/Pin 38): Deeper Sleep State Input.

When the signal to this pin is high, the voltage regulator

enters deeper sleep state and its output is determined

by the parallel resistor value of RDPRSLP and RDPSLP.

When the signal is low, the voltage regulator exits deeper

sleep state.

SGND (Pin 9/Pin 7): Signal Ground. This pin is common

to both controllers. Route separately to the PGND pin.

SENSE1⁺, SENSE2⁺(Pins10,12/Pins8, 9):The(+)Input

toEachDifferentialCurrentComparator.TheI_THpinvoltage

and built-in offsets between SENSE^–and SENSE⁺pins in

conjunction with R_SENSEset the current trip threshold.

FREQSET (Pin 3/Pin 1): Frequency Set Pin. Apply a DC

voltage between 0V and 5V to set the operating frequency

of the internal oscillator. This frequency is the switching

frequency of each phase.

–

SENSE1 , SENSE2 (Pins 11,13/Pins 10, 11): The (–)

PSIB (Pin 4/Pin 2): Power Status Indicator Input. When

the signal to this pin is high, both channels operate in fully

synchronous switching mode for fastest transient and

lowest ripple. When the signal is low, controller enters

powersavingmode, providinghighefficiencyatlightload.

Input to Each Differential Current Comparator.

RDPRSLP (Pin 14/Pin 12): Deeper Sleep State Resistor

+

Pin. Connect a resistor from this pin to V . This resis-

OA

tor in conjunction with RDPSLP resistor sets the output

voltage of the regulator in deeper sleep state.

+

–

ꢁ

, ꢁ

(Pins 5, 6/Pins 3, 4): Inputs to the Internal

OA

Operational Amplifier.

RDPSLP (Pin 15/Pin 14): Deep Sleep Resistor Pin. Con-

+

nect a resistor from this pin to V . This resistor sets the

OA

OAOUT (Pin 7/Pin 5): Output of the Internal Operational

Amplifier.

percentage offset of output voltage in deep sleep state.

3735fa

7

LTC3735

PIN FUNCTIONS ^(G/UHF)

RUN/SS (Pin 16/Pin 15): Combination of Soft-Start,

Run Control Input and Short-Circuit Detection Timer. A

capacitor to ground at this pin sets the ramp time to full

current output. Forcing this pin below 1V causes the IC to

shut down all internal circuitry. All functions are disabled

in shutdown.

SW2, SW1 (Pins 29, 32/Pins 28, 32): Switch Node Con-

nectionstoInductors.Voltageswingatthesepinsisfroma

Schottkydiode(external)voltagedropbelowgroundtoV .

IN

TG2, TG1 (Pins 30, 33/Pins 29, 33): High Current Gate

DrivesforTopN-ChannelMOSFETs. Thesearetheoutputs

of floating drivers with a voltage swing equal to PV

superimposed on the switch node voltage SW.

CC

I

TH

(Pin 17/Pin 16): Error Amplifier Output and Switching

RegulatorCompensationPoint.Bothcurrentcomparator’s

thresholds increase with this control voltage. The normal

voltage range of this pin is from 0V to 2.4V

BOOST2,BOOST1(Pins31,34/Pins30,34):Bootstrapped

Supplies to the Topside Floating Drivers. External capaci-

tors are connected between the BOOST and SW pins, and

Schottky diodes are connected between the BOOST and

RBOOT (Pin 18/Pin 17): Boot-Up Resistor Pin. Connect a

+

PV pins.

resistor from this pin to V . This resistor sets the output

CC

OA

voltage during the initial boot-up.

PGOOD (Pin 35/Pin 35): Power Good Indicator Output.

This pin is open drain when output is within 10% of its

set point. When output is not within the 10% window,

this pin is pulled to ground. An internal timer watches

over VID, state transitions overvoltage or undervoltage

conditions, thenmasksPGOODfromgoinglowfor110µs.

ꢁID0–ꢁID5 (Pins 19, 20, 21, 22, 23, 24/Pins 18, 19, 20,

21, 22, 23): VID Control Logic Input Pins.

BG2, BG1 (Pins 25, 27/Pins 24, 26): High Current Gate

Drives for Bottom N-Channel MOSFETs. Voltage swing at

these pins is from ground to PV .

CC

MCH_PG(Pin36/Pin36):MCHPowerGoodInput.Output

PGND (Pin 26/Pin 25): Driver Power Ground. Connect

voltage remains V

for 15 clock cycles after the asser-

BOOT

to sources of bottom N-channel MOSFETs and the (–)

tion of MCH_PG. This delay is only sensitive to the rising

edge of the MCH_PG logic signal.

terminals of C .

IN

Pꢁ (Pin 28/Pin 27): Power Supply Pin. The internal

CC

SGND (Exposed Pad Pin 39, UHF Only): Signal Ground.

Connect to Pins 7 and 25. The Exposed Pad must be

soldered to the PCB.

controlcircuitsandon-chipgatedriversarepoweredfrom

this voltage source. Decouple to PGND with a minimum of

4.7µFX5R/X7Rceramiccapacitorplaceddirectlyadjacent

to the IC.

NC (Pins 13, 31, UHF Only): No Connect.

3735fa

8

LTC3735

FUNCTIONAL DIAGRAM

R3

R4

R6

RDPRSLP

R5

RBOOT

MCH_PG

RDPSLP

STP_CPUB

DPRSLPVR

MD

DELAY

PV

V

CC

IN

FREQSET

CLK1

CLK2

TO SECOND

CHANNEL

COMPOSITE PG

D

OSCILLATOR

DPRSLPVR

B

DUPLICATE FOR SECOND

CONTROLLER CHANNEL

BOOST

TG

C

B

DROP

OUT

DET

+

TOP

BOT

STP_CPUB

PGOOD

VID CHANGE

C

IN

D1

BOT

PSI

SW

–

+

0.66V

110µs BLANKING

TOP ON

S

Q

SWITCH

LOGIC

PV

RUN

CC

V

FB

R

–

+

BG

0.54V

+

C

OUT

V

OA

PGND

DPRSLPVR

SHDN

V

OUT

A1

+

–

R

SENSE

L

R2

R1

–

V

OA

PV

CC

I

2

1

–

+

–

+

OAOUT

+

SENSE

36k

5.33(V

)

FB

–

3V

0.5µA

SLOPE

COMP

54k

PSIB

V

2.4V

FB

+

PSI

–

V

FB

–

+

EA

V

0.60V

REF

0.60V

0.66V

OV

+

–

PV

CC

5V

C

I

TH

+

1.5µA

SGND

SHDN

RST

RUN

SOFT-

START

C

R

C

C2

6V

5.33(V

)

FB

DPRSLPVR

MD

RUN/SS

VID CHANGE

C

SS

+

–

R

ATTEN

5.33k

RUN

1.5V

6-BIT VID DECODER

R

VID

VID0 VID1 VID2 VID3 VID4 VID5

3735 FD

3735fa

9

LTC3735

OPERATION ^{(Refer to Functional Diagram)}

Main Control Loop

This frequency is the actual switching frequency of either

channel. Because the two channels operate 180°C out of

TheLTC3735usesaconstantfrequency,currentmodestep-

down architecture with the two output stages operating

180 degrees out of phase. During normal operation, each

top MOSFET is turned on when the clock for that channel

sets the RS latch, and turned off when the main current

phase, the apparent frequency at both V and V

is

IN

OUT

twice the actual switching frequency, minimizing ripple

voltages and speeding up transient responses.

Low Current Operation (PSIB)

comparator, I , resets the RS latch. The peak inductor

1

The PSIB pin selects between two modes of operation.

When PSIB is above 0.6V, both channels operate in full

synchronous switching mode. Both bottom drivers (BG1,

BG2) are kept on once they are turned on until their re-

spective oscillator sets the RS latch. The inductor current

can therefore go from output back to input power supply

and could potentially boost the input supply to dangerous

voltage levels—BEWARE! This mode of operation is also

of lower efficiency, given both channels are fully enabled

and much current can circulate between input and output.

However, this mode provides faster transient response,

lower input noise and minimum output ripple.

current at which I resets the RS latch is controlled by

1

the voltage on the I pin, which is the output of error

TH

OA

+

amplifier EA. The V

pin receives the voltage feedback

signal, whichiscomparedtotheinternalreferencevoltage

by the EA. When the load current increases, it causes a

slight decrease in EA inverting input node relative to the

0.6V reference, which in turn causes the I voltage to

TH

increase until the average inductor current matches the

new load current. After the top MOSFET has turned off,

the bottom MOSFET is turned on until either the inductor

currentstartstoreverse, asindicatedbycurrentcompara-

tor I , or the beginning of the next cycle.

2

When PSIB is below 0.6V, the bottom drivers (BG1, BG2)

areturnedoffiftheinductorcurrentstartstoreverse. This

mode of operation prevents current going from output

back to input and eliminates the conduction power loss

related to circulating current. If the DPRSLPVR signal

goes high in this mode, Channel 2 will be shut off and

only Channel 1 will be active in supplying load current.

This further eliminates power MOSFET gate driving and

transitionlossesofChannel2.SinceDPRSLPVRindicates

the entry to deeper sleep state, this “channel shedding”

technique optimizes the voltage regulator efficiency at

light loads. Table 1 summarizes the operation modes for

different pin configurations.

ThetopMOSFETdriversarebiasedfromfloatingbootstrap

capacitor C , which normally is recharged during each off

B

cycle through an external diode when the top MOSFET

turns off. As V decreases to a voltage close to V

,

IN

OUT

the loop may enter dropout and attempt to turn on the

top MOSFET continuously. The dropout detector detects

this and forces the top MOSFET off for about 500ns every

sixth cycle to allow C to recharge.

B

The main control loop is shut down by pulling the RUN/

SS pin low. Releasing RUN/SS allows an internal 1.5µA

current source to charge soft-start capacitor C_SS. When

C_SSreaches 1.5V, the main control loop is enabled with

the internal I_THvoltage clamped at approximately 30%

of its maximum value. As C_SScontinues to charge, the

internal I_THvoltage is gradually released allowing normal,

full-current operation.

Table 1. Low Current Operation Modes

PSIB

DPRSLPꢁR OPERATION MODE

High

High or Low Both Channels ON, Fully Synchronous

Switching, Inductor Current is Allowed to

Reverse

Frequency Programming and Antiphase Operation

Low

Both Channels ON; Reverse Current is

Prevented

The switching frequency of the LTC3735 is determined by

the DC voltage at the FREQSET pin. A DC voltage ranging

from 0V to 2.4V moves the internal oscillator frequency

from 210kHz to 550kHz.

High

Channel 2 is Shut Off, Reverse Current is

Prevented

3735fa

10

LTC3735

OPERATION ^{(Refer to Functional Diagram)}

Output ꢁoltage at Start-Up and at Deeper Sleep State

Power Good

Undernormalconditions, theoutputvoltageoftheregula-

tor is commanded by six VID bits, except at start-up and

at deeper sleep state. At start-up, the RUN/SS capacitor

starts to charge up andits voltagelimits theinrushcurrent

from the input power source. This linearly rising current

limit provides a controlled output voltage rise. During

start-up, the VID command is ignored and the output set

point is determined by the value of the resistor connected

to the RBOOT pin. The VID bits continue to be ignored for

15 switching cycles after the completion of the following

two conditions: 1) output voltage has risen up and has

regulated2)MCH_PGsignalhasasserted.After15switch-

ing cycles, output voltage is fully commanded by VID bits.

The PGOOD pin is connected to the drain of an internal

N-channel MOSFET. The MOSFET turns on when the out-

put voltage is not within 10% of its nominal set point.

When the output voltage is within 10% of its nominal set

point, the MOSFET turns off and PGOOD is high imped-

ance. PGOOD monitors the V

voltage when MCH_PG

BOOT

is not asserted. During VID, deep sleep or deeper sleep

transitions, PGOOD is masked from going low for 110µs,

preventing the system from resetting during CPU mode

changes.WhenVIDbits,STP_CPUBorDPRSLPVRsignals

change again after a previous transition, but before the

timer expires, the internal timer resets.

Short-Circuit Detection

In deeper sleep state, the VID command and STP_CPUB

signal are ignored and the output set point is determined

by the parallel value of the resistors at the RDPRSLP pin

and RDPSLP pin.

The RUN/SS capacitor is used initially to limit the in-

rush current from the input power source. Once the

controllers have been given time, as determined by the

capacitor on the RUN/SS pin, to charge up the output

capacitors and provide full-load current, the RUN/SS

capacitor is then used as a short-circuit timeout circuit.

If the output voltage falls to less than 70% of its nominal

output voltage the RUN/SS capacitor begins discharg-

ing assuming that the output is in a severe overcurrent

and/or short-circuit condition. If the condition lasts for

a long enough period as determined by the size of the

RUN/SScapacitor,thecontrollerwillbeshutdownuntilthe

RUN/SS pin voltage is recycled. This built-in latchoff can

be overidden by providing a current >5µA to the RUN/SS

pin. This current shortens the soft-start period but also

prevents net discharge of the RUN/SS capacitor during a

severeovercurrentand/orshort-circuitcondition.Foldback

current limiting is activated when the output voltage falls

below 70% of its nominal level whether or not the short-

circuit latchoff circuit is enabled.

Operational Amplifier and Deep Sleep Offset

Theinternaloperationalamplifierprovidesaprogrammable

output offset at deep sleep state (when the STP_CPUB

signal is low). The offset percentage is programmed by

+

the resistor from RDPSLP to V

and the resistor from

OA

+

output to V . The amplifier has an output slew rate of

OA

5V/µs and is capable of driving capacitive loads with an

output RMS current typically up to 40mA. The open-loop

gain of the amplifier is >120dB and the unity-gain band-

width is 2MHz.

Output Overvoltage Protection

An overvoltage comparator, OV, guards against transient

overshoots (>10%) as well as other more serious condi-

tions that may overvoltage the output. In this case, the top

MOSFET is turned off and the bottom MOSFET is turned

on until the overvoltage condition is cleared.

3735fa

11

LTC3735

APPLICATIONS INFORMATION

The basic LTC3735 application circuit is shown in

Figure 1 on the first page of this data sheet. External com-

ponentselectionbeginswiththeselectionoftheinductors

based on ripple current requirements and continues with

the current sensing resistors using the calculated peak

inductor current and/or maximum current limit. Next, the

power MOSFETs, D1 and D2 are selected. The operating

frequency and the inductor are chosen based mainly on

the amount of ripple current. Finally, C_INis selected for its

ability to handle the input ripple current (that PolyPhase^®

operationminimizes)andC_OUTischosenwithlowenough

ESR to meet the output ripple voltage and load step

specifications (also minimized with PolyPhase). Current

mode architecture provides inherent current sharing be-

tween output stages. The circuit shown in Figure 1 can

be configured for operation up to an input voltage of 28V

(limited by the external MOSFETs). Current mode control

allows the ability to connect the two output stages to two

different input power supply rails. A heavy output load

can take some power from each input supply according

to the selection of the R_SENSEresistors.

biased with a resistor divider to prevent noise getting

into the system.

A graph for the voltage applied to the FREQSET pin vs fre-

quency is given in Figure 2. As the operating frequency is

increasedthegatedriveandswitchinglosseswillbehigher,

reducing efficiency (see Efficiency Considerations). The

maximum switching frequency is approximately 550kHz.

600

550

500

450

400

350

300

250

200

150

100

0

0.5

1.0

1.5

2.0

2.5

3.0

FREQSET PIN VOLTAGE (V)

3735 F02

Figure 2. Operating Frequency vs ꢁ_FREQSET

R

SENSE

Selection For Output Current

Inductor ꢁalue Calculation and Output Ripple Current

R

are chosen based on the required peak output

SENSE1,2

The operating frequency and inductor selection are inter-

related in that higher operating frequencies allow the use

of smaller inductor and capacitor values. So why would

anyone ever choose to operate at lower frequencies with

larger components? The answer is efficiency. A higher

frequency generally results in lower efficiency because

MOSFET gate charge and transition losses increase

directly with frequency. In addition to this basic tradeoff,

the effect of inductor value on ripple current and low cur-

rent operation must also be considered. The PolyPhase

approach reduces both input and output ripple currents

while optimizing individual output stages to run at a lower

fundamental frequency, enhancing efficiency.

current. TheLTC3735currentcomparatorhasamaximum

threshold of 72mV/R

and an input common mode

SENSE

rangeofSGNDtoPV . Thecurrentcomparatorthreshold

CC

sets the peak inductor current, yielding a maximum aver-

age output current I

the peak-to-peak ripple current, ∆I .

equal to the peak value less half

MAX

L

Assuming a common input power source for each out-

put stage and allowing a margin for variations in the

LTC3735 and external component values yields:

R

SENSE

= 2(40mV/I

)

MAX

Operating Frequency

The inductor value has a direct effect on ripple current.

The inductor ripple current ∆I_L, decreases with higher

inductance or frequency and increases with higher V_IN:

TheLTC3735usesaconstantfrequencyarchitecturewith

the frequency determined by an internal capacitor. This

capacitor is charged by a fixed current plus an additional

current which is proportional to the DC voltage applied

to the FREQSET pin. The FREQSET voltage is internally

set to 1.2V. It is recommended that this pin is actively







V_OUT

fL

V_OUT

∆I_L=

1−



V





IN

where f is the individual output stage operating frequency.

3735fa

12

LTC3735

APPLICATIONS INFORMATION

In a 2-phase converter, the net ripple current seen by

the output capacitor is much smaller than the individual

inductor ripple currents due to ripple cancellation. The

details on how to calculate the net output ripple current

can be found in Linear Technology Application Note 77.

isverydependentoninductortypeselected.Asinductance

increases, core losses go down. Unfortunately, increased

inductance requires more turns of wire and therefore cop-

per losses will increase.

Ferrite designs have very low core loss and are preferred

at high switching frequencies, so design goals can con-

centrate on copper loss and preventing saturation. Ferrite

core material saturates “hard,” which means that induc-

tance collapses abruptly when the peak design current is

exceeded. This results in an abrupt increase in inductor

ripple current and consequent output voltage ripple. Do

not allow the core to saturate!

Figure 3 shows the net ripple current seen by the output

capacitors for 1- and 2-phase configurations. The output

ripple current is plotted for a fixed output voltage as the

duty factor is varied between 10% and 90% on the x-axis.

The graph can be used in place of tedious calculations,

simplifying the design process.

Accepting larger values of ∆I allows the use of low in-

L

ductances, but can result in higher output voltage ripple.

A variety of inductors designed for high current, low volt-

age applications are available from manufacturers such

as Sumida, Coilcraft, Coiltronics, Toko and Panasonic.

A reasonable starting point for setting ripple current is

∆I = 0.4(I )/2, where I is the total load current.

OUT

L

OUT

Remember, the maximum ∆I occurs at the maximum

L

Power MOSFET, D1 and D2 Selection

input voltage. The individual inductor ripple currents

are determined by the frequency, inductance, input and

output voltages.

Two external power MOSFETs must be selected for each

output stage with the LTC3735: one N-channel MOSFET

for the top (main) switch, and one N-channel MOSFET for

the bottom (synchronous) switch.

1.0

1-PHASE

2-PHASE

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

The peak-to-peak drive levels are set by the PV volt-

age. This voltage typically ranges from 4.5V to 7V. Con-

sequently, logic-level threshold MOSFETs must be used

CC

in most applications. Pay close attention to the BV

DSS

specification for the MOSFETs as well; most of the logic-

level MOSFETs are limited to 30V or less.

SelectioncriteriaforthepowerMOSFETsincludethe“ON”

0

resistance R

, gate charge Q , reverse transfer ca-

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

DS(ON)

G

DUTY FACTOR (V /V

)

OUT IN

pacitance C , breakdown voltage BV

and maximum

DSS

RSS

3735 F03

continuous drain current I

.

D(MAX)

Figure 3. Normalized Output Ripple Current

vs Duty Factor [I_RMS≈ 0.3 (∆I_O(P-P)

]

When the LTC3735 is operating at continuous mode in a

step-down configuration, the duty cycles for the top and

bottom MOSFETs of each power stage are approximately:

Inductor Core Selection

Once the values for L1 and L2 are known, the type of

inductor must be selected. High efficiency converters

generally cannot afford the core loss found in low cost

powdered iron cores, forcing the use of more expensive

ferrite, molypermalloy, or Kool Mµ cores. Actual core loss

is independent of core size for a fixed inductor value, but it

V_OUT

Top MOSFET Duty Cycle =

(1)

V

IN

V – V_OUT

IN

Bottom MOSFET Duty Cycle =

(2)

V

IN

3735fa

13

LTC3735

APPLICATIONS INFORMATION

The conduction losses of the top and bottom MOSFETs

are therefore:

where R is the effective driver resistance (of approxi-

DR

mately2Ω),V isthedrivingvoltage(=PV )andV

DR

CC

TH(MIN)

 ²

is the minimum gate threshold voltage of the MOSFET.

PleasenoticethattheswitchinglossofthebottomMOSFET

is effectively negligible because the current conduction of

the antiparalleling diode. This effect is often referred as

zero-voltage-transition(ZVT).SimilarlywhentheLTC3735

converter works under fully synchronous mode at light

load, the reverse inductor current can also go through

the body diode of the top MOSFET and make the turn-on

loss to be negligible. However, equations 7 and 8 have to

be used in calculating the worst-case power loss, which

happens at highest load level.

V_OUT

I

OUT

2



P_CONTOP

=

•

• 1+ δ • ∆T •R_DS(ON)(3)

(

)









V

IN

V – V_OUT

I





 ²

IN

OUT

2

P_CONBOT

=

•

• 1+ δ • ∆T

(

(4)

)







V

IN

•R_DS(ON)

where I

is the total output current at full load, ∆T is the

OUT

difference between MOSFET operating temperature and

room temperature, and δ is the temperature dependency

of R

. δ is roughly 0.004/°C ~ 0.006/°C for low volt-

DS(ON)

The selection criteria of power MOSFETs start with the

stress check:

age MOSFETs.

The power losses of driving the top and bottom MOSFETs

are simply:

V < BV

IN

DSS

I

< I

MAX

D(MAX)

P

= Q • PV • f

(5)

(6)

DRTOP

DRBOT

G

CC

and

= Q • PV • f

G

CC

P

+ P

< top MOSFET maximum power

CONTOP

SWTOP

Use Q data at V = PV in MOSFET data sheets. f is

G

GS

CC

dissipation specification

the switching frequency as described previously. Please

notice that the above gate driving losses are usually not

dissipated by the MOSFETs. Instead they are mainly dis-

sipated on the internal drivers of the LTC3735, if there are

no resistors connected between the drive pins (TG, BG)

and the gates of the MOSFETs.

P

+ P

< bottom MOSFET maximum power

SWBOT

CONBOT

dissipation specification

ThemaximumpowerdissipationallowedforeachMOSFET

depends heavily on MOSFET manufacturing and pack-

aging, PCB layout and power supply cooling method.

Maximum power dissipation data are usually specified

in MOSFET data sheets under different PCB mounting

conditions.

The calculation of MOSFET switching loss is complicated

by several factors including the wide distribution of power

MOSFET threshold voltage, the nonlinearity of current ris-

ing/falling characteristic and the Miller Effect. Given the

data in a typical power MOSFET data sheet, the switch-

ing losses of the top and bottom MOSFETs can only be

estimated as follows:

The next step of selecting power MOSFETs is to minimize

the overall power loss:

P

OVL

= P

+ P

TOP BOT

= (P

P

+ P

SWBOT

+ P

) + (P

+

CONTOP

DRBOT

DRTOP

SWTOP

CONBOT

2

V

•I_OUT

4

IN

+ P

)

(7)

P_SWTOP

per Phase

=

• f •C_RSS•R_DR•

FortypicalmobileCPUapplicationswheretheratiobetween

input and output voltages is higher than 2:1, the bottom

MOSFET conducts load current most of the time while

the main losses of the top MOSFET are for switching and

driving. Therefore a low R

parallel)wouldminimizetheconductionlossofthebottom







1

+



V – V

V



_TH(MIN)

DR

TH(MIN)

part (or multiple parts in

DS(ON)

P

≈ 0

(8)

SWBOT

3735fa

14

LTC3735

APPLICATIONS INFORMATION

MOSFET while a higher R

but lower Q and C

or to choose a capacitor rated at a higher temperature

than required. Several capacitors may also be paral-

leled to meet size or height requirements in the design.

Always consult the capacitor manufacturer if there is any

question.

DS(ON)

G

RSS

part would be desirable for the top MOSFET.

The Schottky diodes, D1 and D2 in Figure 1 conduct dur-

ing the dead-time between the conduction of the top and

bottom MOSFETs. This helps reduce the current flowing

through the body diode of the bottom MOSFET. A body

diodeusuallyhasaforwardconductionvoltagehigherthan

that of a Schottky and is thus detrimental to efficiency. The

charge storage and reverse recovery of a body diode also

cause high frequency rings at the switching nodes (the

conjunctionnodesbetweenthetopandbottomMOSFETs),

which are again not desired for efficiency or EMI. Some

power MOSFET manufacturers integrate a Schottky diode

with a power MOSFET, eliminating the need to parallel an

external Schottky. These integrated Schottky-MOSFETs,

however,havesmallerMOSFETdiesizesthanconventional

partsandarethusnotsuitableforhighcurrentapplications.

0.6

1-PHASE

2-PHASE

0.5

0.4

0.3

0.2

0.1

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

DUTY FACTOR (V /V

)

OUT IN

3735 F04

Figure 4. Normalized RMS Input Ripple Current

vs Duty Factor for 1 and 2 Output Stages

C and C

Selection

IN

OUT

In continuous mode, the source current of each top

It is important to note that the efficiency loss is propor-

tional to the input RMS current squared and therefore a

2-phase implementation results in 75% less power loss

when compared to a single phase design. Battery/input

protection fuse resistance (if used), PC board trace and

connectorresistancelossesarealsoreducedbythereduc-

tion of the input ripple current in a 2-phase system. The

required amount of input capacitance is further reduced

by the factor, 2, due to the reduction in input RMS current.

N-channel MOSFET is a square wave of duty cycle V

/

OUT

V . A low ESR input capacitor sized for the maximum

IN

RMS current must be used. The details of a closed form

equation can be found in Linear Technology Application

Note 77. Figure 4 shows the input capacitor ripple current

for a 2-phase configuration with the output voltage fixed

and input voltage varied. The input ripple current is nor-

malized against the DC output current. The graph can be

used in place of tedious calculations. The minimum input

ripple current can be achieved when the input voltage is

twice the output voltage.

The selection of C

is driven by the required effective

OUT

series resistance (ESR). Typically once the ESR require-

ment has been met, the RMS current rating generally far

In the graph of Figure 4, the 2-phase local maximum input

RMS capacitor currents are reached when:

exceeds the I

requirements. The steady state

RIPPLE(P-P)

output ripple (∆V ) is determined by:

OUT

V_OUT

2k − 1

4

=









1

V

IN

∆V_OUT≈ ∆I_RIPPLEESR+



16• f •C_OUT



where k = 1, 2

where f = operating frequency of each stage, C

=

OUT

These worst-case conditions are commonly used for

design, considering input/output variations and long

term reliability. Note that capacitor manufacturer’s ripple

currentratingsareoftenbasedononly2000hoursoflife.

This makes it advisable to further derate the capacitor,

output capacitance and ∆I

ripple currents.

= interleaved inductor

RIPPLE

∆I

L

can be calculated from the duty factor and the

RIPPLE

∆I of each stage. A closed form equation can be found in

3735fa

15

LTC3735

APPLICATIONS INFORMATION

Linear Technology Application Note 77. Assuming induc-

tors are selected to have same ripple percentage for both

1-phase and 2-phase configurations, Figure 5 shows the

reduction of output ripple current by 2-phase operation.

Not only the ripple amplitude is more than halved, but

the ripple frequency is also doubled. Compared with the

output voltage ripple for 1-phase:

Manufacturers such as Nichicon, United Chemicon

and Sanyo should be considered for high performance

through-hole capacitors. The OS-CON semiconductor

dielectric capacitor available from Sanyo has the lowest

(ESR)(size) product of any aluminum electrolytic at a

somewhat higher price. An additional ceramic capacitor

in parallel with OS-CON type capacitors is recommended

to reduce the inductance effects.









1

∆V_OUT≈ ∆I_RIPPLEESR+

In surface mount applications, multiple capacitors may

have to be paralleled to meet the ESR or RMS current

handling requirements of the application. Aluminum elec-

trolytic and dry tantalum capacitors are both available in

surface mount configurations. New special polymer (SP)

surface mount capacitors from Panasonic offer very low

ESR also but have much lower capacitive density per unit

volume.Inthecaseoftantalum,itiscriticalthatthecapaci-

tors are surge tested for use in switching power supplies.

SeveralexcellentchoicesaretheAVXTPS,AVXTPSVorthe

KEMET T510 series of surface mount tantalums, available

incaseheightsrangingfrom2mmto4mm.Othercapacitor

typesincludeSanyoOS-CON,POSCAPs,KemetAO-CAPs,

Nichicon PL series and Sprague 595D series. Consult

the manufacturer for other specific recommendations. A

combination of capacitors will often result in maximizing

performance and minimizing overall cost and size.



8• f •C_OUT



∆V

of2-phaseislessthan50%ofthatof1-phase,given

OUT

the same output capacitor ESRs. Or, to have same ∆V

OUT

2-phase only need half the number of output capacitors

that are needed in 1-phase.

The output ripple varies with input voltage since ∆I is a

L

functionofinputvoltage.Theoutputripplewillbelessthan

25mV at max V with ∆I = 0.4I

/2 assuming:

OUT(MAX)

IN

L

C

OUT

C

OUT

required ESR < 4(R

) and

SENSE

> 1/(16f)(R

)

SENSE

The LTC3735 employs OPTI-LOOP technique to compen-

satetheswitchingregulatorloopwithexternalcomponents

(through I_THpin). OPTI-LOOP compensation speeds

up regulator’s transient response, minimizes output

capacitanceandeffectivelyremovesconstraintsonoutput

capacitor ESR. It opens a much wider selection of output

capacitortypesandavarietyofcapacitormanufacturesare

availableforhighcurrent,lowvoltageswitchingregulators.

Pꢁ Decoupling

CC

The PV pin supplies power to the top and bottom gate

CC

drivers and therefore must be bypassed to power ground

with a minimum of 4.7µF ceramic or tantalum capacitor.

Since the gate driving currents are of high amplitude and

high slew rate, this bypassing capacitor should be placed

50

40

30

20

10

very close to the PV and PGND pins to minimize the

CC

parasitic inductance. Do NOT apply greater than 7V to

the PV pin.

CC

The PV pin also supplies current to the internal control

CC

circuitry of the LTC3735. This supply current is much

lower than that of the current for the external MOSFET

gate drive. Ceramic capacitors are very good for high

frequency filtering and a 0.1µF ~ 1µF ceramic capacitor

should be placed adjacent to the PV_CCand SGND pins.

0

0.5

0.1 0.2 0.3 0.4

0.6 0.7 0.8 0.9

DUTY FACTOR (V /V

)

OUT IN

3735 F05

Figure 5. Output Ripple Current Reduction

of 2-Phase Over Single Phase

3735fa

16

LTC3735

APPLICATIONS INFORMATION

Topside MOSFET Driver Supply (C ,D ) (Refer to

An internal 1.5µA current source charges up the soft-start

B

Functional Diagram)

capacitor, C .When the voltage on RUN/SS reaches 1.5V,

SS

the controller is permitted to start operating. As the volt-

age on RUN/SS increases from 1.5V to 3.0V, the internal

ExternalbootstrapcapacitorsC andC connectedtothe

B1

B2

BOOST1 and BOOST2 pins supply the gate drive voltages

current limit is increased from 25mV/R

SENSE

to 72mV/

SENSE

for the topside MOSFETs. Capacitor C in the Functional

B

R

. The output current thus ramps up slowly, elimi-

Diagram is charged though diode D from PV when the

B

CC

nating the starting surge current required from the input

power supply. If RUN/SS has been pulled all the way to

ground there is a delay before starting of approximately:

SW pin is low. When the topside MOSFET turns on, the

driver places the C voltage across the gate-source of the

B

desired MOSFET. This enhances the MOSFET and turns on

the topside switch. The switch node voltage, SW, rises to

V and the BOOST pin rises to V + PV . The value of

1.5V

1.5µA

t_DELAY

=

C = 1s/µF C

SS SS

(

)

IN

CC

the boost capacitor C needs to be 30 to 100 times that of

B

The time for the output current to ramp up is then:

the total input capacitance of the topside MOSFET(s). The

reverse breakdown of D must be greater than PV

3V − 1.5V

1.5µA

B

CC(MAX).

t_IRAMP

=

C = 1s/µF C

SS SS

(

)

ꢁID Output ꢁoltage Programming

By pulling the RUN/SS pin below 1V the LTC3735 is put

After 27µs ~ 71µs t

delay, the output voltage of the

BOOT

into low current shutdown (I < 100µA). The RUN/SS pin

Q

regulator is digitally programmed as defined in Table 2

using the VID0 to VID5 logic input pins. The VID logic

inputs program a precision, 0.25% internal feedback re-

sistive divider. The LTC3735 has an output voltage range

of 0.700V to 1.708V in 16mV steps.

can be driven directly from logic as shown in Figure 6.

Diode D1 in Figure 6 reduces the start delay but allows

C

SS

to ramp up slowly providing the soft-start function.

The RUN/SS pin has an internal 6V zener clamp (see

Functional Diagram).

Refering to the Functional Diagram, there is a resistor,

PV

CC

R

, from V to ground. The value of R is controlled

VID

FB VID

3.3V OR 5V

RUN/SS

by the six VID input pins. Another internal resistor, 5.33k

R

SS

*

D1

(R ),completestheresistivedivider.Theoutputvoltage

ATTEN

C

SS

is thus set by the ratio of (R + 5.33k) to R

.

VID

C

SS

3735 F06

Each VID digital pin is a high impedance input. There-

fore they must be actively pulled high or pulled low. The

logic low threshold of the VID pins is 0.3V; the logic high

threshold is 0.7V.

*OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF

Figure 6. RUN/SS Pin Interfacing

Start-Up Sequence (Refer to the Functional Diagram)

Soft-Start/Run Function

After soft-start, the output voltage of the regulator settles

TheRUN/SSpinprovidesthreefunctions:1)run/shutdown,

2) soft-start and 3) an optional short-circuit latchoff timer.

Soft-startreducestheinputpowersources’surgecurrents

by gradually increasing the controller’s current limit. The

latchofftimerpreventsveryshort, extremeloadtransients

from tripping the overcurrent latch. A small pull-up cur-

rent (>5µA) supplied to the RUN/SS pin will prevent the

overcurrentlatchfromoperating.Thefollowingparagraph

describes how the functions operate.

at a voltage level equal to V

.

BOOT

R2• R3+ R5

(

)

V_BOOT= 0.6V •

R5• R1+ R2

(

)

ByusingdifferentR5resistors,V

canbeprogrammed.

BOOT

3735fa

17

LTC3735

APPLICATIONS INFORMATION

Table 2. ꢁID Output ꢁoltage Programming

ꢁID5

0

ꢁID4

0

1

ꢁID3

0

1

0

1

ꢁID2

0

1

0

1

0

1

0

1

ꢁID1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

ꢁID0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

LTC3735

1.708V

1.692V

1.676V

1.660V

1.644V

1.628V

1.612V

1.596V

1.580V

1.564V

1.548V

1.532V

1.516V

1.500V

1.484V

1.468V

1.452V

1.436V

1.420V

1.404V

1.388V

1.372V

1.356V

1.340V

1.324V

1.308V

1.292V

1.276V

1.260V

1.244V

1.228V

1.212V

ꢁID5

1

ꢁID4

0

1

ꢁID3

0

1

0

1

ꢁID2

0

1

0

1

0

1

0

1

ꢁID1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

ꢁID0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

LTC3735

1.196V

1.180V

1.164V

1.148V

1.132V

1.116V

1.100V

1.084V

1.068V

1.052V

1.036V

1.020V

1.004V

0.988V

0.972V

0.956V

0.940V

0.924V

0.908V

0.892V

0.876V

0.860V

0.844V

0.828V

0.812V

0.796V

0.780V

0.764V

0.748V

0.732V

0.716V

0.700V

3735fa

18

LTC3735

APPLICATIONS INFORMATION

Aftertheoutputvoltageentersthe 10%regulationwindow

Output ꢁoltage Set in Deep Sleep and Deeper Sleep

States (Refer to the Functional Diagram)

centered at V , the internal power good comparator

BOOT

issues a logic high signal. Refer to the timing diagram in

Figure 7. This signal then enters a logic AND gate, with

MCH_PG being the other input, and the output of the gate

is PG shown in Figure 7. This composite PG signal is then

The output voltage can be offset by the STP_CPUB signal.

When STP_CPUB becomes low, the output voltage will be

a certain percentage lower than that set by the VID bits in

Table 2. This state is defined to be the deep sleep state.

Referring to the Functional Diagram, we can caluculate

the STP_CPUB offset to be:

delayed by t

amount of time and then becomes MD.

BOOT

As soon as MD is asserted, the output voltage changes

from V

to V , a voltage level totally controlled by

BOOT

VID

R3

R3+ R4

the six VID bits. In the LTC3735, the time t

is set to

BOOT

STP%= –

•100%

be 15 switching cycles:

1

t_BOOT= 15

f_S

By using different R4 resistors, STP_CPUB offset can be

programmed.

The output voltage could also be set by external resistors

R6 and R4 when DPRSLPVR input is high. This state is

defined to be the deeper sleep state. The output voltage

If f is set at 210kHz, t

= 71µs

= 27µs

S

BOOT

If f is set at 550kHz, t

S

BOOT

is set to V

, regardless of the VID setting:

DPRSLPVR

R2• R3+ R6||R4

(

)

RUN/SS

1.5V

V_DPRSLPVR= 0.6V •

R6||R4 • R1+ R2

( ) (

)

V

VID

V

BOOT

By using different value R6 resistors, V

programmed.

can be

DPRSLPVR

V

OUT

90% V

BOOT

(The digital input threshold voltage is set to 1.8V for

STP_CPUB, DPRSLPVR and MCH_PG inputs.)

INTERNAL PG

(OUTPUT OF

INTERNAL

POWER GOOD

COMPARATOR)

Power Good Masking

The PGOOD output monitors V . When V

is not

OUT

MCH_PG

within 10% of the set point, PGOOD is pulled low with

an internal MOSFET. When V is within the regulation

OUT

window, PGOOD is high impedance. PGOOD should be

COMPOSITE PG

(=(INTERNAL PG)

AND (MCH_PG))

pulled up by an external resistor.

During VID changes, deep sleep and deeper sleep transi-

tions, the output voltage can initially be out of the 10%

window of the newly set regulation point. To avoid nui-

sance indications from PGOOD, a timer masks PGOOD for

t

BOOT

MD

110µs. If V

is still out of regulation after this blanking

OUT

VALID

time, PGOOD goes low. Any overvoltage or undervoltage

condition is also masked for 110µs before it is reported

by PGOOD.

INVALID

VID BITS

3735 F07

TIME

Figure 7. Start-Up Timing Diagram

3735fa

19

LTC3735

APPLICATIONS INFORMATION

begins discharging on the assumption that the output is in

an overcurrent condition. If the condition lasts for a long

ThemaskingcircuitryalsoadaptivelytracksVIDandstate

changes. If a new change in VID or state happens before

the 110µs masking timer expires, the timer resets and

starts a fresh count of 110µs. This prevents the system

fromrebootingunderfrequentoutputvoltagetransitions.

Refer to Figure 8 for the PGOOD timing diagram.

enough period as determined by the size of the C , the

SS

controller will be shut down until the RUN/SS pin voltage

is recycled. If the overload occurs during start-up, the

time can be approximated by:

5

t

≈ (C • 0.7V)/(1.5µA) = 4.6 • 10 (C )

Duringstart-up,PGOODisactivelypulledlowuntiltheRUN/

SS pin voltage reaches its arming voltage, which is 4.2V

typically, only then is the PGOOD pull-low signal released.

WhenRUN/SSgoeslow,PGOODgoeslowsimultaneously.

LO1

SS

If the overload occurs after start-up, the voltage on C

will continue charging and will provide additional time

SS

before latching off:

6

t

≈ (C • 2V)/(1.5µA) = 1.3 • 10 (C )

LO2

SS

VID BITS

This built-in overcurrent latchoff can be overridden by

providing a pull-up resistor, R , to the RUN/SS pin as

SS

shown in Figure 6. This resistance shortens the soft-

start period and prevents the discharge of the RUN/SS

capacitor during a severe overcurrent and/or short-circuit

V

OUT

INTERNAL PG

(OUTPUT OF

INTERNAL

POWER GOOD

COMPARATOR)

condition. When deriving the 5µA current from PV as in

CC

the figure, current latchoff is always defeated.

Why should you defeat current latchoff? During the pro-

totyping stage of a design, there may be a problem with

noise pickup or poor layout causing the protection circuit

to latch off the controller. Defeating this feature allows

troubleshooting of the circuit and PC layout. The internal

short-circuit and foldback current limiting still remains

active, thereby protecting the power supply system from

failure.Adecisioncanbemadeafterthedesigniscomplete

whether to rely solely on foldback current limiting or to

enablethelatchofffeaturebyremovingthepull-upresistor.

PGOOD

MASKING

110µs

PGOOD

3735 F08

TIME

Figure 8. PGOOD Timing Diagram

Fault Conditions: Overcurrent Latchoff

The value of the soft-start capacitor C may need to be

SS

scaled with output voltage, output capacitance and load

current characteristics. The minimum soft-start capaci-

tance is given by:

The RUN/SS pin also provides the ability to latch off the

controller when an overcurrent condition is detected. The

RUN/SS capacitor, C , is used initially to limit the inrush

SS

current. After the controller has been started and been

given adequate time to charge up the output capacitors

andprovidefullloadcurrent,theRUN/SScapacitorisused

for a short-circuit timer. If the output voltage falls to less

-4

C

SS

> (C

)(V )(10 )(R

)

OUT

SENSE

A recommended soft-start capacitor of C = 0.1µF will

SS

be sufficient for most applications.

than 70% of its nominal value after C reaches 4.2V, C

SS

3735fa

20

LTC3735

APPLICATIONS INFORMATION

Minimum On-Time Considerations

R_SENSE

m

R3

R_AVP

AVP ≅ –35.5•

•

,

Minimum on-time, t , is the smallest time duration

ON(MIN)

(9)

that the LTC3735 is capable of turning on the top MOSFET.

It is determined by internal timing delays and the gate

charge required to turn on the top MOSFET. Low duty

cycle applications may approach this minimum on-time

limit and care should be taken to ensure that:

V_OUT

0.6V

if g_m•R3> 10•

whereR

isthecurrentsenseresistor,misthenumber

SENSE

of phases, (m = 2 for LTC3735) R3 and R

are defined

AVP

V_OUT

in Figure 9. g is the transconductance gain for the error

m

t_{ON MIN}

<

(

)

amplifier, it is about 4.5mmho for LTC3735. Rewriting

V f

_IN( )

Equation 9 we can estimate the AVP resistor to be:

If the duty cycle falls below what can be accommodated

by the minimum on-time, the LTC3735 will begin to skip

cyclesresultinginvariablefrequencyoperation.Theoutput

voltage will continue to be regulated, but the ripple current

and ripple voltage will increase.

35.5•R3•R_SENSE

R_AVP

≅

(10)

m•|AVP|

V

OUT+

R3

R

The minimum on-time for the LTC3735 is generally less

than150ns.However,asthepeaksensevoltagedecreases,

the minimum on-time gradually increases. This is of par-

ticular concern in forced continuous applications with low

ripple current at light loads. If the duty cycle drops below

the minimum on-time limit in this situation, a significant

amount of cycle skipping can occur with correspondingly

larger ripple current and ripple voltage.

AVP

+

–

V

OA

+

OAOUT

R2

R1

–

If an application can operate close to the minimum

on-time limit, an inductor must be chosen that has a low

enough inductance to provide sufficient ripple amplitude

to meet the minimum on-time requirement. As a general

rule, keep the inductor ripple current of each phase equal

FB

–

+

I

TH

VID

0.6V

3735 F09

to or greater than 15% of I

at V

.

OUT(MAX)

IN(MAX)

Figure 9. Simplified Schematic Diagram

for AꢁP Design in LTC3735

Active ꢁoltage Positioning

Activevoltagepositioningcanbeusedtominimizepeak-to-

peak output voltage excursion under worst-case transient

loading conditions. The open-loop DC gain of the control

loop is reduced depending upon the maximum load step

specifications. Active voltage positioning can easily be

addedtotheLTC3735.Figure9showstheequivalentcircuit

forimplementingAVP.Theloadlineslopeisestimatedtobe:

We also adopt the current sense resistors as part of

voltage positioning slopes. So the total load line slope is

estimated to be:

R_SENSE

m

R_SENSE

m

R3

R_AVP

AVP ≅ –35.5•

•

–

,

(11)

V_OUT

0.6V

if g_m•R3>>

3735fa

21

LTC3735

APPLICATIONS INFORMATION

Rewriting this equation, we can estimate the R

value

(12)

and higher currents required by high performance digital

systems is not doubling but quadrupling the importance

of loss terms in the switching regulator system!

AVP

to be:

35.5•R3

R_AVP≅

2) Transition losses apply only to the topside MOSFET(s),

and are significant only when operating at high input volt-

ages (typically 12V or greater). Transition losses can be

estimated from:

m •|AVP|

–1

R_SENSE

Typically the calculation results based on these equations

have 10% tolerance. So the resistor values need to be

fine tuned.

2

V •I

IN OUT

• f •C

•R

•

DR

Transition Loss =

per Phase

RSS

4

Efficiency Considerations





1

+





The percent efficiency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efficiency and which change would

produce the most improvement. Percent efficiency can

be expressed as:

V

– V

V





DR

TH(MIN)

3)PV drivesbothtopandbottomMOSFETs.TheMOSFET

CC

driver current results from switching the gate capacitance

of the power MOSFETs. Each time a MOSFET gate is

switched from low to high to low again, a packet of charge

%Efficiency = 100% – (L1 + L2 + L3 + ...)

dQ moves from PV to ground. The resulting dQ/dt is a

CC

where L1, L2, etc. are the individual losses as a percent-

age of input power.

current out of PV that is typically much larger than the

CC

control circuit current. In continuous mode, I

=

GATECHG

(Q + Q )f, where Q and Q are the gate charges of the

Although all dissipative elements in the circuit produce

losses, four main sources usually account for most of

T

B

T

B

topside and bottom side MOSFETs and f is the switching

2

frequency.

the losses in LTC3735 circuits: 1) I R losses, 2) Topside

MOSFET transition losses, 3) PV supply current and

CC

4) The input capacitor has the difficult job of filtering

the large RMS input current to the regulator. It must

have a very low ESR to minimize the AC I R loss and

4) C loss.

IN

2

1) I R losses are predicted from the DC resistances of

sufficient capacitance to prevent the RMS current from

causing additional upstream losses in fuses or batteries.

The LTC3735 2-phase architecture typically halves the

input and output capacitor requirements over 1-phase

solutions.

the fuse (if used), MOSFET, inductor, and current sense

resistor. In continuous mode the average output current

flowsthroughLandR

, butis“chopped”betweenthe

SENSE

topside MOSFET and the synchronous MOSFET. If the two

MOSFETs have approximately the same R

, then the

DS(ON)

resistance of one MOSFET can simply be summed with

Other losses, including C

ESR loss, Schottky diode

OUT

2

the resistances of L, R

and ESR to obtain I R losses.

DS(ON)

SENSE

conduction loss during dead time, inductor core loss and

internal control circuitry supply current generally account

for less than 2% additional loss.

For example, if each R

= 10mΩ, R = 10mΩ, and

L

R

= 5mΩ, then the total resistance is 25mΩ. This

SENSE

results in losses ranging from 2% to 8% as the output

current increases from 3A to 15A per output stage for a 5V

output, or a 3% to 12% loss per output stage for a 3.3V

Checking Transient Response

The regulator loop response can be checked by look-

ing at the load transient response. Switching regulators

take several cycles to respond to a step in DC (resistive)

output. Efficiency varies as the inverse square of V

for

OUT

the same external components and output power level.

Thecombinedeffectsofincreasinglyloweroutputvoltages

3735fa

22

LTC3735

APPLICATIONS INFORMATION

load current. When a load step occurs, V

shifts by an

The output voltage settling behavior is related to the

stability of the closed-loop system and will demonstrate

the actual overall supply performance.

OUT

amount equal to ∆I

(ESR), where ESR is the effective

LOAD

series resistance of C . ∆I

also begins to charge or

OUT

LOAD

discharge C

generating the feedback error signal that

OUT

Automotive Considerations: Plugging into the

Cigarette Lighter

forces the regulator to adapt to the current change and

return V to its steady-state value. During this recovery

OUT

time V

can be monitored for excessive overshoot or

OUT

As battery-powered devices go mobile, there is a natural

interest in plugging into the cigarette lighter in order to

conserveorevenrechargebatterypacksduringoperation.

But before you connect, be advised: you are plugging into

thesupplyfromhell.Themainbatterylineinanautomobile

is the source of a number of nasty potential transients,

includingload-dump,reverse-batteryanddouble-battery.

ringing, which would indicate a stability problem. The

availability of the I pin not only allows optimization of

TH

control loop behavior but also provides a DC coupled and

AC filtered closed loop response test point. The DC step,

rise time, and settling at this test point truly reflects the

closed loop response. Assuming a predominantly second

ordersystem, phasemarginand/or dampingfactorcanbe

estimated using the percentage of overshoot seen at this

pin.Thebandwidthcanalsobeestimatedbyexaminingthe

Load-dump is the result of a loose battery cable. When the

cable breaks connection, the field collapse in the alterna-

tor can cause a positive spike as high as 60V which takes

several hundred milliseconds to decay. Reverse-battery is

just what it says, while double-battery is a consequence of

tow truck operators finding that a 24V jump start cranks

cold engines faster than 12V.

rise time at the pin. The I external components shown

TH

in the Figure 1 circuit will provide an adequate starting

point for most applications.

The I series R -C filter sets the dominant pole-zero

TH

C

loop compensation. The values can be modified slightly

(from 0.2 to 5 times their suggested values) to optimize

transient response once the final PC layout is done and

the particular output capacitor type and value have been

determined. The output capacitors need to be decided

upon first because the various types and values determine

the loop gain and phase. An output current pulse of 20%

to 80% of full-load current having a rise time of <1µs will

The network shown in Figure 10 is the most straightfor-

ward approach to protect a DC/DC converter from the

ravages of an automotive power line. The series diode

prevents current from flowing during reverse-battery,

while the transient suppressor clamps the input voltage

during load-dump. Note that the transient suppressor

should not conduct during double-battery operation, but

must still clamp the input voltage below breakdown of

the converter. Although the LT3735 has a maximum input

voltage of 32V, most applications will be limited to 30V

produce output voltage and I pin waveforms that will

TH

give a sense of the overall loop stability without breaking

the feedback loop. The initial output voltage step result-

ing from the step change in output current may not be

within the bandwidth of the feedback loop, so this signal

cannot be used to determine phase margin. This is why

by the MOSFET BV_DSS

.

V

BAT

12V

+

it is better to look at the I pin signal which is in the

PV

CC

TH

feedbackloopandisthefilteredandcompensatedcontrol

loop response. The gain of the loop will be increased

by increasing R and the bandwidth of the loop will be

C

LTC3735

increased by decreasing C . If R is increased by the

C

3735 F10

same factor that C is decreased, the zero frequency will

C

be kept the same, thereby keeping the phase the same in

Figure 10. Automotive Application Protection

the most critical frequency range of the feedback loop.

3735fa

23

LTC3735

APPLICATIONS INFORMATION

Design Example

2

1.5V 35A





P_TOP

=

•

• 1+ 0.005• 85°C–25°C •

(

)

(

)







As a design example, assume V = 12V (nominal), V

IN



21V

2

= 21V (max), V

(each phase).

= 1.5V, I

= 35A, and f = 350kHz

OUT

MAX

21V²•17.5A

0.008Ω +

•350kHz •307pF •

Theinductancevalueischosenfirstbasedona40%ripple

current assumption. The highest value of ripple current

occurs at the maximum input voltage. The minimum

inductance for 40% ripple current is:

2

1







2Ω •

+

= 1.26W







5V –1V 1V

Equation 4 gives the worst-case power loss dissipated





V_OUT

f • ∆I

V_OUT

1.5V

L ≥

• 1–

=

•

by the bottom MOSFET (assuming FDS7760 and T =







J

V

350kHz • 40%•17.5A

(

)



IN

85°C again):

1.5V

21V





2

1–

= 0.57µH

21V –1.5V 35A













P_BOT

=

•









21V

2

Using L = 0.6µH, a common “off-the-shelf” value results

in 38%ripple current. The peak inductor current will be

the maximum DC current plus one half of the ripple cur-

rent, or 21A.

1+ 0.005• 85°C–25°C •0.008Ω

(

)

(

)

= 2.95W

Therefore it is necessary to have two FDS7760s in parallel

to split the power loss.

TietheFREQSETpinto1.2V, resistivelydivideddownfrom

PV to have 350kHz operation for each phase.

CC

A short-circuit to ground will result in a folded back cur-

rent of about:

The minimum on-time also occurs at maximum input

voltage:





25mV

1

200ns•21V

I_SC=

+ •

= 16A

V_OUT

1.5V







0.002Ω 2  0.6µH

t_ON(MIN)

=

= 204ns

V • f 21V •350kHz

IN

The worst-case power dissipation by the bottom MOSFET

under short-circuit conditions is:

which is larger than 150ns, the typical minimum on time

of the LTC3735.

1

–200ns

2

R

and R

can be calculated by using a con-

SENSE2

350kHz

SENSE1

P

=

• 16A •

(

)

BOT

1

servative maximum sense voltage threshold of 40mV and

taking into account of the peak current:

350kHz

40mV

21A

1+ 0.005• 85°C–25°C •0.008Ω

(

)

(

)

R_SENSE

=

= 0.002Ω

= 2.48W

The power loss dissipated by the top MOSFET can be cal-

culated with equations 3 and 7. Using a Fairchild FDS7760

which is less than normal, full load conditions.

The nominal duty cycle of this application is equation 1:

1.5V

as an example: R

= 8mΩ, Q = 55nC at 5V V , C

DS(ON)

G GS RSS

= 307pF, V

= 1V. At maximum input voltage with

TH(MIN)

DC=

= 12.5%

T (estimated) = 85°C at an elevated ambient temperature:

J

12V

3735fa

24

LTC3735

APPLICATIONS INFORMATION

Using Figure 4, the RMS input ripple current will be:

stable.Thepowergroundreturnstothesourcesofthebot-

tom N-channel MOSFETs, anodes of the Schottky diodes,

I

= 35A • 0.22 = 7.7A

INRMS

and (–) plates of C , which should have the shortest trace

IN

An input capacitor(s) with a 8A RMS current rating is

required.

length possible.

–

+

3) Are the SENSE and SENSE leads routed together

with minimum PC trace spacing? The filter capacitors

The output capacitor ripple current is calculated by using

the inductor ripple current and multiplying by the factor

obtained from Figure 3. The output ripple will be highest

at the maximum input voltage since the duty cycle is less

than 50%. The maximum output current ripple is:

+

–

between SENSE and SENSE pin pairs should be as

close as possible to the LTC3735. Ensure accurate cur-

rent sensing with Kelvin connections at the current sense

resistor. See Figure 11.

1.5V

350kHz •0.6µH

4) Does the (+) plate of C connect to the drains of the

IN

∆I_OUT(MAX)

=

•0.77= 5.5A_P-P

topside MOSFETs as closely as possible? This capacitor

provides the AC current to the MOSFETs. Keep the input

current path formed by the input capacitor, top and bot-

tom MOSFETs, and the Schottky diode on the same side

of the PC board in a tight loop to minimize conducted and

radiated EMI.

Assuming the ESR of output capacitor(s) is 5mΩ, the

output ripple voltage is:





1

∆V_OUT≈ 5.5A_P-P5mΩ +





16•350kHz • 4•270µF

(

)





5) Keep the “noisy” nodes, SW, BOOST, TG and BG away

from sensitive small-signal nodes. Ideally the switch

nodes should be placed at the furthest point from the

LTC3735.

= 28.4mV_P-P

PC Board Layout Checklist

The diagram in Figure 12 illustrates all branch currents in

a 2-phase switching regulator. It becomes very clear after

studying the current waveforms why it is critical to keep

the high-switching-current paths to a small physical size.

High electric and magnetic fields will radiate from these

“loops” just as radio stations transmit signals. The output

capacitor ground should return to the negative terminal of

the input capacitor and not share a common ground path

with any switched current paths. The left half of the circuit

givesrisetothe“noise”generatedbyaswitchingregulator.

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the LTC3735. Check the following in your layout:

1) Are the signal and power grounds segregated? Keep

the SGND at one end of a PC board to prevent MOSFET

currents from traveling under the IC. The IC signal ground

pin should be used to hook up all control circuitry on one

side of the IC, routing the copper through SGND, under

the IC covering the “shadow” of the package, connecting

to the PGND pin and then continuing on to the (–) plate

of C

.

PADS OF SENSE RESISTOR

OUT

2) Is the PV decoupling capacitor connected immedi-

CC

ately adjacent to the PV and PGND pins? A 1µF ceramic

CC

TRACE TO OUTPUT CAP (+)

TRACE TO INDUCTOR

capacitor of the X7R or X5R material is small enough to

fit very close to the IC to minimize the ill effects of the

large current pulses drawn to drive the power MOSFETs.

An additional 4.7µF ~ 10µF of ceramic, tantalum or other

3735 F11

+

–

SENSE

Figure 11. Proper Current Sense Connections

low ESR capacitor is recommended in order to keep PV

CC

3735fa

25

LTC3735

APPLICATIONS INFORMATION

SW1

D1

L1

R

SENSE1

V

OUT

IN

R

IN

C

OUT

+

C

R

L

IN

SW2

L2

R

SENSE2

D2

BOLD LINES INDICATE

HIGH, SWITCHING

CURRENT LINES.

KEEP LINES TO A

MINIMUM LENGTH.

3735 F12

Figure 12. Instantaneous Current Path Flow in a Multiple Phase Switching Regulator

Simplified ꢁisual Explanation of How a 2-Phase

Controller Reduces Both Input and Output RMS Ripple

Current

The ground terminations of the sychronous MOSFETs and

Schottky diodes should return to the negative plate(s) of

the input capacitor(s) with a short isolated PC trace since

veryhighswitchedcurrentsarepresent.Aseparateisolated

path from the negative plate(s) of the input capacitor(s)

should be used to tie in the IC power ground pin (PGND)

and the signal ground pin (SGND). This technique keeps

inherent signals generated by high current pulses from

taking alternate current paths that have finite impedances

during the total period of the switching regulator. External

OPTI-LOOP compensation allows overcompensation for

PC layouts which are not optimized but this is not the

recommended design procedure.

A multiphase power supply significantly reduces the

amount of ripple current in both the input and output

capacitors. The RMS input ripple current is divided by,

and the effective ripple frequency is multiplied up by the

number of phases used (assuming that the input voltage

is greater than the number of phases used times the out-

put voltage). The output ripple amplitude is also reduced

by, and the effective ripple frequency is increased by the

number of phases used. Figure 13 graphically illustrates

the principle.

3735fa

26

LTC3735

APPLICATIONS INFORMATION

SINGLE PHASE

DUAL PHASE

Figure 4 illustrates the RMS input current drawn from

the input capacitance vs the duty cycle as determined

by the ratio of input and output voltage. The peak input

RMS current level of the single phase system is reduced

by 50% in a 2-phase solution due to the current splitting

between the two stages.

SW V

SW1 V

SW2 V

I

CIN

I

L1

L2

I

COUT

An interesting result of the 2-phase solution is that the

V

which produces worst-case ripple current for the

IN

I

input capacitor, V

= V /2, in the single phase design

CIN

OUT

IN

produces zero input current ripple in the 2-phase design.

I

COUT

The output ripple current is reduced significantly when

compared to the single phase solution using the same

RIPPLE

3735 F13

inductance value because the V /L discharge current

OUT

Figure 13. Single and 2-Phase Current Waveforms

term from the stage that has its bottom MOSFET on sub-

tracts current from the (V – V )/L charging current

IN

OUT

The worst-case RMS ripple current for a single stage de-

sign peaks at an input voltage of twice the output voltage.

The worst-case RMS ripple current for a two stage design

results in peak outputs of 1/4 and 3/4 of input voltage.

When the RMS current is calculated, higher effective duty

factor results and the peak current levels are divided as

long as the currents in each stage are balanced. Refer

to Linear Technology Application Note 19 for a detailed

description of how to calculate RMS current for the single

stage switching regulator. Figures 3 and 4 illustrate how

the input and output currents are reduced by using an

additional phase. The input current peaks drop in half and

the frequency is doubled for this 2-phase converter. The

input capacity requirement is thus reduced theoretically

by a factor of four! Ceramic input capacitors with their

low ESR characteristics can be used.

resulting from the stage which has its top MOSFET on.

The output ripple current is:













1–2D (1–D)

1–2D + 1

2V_OUT

fL

∆I_RIPPLE

=

where D is duty factor.

The input and output ripple frequency is increased by

the number of stages used, reducing the output capacity

requirements.WhenV isapproximatelyequalto2(V

)

IN

OUT

as illustrated in Figures 3 and 4, very low input and output

ripple currents result.

3735fa

27

LTC3735

TYPICAL APPLICATION

Figure 14 shows a typical application using the LTC3735

to power the mobile CPU core. The input can vary from

5V to 24V; the output voltage can be programmed from

0.7V to 1.708V with a maximum current of 32A. By only

modifying the external MOSFET and inductor selection,

higher load current capability (up to 40A) can be achieved.

1.708V. When the STP_CPUB signal is low, a deep sleep

state is indicated and the output voltage is decreased by

about1.04%.WhentheDPRSLPVRsignalishigh,adeeper

sleep state is indicated and the output voltage becomes

0.748V regardless of the states of the VID bits. Active

voltage positioning is accomplished with a resistor from

+

the I to the V

pin. Lower resistance yields a steeper

TH

OA

The power supply in Figure 14 receives a VRON signal for

ON/OFF control. After soft-start, the output voltage is set

at 1.2V until the assertion of the MCH_PG signal. After

about a 50µs delay, the VID5-VID0 bits gain the control

over the output voltage and program it between 0.7V and

AVP slope while higher resistance provides a flatter slope.

Finally, the PGOOD output is masked for 110µs during VID

change or state transition.

1µF

D1

L1

36

2

33

32

27

26

10

11

V

_PG/MCH_PG

DPRSLPVR

STP_CPUB

PSIB

MCH_PG

DPRSLPVR

STP_CPUB

PSIB

TG1

SW1

BG1

Q1

Q2

0.8µH

CCP

0.002Ω

3.3V

2k

+

8

S1

V

IN

5V ~ 24V

4

C1

10µF ×4

35V X5R

10Ω

PGND

+

3

PGOOD

V

FREQSET SENSE1

OUT

5V

1nF

0.7V ~ 1.708V

AT 32A

19

20

21

22

23

24

35

17

16

–

VID0

VID1

VID2

VID3

VID4

VID5

VID0

VID1

VID2

VID3

VID4

VID5

SENSE1

100k

+

C5

×3

Si1034X

2.2µF

1µF

D2

LTC3735

L2

30

29

25

Q3

Q4

TG2

SW2

BG2

0.8µH

0.002Ω

+

V

RON

S2

C5: PANSONIC SP CAPS EEFSX0D181R

OR SANYO POSCAP 2R5TPE220M9

D1, D2: B340A

232k

100pF

10Ω

12

13

18

14

15

5

+

V

+

OA

L1, L2: CDEP 104-OR8MC-L

PGOOD

SENSE2

10Ω

Q1, Q3: IRF7811W OR Si7860DP

Q2, Q4: IRF7811W ¥2 OR Si7856DP

1nF

–

I

SENSE2

TH

1000pF

1M

12.7k

13.3k

100Ω

3.3k

470pF

RUN/SS

SGND

RBOOT

56.2k

13.3k

470pF

9

1

3.3V

3.3V CLK_EN# 3.3V

2k

RDPRSLP

100Ω

+

1.27M

47pF

OUT

V

FB

RDPSLP

+

1µF

X5R

S1

S2

28

34

31

+

PV

CC

V

OA

1M

249k

1.9k

2N7002

7

1M 1%

BOOST1

BOOST2

OAOUT

–

4.12k

43.2k

IMVP4_PG

MMBT3904

5V

PSIB

6

4.7µF

X5R

V

OA

MMBT3904

80.6k

BAT54

0.1µF

549k

1µF

SW2

SW1

BAT54C

0.1µF

PGOOD

3735 F14

V

RON

Figure 14. 5ꢁ to 24ꢁ Input, 0.7ꢁ to 1.708ꢁ Output, 32A IMꢁP-Iꢁ Compatible Power Supply

3735fa

28

LTC3735

PACKAGE DESCRIPTION

G Package

36-Lead Plastic SSOP (5.3mm)

(Reference LTC DWG # 05-08-1640)

12.50 – 13.10*

(.492 – .516)

1.25 0.12

5.3 – 5.7

36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19

7.8 – 8.2

7.40 – 8.20

(.291 – .323)

0.42 0.03

0.65 BSC

5

7

8

RECOMMENDED SOLDER PAD LAYOUT

1

2

3

4

6

9 10 11 12 13 14 15 16 17 18

2.0

(.079)

MAX

5.00 – 5.60**

(.197 – .221)

0° – 8°

0.65

(.0256)

BSC

0.09 – 0.25

(.0035 – .010)

0.55 – 0.95

(.022 – .037)

0.05

0.22 – 0.38

(.009 – .015)

TYP

(.002)

NOTE:

MIN

1. CONTROLLING DIMENSION: MILLIMETERS

G36 SSOP 0204

MILLIMETERS

2. DIMENSIONS ARE IN

(INCHES)

3. DRAWING NOT TO SCALE

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED .152mm (.006") PER SIDE

**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE

3735fa

29

LTC3735

PACKAGE DESCRIPTION

UHF Package

38-Lead Plastic QFN (5mm × 7mm)

(Reference LTC DWG # 05-08-1701 Rev C)

0.70 ± 0.05

5.50 ± 0.05

4.10 ± 0.05

3.00 REF

5.15 0.05

3.15 0.05

PACKAGE

OUTLINE

0.25 ± 0.05

0.50 BSC

5.5 REF

6.10 ± 0.05

7.50 ± 0.05

RECOMMENDED SOLDER PAD LAYOUT

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

PIN 1 NOTCH

R = 0.30 TYP OR

0.35 × 45° CHAMFER

0.75 ± 0.05

3.00 REF

5.00 ± 0.10

37

38

0.00 – 0.05

0.40 ±0.10

PIN 1

TOP MARK

1

2

(SEE NOTE 6)

5.15 0.10

5.50 REF

7.00 ± 0.10

3.15 0.10

(UH) QFN REF C 1107

0.200 REF 0.25 ± 0.05

R = 0.125

TYP

R = 0.10

TYP

0.50 BSC

BOTTOM VIEW—EXPOSED PAD

NOTE:

1. DRAWING CONFORMS TO JEDEC PACKAGE

OUTLINE M0-220 VARIATION WHKD

2. DRAWING NOT TO SCALE

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

3735fa

3. ALL DIMENSIONS ARE IN MILLIMETERS

30

LTC3735

REVISION HISTORY

REꢁ

DATE

DESCRIPTION

PAGE NUMBER

A

4/11

Updated Figure 14

Updated Related Parts

28

32

3735fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

31

LTC3735

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LTC3816

Single Phase DC/DC Controller for Intel IMVP-6/6+/6.5 CPUs

7-Bit IMVP-6 VID: 0.00V ≤ V

≤ 1.50V,

OUT

4.5V ≤ V ≤ 36V, Very Low Duty Cycle Capable

IN

LTC3732

LTC3734

3-Phase, 5-Bit VID, 600kHz, Synchronous Controller

Single Phase DC/DC Controller for IMVP-4

5-Bit VRM 9/9.1: 1.10V ≤ V

≤ 1.85V

OUT

6-Bit IMVP-4 VID: 0.70V ≤ V

≤ 1.708V,

OUT

4.5V ≤ V ≤ 30V, Lossless Voltage Positioning

IN

LTC3869/LTC3869-2 Dual, 2-Phase Synchronous Step-Down DC/DC Controllers with

Excellent Current Share when Paralleled

Phase-Lockable Fixed 250kHz to 780kHz Frequency,

4V ≤ V ≤ 38V, 0.8V ≤ V

≤ 12.5V

OUT

IN

LTC3856

2-Phase, Single Output Synchronous Step-Down DC/DC Controller

with Diff Amp and DCR Temperature Compensation

Phase-Lockable Fixed 250kHz to 770kHz Frequency,

4.5V ≤ V ≤ 38V, 0.8V ≤ V ≤ 5V

IN

OUT

LTC3850/LTC3850-1 Dual 2-Phase, High Efficiency Synchronous Step-Down DC/DC

Phase-Lockable Fixed 250kHz to 780kHz Frequency,

4V ≤ V ≤ 30V, 0.8V ≤ V ≤ 5.25V

LTC3850-2

Controller, R

or DCR Current Sensing and Tracking

SENSE

IN

OUT

LTC3860

Dual, Multiphase, Synchronous Step-Down DC/DC Controller with

Diff Amp and Three-State Output Drive

Operates with Power Blocks, DRMOS Devices or External

Drivers/MOSFETs, 3V ≤ V ≤ 24V, t = 20ns

IN

ON(MIN)

LTC3855

LTC3829

LTC3853

Dual, Multiphase, Synchronous Step-Down DC/DC Controller with

Diff Amp and DCR Temperature Compensation

Phase-Lockable Fixed Frequency 250kHz to 770kHz,

4.5V ≤ V ≤ 38V, 0.8V ≤ V ≤ 12V

IN

OUT

3-Phase, Single Output Synchronous Step-Down Controller with Diff Phase-Lockable Fixed 250kHz to 770kHz Frequency,

Amp and DCR Temperature Compensation 4.5V ≤ V ≤ 38V, 0.8V≤ V ≤ 5V

IN

OUT

Triple Output, Multiphase Synchronous Step-Down DC/DC Controller, Phase-Lockable Fixed 250kHz to 750kHz Frequency,

or DCR Current Sensing and Tracking 4V ≤ V ≤ 24V, V Up to 13.5V

R

SENSE

IN

OUT3

3735fa

LT 0411 REV A • PRINTED IN USA

32 ^{LinearTechnology Corporation}

1630 McCarthy Blvd., Milpitas, CA 95035-7417

●

 LINEAR TECHNOLOGY CORPORATION 2002

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC3850EGN
厂家：	Linear
描述：	IC 0.1 A DUAL SWITCHING CONTROLLER, 860 kHz SWITCHING FREQ-MAX, PDSO28, 0.150 INCH, PLASTIC, SSOP-28, Switching Regulator or Controller 控制器
文件：	总32页 (文件大小：388K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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