LTC3769IUF#PBF [Linear]
LTC3769 - 60V Low IQ Synchronous Boost Controller; Package: QFN; Pins: 24; Temperature Range: -40°C to 85°C;
| 型号： | LTC3769IUF#PBF |
| 厂家： | 
Linear |
| 描述： | LTC3769 - 60V Low IQ Synchronous Boost Controller; Package: QFN; Pins: 24; Temperature Range: -40°C to 85°C |
| 文件： | 总32页 (文件大小：432K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3769
60V Low I Synchronous
Q
Boost Controller
FEATURES
DESCRIPTION
n
Synchronous Operation for Highest Efficiency and
The LTC®3769 is a high performance single output syn-
chronous boost converter controller that drives an all
N-channel power MOSFET stage. Synchronous rectifica-
tion increases efficiency, reduces power losses and eases
thermal requirements, simplifying high power boost ap-
plications. The 28µA no-load quiescent current extends
operating run time in battery-powered systems.
Reduced Heat Dissipation
n
Wide V Range: 4.5V to 60V (65V Abs Max);
IN
Operates Down to 2.3V After Start-Up
Output Voltage Up to 60V
n
n
n
n
n
n
n
n
n
n
n
±±1 ±.200V Reference Voltage
R
or Inductor DCR Current Sensing
SENSE
±001 Duty Cycle Capability for Synchronous MOSFET
A 4.5V to 60V input supply range encompasses a wide
range of system architectures and battery chemistries.
When biased from the output of the boost converter or
anotherauxiliarysupply, theLTC3769canoperatefroman
input supply as low as 2.3V after start-up. The operating
frequency can be set within a 50kHz to 900kHz range or
synchronized to an external clock using the internal PLL.
Low Quiescent Current: 28μA
Phase-Lockable Frequency (75kHz to 850kHz)
Programmable Fixed Frequency (50kHz to 900kHz)
Power Good Output Voltage Monitor
Low Shutdown Current: 4µA
Internal LDO Powers Gate Drive from VBIAS or EXTV
CC
Thermally Enhanced Low Profile 24-Pin 4mm × 4mm
The SS pin ramps the output voltage during start-up. The
PLLIN/MODE pin selects Burst Mode® operation, pulse-
skipping mode or forced continuous mode at light loads.
QFN Package and 20-Lead TSSOP Package
APPLICATIONS
L, LT, LTC, LTM, Burst Mode, OPTI-LOOP, Linear Technology and the Linear logo are registered
trademarks of Linear Technology Corporation. All other trademarks are the property of their
respective owners. Protected by U. S. Patents, including 5408150, 5481178, 5705919,
5929620, 6177787, 6498466, 6580258, 6611131.
n
Industrial
n
Automotive
n
Medical
Military
n
TYPICAL APPLICATION
±20W, ±2V to 24V/5A Synchronous Boost Converter
Efficiency and Power Loss
vs Output Current
3.3µH
100
90
80
70
60
50
40
10
1
4mΩ
V
V
IN
OUT
24V/5A
4.5V TO 60V
22µF
220µF
DOWN TO 2.3V
AFTER START-UP IF
VBIAS IS POWERED
VBIAS
EFFICIENCY
+
–
SENSE
SENSE
RUN
SS
10nF
V
FOLLOWS V FOR V > 24V
IN IN
OUT
FROM V
OUT
BG
LTC3769
8.66K
100pF
POWER
LOSS
0.1
15nF
ITH
TG
0.01
SW
PLLIN/MODE
FREQ
0.1µF
BOOST
0.001
OVMODE
ILIM
0.0001 0.001
0.01
0.1
1
10
OUTPUT CURRENT (A)
INTV
CC
3769 TA01b
4.7µF
232k
VFB
PGOOD
EXTV
CC
12.1k
GND
3769 TA01a
3769fa
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For more information www.linear.com/LTC3769
LTC3769
(Notes ±, 3)
ABSOLUTE MAXIMUM RATINGS
EXTV ...................................................... –0.3V to 14V
VBIAS ........................................................ –0.3V to 65V
BOOST ........................................................–0.3V to 71V
SW................................................................ –5V to 65V
RUN ............................................................. –0.3V to 8V
Maximum Current Sourced into Pin
CC
+
–
SENSE , SENSE ........................................ –0.3V to 65V
+
–
(SENSE -SENSE )............................................–0.3Vto 0.3V
ILIM, SS, ITH, FREQ, PHASMD, VFB.....–0.3V to INTV
CC
Operating Junction Temperature
Range (Note 2)........................................–55°C to 150°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec) SSOP ........300°C
From Source >8V..............................................100µA
PGOOD, PLLIN/MODE ................................. –0.3V to 6V
INTV , (BOOST - SW) ..................................–0.3V to 6V
CC
PIN CONFIGURATION
TOP VIEW
TOP VIEW
ILIM
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
PGOOD
VBIAS
24 23 22 21 20 19
INTV
CC
VBIAS
PGOOD
ILIM
1
2
3
4
5
6
18 SW
FREQ
EXTV
CC
OVMODE
17
16
GND
PLLIN/MODE
RUN
INTV
CC
ITH
25
GND
BG
21
GND
NC
15 VFB
BOOST
TG
+
–
INTV
CC
SENSE
14
SS
NC
13 SENSE
–
SENSE
SW
7
8
9 10 11 12
+
SENSE
OVMODE
ITH
VFB 10
FE PACKAGE
20-LEAD PLASTIC TSSOP
UF PACKAGE
24-LEAD (4mm × 4mm) PLASTIC QFN
T
= 150°C, θ = 38°C/W
JA
JMAX
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
T
JMAX
= 150°C, θ = 47°C/W
JA
EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
LTC3769EUF#PBF
LTC3769IUF#PBF
LTC3769HUF#PBF
LTC3769MPUF#PBF
LTC3769EFE#PBF
LTC3769IFE#PBF
LTC3769HFE#PBF
LTC3769MPFE#PBF
TAPE AND REEL
PART MARKING*
3769
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3769EUF#TRPBF
LTC3769IUF#TRPBF
LTC3769HUF#TRPBF
LTC3769MPUF#TRPBF
LTC3769EFE#TRPBF
LTC3769IFE#TRPBF
LTC3769HFE#TRPBF
LTC3769MPFE#TRPBF
–40°C to 125°C
–40°C to 125°C
–40°C to 150°C
–55°C to 150°C
–40°C to 125°C
–40°C to 125°C
–40°C to 150°C
–55°C to 150°C
24-Lead (4mm × 4mm) Plastic QFN
24-Lead (4mm × 4mm) Plastic QFN
24-Lead (4mm × 4mm) Plastic QFN
24-Lead (4mm × 4mm) Plastic QFN
20-Lead Plastic SSOP
3769
3769
3769
LTC3769FE
LTC3769FE
LTC3769FE
LTC3769FE
20-Lead Plastic SSOP
20-Lead Plastic SSOP
20-Lead Plastic SSOP
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3769fa
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For more information www.linear.com/LTC3769
LTC3769
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C, VBIAS = ±2V, unless otherwise noted (Note 2).
SYMBOL
Main Control Loop
VBIAS Chip Bias Voltage Operating Range
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
4.5
2.3
60
60
V
V
V
IN
SENSE Pins Common Mode Range (BOOST
Converter Input Supply Voltage)
V
V
Regulated Output Voltage Range
Regulated Feedback Voltage
Feedback Current
V
60V
1.212
50
V
V
OUT
IN
l
I
= 1.2V (Note 4)
1.188
1.200
5
FB
TH
(Note 4)
nA
%/V
%
Reference Line Voltage Regulation
VBIAS = 6V to 60V
Measured in Servo Loop;
ΔI Voltage = 1.2V to 0.7V
0.002
0.01
0.02
0.1
l
l
Output Voltage Load Regulation
(Note 4)
TH
Measured in Servo Loop;
ΔI Voltage = 1.2V to 2V
–0.01
2
–0.1
%
TH
Error Amplifier Transconductance
I
= 1.2V
mmho
TH
I
Input DC Supply Current (VBIAS Pin)
Pulse-Skipping or Forced Continuous Mode
Sleep Mode
(Note 5)
RUN = 5V; V = 1.25V (No Load)
Q
0.9
28
4
mA
µA
µA
FB
RUN = 5V; V = 1.25V (No Load)
45
10
FB
Shutdown
RUN = 0V
SW Pin Current
V
= 12V; V
= 16.5V;
BOOST
700
µA
SW
FREQ = 0V, Forced Continuous or
Pulse-Skipping Mode
l
l
UVLO
INTV Undervoltage Lockout Thresholds
V
V
Ramping Up
Ramping Down
4.1
3.8
4.3
V
V
CC
INTVCC
INTVCC
3.6
l
V
RUN Pin ON Threshold
RUN Pin Hysteresis
V
Rising
1.18
1.28
100
4.5
0.5
10
1.38
V
mV
µA
RUN
RUN
RUN Pin Hysteresis Current
RUN Pin Current
V
V
V
> 1.28V
RUN
RUN
< 1.28V
µA
Soft-Start Charge Current
Maximum Current Sense Threshold
= GND
7
13
µA
SS
l
l
l
V
V
FB
V
FB
V
FB
= 1.1V, I = INTV
CC
90
68
42
100
75
50
110
82
56
mV
mV
mV
SENSE(MAX)
LIM
LIM
LIM
= 1.1V, I = Float
= 1.1V, I = GND
+
SENSE Pin Current
V
V
C
C
C
C
= 1.1V, I = Float
200
300
1
µA
µA
ns
ns
ns
ns
Ω
FB
LIM
–
SENSE Pin Current
= 1.1V, I = Float
LIM
FB
Top Gate Rise Time
= 3300pF (Note 6)
= 3300pF (Note 6)
= 3300pF (Note 6)
= 3300pF (Note 6)
20
20
LOAD
LOAD
LOAD
LOAD
Top Gate Fall Time
Bottom Gate Rise Time
20
Bottom Gate Fall Time
20
Top Gate Pull-Up Resistance
Top Gate Pull-Down Resistance
Bottom Gate Pull-Up Resistance
Bottom Gate Pull-Down Resistance
1.2
1.2
1.2
1.2
30
Ω
Ω
Ω
Top Gate Off to Bottom Gate On Switch-On
Delay Time
C
C
= 3300pF (Each Driver)
= 3300pF (Each Driver)
ns
LOAD
LOAD
Bottom Gate Off to Top Gate On Switch-On
Delay Time
30
ns
Maximum BG Duty Factor
Minimum BG On-Time
96
%
t
(Note 7)
110
ns
ON(MIN)
3769fa
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For more information www.linear.com/LTC3769
LTC3769
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C, VBIAS = ±2V, unless otherwise noted (Note 2).
SYMBOL
PARAMETER
CONDITIONS
6V < V < 60V, V = 0
EXTVCC
MIN
5.2
5.2
4.5
TYP
MAX
UNITS
INTV Linear Regulator
CC
Internal V Voltage
5.4
0.5
5.4
0.5
4.8
5.6
2
V
%
V
CC
BIAS
INTV Load Regulation
I
= 0mA to 50mA
CC
CC
Internal V Voltage
6V < V
< 13V
EXTVCC
5.6
2
CC
INTV Load Regulation
I
= 0mA to 40mA, V = 8.5V
EXTVCC
%
V
CC
CC
l
EXTV Switchover Voltage
EXTV Ramping Positive
5
CC
CC
EXTV Hysteresis
250
mV
CC
Oscillator and Phase-Locked Loop
Programmable Frequency
R
R
R
= 25k
= 60k
= 100k
105
400
760
kHz
kHz
kHz
FREQ
FREQ
FREQ
335
465
f
Lowest Fixed Frequency
V
V
= 0V
320
488
75
350
535
380
585
850
kHz
kHz
kHz
LOW
FREQ
FREQ
Highest Fixed Frequency
Synchronizable Frequency
= INTV
CC
l
PLLIN/MODE = External Clock
PGOOD Output
PGOOD Voltage Low
PGOOD Leakage Current
PGOOD Trip Level
I
= 2mA
= 5V
0.2
0.4
1
V
PGOOD
V
V
µA
PGOOD
with Respect to Set Regulated Voltage
FB
V
FB
Ramping Negative
–12
8
–10
2.5
–8
12
%
%
Hysteresis
V
Ramping Positive
Hysteresis
10
2.5
%
%
FB
PGOOD Delay
PGOOD Going High to Low
45
µs
V
OV Protection Threshold
V
Ramping Positive, OVMODE = 0V
1.296
1.32
1.344
FB
BOOST Charge Pump
BOOST Charge Pump Available Output
Current
V
= 12V; V
– V = 4.5V;
55
µA
SW
BOOST
SW
FREQ = 0V, Forced Continuous or
Pulse-Skipping Mode
Note ±: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
temperature (T , in °C) and power dissipation (P , in Watts) according to
A D
the formula: T = T + (P • θ ), where θ = 47°C/W for the QFN package
J
A
D
JA
JA
and θ = 38°C/W for the TSSOP package.
JA
Note 3: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. The maximum
rated junction temperature will be exceeded when this protection is active.
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability or permanently damage
the device.
Note 2: The LTC3769 is tested under pulsed load conditions such that
T ≈ T . The LTC3769E is guaranteed to meet specifications from
J
A
0°C to 85°C junction temperature. Specifications over the –40°C to
125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC3769I is guaranteed over the –40°C to 125°C operating junction
temperature range, the LTC3769H is guaranteed over the –40°C to 150°C
operating temperature range and the LTC3769MP is tested and guaranteed
over the full –55°C to 150°C operating junction temperature range. High
junction temperatures degrade operating lifetimes; operating lifetime
is derated for junction temperatures greater than 125°C. Note that the
maximum ambient temperature consistent with these specifications is
determined by specific operating conditions in conjunction with board
layout, the rated package thermal impedance and other environmental
Note 4: The LTC3769 is tested in a feedback loop that servos V to the
FB
output of the error amplifier while maintaining I at the midpoint of the
TH
current limit range.
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency.
Note 6: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 7: See Minimum On-Time Considerations in the Applications
Information section.
factors. The junction temperature (T , in °C) is calculated from the ambient
J
3769fa
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For more information www.linear.com/LTC3769
LTC3769
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C unless otherwise noted.
Efficiency and Power Loss
vs Output Current
Efficiency and Power Loss
vs Output Current
100
90
80
70
60
50
40
10
1
100
90
80
70
60
50
40
30
20
10
0
10
1
EFFICIENCY
0.1
POWER
LOSS
0.1
V
V
= 12V
IN
OUT
0.01
0.001
0.0001
= 24V
FIGURE 8 CIRCUIT
0.01
FCM EFFICIENCY
FCM LOSS
V
V
= 12V
IN
OUT
PULSE-SKIPPING EFFICIENCY
PULSE-SKIPPING LOSS
= 24V
FIGURE 8 CIRCUIT
0.001
0.01
0.1
1
10
0.0001 0.001
0.01
0.1
1
10
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
3769 G01
3769 G02
Load Step
Burst Mode Operation
Load Step
Forced Continuous Mode
Efficiency vs Input Voltage
100
99
I
= 2A
LOAD
LOAD STEP
2A/DIV
LOAD STEP
FIGURE 8 CIRCUIT
2A/DIV
INDUCTOR
CURRENT
5A/DIV
INDUCTOR
CURRENT
5A/DIV
98
97
96
95
94
93
V
= 12V
OUT
V
= 24V
OUT
V
V
OUT
OUT
500mV/DIV
500mV/DIV
3769 G04
3769 G05
V
V
= 12V
200µs/DIV
V
V
= 12V
200µs/DIV
IN
OUT
IN
OUT
= 24V
= 24V
LOAD STEP FROM 200mA TO 2.5A
FIGURE 8 CIRCUIT
LOAD STEP FROM 200mA TO 2.5A
FIGURE 8 CIRCUIT
5
10
15
25
0
20
INPUT VOLTAGE (V)
3769 G03
Load Step
Pulse-Skipping Mode
Inductor Currents at Light Load
Soft Start-Up
LOAD STEP
2A/DIV
INDUCTOR
CURRENT
5A/DIV
FORCED
CONTINUOUS
MODE
Burst Mode
OPERATION
5A/DIV
V
OUT
V
OUT
5V/DIV
PULSE-
SKIPPING MODE
500mV/DIV
3769 G06
3769 G07
V
RUN
V
V
= 12V
200µs/DIV
V
V
LOAD
= 12V
IN
5µs/DIV
IN
OUT
5V/DIV
0V
= 24V
= 24V
OUT
LOAD STEP FROM 200mA TO 2.5A
FIGURE 8 CIRCUIT
I
= 200µA
FIGURE 8 CIRCUIT
3769 G08
V
V
= 12V
20ms/DIV
IN
OUT
= 24V
FIGURE 8 CIRCUIT
3769fa
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For more information www.linear.com/LTC3769
LTC3769
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C unless otherwise noted.
Soft-Start Pull-Up Current
vs Temperature
Regulated Feedback Voltage
vs Temperature
Shutdown Current vs Temperature
11.0
10.5
10.0
9.5
1.212
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
V
IN
= 12V
1.209
1.206
1.203
1.200
1.197
1.194
1.191
1.188
9.0
–35 –10
40 65 90 115 140
15
TEMPERATURE (°C)
–60
–35 –10
40 65 90 115 140
15
TEMPERATURE (°C)
–60
–35 –10
40 65 90 115 140
–60
15
TEMPERATURE (°C)
3769 G09
3769 G10
3769 G11
Shutdown (RUN) Threshold
vs Temperature
Quiescent Current vs Temperature
Shutdown Current vs Input Voltage
50
45
40
35
30
25
20
15
10
1.40
1.35
1.30
1.25
1.20
1.15
1.10
12.5
10.0
7.5
5.0
2.5
0
V
V
= 12V
V
IN
= 12V
IN
FB
= 1.25V
RUN = GND
RUN RISING
RUN FALLING
–35 –10
40 65 90 115 140
–60
15
–35 –10 15 40 65 90 115 140
TEMPERATURE (°C)
10
20 25 30 35 40 45 50 55 60 65
15
–60
5
TEMPERATURE (°C)
INPUT VOLTAGE (V)
3769 G14
3769 G13
3769 G12
Undervoltage Lockout Threshold
vs Temperature
INTVCC Line Regulation
4.4
4.3
4.2
4.1
4.0
3.9
3.8
3.7
3.6
3.5
3.4
5.5
5.4
5.3
5.2
5.1
5.0
4.9
4.8
4.7
4.6
4.5
INTV RISING
CC
INTV FALLING
CC
–35 –10
40 65 90 115 140
–60
15
0
5 10 15 20 25 30 35 40 45 50 55 60 65
INPUT VOLTAGE (V)
TEMPERATURE (°C)
3769 G15
3769 G16
3769fa
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For more information www.linear.com/LTC3769
LTC3769
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C unless otherwise noted.
EXTVCC Switchover and INTVCC
Voltages vs Temperature
Oscillator Frequency
vs Temperature
INTVCC vs INTVCC Load Current
5.50
5.45
5.40
5.35
5.30
5.25
5.20
5.15
5.10
5.05
5.00
6.0
5.8
5.6
5.4
5.2
5.0
4.8
4.6
4.4
4.2
4.0
600
550
500
450
400
350
300
V
= 12V
IN
FREQ = INTV
CC
EXTV = 0V
INTV
CC
CC
EXTV RISING
CC
EXTV = 6V
CC
FREQ = GND
EXTV FALLING
CC
40 60 80 100 120 200
140 160 180
0
20
–35 –10
40 65 90 115 140
–60
15
–35 –10
40 65 90 115 140
–60
15
INTV LOAD CURRENT (mA)
TEMPERATURE (°C)
TEMPERATURE (°C)
CC
3769 G17
3769 G18
3769 G19
Oscillator Frequency
vs Input Voltage
Maximum Current Sense
Threshold vs ITH Voltage
SENSE Pin Input Current
vs Temperature
360
358
356
354
352
350
348
346
344
342
340
120
100
80
260
240
220
200
180
160
140
120
100
80
FREQ = GND
V
LIM
= 12V
SENSE
I
= FLOAT
+
SENSE PIN
PULSE-SKIPPING MODE
Burst Mode
OPERATION
60
40
20
I
= GND
LIM
0
I
= FLOAT
LIM
LIM
I
= INTV
CC
60
40
20
0
–20
–40
–60
FORCED CONTINUOUS MODE
–
SENSE PIN
0.8
VOLTAGE (V)
1.2 1.4
0
0.2 0.4 0.6
1.0
5
10
20 25 30 35 40 45 50 55 60 65
–35 –10
40 65 90 115 140
15
–60
15
INPUT VOLTAGE (V)
I
TH
TEMPERATURE (°C)
3769 G20
3769 G22
3769 G21
SENSE Pin Input Current
SENSE Pin Input Current
vs VSENSE Voltage
vs ITH Voltage
260
260
V
= 12V
+
SENSE
I
= INTV
CC
I
= INTV
CC
SENSE PIN
LIM
LIM
240
220
200
180
160
140
120
100
80
240
220
200
180
160
140
120
100
80
LIM
I
= FLOAT
= GND
I
= FLOAT
= GND
LIM
I
+
SENSE PIN
I
LIM
LIM
60
40
20
0
60
40
20
0
I
I
I
= INTV
CC
= FLOAT
= GND
LIM
LIM
LIM
I
I
I
= INTV
CC
= FLOAT
= GND
LIM
LIM
LIM
–
–
SENSE PIN
SENSE PIN
0
1
I
1.5
2
2.5
3
5
10 15 20 25 30 35 40 45 50 55 60 65
COMMON MODE VOLTAGE (V)
0.5
VOLTAGE (V)
V
TH
SENSE
3769 G23
3769 G24
3769fa
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For more information www.linear.com/LTC3769
LTC3769
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C unless otherwise noted.
Charge Pump Charging Current
Maximum Current Sense
Charge Pump Charging Current
Threshold vs Duty Cycle
vs Operating Frequency
vs Switch Voltage
70
60
50
40
30
20
10
0
120
100
80
60
40
20
0
80
70
60
50
40
30
20
10
0
FREQ = GND
FREQ = INTV
T = –60°C
I
= INTV
CC
LIM
CC
T = –45°C
T = 25°C
I
= FLOAT
= GND
LIM
I
LIM
T = 130°C
T = 155°C
20 30 40 50 60
DUTY CYCLE (%)
100
0
10
70 80 90
5
15
25
35
45
55
65
50 150 250 350 450 550 650 750
OPERATING FREQUENCY (kHz)
SWITCH VOLTAGE (V)
3769 G26
3769 G27
3769 G25
PIN FUNCTIONS (QFN/TSSOP)
VBIAS (Pin ±/Pin ±9): Main Supply Pin. It is normally
FREQ (Pin 7/Pin 3): Frequency Control Pin for the Internal
tied to the input supply V or to the output of the boost
VCO. Connecting the pin to GND forces the VCO to a fixed
IN
converter. A bypass capacitor should be tied between this
pin and the signal ground pin. The operating voltage range
on this pin is 4.5V to 60V (65V abs max).
low frequency of 350kHz. Connecting the pin to INTV
CC
forces the VCO to a fixed high frequency of 535kHz. The
frequency can be programmed from 50kHz to 900kHz
by connecting a resistor from the FREQ pin to GND. The
resistor and an internal 20μA source current create a volt-
age used by the internal oscillator to set the frequency.
Alternatively, this pin can be driven with a DC voltage to
vary the frequency of the internal oscillator.
PGOOD (Pin 2/Pin 20): Power Good Indicator. Open-drain
logic output that is pulled to ground when the output volt-
age is more than 10% away from the regulated output
voltage. To avoid false trips the output voltage must be
outside the range for 45μs before this output is activated.
GND (Pin 8, ±0, 24, Exposed Pad Pin 25/ Pin 4, Exposed
Pad Pin 2±): Ground. All ground pins must be connected
and the exposed pad must be soldered to the PCB for
rated electrical and thermal performance.
ILIM (Pin 3/Pin ±): Current Comparator Sense Voltage
Range Input. This pin is used to set the peak current
sense voltage in the current comparator. Connect this
pin to SGND, leave floating or connect to INTV to set
CC
the peak current sense voltage to 50mV, 75mV or 100mV,
respectively.
PLLIN/MODE (Pin 9/Pin 5): External Synchronization
Input to Phase Detector and Forced Continuous Mode
Input. When an external clock is applied to this pin, the
phase-locked loop will force the rising edge of BG to be
synchronized with the rising edge of the external clock.
When an external clock is applied to this pin, the OVMODE
pinisusedtodeterminehowtheLTC3769operatesatlight
load. When not synchronizing to an external clock, this
INTV (Pins5,22/Pins2, ±7):OutputofInternal5.4VLDO.
CC
Power supply for control circuits and gate drivers. De-
couple pin 22/17 to GND with a minimum 4.7μF low ESR
ceramic capacitor. Connect pin 5/2 to pin 22/17 with a
trace on the printed circuit board.
3769fa
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For more information www.linear.com/LTC3769
LTC3769
PIN FUNCTIONS (QFN/TSSOP)
input determines how the LTC3769 operates at light loads.
Pulling this pin to ground selects Burst Mode operation.
An internal 100k resistor to ground also invokes Burst
Mode operation when the pin is floated. Tying this pin
OVMODE (Pin ±7/Pin ±2): Overvoltage Mode Selection
Input. This pin is used to select how the LTC3769 operates
when the output feedback voltage (V ) is overvoltage
FB
(>110% of its normal regulated point of 1.2V). It is also
used to determine the light-load mode of operation when
the LTC3769 is synchronized to an external clock through
the PLLIN/MODE pin.
to INTV forces continuous inductor current operation.
CC
Tying this pin to a voltage greater than 1.2V and less than
INTV – 1.3V selects pulse-skipping operation. This can
CC
be done by adding a 100k resistor between the PLLIN/
When OVMODE is tied to ground, overvoltage protection
is enabled and the top MOSFET gate (TG) is turned on
continuously until the overvoltage condition is cleared.
When OVMODE is grounded, the LTC3769 operates in
forced continuous mode when synchronized. There is an
internal weak pull-down resistor that pulls the OVMODE
pin to ground when it is left floating.
MODE pin and INTV .
CC
RUN (Pin ±±/Pin 6): Run Control Input. Forcing this pin
below 1.28V shuts down the controller. Forcing this pin
below 0.7V shuts down the entire LTC3769, reducing
quiescent current to approximately 4µA. An external
resistor divider connected to V can set the threshold
IN
for converter operation. Once running, a 4.5µA current is
sourced from the RUN pin allowing the user to program
hysteresis using the resistor values.
When OVMODE is tied to INTV , overvoltage protection
CC
is disabled and TG is not forced on during an overvolt-
age event. Instead, the state of TG is determined by the
mode of operation selected by the PLLIN/MODE pin and
the inductor current. See the Operation section for more
SS (Pin ±2/Pin 7): Output Soft-Start Input. A capacitor to
ground at this pin sets the ramp rate of the output voltage
during start-up.
details. When OVMODE is tied to INTV , the LTC3769
CC
operates in pulse-skipping mode when synchronized.
–
SENSE (Pin±3/Pin8):NegativeCurrentSenseComparator
Input. The (–) input to the current comparator is normally
connected to the negative terminal of a current sense
resistor connected in series with the inductor.
SW (Pin ±8/Pin ±3): Switch Node. Connect to the source
of the synchronous N-channel MOSFET, the drain of the
main N-channel MOSFET and the inductor.
+
SENSE (Pin±4/Pin9):PositiveCurrentSenseComparator
TG (Pin ±9/Pin ±4): Top Gate. Connect to the gate of the
Input. The (+) input to the current comparator is normally
connectedtothepositiveterminalofacurrentsenseresis-
tor. The current sense resistor is normally placed at the
input of the boost controller in series with the inductor.
This pin also supplies power to the current comparator.
Thecommon modevoltagerange onSENSE and SENSE
pins is 2.3V to 60V (65V abs max).
synchronous N-channel MOSFET.
BOOST (Pin 20/Pin ±5): Floating power supply for the
synchronous N-channel MOSFET. Bypass to SW with a
capacitor and supply with a Schottky diode connected
to INTV .
CC
+
–
BG (Pin 2±/Pin ±6): Bottom Gate. Connect to the gate of
the main N-channel MOSFET.
VFB (Pin ±5/Pin ±0): Error Amplifier Feedback Input. This
pin receives the remotely sensed feedback voltage from
an external resistive divider connected across the output.
EXTV (Pin23/Pin±8):ExternalPowerInputtoaninternal
CC
LDOConnectedtoINTV .ThisLDOsuppliesINTV power,
CC
CC
bypassing the internal LDO powered from V
whenever
BIAS
ITH (Pin ±6/Pin ±±): Current Control Threshold and Error
AmplifierCompensationPoint.Thevoltageonthispinsets
the current trip threshold.
EXTV is higher than 4.7V. See EXTV Connection in the
CC
CC
Applications Information section. Do not float or exceed
14V on this pin. Connect to ground if not used.
3769fa
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For more information www.linear.com/LTC3769
LTC3769
BLOCK DIAGRAM
INTV
CC
D
BOOST
TG
B
S
R
Q
C
B
SHDN
SWITCHING
LOGIC
V
OUT
SW
AND
20µA
FREQ
CHARGE
PUMP
INTV
CC
C
OUT
BG
VCO
CLK
+
0.425V
–
SLEEP
PGND
L
–
+
PFD
I
I
REV
CMP
+
+
–
+
–
–
–
2mV
SENSE
SENSE
OVMODE
2.8V
0.7V
R
SENSE
5M
+
PLLIN/
MODE
SLOPE COMP
SENS LO
V
SYNC
DET
IN
C
+
IN
100k
–
2.3V
ILIM
VFB
CURRENT
LIMIT
–
+
+
1.2V
EA
VBIAS
EXTV
SS
SHDN
+
–
CC
OV
1.32V
5.4V
LDO
5.4V
LDO
+
–
C
C
ITH
0.5µA/
4.5µA
EN
EN
3.8V
R
C
C
PGOOD
C2
+
+
–
1.32V
10µA
SS
11V
–
4.8V
INTV
CC
SGND
VFB
+
–
SENS
LO
SHDN
RUN
1.08V
3769 BD
C
SS
3769fa
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For more information www.linear.com/LTC3769
LTC3769
OPERATION
Main Control Loop
NOTE: Do not apply a heavy load to the boost converter for
an extended time while the LTC3769 is in shutdown. The
top MOSFET is turned off during shutdown and the output
load may cause excessive dissipation in the body diode.
The LTC3769 uses a constant-frequency, current mode
step-up architecture. During normal operation, each
external bottom MOSFET is turned on when the clock for
that channel sets the RS latch, and is turned off when the
main current comparator, ICMP, resets the RS latch. The
peak inductor current at which ICMP trips and resets the
latch is controlled by the voltage on the ITH pin, which is
the output of the error amplifier EA. The error amplifier
compares the output voltage feedback signal at the VFB
pin (which is generated with an external resistor divider
The RUN pin may be externally pulled up or driven directly
by logic. When driving the RUN pin with a low impedance
source, do not exceed the absolute maximum rating of
8V. The RUN pin has an internal 11V voltage clamp that
allows the RUN pin to be connected through a resistor to
a higher voltage (for example, V ), as long as the maxi-
IN
mum current into the RUN pin does not exceed 100μA.
connected across the output voltage, V , to ground), to
OUT
An external resistor divider connected to V can set the
IN
theinternal1.200Vreferencevoltage. Inaboostconverter,
the required inductor current is determined by the load
threshold for converter operation. Once running, a 4.5μA
current is sourced from the RUN pin allowing the user to
program hysteresis using the resistor values.
current, V and V . When the load current increases,
IN
OUT
it causes a slight decrease in VFB relative to the reference,
which causes the EA to increase the ITH voltage until the
averageinductorcurrentineachchannelmatchesthenew
requirement based on the new load current.
The start-up of the controller’s output voltage V
is
OUT
controlled by the voltage on the SS pin. When the voltage
on the SS pin is less than the 1.2V internal reference, the
LTC3769 regulates the VFB voltage to the SS pin voltage
instead of the 1.2V reference. This allows the SS pin to
be used to program a soft-start by connecting an external
capacitor from the SS pin to SGND. An internal 10μA
pull-up current charges this capacitor creating a voltage
ramp on the SS pin. As the SS voltage rises linearly from
After the bottom MOSFET is turned off each cycle, the
top MOSFET is turned on until either the inductor current
starts to reverse, as indicated by the current comparator,
I
, or the beginning of the next clock cycle.
REV
INTV /EXTV Power
CC
CC
0V to 1.2V (and beyond up to INTV ), the output voltage
CC
Power for the top and bottom MOSFET drivers and most
rises smoothly to its final value.
other internal circuitry is derived from the INTV pin.
CC
When the EXTV pin is tied to a voltage less than 4.8V,
CC
Light Load Current Operation—Burst Mode Operation,
Pulse-Skipping or Continuous Conduction
(PLLIN/MODE Pin)
the VBIAS LDO (low dropout linear regulator) supplies
5.4V from VBIAS to INTV . If EXTV is taken above
CC
CC
4.8V, the VBIAS LDO is turned off and an EXTV LDO is
CC
TheLTC3769canbeenabledtoenterhighefficiencyBurst
Mode operation, constant-frequency, pulse-skipping
mode or forced continuous conduction mode at low
load currents. To select Burst Mode operation, tie the
PLLIN/MODE pin to ground (e.g., SGND). To select
forced continuous operation, tie the PLLIN/MODE pin to
turned on. Once enabled, the EXTV LDO supplies 5.4V
CC
from EXTV to INTV . Using the EXTV pin allows the
CC
CC
CC
INTV power to be derived from an external source, thus
CC
removing the power dissipation of the VBIAS LDO.
Shutdown and Start-Up (RUN and SS Pins)
INTV . To select pulse-skipping mode, tie the PLLIN/
MODE pin to a DC voltage greater than 1.2V and less
CC
The LTC3769 can be shut down using the RUN pin. Pulling
this pin below 1.28V shuts down the main control loops.
Pulling this pin below 0.7V disables the controller and
than INTV – 1.3V.
CC
most internal circuits, including the INTV LDOs. In this
When the controller is enabled for Burst Mode opera-
tion, the minimum peak current in the inductor is set to
CC
state, the LTC3769 draws only 4μA of quiescent current.
3769fa
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For more information www.linear.com/LTC3769
LTC3769
OPERATION
approximately 30% of the maximum sense voltage even
though the voltage on the ITH pin indicates a lower value.
If the average inductor current is higher than the required
current, the error amplifier EA will decrease the voltage
on the ITH pin. When the ITH voltage drops below 0.425V,
the internal sleep signal goes high (enabling sleep mode)
and both external MOSFETs are turned off.
operation). This mode, like forced continuous operation,
exhibits low output ripple as well as low audio noise and
reduced RF interference as compared to Burst Mode
operation. It provides higher low current efficiency than
forced continuous mode, but not nearly as high as Burst
Mode operation.
Frequency Selection and Phase-Locked Loop
(FREQ and PLLIN/MODE Pins)
In sleep mode much of the internal circuitry is turned off
and the LTC3769 draws only 28μA of quiescent current.
In sleep mode the load current is supplied by the output
capacitor. Astheoutputvoltagedecreases, theEA’s output
beginstorise. Whentheoutputvoltagedropsenough, the
sleep signal goes low and the controller resumes normal
operation by turning on the bottom external MOSFET on
the next cycle of the internal oscillator.
Theselectionofswitchingfrequencyisatrade-offbetween
efficiency and component size. Low frequency opera-
tion increases efficiency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage.
The switching frequency of the LTC3769’s controllers can
be selected using the FREQ pin.
When the controller is enabled for Burst Mode operation,
the inductor current is not allowed to reverse. The reverse
currentcomparator(I )turnsoffthetopexternalMOSFET
just before the inductor current reaches zero, preventing
it from reversing and going negative. Thus, the controller
operates in discontinuous current operation.
If the PLLIN/MODE pin is not being driven by an external
clock source, the FREQ pin can be tied to SGND, tied to
REV
INTV ,orprogrammedthroughanexternalresistor.Tying
CC
FREQ to SGND selects 350kHz while tying FREQ to INTV
CC
selects535kHz.PlacingaresistorbetweenFREQandSGND
allows the frequency to be programmed between 50kHz
and 900kHz, as shown in Figure 7.
In forced continuous operation or when clocked by an
external clock source to use the phase-locked loop (see
theFrequencySelectionandPhase-LockedLoopsection),
the inductor current is allowed to reverse at light loads or
under large transient conditions. The peak inductor cur-
rent is determined by the voltage on the ITH pin, just as
in normal operation. In this mode, the efficiency at light
loads is lower than in Burst Mode operation. However,
continuous operation has the advantages of lower output
voltage ripple and less interference to audio circuitry, as
it maintains constant-frequency operation independent
of load current.
A phase-locked loop (PLL) is available on the LTC3769
to synchronize the internal oscillator to an external clock
source that is connected to the PLLIN/MODE pin. The
LTC3769’s phase detector adjusts the voltage (through an
internallowpass filter)ofthe VCO inputso thatthe turn-on
of the external bottom MOSFET is 180° out-of-phase to
the rising edge of the external clock source. When syn-
chronized, the LTC3769 will operate in forced continuous
mode of operation if the OVMODE pin is grounded. If the
OVMODE pin is tied to INTV , the LTC3769 will operate
CC
in pulse-skipping mode of operation when synchronized.
WhenthePLLIN/MODEpinisconnectedforpulse-skipping
mode,theLTC3769operatesinPWMpulse-skippingmode
at light loads. In this mode, constant-frequency operation
is maintained down to approximately 1% of designed
maximum output current. At very light loads, the current
comparator ICMP may remain tripped for several cycles
and force the external bottom MOSFET to stay off for
the same number of cycles (i.e., skipping pulses). The
inductor current is not allowed to reverse (discontinuous
The VCO input voltage is prebiased to the operating fre-
quency set by the FREQ pin before the external clock is
applied. If prebiased near the external clock frequency,
the PLL loop only needs to make slight changes to the
VCO input in order to synchronize the rising edge of the
external clock’s to the rising edge of BG1. The ability to
prebias the loop filter allows the PLL to lock-in rapidly
without deviating far from the desired frequency.
3769fa
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For more information www.linear.com/LTC3769
LTC3769
OPERATION
The typical capture range of the LTC3769’s PLL is from
approximately 55kHz to 1MHz, and is guaranteed to lock
to an external clock source whose frequency is between
75kHz and 850kHz.
Power Good
The PGOOD pin is connected to an open drain of an
internal N-channel MOSFET. The MOSFET turns on and
pulls the PGOOD pin low when the VFB pin voltage is not
within 10% of the 1.2V reference voltage. The PGOOD
pin is also pulled low when the corresponding RUN pin
is low (shut down). When the VFB pin voltage is within
the 10% requirement, the MOSFET is turned off and the
pin is allowed to be pulled up by an external resistor to a
source of up to 6V (abs max).
The typical input clock thresholds on the PLLIN/MODE
pin are 1.6V (rising) and 1.2V (falling). The recommended
maximumamplitudeforlowlevelandminimumamplitude
forhighlevelofexternalclockare0Vand2.5V,respectively.
Operation When V > Regulated V
IN
OUT
WhenV risesabovetheregulatedV voltage,theboost
IN
OUT
Overvoltage Mode Selection
controller can behave differently depending on the mode,
The OVMODE pin is used to select how the LTC3769
operates during an overvoltage event, defined as when
the output feedback voltage (V ) is greater than 110%
of its normal regulated point of 1.2V. It is also used to
determine the light-load mode of operation when the
LTC3769 is synchronized to an external clock through the
PLLIN/MODE pin.
inductor current and V voltage. In forced continuous
IN
mode, the control loop works to keep the top MOSFET on
FB
continuouslyonceV risesaboveV .Theinternalcharge
IN
OUT
pump delivers current to the boost capacitor to maintain
a sufficiently high TG voltage. The amount of current the
charge pump can deliver is characterized by two curves
in the Typical Performance Characteristics section.
The OVMODE pin is a logic input that should normally be
In pulse-skipping mode, if V is between 100% and
IN
tied to INTV or grounded. Alternatively, the pin can be
CC
110% of the regulated V
voltage, TG turns on if the
OUT
left floating, which allow a weak internal resistor to pull
it down to ground.
inductor current rises above a certain threshold and turns
off if the inductor current falls below this threshold. This
threshold current is set to approximately 6%, 4% or
3% of the maximum ILIM current when the ILIM pin is
OVMODE = INTV : An overvoltage event causes the
CC
error amplifier to pull the ITH pin low. In Burst Mode
operation, this causes the LTC3769 to go to sleep and TG
and BG are held off. In pulse-skipping mode, BG is held
off and TG will turn on if the inductor current is positive.
In forced continuous mode, TG (and BG) will switch on
and off as the LTC3769 will regulate the inductor current
to a negative peak value (corresponding to ITH = 0V) to
discharge the output.
grounded, floating or tied to INTV , respectively. If the
CC
controller is programmed to Burst Mode operation under
this same V window, then TG remains off regardless of
IN
the inductor current.
If the OVMODE pin is grounded and V rises above 110%
IN
of the regulated V
voltage in any mode, the controller
OUT
turns on TG regardless of the inductor current. In Burst
Mode operation, however, the internal charge pump turns
off if the chip is asleep. With the charge pump off, there
would be nothing to prevent the boost capacitor from
discharging, resultinginaninsufficientTGvoltageneeded
to keep the top MOSFET completely on. To prevent exces-
sive power dissipation across the body diode of the top
MOSFET in this situation, the chip can be switched over
to forced continuous mode to enable the charge pump;
a Schottky diode can also be placed in parallel with the
top MOSFET.
When OVMODE is tied to INTV , the LTC3769 operates
CC
in pulse-skipping mode when synchronized.
In summary, with OVMODE = INTV , the inductor cur-
CC
rent is not allowed to go negative (reverse from output to
input) except in forced continuous mode, where it does
reversecurrentbutinacontrolledmannerwitharegulated
negative peak current. OVMODE should be tied to INTV
CC
in applications where the output voltage may sometimes
be above its regulation point (for example, if the output
3769fa
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For more information www.linear.com/LTC3769
LTC3769
OPERATION
is a battery or if there are other power supplies driving
the output) and no reverse current flow from output to
input is desired.
Operation at Low SENSE Pin Common Mode Voltage
ThecurrentcomparatorintheLTC3769ispowereddirectly
+
from the SENSE pin. This enables the common mode
+
–
OVMODE Grounded or Left Floating: When OVMODE is
groundedorleftfloating,overvoltageprotectionisenabled
and TG is turned on continuously until the overvoltage
condition is cleared, regardless of whether Burst Mode
operation, pulse-skipping mode, or forced continuous
mode is selected by the PLLIN/MODE pin. This can cause
large negative inductor currents to flow from the output
to the input if the output voltage is higher than the input
voltage.
voltage of the SENSE and SENSE pins to operate at as
low as 2.3V, which is below the UVLO threshold. Figure 10
showsatypicalapplicationinwhichthecontroller’sVBIAS
is powered from V
while the V supply can go as low
OUT
IN
+
as 2.3V. If the voltage on SENSE drops below 2.3V, the
SS pin will be held low. When the SENSE voltage returns
to the normal operating range, the SS pin will be released,
initiating a new soft-start cycle.
BOOST Supply Refresh and Internal Charge Pump
Note however that in Burst Mode operation, the LTC3769
isinsleepduringanovervoltagecondition, whichdisables
theinternaloscillatorandBOOST-SWchargepump.Sothe
BOOST-SW voltage may discharge (due to leakage) if the
overvoltage conditions persists indefinitely. If BOOST-SW
discharges, then by definition TG would turn off.
ThetopMOSFETdriverisbiasedfromthefloatingbootstrap
capacitor, C , which normally recharges during each cycle
B
through an external diode when the bottom MOSFET turns
on. There are two considerations for keeping the BOOST
supply at the required bias level. During start-up, if the
bottom MOSFET is not turned on within 200μs after UVLO
goes low, the bottom MOSFET will be forced to turn on for
~400ns. This forced refresh generates enough BOOST-SW
voltageto allow the top MOSFET ready to be fullyenhanced
instead of waiting for the initial few cycles to charge up.
Thereisalsoaninternalchargepumpthatkeepstherequired
bias on BOOST. The charge pump always operates in both
forcedcontinuousmodeandpulse-skippingmode.InBurst
Modeoperation,thechargepumpisturnedoffduringsleep
and enabled when the chip wakes up. The internal charge
pump can normally supply a charging current of 55μA.
When OVMODE is grounded or left floating, the LTC3769
operates in forced continuous mode when synchronized.
OVMODE should be tied to ground or left floating in cir-
cuits, such as automotive applications, where the input
voltage can often be above the regulated output voltage
and it is desirable to turn on TG to “pass through” the
input voltage to the output.
3769fa
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For more information www.linear.com/LTC3769
LTC3769
APPLICATIONS INFORMATION
+
TheTypicalApplicationonthefirstpageisabasicLTC3769
application circuit. The LTC3769 can be configured to use
either inductor DCR (DC resistance) sensing or a discrete
The SENSE pin also provides power to the current com-
parator. It draws ~200μA during normal operation. There
is a small base current of less than 1μA that flows into
–
–
sense resistor (R
) for current sensing. The choice
SENSE
the SENSE pin. The high impedance SENSE input to the
current comparators allows accurate DCR sensing.
between the two current sensing schemes is largely a
design trade-off between cost, power consumption and
accuracy. DCR sensing is becoming popular because it
does not require current sensing resistors and is more
power-efficient, especially in high current applications.
However, current sensing resistors provide the most
accurate current limits for the controller. Other external
component selection is driven by the load requirement,
Filter components mutual to the sense lines should be
placed close to the LTC3769, and the sense lines should
run close together to a Kelvin connection underneath the
current sense element (shown in Figure 1). Sensing cur-
rent elsewhere can effectively add parasitic inductance
and capacitance to the current sense element, degrading
the information at the sense terminals and making the
programmed current limit unpredictable. If DCR sensing
is used (Figure 2b), resistor R1 should be placed close to
the switching node, to prevent noise from coupling into
sensitive small-signal nodes.
and begins with the selection of R
(if R
is used)
SENSE
SENSE
andinductorvalue.Next,thepowerMOSFETsareselected.
Finally, input and output capacitors are selected.
+
–
SENSE and SENSE Pins
+
–
TO SENSE FILTER,
The SENSE and SENSE pins are the inputs to the cur-
rent comparators. The common mode input voltage range
of the current comparators is 2.3V to 60V. The current
sense resistor is normally placed at the input of the boost
controller in series with the inductor.
NEXT TO THE CONTROLLER
V
IN
INDUCTOR OR R
3769 F01
SENSE
Figure ±. Sense Lines Placement with
Inductor or Sense Resistor
VBIAS
V
IN
VBIAS
V
IN
+
+
SENSE
SENSE
C1
R2
(OPTIONAL)
DCR
L
–
–
SENSE
INTV
SENSE
INTV
CC
CC
INDUCTOR
R1
LTC3769
LTC3769
BOOST
BOOST
TG
TG
V
OUT
SW
BG
V
SW
BG
OUT
GND
GND
3769 F02b
3769 F02a
L
DCR
R2
R1 + R2
||
PLACE C1 NEAR SENSE PINS (R1 R2) • C1 =
R
= DCR •
SENSE(EQ)
(2a) Using a Resistor to Sense Current
(2b) Using the Inductor DCR to Sense Current
Figure 2. Two Different Methods of Sensing Current
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Sense Resistor Current Sensing
If the external R1||R2 • C1 time constant is chosen to be
exactly equal to the L/DCR time constant, the voltage drop
across the external capacitor is equal to the drop across
theinductorDCRmultipliedbyR2/(R1+R2).R2scalesthe
voltage across the sense terminals for applications where
the DCR is greater than the target sense resistor value.
To properly dimension the external filter components, the
DCR of the inductor must be known. It can be measured
using a good RLC meter, but the DCR tolerance is not
always the same and varies with temperature. Consult
the manufacturers’ data sheets for detailed information.
A typical sensing circuit using a discrete resistor is shown
in Figure 2a. R
output current.
is chosen based on the required
SENSE
The current comparator has a maximum threshold
V
. When the ILIM pin is grounded, floating or
CC
SENSE(MAX)
tied to INTV , the maximum threshold is set to 50mV,
75mV or 100mV, respectively. The current comparator
threshold sets the peak of the inductor current, yielding
a maximum average inductor current, I
, equal to the
MAX
peak value less half the peak-to-peak ripple current, ΔI .
L
Using the inductor ripple current value from the induct-
or value calculation section, the target sense resistor
value is:
To calculate the sense resistor value, use the equation:
VSENSE(MAX)
RSENSE
=
ΔIL
VSENSE(MAX)
IMAX
+
RSENSE(EQUIV)
=
2
ΔIL
IMAX
+
2
The actual value of I
depends on the required output
MAX
current I
and can be calculated using:
OUT(MAX)
To ensure that the application will deliver full load current
over the full operating temperature range, choose the
minimum value for the maximum current sense threshold
VOUT
IMAX = IOUT(MAX)
•
V
(V
).
IN
SENSE(MAX)
Next, determine the DCR of the inductor. Where provided,
use the manufacturer’s maximum value, usually given at
20°C. Increase this value to account for the temperature
coefficient of resistance, which is approximately 0.4%/°C.
Aconservativevalueforthemaximuminductortemperature
When using the controller in low V and very high voltage
IN
output applications, the maximum inductor current and
correspondingly the maximum output current level will
be reduced due to the internal compensation required to
meet stability criterion for boost regulators operating at
greater than 50% duty factor. A curve is provided in the
Typical Performance Characteristics section to estimate
this reduction in peak inductor current level depending
upon the operating duty factor.
(T
) is 100°C.
L(MAX)
To scale the maximum inductor DCR to the desired sense
resistor value, use the divider ratio:
RSENSE(EQUIV)
RD =
Inductor DCR Sensing
DCRMAX at TL(MAX)
For applications requiring the highest possible efficiency
at high load currents, the LTC3769 is capable of sensing
the voltage drop across the inductor DCR, as shown in
Figure 2b. The DCR of the inductor can be less than 1mΩ
for high current inductors. In a high current application
requiring such an inductor, conduction loss through a
sense resistor could reduce the efficiency by a few percent
compared to DCR sensing.
C1 is usually selected to be in the range of 0.1μF to 0.47μF.
ThisforcesR1||R2toaround2k, reducingerrorthatmight
–
have been caused by the SENSE pin’s 1μA current.
The equivalent resistance R1|| R2 is scaled to the room
temperature inductance and maximum DCR:
L
R1||R2=
(DCR at 20°C)•C1
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The sense resistor values are:
The inductor value also has secondary effects. The tran-
sition to Burst Mode operation begins when the average
inductor current required results in a peak current below
R1||R2
RD
R1•RD
1−RD
R1=
; R2 =
25% of the current limit determined by R
. Lower
SENSE
inductor values (higher ΔI ) will cause this to occur at
L
The maximum power loss in R1 is related to duty cycle,
and will occur in continuous mode at V = 1/2V
lower load currents, which can cause a dip in efficiency in
the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to decrease. Once the value of L is known, an
inductor with low DCR and low core losses should be
selected.
:
OUT
IN
(VOUT − V )•V
IN
IN
P
=
LOSS_R1
R1
Ensure that R1 has a power rating higher than this value.
If high efficiency is necessary at light loads, consider this
power loss when deciding whether to use DCR sensing or
sense resistors. Light load power loss can be modestly
higher with a DCR network than with a sense resistor, due
totheextraswitchinglossesincurredthroughR1.However,
DCR sensing eliminates a sense resistor, reduces conduc-
tion losses and provides higher efficiency at heavy loads.
Peak efficiency is about the same with either method.
Power MOSFET Selection
Two external power MOSFETs must be selected for the
LTC3769: one N-channel MOSFET for the bottom (main)
switch, and one N-channel MOSFET for the top (synchro-
nous) switch.
The peak-to-peak gate drive levels are set by the INTV
CC
voltage. This voltage is typically 5.4V during start-up
Inductor Value Calculation
(see EXTV pin connection). Consequently, logic-level
CC
The operating frequency and inductor selection are in-
terrelated in that higher operating frequencies allow the
use of smaller inductor and capacitor values. Why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because
of MOSFET gate charge and switching losses. Also, at
higher frequency the duty cycle of body diode conduction
is higher, which results in lower efficiency. In addition to
this basic trade-off, the effect of inductor value on ripple
currentandlowcurrentoperationmustalsobeconsidered.
threshold MOSFETs must be used in most applications.
Pay close attention to the BV
specification for the
DSS
MOSFETs as well; many of the logic level MOSFETs are
limited to 30V or less.
Selection criteria for the power MOSFETs include the
on-resistance R
, Miller capacitance C
DS(ON)
, input
MILLER
voltage and maximum output current. Miller capacitance,
C
, can be approximated from the gate charge curve
MILLER
usually provided on the MOSFET manufacturer’s data
sheet. C is equal to the increase in gate charge
MILLER
along the horizontal axis while the curve is approximately
flat divided by the specified change in VDS. This result
is then multiplied by the ratio of the application applied
VDS to the gate charge curve specified VDS. When the IC
is operating in continuous mode, the duty cycles for the
top and bottom MOSFETs are given by:
The inductor value has a direct effect on ripple current.
The inductor ripple current ΔI decreases with higher
L
inductance or frequency and increases with higher V :
IN
⎛
⎞
V
f•L
V
IN
VOUT
IN
ΔIL =
1−
⎜
⎟
⎝
⎠
VOUT − V
IN
Accepting larger values of ΔI allows the use of low
L
Main SwitchDuty Cycle=
VOUT
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
V
VOUT
IN
Synchronous SwitchDuty Cycle=
setting ripple current is ΔI = 0.3(I
). The maximum
L
MAX
ΔI occurs at V = 1/2V .
L
IN
OUT
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If the maximum output current is I
the MOSFET
Although ceramic capacitors can be relatively tolerant of
overvoltage conditions, aluminum electrolytic capacitors
are not. Be sure to characterize the input voltage for any
possible overvoltage transients that could apply excess
stress to the input capacitors.
OUT(MAX)
power dissipation at maximum output current is given by:
(VOUT V )V
2
IN
OUT
PMAIN
=
•
• 1+
(
IOUT(MAX)
)
V2
IN
IOUT(MAX)
ThevalueofC isafunctionofthesourceimpedance, and
3
IN
• RDS(ON) +k •VOUT
• CMILLER • f
•
ingeneral,thehigherthesourceimpedance,thehigherthe
required input capacitance. The required amount of input
capacitance is also greatly affected by the duty cycle. High
output current applications that also experience high duty
cycles can place great demands on the input supply, both
in terms of DC current and ripple current.
V
IN
V
IN
PSYNC
=
• IO2UT(MAX) • 1+ •R
DS(ON)
(
)
VOUT
Inaboostconverter,theoutputhasadiscontinuouscurrent,
where d is the temperature dependency of R
. The
DS(ON)
so C
must be capable of reducing the output voltage
OUT
constant k, which accounts for the loss caused by reverse
recoverycurrent,isinverselyproportionaltothegatedrive
current and has an empirical value of 1.7.
ripple.TheeffectsofESR(equivalentseriesresistance)and
the bulk capacitance must be considered when choosing
the right capacitor for a given output ripple voltage. The
steady ripple voltage due to charging and discharging
the bulk capacitance in a single phase boost converter
is given by:
2
BothMOSFETshaveI RlosseswhilethebottomN-channel
equation includes an additional term for transition losses,
which are highest at low input voltages. For high V the
IN
high current efficiency generally improves with larger
IOUT(MAX) •(VOUT − V
)
MOSFETs, while for low V the transition losses rapidly
IN
IN(MIN)
VRIPPLE
=
V
increasetothepointthattheuseofahigherR
device
DS(ON)
COUT •VOUT •f
withlowerC
actuallyprovideshigherefficiency.The
MILLER
synchronous MOSFET losses are greatest at high input
voltage when the bottom switch duty factor is low or dur-
ing overvoltage when the synchronous switch is on close
to 100% of the period.
where C
is the output filter capacitor.
OUT
The steady ripple due to the voltage drop across the ESR
is given by:
ΔV
= I
• ESR
The term (1+ d) is generally given for a MOSFET in the
ESR
L(MAX)
form of a normalized R
vs Temperature curve, but
DS(ON)
Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, special polymer, aluminum electrolytic and
ceramic capacitors are all available in surface mount
packages. Ceramic capacitors have excellent low ESR
characteristics but can have a high voltage coefficient.
Capacitors are now available with low ESR and high ripple
current ratings (e.g., OS-CON and POSCAP).
d = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
C and C
IN
Selection
OUT
The input ripple current in a boost converter is relatively
low(comparedwiththeoutputripplecurrent),becausethis
currentiscontinuous.TheinputcapacitorC voltagerating
IN
should comfortably exceed the maximum input voltage.
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Setting Output Voltage
LTC3769
SS
The LTC3769 output voltage is set by an external feedback
resistordividercarefullyplacedacrosstheoutput,asshown
in Figure 3. The regulated output voltage is determined by:
C
SS
GND
3769 F04
⎛
⎞
RB
RA
V
OUT =1.2V 1+
⎜
⎟
Figure 4. Using the SS Pin to Program Soft-Start
⎝
⎠
Great care should be taken to route the VFB line away
from noise sources, such as the inductor or the SW line.
Also place the feedback resistor divider close to the VFB
pin and keep the VFB node as small as possible to avoid
noise pickup.
INTV Regulators
CC
The LTC3769 features two separate internal P-channel
low dropout linear regulators (LDO) that supply power at
the INTV pin from either the VBIAS supply pin or the
CC
EXTV pin depending on the connection of the EXTV
CC
CC
V
pin. INTV powers the gate drivers and much of the
OUT
CC
LTC3769’s internal circuitry. The VBIAS LDO and the
R
B
A
LTC3769
VFB
EXTV LDO regulate INTV to 5.4V. Each of these can
CC
CC
supplyatleast50mAandmustbebypassedtogroundwith
a minimum of a 4.7μF ceramic capacitor. Good bypassing
is needed to supply the high transient currents required
by the MOSFET gate drivers and to prevent interaction
between the channels.
R
3769 F03
Figure 3. Setting Output Voltage
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maxi-
mum junction temperature rating for the LTC3769 to be
Soft-Start (SS Pin)
The start-up of V
SS pin. When the voltage on the SS pin is less than the
internal 1.2V reference, the LTC3769 regulates the VFB
pin voltage to the voltage on the SS pin instead of 1.2V.
is controlled by the voltage on the
OUT
exceeded. The INTV current, which is dominated by the
CC
gate charge current, may be supplied by either the VBIAS
LDO or the EXTV LDO. When the voltage on the EXTV
CC
CC
pin is less than 4.8V, the VBIAS LDO is enabled. In this
Soft-startisenabledbysimplyconnectingacapacitorfrom
the SS pin to ground, as shown in Figure 4. An internal
10μA current source charges the capacitor, providing a
linear ramping voltage at the SS pin. The LTC3769 will
case, power dissipation for the IC is highest and is equal
to VBIAS • I
. The gate charge current is dependent
INTVCC
on operating frequency, as discussed in the Efficiency
Considerations section. The junction temperature can be
estimated by using the equations given in Note 3 of the
Electrical Characteristics. For example, at 70°C ambient
regulate the VFB pin (and hence, V ) according to the
OUT
voltage on the SS pin, allowing V
to rise smoothly
OUT
from V to its final regulated value. The total soft-start
IN
temperature, theLTC3769INTV currentislimitedtoless
CC
time will be approximately:
than 19mA in the QFN package from a 60V VBIAS supply
1.2V
10µA
when not using the EXTV supply:
CC
t
SS =CSS •
T = 70°C + (19mA)(60V)(47°C/W) = 125°C
J
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In the TSSOP package, the INTV current is limited to
Topside MOSFET Driver Supply (C , D )
B B
CC
less than 24mA from a 60V supply when not using the
An external bootstrap capacitor C connected to the
B
EXTV supply:
CC
BOOST pin supplies the gate drive voltage for the topside
T = 70°C + (24mA)(60V)(38°C/W) = 125°C
J
MOSFET. Capacitor C in the Block Diagram is charged
B
though external diode D from INTV when the SW pin
B
CC
To prevent the maximum junction temperature from being
exceeded, the input supply current must be checked while
operating in continuous conduction mode (PLLIN/MODE
is low. When the topside MOSFET is to be turned on, the
driver places the C voltage across the gate and source
B
of the desired MOSFET. This enhances the MOSFET and
= INTV ) at maximum V .
CC
IN
turns on the topside switch. The switch node voltage, SW,
When the voltage applied to EXTV rises above 4.8V, the
rises to V
and the BOOST pin follows. With the topside
CC
OUT
V LDO is turned off and the EXTV LDO is enabled. The
MOSFETon, theboostvoltageisabovetheoutputvoltage:
IN
CC
EXTV LDO remains on as long as the voltage applied to
V
= V
+ V
. The value of the boost capacitor
CC
BOOST
OUT
INTVCC
EXTV remains above 4.55V. The EXTV LDO attempts
C needstobe100timesthatofthetotalinputcapacitance
CC
CC
B
to regulate the INTV voltage to 5.4V, so while EXTV
of the topside MOSFET(s). The reverse breakdown of the
CC
CC
CC
CC
is less than 5.4V, the LDO is in dropout and the INTV
external diode D must be greater than V
.
B
OUT(MAX)
voltage is approximately equal to EXTV . When EXTV
CC
The external diode D can be a Schottky diode or silicon
B
is greater than 5.4V, up to an absolute maximum of 14V,
diode,butineithercaseitshouldhavelowleakageandfast
recovery. Paycloseattentiontothereverseleakageathigh
temperatures, where it generally increases substantially.
INTV is regulated to 5.4V.
CC
Significant thermal gains can be realized by powering
INTV from an external supply. Tying the EXTV pin
CC
CC
The topside MOSFET driver includes an internal charge
pumpthatdeliverscurrenttothebootstrapcapacitorfrom
the BOOST pin. This charge current maintains the bias
voltage required to keep the top MOSFET on continuously
during dropout/overvoltage conditions. The Schottky/
silicon diode selected for the topside driver should have a
reverse leakage less than the available output current the
charge pump can supply. Curves displaying the available
charge pump current under different operating conditions
can be found in the Typical Performance Characteristics
section.
to a 5V supply reduces the junction temperature in the
previous example from 125°C to 75°C in a QFN package:
T = 70°C + (19mA)(5V)(47°C/W) = 75°C
J
and from 125°C to 75°C in the TSSOP package:
T = 70°C + (24mA)(5V)(38°C/W) = 75°C
J
The following list summarizes possible connections for
EXTV :
CC
EXTV Grounded.ThiswillcauseINTV tobepowered
CC
CC
fromtheinternal5.4Vregulatorresultinginanefficiency
penalty at high V voltages.
A leaky diode D in the boost converter can not only
B
BIAS
prevent the top MOSFET from fully turning on but it can
EXTV Connected to an External Supply. If an external
CC
also completely discharge the bootstrap capacitor C and
B
supply is available in the 5V to 14V range, it may be
create a current path from the input voltage to the BOOST
used to provide power. Ensure that EXTV is always
CC
pin to INTV . This can cause INTV to rise if the diode
CC
CC
lower than or equal to VBIAS.
leakage exceeds the current consumption on INTV .
CC
This is particularly a concern in Burst Mode operation
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where the load on INTV can be very small. The external
an amount of time corresponding to the phase difference.
The voltage at the VCO input is adjusted until the phase
and frequency of the internal and external oscillators are
identical. At the stable operating point, the phase detector
output is high impedance and the internal filter capacitor,
CC
Schottky or silicon diode should be carefully chosen such
that INTV never gets charged up much higher than its
CC
normal regulation voltage.
Fault Conditions: Overtemperature Protection
C
, holds the voltage at the VCO input.
LP
At higher temperatures, or in cases where the internal
power dissipation causes excessive self heating on-chip
1000
900
800
700
600
500
400
300
200
100
(such as an INTV short to ground), the overtemperature
CC
shutdown circuitry will shut down the LTC3769. When the
junction temperature exceeds approximately 170°C, the
overtemperaturecircuitrydisablestheINTV LDO,causing
CC
the INTV supply to collapse and effectively shut down
CC
the entire LTC3769 chip. Once the junction temperature
dropsbacktoapproximately155°C, theINTV LDOturns
CC
back on. Long term overstress (T > 125°C) should be
J
avoided as it can degrade the performance or shorten
0
15 25 35 45 55 65 75 85 95 105 115 125
the life of the part.
FREQ PIN RESISTOR (kΩ)
3769 F05
Since the shutdown may occur at full load, beware that
the load current will result in high power dissipation in the
body diodes of the top MOSFETs. In this case, the PGOOD
output may be used to turn the system load off.
Figure 5. Relationship Between Oscillator
Frequency and Resistor Value at the FREQ Pin
Typically,theexternalclock(onthePLLIN/MODEpin)input
highthresholdis1.6V,whiletheinputlowthresholdis1.2V.
Phase-Locked Loop and Frequency Synchronization
The LTC3769 has an internal phase-locked loop (PLL)
comprised of a phase frequency detector, a lowpass filter
and a voltage-controlled oscillator (VCO). This allows
the turn-on of the bottom MOSFET to be locked signal
applied to 180 degrees out-of-phase to the rising edge of
the externalclock. The phase detectorisan edge-sensitive
digitaltypethatprovideszerodegreesphaseshiftbetween
the external and internal oscillators. This type of phase
detector does not exhibit false lock to harmonics of the
external clock.
Note that the LTC3769 can only be synchronized to an
external clock whose frequency is within range of the
LTC3769’s internal VCO, which is nominally 55kHz to
1MHz.Thisisguaranteedtobebetween75kHzand850kHz.
RapidphaselockingcanbeachievedbyusingtheFREQpin
to set a free-running frequency near the desired synchro-
nization frequency. The VCO’s input voltage is prebiased
at a frequency corresponding to the frequency set by the
FREQ pin. Once prebiased, the PLL only needs to adjust
the frequency slightly to achieve phase lock and synchro-
nization. Although it is not required that the free-running
frequency be near external clock frequency, doing so will
prevent the operating frequency from passing through a
large range of frequencies as the PLL locks.
If the external clock frequency is greater than the internal
oscillator’sfrequency,f ,thencurrentissourcedcontinu-
OSC
ously from the phase detector output, pulling up the VCO
input. When the external clock frequency is less than f
,
OSC
current is sunk continuously, pulling down the VCO input.
If the external and internal frequencies are the same but
exhibit a phase difference, the current sources turn on for
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Table 1 summarizes the different states in which the FREQ
pin can be used.
Although all dissipative elements in the circuit produce
losses, five main sources usually account for most of the
losses in LTC3769 circuits: 1) IC VBIAS current, 2) INTV
CC
Table ±.
2
regulatorcurrent,3)I Rlosses,4)bottomMOSFETtransi-
FREQ PIN
PLLIN/MODE PIN
DC Voltage
FREQUENCY
350kHz
tion losses, 5) body diode conduction losses.
0V
1. The VBIAS current is the DC supply current given in the
ElectricalCharacteristicstable,whichexcludesMOSFET
driver and control currents. VBIAS current typically
results in a small (<0.1%) loss.
INTV
DC Voltage
535kHz
CC
Resistor
DC Voltage
50kHz to 900kHz
Any of the Above
External Clock
Phase Locked to
External Clock
2. INTV current is the sum of the MOSFET driver and
CC
Minimum On-Time Considerations
Minimum on-time, t , is the smallest time duration
that the LTC3769 is capable of turning on the bottom
MOSFET. It is determined by internal timing delays and
the gate charge required to turn on the top MOSFET. Low
duty cycle applications may approach this minimum on-
time limit.
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge, dQ, moves
ON(MIN)
from INTV to ground. The resulting dQ/dt is a current
CC
out of INTV that is typically much larger than the
CC
control circuit current. In continuous mode, I
GATECHG
= f(Q + Q ), where Q and Q are the gate charges of
T
B
T
B
In forced continuous mode, if the duty cycle falls below
what can be accommodated by the minimum on-time,
the controller will begin to skip cycles but the output will
continuetoberegulated.Morecycleswillbeskippedwhen
the topside and bottom side MOSFETs.
2
3. DC I R losses. These arise from the resistances of the
MOSFETs,sensingresistor,inductorandPCboardtraces
andcausetheefficiencytodropathighoutputcurrents.
V increases. Once V rises above V , the loop keeps
IN
IN
OUT
the top MOSFET continuously on. The minimum on-time
4. Transition losses apply only to the bottom MOSFET(s),
and become significant only when operating at low
inputvoltages.Transitionlossescanbeestimatedfrom:
for the LTC3769 is approximately 110ns.
Efficiency Considerations
VOUT
Transition Loss=(1.7)
3 • IOUT(MAX)• CRSS •f
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the greatest improvement. Percent efficiency
can be expressed as:
V
IN
5. Body diode conduction losses are more significant at
higherswitchingfrequency. Duringthedeadtime, theloss
in the top MOSFET is I
• V , where V is around 0.7V.
OUT
DS DS
At higher switching frequency, the dead time becomes a
good percentage of switching cycle and causes the ef-
ficiency to drop.
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc., are the individual losses as a percent-
age of input power.
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Other hidden losses, such as copper trace and internal
batteryresistances,canaccountforanadditionalefficiency
degradation in portable systems. It is very important to
includethesesystem-levellossesduringthedesignphase.
Placing a power MOSFET and load resistor directly across
the output capacitor and driving the gate with an ap-
propriate signal generator is a practical way to produce
a realistic load step condition. The initial output voltage
step resulting from the step change in output current may
not be within the bandwidth of the feedback loop, so this
signal cannot be used to determine phase margin. This
is why it is better to look at the ITH pin signal which is
in the feedback loop and is the filtered and compensated
control loop response.
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V
shifts by an
OUT
amount equal to ΔI
• ESR, where ESR is the effective
The gain of the loop will be increased by increasing R
LOAD
C
series resistance of C . ΔI
also begins to charge
and the bandwidth of the loop will be increased by de-
OUT
LOAD
or discharge C , generating the feedback error signal
OUT
creasing C . If RC is increased by the same factor that C
C C
that forces the regulator to adapt to the current change
is decreased, the zero frequency will be kept the same,
thereby keeping the phase shift the same in the most
critical frequency range of the feedback loop. The output
voltage settling behavior is related to the stability of the
closed-loopsystemandwilldemonstratetheactualoverall
supply performance.
and return V
to its steady-state value. During this
can be monitored for excessive over-
OUT
recovery time V
OUT
shoot or ringing, which would indicate a stability problem.
OPTI-LOOP® compensation allows the transient response
to be optimized over a wide range of output capacitance
and ESR values. The availability of the ITH pin not only
allows optimization of control loop behavior, but it also
providesaDCcoupledandACfilteredclosedloopresponse
test point. The DC step, rise time and settling at this test
point truly reflects the closed loop response. Assuming a
predominantly second order system, phase margin and/
or damping factor can be estimated using the percentage
of overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin. The ITH
external components shown in the Figure 10 circuit will
provide an adequate starting point for most applications.
A second, more severe transient is caused by switching
in loads with large (>1μF) supply bypass capacitors. The
dischargedbypasscapacitorsareeffectivelyputinparallel
with C
, causing a rapid drop in V
. No regulator can
OUT
OUT
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
C
LOAD
to C
is greater than 1:50, the switch rise time
OUT
should be controlled so that the load rise time is limited to
approximately 25 • C . Thus, a 10μF capacitor would
LOAD
require a 250μs rise time, limiting the charging current
to about 200mA.
The ITH series R -C filter sets the dominant pole-zero
C
C
loop compensation. The values can be modified slightly
to optimize transient response once the final PC layout
is complete and the particular output capacitor type and
value have been determined. The output capacitors must
beselectedbecausethevarioustypesandvaluesdetermine
the loop gain and phase. An output current pulse of 20%
to 80% of full-load current having a rise time of 1μs to
10μs will produce output voltage and ITH pin waveforms
that will give a sense of the overall loop stability without
breaking the feedback loop.
Design Example
As a design example, assume V = 12V (nominal),
IN
V
IN
= 22V(max),V =24V,I
=4A,V
=
OUT
OUT(MAX)
SENSE(MAX)
75mV, and f = 350kHz.
Theinductancevalueischosenfirstbasedona30%ripple
current assumption. Tie the FREQ pin to GND, generat-
3769fa
23
For more information www.linear.com/LTC3769
LTC3769
APPLICATIONS INFORMATION
ing 350kHz operation. The minimum inductance for 30%
ripple current is:
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 6. Figure 7 illustrates the current
waveformspresentinthe synchronousregulatoroperating
inthecontinuousmode.Checkthefollowinginyourlayout:
⎛
⎞
V
f•L
V
IN
VOUT
IN
ΔIL =
1−
⎜
⎟
⎝
⎠
The largest ripple happens when V = 1/2V
where the average maximum inductor current is:
= 12V,
OUT
IN
VOUT
1. Put the bottom N-channel MOSFET MBOT and the top
N-channel MOSFET MTOP1 in one compact area with
IMAX = IOUT(MAX)
•
= 8A
V
IN
C
.
OUT
A 6.8μH inductor will produce a 31% ripple current. The
peak inductor current will be the maximum DC value plus
one half the ripple current, or 9.25A.
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return of
C
mustreturntothecombinedC (–)terminals.
INTVCC
OUT
The R
resistor value can be calculated by using the
SENSE
The path formed by the bottom N-channel MOSFET
and the capacitor should have short leads and PC trace
lengths. The output capacitor (–) terminals should be
connected as close as possible to the source terminals
of the bottom MOSFETs.
maximum current sense voltage specification with some
accommodation for tolerances:
75mV
RSENSE
≤
= 0.008Ω
9.25A
Choosing 1% resistors: R = 5k and R = 95.3k yields an
A
B
3. Does the LTC3769 VFB pin’s resistive divider connect to
output voltage of 24.072V.
the (+) terminal of C ? The resistive divider must be
OUT
connected between the (+) terminal of C
and signal
The power dissipation on the top side MOSFET can be
easily estimated. Choosing a Vishay Si7848BDP MOS-
OUT
ground and placed close to the VFB pin. The feedback
resistor connections should not be along the high cur-
rent input feeds from the input capacitor(s).
FET results in: R
= 0.012Ω, C
= 150pF.
DS(ON)
MILLER
At maximum input voltage with T (estimated) = 50°C:
–
+
4. Are the SENSE and SENSE leads routed together with
minimumPCtracespacing?Thefiltercapacitorbetween
(24V –12V)24V
PMAIN
=
•(4A)2
(12V)2
+
–
SENSE and SENSE should be as close as possible
to the IC. Ensure accurate current sensing with Kelvin
connections at the sense resistor.
• 1+(0.005)(50°C–25°C) •0.012
[
]
4A
12V
+ (1.7)(24V)3
(150pF)(350kHz)= 0.84W
5. Is the INTV decoupling capacitor connected close
CC
to the IC, between the INTV and the power ground
pins? This capacitor carries the MOSFET drivers’ cur-
rent peaks. An additional 1μF ceramic capacitor placed
C
is chosen to filter the square current in the output.
CC
OUT
The maximum output current peak is:
31%
2
⎛
⎝
⎞
immediately next to the INTV and GND pins can help
IOUT(PEAK) = 8• 1+
= 9.3A
CC
⎜
⎟
⎠
improve noise performance substantially.
A low ESR (5mΩ) capacitor is suggested. This capacitor
will limit output voltage ripple to 46.5mV (assuming ESR
dominates the ripple).
3769fa
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For more information www.linear.com/LTC3769
LTC3769
APPLICATIONS INFORMATION
+
SENSE
SENSE
PGOOD
SW
V
PULLUP
–
R
SENSE
L1
LTC3769
OVMODE
TG
C
B
BOOST
BG
FREQ
+
M1
M2
f
IN
PLLIN/MODE
RUN
VBIAS
GND
VFB
+
V
IN
ITH
SS
GND
INTV
CC
V
OUT
3769 F06
Figure 6. Recommended Printed Circuit Layout Diagram
L1
V
SW
R
OUT
V
SENSE
IN
R
IN
C
R
L
OUT
C
IN
3769 F07
BOLD LINES INDICATE HIGH SWITCHING CURRENT.
KEEP LINES TO A MINIMUM LENGTH
Figure 7. Branch Current Waveforms
3769fa
25
For more information www.linear.com/LTC3769
LTC3769
APPLICATIONS INFORMATION
inputs or inadequate loop compensation. Overcompensa-
tion of the loop can be used to tame a poor PC layout if
regulator bandwidth optimization is not required.
6. Keep the switching node (SW), top gate node (TG) and
boost node (BOOST) away from sensitive small-signal
nodes.Allofthesenodeshaveverylargeandfastmoving
signalsand,therefore,shouldbekeptontheoutputside
of the LTC3769 and occupy a minimal PC trace area.
Reduce V from its nominal level to verify operation with
IN
high duty cycle. Check the operation of the undervoltage
lockout circuit by further lowering V while monitoring
7. Use a modified “star ground” technique: a low imped-
ance, large copper area central grounding point on
the same side of the PC board as the input and output
IN
the outputs to verify operation.
Investigate whether any problems exist only at higher out-
put currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG,
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
sensing pins needs to be placed immediately adjacent to
the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
capacitive coupling.
capacitors with tie-ins for the bottom of the INTV
decouplingcapacitor,thebottomofthevoltagefeedback
resistive divider and the GND pins of the IC.
CC
PC Board Layout Debugging
It is helpful to use a DC-50MHz current probe to monitor
the current in the inductor while testing the circuit. Moni-
tor the output switching node (SW pin) to synchronize
the oscilloscope to the internal oscillator and probe the
actual output voltage. Check for proper performance over
the operating voltage and current range expected in the
application. The frequency of operation should be main-
tained over the input voltage range down to dropout and
until the output load drops below the low current opera-
tion threshold— typically 10% of the maximum designed
current level in Burst Mode operation.
An embarrassing problem which can be missed in an oth-
erwiseproperlyworkingswitchingregulator, resultswhen
the current sensing leads are hooked up backwards. The
output voltage under this improper hook-up will still be
maintained, but the advantages of current mode control
will not be realized. Compensation of the voltage loop will
be much more sensitive to component selection. This
behavior can be investigated by temporarily shorting out
the current sensing resistor—don’t worry, the regulator
will still maintain control of the output voltage.
Thedutycyclepercentageshouldbemaintainedfromcycle
to cycle in a well designed, low noise PCB implementa-
tion. Variation in the duty cycle at a subharmonic rate can
suggest noise pickup at the current or voltage sensing
3769fa
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For more information www.linear.com/LTC3769
LTC3769
TYPICAL APPLICATIONS
VBIAS
+
SENSE
V
IN
5V TO 24V
R
C
SENSE
IN
LTC3769
I
4mΩ
LIM
22µF
–
SENSE
EXTV
CC
L
OVMODE
PLLIN/MODE
RUN
3.3µH
TG
FREQ
V
24V
5A*
OUT
C
0.1µF
SS
SW
C
0.1µF
D
+
C
B
MTOP
MBOT
OUTA
C
SS
OUTB
22µF
150µF
BOOST
BG
×4
C
ITH
15nF
R
12.1k
ITH
ITH
C
ITHA
100pF
INTV
CC
C
INT
4.7µF
GND
R
A
12.1k
100k
VFB
PGOOD
R
S
232k
3769 F08
C
C
, C
OUTB
D: BAS140W
: TDK C4532X5R1E226M
IN OUTA
: SUNCON 35HVH150M
L: PULSE PA1494.362NL
MBOT, MTOP: RENESAS RJK0452, RJK0453
*WHEN V < 8V, MAXIMUM LOAD CURRENT AVAILABLE IS REDUCED. WHEN V > 24V, V
FOLLOWS V .
IN
IN
IN
OUT
Figure 8. High Efficiency 24V Boost Converter
VBIAS
+
SENSE
V
IN
5V TO 28V
R
SENSE
LTC3769
C
IN
4mΩ
I
LIM
22µF
–
SENSE
EXTV
CC
L
OVMODE
PLLIN/MODE
RUN
3.3µH
TG
FREQ
V
28V
4A*
OUT
C
0.1µF
SS
SW
C
0.1µF
D
+
C
B
OUTA
MTOP
MBOT
C
SS
OUTB
22µF
150µF
BOOST
BG
×4
C
ITH
15nF
R
8.66k
ITH
ITH
C
ITHA
220pF
INTV
CC
C
INT
4.7µF
GND
R
12.1k
A
100k
VFB
PGOOD
R
S
261k
3769 F09
C
C
, C
OUTB
D: BAS140W
: TDK C4532X7R1H685K
IN OUTA
: SUNCON 63CE220KX
L: PULSE PA1494.362NL
MBOT, MTOP: RENESAS HAT2169H
*WHEN V < 8V, MAXIMUM LOAD CURRENT AVAILABLE IS REDUCED. WHEN V > 28V, V
FOLLOWS V .
IN
IN
IN
OUT
Figure 9. High Efficiency 28V Boost Converter
3769fa
27
For more information www.linear.com/LTC3769
LTC3769
TYPICAL APPLICATIONS
VBIAS
V
IN
5V TO 60V START-UP
VOLTAGE OPERATES THROUGH
TRANSIENTS DOWN TO 2.3V
+
C
C
INB
+
+
SENSE
INA
10µF
50µF
R
×2
SENSE
2mΩ
×2
LTC3769
I
LIM
EXTV
CC
–
SENSE
OVMODE
L
1.3µH
RUN
FREQ
TG
V
10V
5A
*
OUT
C
SS
0.1µF
SW
C
C
C
B
MTOP
OUTA
OUTB
0.1µF
10µF
56µF
SS
×3
×2
C
ITH
10nF
BOOST
BG
R
ITH
4.75k
MBOT
ITH
C
ITHA
820pF
D
INTV
CC
C
INT
4.7µF
R
A
GND
64.9k
VFB
PLLIN/MODE
R
B
100k
475k
PGOOD
3769 F10
L: WÜRTH 7443551130
MBOT, MTOP: INFINEON BSC028N06L53
D: BAS170W
C
C
, C
: GRM32ER71J106KA12L
: SUNCON 63HVH56M
INA OUTA
, C
INB OUTB
*WHEN V > 10V, V
IN
FOLLOWS V .
IN
OUT
Figure 10. High Efficiency 10V Boost Converter
VBIAS
SENSE
V
IN
8V TO 24V
+
I
LIM
C
IN
22µF
LTC3769
100
98
96
94
92
90
88
86
R
53.6k
1%
S2
EXTV
CC
C1
0.1µF
L
R
26.1k
1%
S1
V
IN
= 12V
= 9V
OVMODE
10.2µH
RUN
FREQ
V
41.2k
–
IN
IN
SENSE
TG
C
SS
0.1µF
V
= 6V
V
24V*
4A
OUT
SW
C
SS
+
B
MTOP
MBOT
C
OUTA
C
0.1µF
OUTB
C
ITH
22µF
220µF
R
ITH
15nF
BOOST
BG
×4
8.66k
ITH
C
D
ITHA
220pF
INTV
CC
C
INT
4.7µF
GND
PLLIN/MODE
R
A
0
1
2
3
4
5
6
12.1k
100k
OUTPUT CURRENT (A)
VFB
PGOOD
3769 F11b
R
B
232k
3769 F11a
C1: TDK C1005X7R1C104K
C
C
, C : TDK C4532X5R1E226M
IN OUTA
: SUNCON, 50CE220AX
OUTB
L: PULSE PA2050.103NL
MBOT, MTOP: RENESAS RJK0305
D: INFINEON BAS140W
Figure 11. High Efficiency 24V Boost Converter with Inductor DCR Current Sensing
3769fa
28
For more information www.linear.com/LTC3769
LTC3769
TYPICAL APPLICATIONS
VBIAS
+
SENSE
V
IN
5V TO 60V
LTC3769
R
C
SENSE
IN
6mΩ
10µF
EXTV
CC
OVMODE
–
×2
SENSE
L
6.8µH
PLLIN/MODE
RUN
TG
47.5k
D
FREQ
V
24V*
2A
OUT
C
SS
0.1µF
SW
+
C
OUTB
C
SS
OUTA
56µF
10µF
BOOST
BG
×2
C
ITH
10nF
C
R
24.9k
ITH
MBOT
ITH
I
LIM
100pF
ITHA
INTV
CC
C
INT
4.7µF
12.1k
1%
GND
100k
VFB
PGOOD
232k
1%
3769 F12
C
OUTB
D: DIODES INC B360
, C
: MURATA GRM32ER71J106KA12L
IN OUTA
C
: SUNCON 63HVH56M
L: COILCRAFT XAL1010 6.8µH
MBOT: INFINEON BSC100NO6LS
*WHEN V > 24V, V
FOLLOWS V .
IN
IN
OUT
Figure 12. Low IQ Nonsynchronous 24V/2A Boost Converter
V
IN
18V TO 32V
VBIAS
+
SENSE
LTC3769
4.7µF
×3
4mΩ
EXTV
CC
+
–
SENSE
OVMODE
ILIM
33µF
•
L1
PLLIN/MODE
RUN
TG
4.7µF
FREQ
D1
V
OUT
0.1µF
24V
SW
2.5A
4.7µF
×5
SS
(×4)
M1
L1
15nF
+
•
220µF
×2
12.1k
BG
ITH
100pF
BOOST
INTV
CC
12.1k
4.7µF
VFB
GND
232k
3769 F13
L1: COILTRONICS, VERSAPAC VPH5-0067-R
D1: CENTRAL SEMICONDUCTOR, CMSH5-60
M1: INFINEON BSC0281106LS3
Figure 13. Low IQ 24VOUT SEPIC Converter
3769fa
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For more information www.linear.com/LTC3769
LTC3769
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-ꢀ697 Rev B)
BOTTOM VIEW—EXPOSED PAD
PIN ꢀ NOTCH
R = 0.20 TYP OR
0.35 × 45° CHAMFER
R = 0.ꢀꢀ5
TYP
0.75 0.05
4.00 0.ꢀ0
(4 SIDES)
23 24
0.70 0.05
PIN ꢀ
TOP MARK
(NOTE 6)
0.40 0.ꢀ0
ꢀ
2
2.45 0.05
(4 SIDES)
4.50 0.05
2.45 0.ꢀ0
(4-SIDES)
3.ꢀ0 0.05
PACKAGE
OUTLINE
(UF24) QFN 0ꢀ05 REV
0.25 0.05
0.50 BSC
B
0.200 REF
0.25 0.05
0.50 BSC
0.00 – 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
ꢀ. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION
(WGGD-X)—TO BE APPROVED
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.ꢀ5mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev K)
Exposed Pad Variation CA
6.07
(.239)
6.40 – 6.60*
(.252 – .260)
4.95
(.195)
DETAIL A
4.95
(.195)
1.98
(.078)
REF
20 1918 17 16 15 14 1312 11
6.60 ±0.10
4.50 ±0.10
DETAIL A
2.74
(.108)
0.56
(.022)
REF
6.40
(.252)
BSC
2.74
(.108)
SEE NOTE 4
0.45 ±0.05
1.05 ±0.10
DETAIL A IS THE PART OF
THE LEAD FRAME FEATURE
FOR REFERENCE ONLY
NO MEASUREMENT PURPOSE
0.65 BSC
5
7
8
1
2
3
4
6
9 10
RECOMMENDED SOLDER PAD LAYOUT
6.07
(.239)
1.20
(.047)
MAX
4.30 – 4.50*
(.169 – .177)
0.25
REF
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
0.05 – 0.15
(.002 – .006)
0.195 – 0.30
FE20 (CA) TSSOP REV K 0913
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
MILLIMETERS
(INCHES)
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
3769fa
30
For more information www.linear.com/LTC3769
LTC3769
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
09/15 Corrected pin 13 and pin 14 functions.
9
3769fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
31
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC3769
TYPICAL APPLICATION
VBIAS
+
SENSE
V
IN
LTC3769
5V TO 55V
R
C
4.7µF
×3
SENSE
IN
3mΩ
EXTV
CC
OVMODE
–
SENSE
L
10µH
PLLIN/MODE
RUN
TG
30.1k
FREQ
V
OUT
C
SS
0.1µF
48V
SW
C
0.1µF
D
+
C
4.7µF
×5
B
OUTA
2.5A*
MTOP
MBOT
C
33µF
×2
SS
OUTB
BOOST
BG
C
ITH
15nF
V
OUT
FOLLOWS V
IN
IN
R
15k
ITH
WHEN V > 48V
ITH
C
ITHA
100pF
INTV
CC
C
INT
4.7µF
100k
100k
PGOOD
GND
R
12.1k
A
VFB
R
B
475k
PGND
3769 F14
C
, C
: TDK C3225X7S2A475M
IN OUTA
C
: SUNCON 63HVH33M
OUTB
D: BAS170W
L: SER2918H-103
MBOT, MTOP: BSC028N06L53
*WHEN V < 13V, MAXIMUM LOAD CURRENT AVAILABLE IS REDUCED.
IN
Figure 14. High Efficiency 48V/2.5A Boost Converter
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC3784
2-Phase Single Output Synchronous Boost Controller 4.5V ≤ V ≤ 60V, V
Up to 60V, 50kHz to 900kHz, 4mm × 5mm
OUT
IN
QFN-28 and SSOP-28 Packages
LTC3788/LTC3788-1
LTC3787
Multiphase, Dual Output Synchronous Step-Up
Controller
4.5V (Down to 2.5V After Start-Up) ≤ V ≤ 38V, V
Up to 60V, 50kHz to
OUT
IN
900kHz Fixed Operating Frequency, 5mm × 5mm QFN-32, SSOP-28
2-Phase Single Output Synchronous Boost Controller
4.5V ≤ V ≤ 38V, V
Up to 60V, 50kHz to 900kHz, 4mm × 5mm
OUT
IN
QFN-28 and SSOP-28 Packages
LTC3786
Low I Synchronous Step-Up Controller
4.5V (Down to 2.5V After Start-Up) ≤ V ≤ 38V, V
Up to 60V, 50kHz to
OUT
Q
IN
900kHz Fixed Operating Frequency, 3mm × 3mm QFN-32, MSOP-16E
LTC3862/LTC3862-1/
LTC3862-2
Multiphase, Dual Channel Single Output Current
Mode Step-Up DC/DC Controller
4V ≤ V ≤ 36V, 5V or 10V Gate Drive, 75kHz to 500kHz Fixed Operating
IN
Frequency, SSOP-24, TSSOP-24, 5mm × 5mm QFN-24
LT3757/LT3758
Boost, Flyback, SEPIC and Inverting Controller
2.9V ≤ V ≤ 40V/100V, 100kHz to 1MHz Fixed Operating Frequency,
IN
3mm × 3mm DFN-10 and MSOP-10E
LTC3859AL
Low I , Triple Output Buck/Buck/Boost Synchronous All Outputs Remain in Regulation Through Cold Crank, 4.5V (Down to
Q
DC/DC Controller
2.5V After Start-Up) ≤ V ≤ 38V, V
Up to 24V, V
OUT(BUCKS) OUT(BOOST)
IN
Up to 60V, I = 28µA
Q
LTC3789
High Efficiency Synchronous 4-Switch Buck-Boost
DC/DC Controller
4V ≤ V ≤ 38V, 0.8V ≤ V
≤ 38V, 4mm × 5mm QFN-28 and SSOP-28
OUT
IN
LT8705
80V V and V
Synchronous 4-Switch Buck-Boost
V
Range: 2.8V (Need EXTV > 6.4V) to 80V, V
Range: 1.3V to 80V,
IN
OUT
IN
CC
OUT
DC/DC Controller
Four Regulation Loops
LTC3890/LTC3890-1/
60V, Low I , Dual 2-Phase Synchronous Step-Down Phase-Lockable Fixed Frequency 50kHz to 900kHz, 4V ≤ V ≤ 60V,
Q
IN
LTC3890-2/LTC3890-3 DC/DC Controller
0.8V ≤ V
≤ 24V, I = 50μA
OUT Q
3769fa
LT 0915 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
32
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC3769
●
●
LINEAR TECHNOLOGY CORPORATION 2014
相关型号：
LTC3769MPFE#PBF
LTC3769 - 60V Low IQ Synchronous Boost Controller; Package: TSSOP; Pins: 20; Temperature Range: -55°C to 125°C
Linear
LTC3769MPUF#PBF
LTC3769 - 60V Low IQ Synchronous Boost Controller; Package: QFN; Pins: 24; Temperature Range: -55°C to 125°C
Linear
LTC3770EUH#PBF
LTC3770 - Fast No RSENSE Step-Down Synchronous Controller with Margining, Tracking and PLL; Package: QFN; Pins: 32; Temperature Range: -40°C to 85°C
Linear
LTC3770EUH#TRPBF
LTC3770 - Fast No RSENSE Step-Down Synchronous Controller with Margining, Tracking and PLL; Package: QFN; Pins: 32; Temperature Range: -40°C to 85°C
Linear
LTC3772BEDDB#TR
LTC3772B - Micropower No RSENSE Constant Frequency Step-Down DC/DC Controller; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C
Linear
LTC3772BEDDB#TRM
LTC3772B - Micropower No RSENSE Constant Frequency Step-Down DC/DC Controller; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C
Linear
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