LTC3770EUH#TRPBF [Linear]
LTC3770 - Fast No RSENSE Step-Down Synchronous Controller with Margining, Tracking and PLL; Package: QFN; Pins: 32; Temperature Range: -40°C to 85°C;
| 型号： | LTC3770EUH#TRPBF |
| 厂家： | 
Linear |
| 描述： | LTC3770 - Fast No RSENSE Step-Down Synchronous Controller with Margining, Tracking and PLL; Package: QFN; Pins: 32; Temperature Range: -40°C to 85°C 控制器 |
| 文件： | 总24页 (文件大小：302K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3770
Fast No RSENSETM Step-Down
Synchronous Controller with
Margining, Tracking and PLL
U
FEATURES
DESCRIPTIO
■
Wide VIN Range: 4V to 32V
The LTC®3770 is a synchronous step-down switching
regulator controller with output voltage up/down tracking
capability and voltage margining. Its advanced functions
and high accuracy reference are ideal for powering
high performance server, ASIC and computer memory
systems.
■
±0.67% 0.6V Reference Voltage
■
Output Voltage Tracking Capability
■
Programmable Margining
■
Sense Resistor Optional
■
True Current Mode Control
■
2% to 90% Duty Cycle at 200kHz
The LTC3770 uses a constant on-time, valley current
mode control architecture to deliver very low duty factors
without requiring a sense resistor. The operating fre-
quency is selected by an external resistor and is compen-
sated for variations in input supply voltage. An internal
phase-lock loop allows the IC to be synchronized to an
external clock.
■
t
ON(MIN) ≤ 100ns
■
■
■
■
■
■
■
■
■
Phase Lock Loop Frequency Synchronization
Powerful Dual N-Channel MOSFET Driver
Adjustable Cycle-by-Cycle Current Limit
Adjustable Switching Frequency
Programmable Soft-Start
Current Foldback Protection (Disabled at Start-Up)
Output Overvoltage Protection
Micropower Shutdown: IQ < 30µA
Power Good Output Voltage Monitor
Tracks the Reference Input Pin
Available in (5mm × 5mm) QFN and 28-Lead
Fault protection is provided by an overvoltage comparator
andinputundervoltagelockout. Theregulatorcurrentlimit
is user programmable. A wide supply range allows volt-
agesashighas32Vtobesteppeddowntoaslowasa0.6V
output. Power supply sequencing is accomplished using
an external soft-start timing capacitor.
■
SSOP Packages U
, LTC and LT are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners. No R
Technology Corporation. Protected by U.S. Patents including 5481178, 5487554, 6580258,
6304066, 6476589, 6774611.
is a trademark of Linear
SENSE
APPLICATIO S
■
Distributed Power Systems
Server Power Supply
■
U
TYPICAL APPLICATIO
High Efficiency Step-Down Converter
Efficiency and Power Loss vs Load Current
100
95
90
85
80
75
70
65
60
55
50
10
PGOOD
MARGIN
I
ON
V
V
= 5V
IN
OUT
68k
= 2.5V
V
0.01µF
IN
V
IN
10k
5V TO 28V
EFFICIENCY
PLLFLTR
PLLIN
10µF
35V
x3
Si4884
TG
1
1.8µH
0.1µF
SW
V
2.5V
10A
OUT
TRACK/SS
0.22µF
BOOST
LTC3770
SGND INTV
+
I
TH
180µF
4V
x2
10k
CMDSH-3
1000pF
V
POWER LOSS
CC
CC
0.1
DRV
RUN
B340A
Si4874
V
BG
+
OUT
ON
SENSE
V
V
RNG
95.3k
30.1k
10µF
REFOUT
0.01
10
–
SENSE
PGND
10k
82k
0.01
0.1
1
V
LOAD CURRENT (A)
REFIN
3770 TA01b
MPGM
V
FB
3770 TA01
3770f
1
LTC3770
W W
U W
ABSOLUTE AXI U RATI GS
(Note 1)
INTVCC, ZVIN Voltages .................................7V to –0.3V
TG, BG, INTVCC Peak Currents................................... 4A
TG, BG, INTVCC RMS Currents ............................. 50mA
Operating Ambient Temperature
Range (Note 4) ................................... –40°C to 85°C
Junction Temperature (Note 2)............................. 125°C
Storage Temperature Range ................. –65°C to 125°C
QFN Reflow Peak Body Temperature .................... 245°C
Lead Temperature (Soldering, 10 sec).................. 300°C
Input Supply Voltage (VIN, VINSNS) ............32V to –0.3V
Boosted Topside Driver Supply Voltage
(BOOST) ................................................38V to –0.3V
SENSE+, SW Voltage ....................................32V to –5V
DRVCC, (BOOST – SW) Voltages .................7V to –0.3V
VON, VRNG, PGOOD Voltages .... INTVCC + 0.3V to –0.3V
PLLFLTR, ITH, VFB, VREFIN Voltages ..........2.7V to –0.3V
TRACK/SS, FCB, Z0, Z1, Z2, RUN, PLLIN, MARGIN0,
MARGIN1 Voltages............... INTVCC + 0.3V to –0.3V
U W
U
PACKAGE/ORDER I FOR ATIO
TOP VIEW
TOP VIEW
ORDER PART
NUMBER
ORDER PART
NUMBER
1
2
FCB
Z0
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RUN
V
ON
LTC3770EG
LTC3770EUH
32 31 30 29 28 27 26 25
3
BOOST
TG
PGOOD
+
V
1
2
3
4
5
6
7
8
24 SENSE
23 SENSE
RNG
4
V
RNG
–
V
I
FB
5
SW
V
I
FB
PGND
BG
22
21
TH
6
PGND
BG
TH
G PART
MARKING
UH PART
MARKING
SGND
MARGIN1
MARGIN0
7
SGND
MARGIN1
MARGIN0
33
20 DRV
CC
8
INTV
CC
INTV
19
CC
LTC3770EG
3770
9
Z2
Z1
I
18 Z2
17 Z1
ON
REFIN
10
11
12
13
14
I
ON
REFIN
V
ZV
IN
V
9
10 11 12 13 14 15 16
V
V
IN
REFOUT
MPGM
PLLIN
PLLFLTR
TRACK/SS
UH PACKAGE
G PACKAGE
32-LEAD (5mm × 5mm) PLASTIC QFN
28-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 34°C/ W
TJMAX = 125°C, θJA = 130°C/ W
EXPOSED PAD IS SGND (PIN 33)
MUST BE SOLDERED TO THE PCB
Consult LTC Marketing for parts specified with wider operating temperature ranges.
3770f
2
LTC3770
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VIN = 15V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Main Control Loop
I
Input DC Supply Current
Normal Operation
Shutdown Supply Current
Q
1300
30
2200
50
µA
µA
V
Feedback Voltage Accuracy (Note 3)
V
V
= V
= V
; I = 1.2V (0°C to 85°C)
REFOUT TH
; I = 1.2V
REFOUT TH
0.596
0.594
0.6
0.6
0.604
0.606
V
V
FB
REFIN
REFIN
●
V
V
V
Feedback Voltage Line Regulation
Feedback Voltage Load Regulation
Run Pin On Threshold
V
= 4V to 30V, I = 1.2V (Note 3)
0.002
–0.05
1.5
%/V
%
FB(LINEREG)
FB(LOADREG)
RUN
IN
TH
I
= 0.5V to 1.9V (Note 3)
–0.3
1.9
TH
V
V
Rising
1
V
RUN
SS/TRACK
I
I
Soft-Start Charging Current
Feedback Pin Input Current
Error Amplifier Transconductance
Forced Continuous Threshold
Forced Continuous Pin Current
On-Time
= 0V
–1.1
–100
1
–1.4
–20
1.3
–1.7
100
1.6
µA
nA
mS
V
SS/TRACK
FB
g
I
= 1.2V (Note 3)
TH
●
●
m(EA)
V
0.57
0.6
0.63
–2
FCB
FCB
ON
I
t
V
= 0V
–1
µA
FCB
I
I
= –60µA, V = 1.5V
210
90
250
115
290
150
ns
ns
ON
ON
ON
= –60µA, V = 0V
ON
t
t
Minimum On-Time
I
= –180µA, V = 0V
50
100
400
ns
ns
ON(MIN)
OFF(MIN)
ON
ON
Minimum Off-Time
250
V
Maximum Current Sense Threshold
V
V
V
= 1V, V = V
– 30mV
– 30mV
●
●
●
113
50
228
133
67
268
153
84
308
mV
mV
mV
SENSE(MAX)
RNG
RNG
RNG
FB
REFIN
REFIN
–
+
V
– V
= 0V, V = V
SENSE
SENSE
FB
= INTV , V = V
– 30mV
CC FB
REFIN
V
Minimum Current Sense Threshold
V
V
V
= 1V, V = V
+ 30mV
+ 30mV
–60
–30
–120
mV
mV
mV
SENSE(MIN)
RNG
RNG
RNG
FB
REFIN
REFIN
–
+
V
– V
= 0V, V = V
SENSE
SENSE
FB
= INTV , V = V
+ 30mV
CC FB
REFIN
∆V
Output Overvoltage Fault Threshold Offset
Undervoltage Lockout
7
10
3.2
3.3
1.4
1.18
1.9
1.2
1.9
0.7
20
13
3.9
4
%
V
FB(OV)
+
V
V
V
V
V
V
Falling
●
●
IN(UVLO )
IN
IN
–
Undervoltage Lockout
Rising
V
IN(UVLO )
MARGIN0, MARGIN1 Input Thresholds
MPGM Pin Voltage
V
MGN(TH)
MPGM
V
TG R
TG R
BG R
BG R
TG Driver Pull-Up On Resistance
TG Driver Pull-Down On Resistance
BG Driver Pull-Up On Resistance
BG Driver Pull-Down On Resistance
TG Rise Time
TG High
TG Low
BG High
BG Low
2.5
2.5
3
Ω
Ω
Ω
Ω
ns
ns
ns
ns
UP
DOWN
UP
1.5
DOWN
TG t
TG t
C
C
C
C
= 3300pF
= 3300pF
= 3300pF
= 3300pF
r
f
LOAD
LOAD
LOAD
LOAD
TG Fall Time
20
BG t
BG t
BG Rise Time
20
r
f
BG Fall Time
20
3770f
3
LTC3770
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VIN = 15V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Internal V Regulator
CC
V
Internal V Voltage
6V < V < 30V
●
4.7
5
5.3
V
INTVCC
CC
IN
∆V
Internal V Load Regulation
I
= 0mA to 20mA
–0.1
±2
%
LDO(LOADREG)
CC
CC
Phased-Locked Loop
R
PLLIN
PLLIN Input Resistance
50
kΩ
I
Phase Detector Output Current
Sink Capability
Source Capability
PLLFLTR
f
f
< f
0
> f
0
–15
15
µA
µA
PLLIN
PLLIN
PGOOD Output
∆V
∆V
∆V
PGOOD Upper Threshold
PGOOD Lower Threshold
PGOOD Hysteresis
V
V
V
Rising
7
10
–10
1.5
13
–13
3
%
%
%
V
FBH
FB
Falling
–7
FBL
FB
Returning
FB(HYS)
FB
V
PGOOD Low Voltage
I
= 5mA
0.15
0.4
PGL
PGOOD
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 3: The 3770 is tested in a feedback loop that adjusts V to achieve a
FB
specified error amplifier output voltage (I ). For these tests, V
=
TH
REFOUT
V
.
REFIN
Note 2: T is calculated from the ambient temperature T and power
J
A
dissipation P as follows:
Note 4: The LTC3770E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
D
LTC3770EG: T = T + (P • 130°C/W)
J
A
D
LTC3770EUH: T = T + (P • 34°C/W)
J
A
D
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Current Sense Threshold
vs ITH Voltage
On-Time vs ION Current
On-Time vs VON Voltage
10k
1k
300
200
100
0
1200
1000
800
600
400
200
0
2V
V
= 0V
I
= 60µA
V
=
VON
ION
RNG
1.4V
1V
0.7V
0.5V
100
10
–100
–200
0
1.0
1.5
2.0
2.5
3.0
0.5
1
10
100
2
3
4
5
0
1
I
VOLTAGE (V)
I
ON
CURRENT (µA)
TH
V
VOLTAGE (V)
ON
3770 G02
3770 G01
3770 G03
3770f
4
LTC3770
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Maximum Current Sense
Threshold vs VRNG Voltage
Maximum Current Sense
Threshold vs Temperature
On-Time vs Temperature
150
140
130
120
110
100
300
250
200
150
100
50
300
250
200
150
V
= 1V
I
= 30µA
VON
RNG
ION
V
= 0V
100
50
0
0
50
75 100 125
50
TEMPERATURE (°C)
100 125
0.5
0.75
1.0
V
1.25
VOLTAGE (V)
1.5
1.75
2.0
–50 –25
0
25
–50 –25
0
25
75
TEMPERATURE (°C)
RNG
3770 G05
3770 G06
3770 G04
Error Amplifier gm vs Temperature
Input Current vs Input Voltage
Shutdown Current vs Input Voltage
1.6
1.4
1.2
1.0
0.8
0.6
2.5
2.0
1.5
1.0
0.5
0
60
50
40
30
20
10
0
–50 –25
0
25
50
75 100 125
0
5
10
15
20
INPUT VOLTAGE (V)
25
30
35
0
15
20
25
30
35
5
10
TEMPERATURE (°C)
INPUT VOLTAGE (V)
3770 G07
3770 G08
3770 G09
Undervoltage Lockout Threshold
vs Temperature
INTVCC Load Regulation
FCB Pin Current vs Temperature
0
–0.1
–0.2
–0.3
–0.4
0
–0.25
–0.50
–0.75
4.0
3.5
3.0
2.5
–1.00
–1.25
–1.50
2.0
0
10
20
30
40
50
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
–50 –25
0
25
50
75 100 125
3770 G12
TEMPERATURE (C)
INTV LOAD CURRENT (mA)
CC
3770 G10
3770 G11
3770f
5
LTC3770
TYPICAL PERFOR A CE CHARACTERISTICS
U W
Track Up
Track Down
Transient Response
FIGURE 12 CIRCUIT
FIGURE 12 CIRCUIT
TRACK/SS
FIGURE 12 CIRCUIT
TRACK/SS
V
OUT
100mV/DIV
TRACK/SS
FB
500mV/DIV
AND V
V
FB
V
FB
TRACK/SS
AND V
V
OUT
V
OUT
FB
V
OUT
2V/DIV
500mV/DIV
I
L
V
5A/DIV
STEP
OUT
2V/DIV
0A TO 10A
3770 G13
3770 G14
3770 G15
250ms/DIV
250ms/DIV
20µs/DIV
Efficiency vs Load Current
ITH Voltage vs Load Current
Frequency vs Input Voltage
2.5
2.0
1.5
1.0
0.5
0
480
460
440
420
400
380
360
340
320
300
100
95
90
85
80
75
70
65
60
55
50
FIGURE 12 CIRCUIT
FIGURE 12 CIRCUIT
I
= 10A
= 0A
15
OUT
DISCONTINUOUS
MODE
CONTINUOUS
MODE
CONTINUOUS
MODE
I
OUT
DISCONTINUOUS
MODE
FCB = 0V
FIGURE 12 CIRCUIT
0.01
0.1
1
10
0
2
4
6
8
10
12
0
5
10
20
25
30
LOAD CURRENT (A)
LOAD CURRENT (A)
INPUT VOLTAGE (V)
3770 G16
3770 G17
3770 G18
Efficiency vs Input Voltage
Frequency vs Load Current
100
95
90
85
80
75
70
500
FCB = 5V
FIGURE 12 CIRCUIT
FIGURE 12 CIRCUIT
450
400
350
300
250
200
150
100
50
I
= 10A
LOAD
CONTINUOUS
MODE
I
= 1A
LOAD
DISCONTINUOUS
MODE
0
0
5
10
15
20
25
30
0
2
4
6
8
10
12
INPUT VOLTAGE (V)
LOAD CURRENT (A)
3770 G19
3770 G20
3770f
6
LTC3770
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Current Limit Foldback
Ion Current vs VIN
160
140
120
100
80
140
120
100
80
V
= 1V
R
= 82k
ON
RNG
60
60
40
40
20
20
0
0
0
0.2
0.3
(V)
0.4
0.5
0.6
0
5
10
15
20
25
30
35
0.1
V
INPUT VOLTAGE (V)
FB
3770 G21
3770 G22
U
U
U
PI FU CTIO S (UH Package/G Package)
VRNG (Pin 1/Pin 4): Sense Voltage Range Input. The
voltage at this pin is ten times the nominal sense voltage
atmaximumoutputcurrentandcanbesetfrom0.5Vto2V
by a resistive divider from INTVCC. The nominal sense
voltage defaults to 50mV when this pin is tied to ground,
200mV when tied to INTVCC. Do not set this voltage
between 0.5V to ground or 2V to INTVCC.
MARGIN0 (Pin 6/Pin 9): The LSB Logic Input for the
Margining Function. Together with the MARGIN1 pin
determines whether the IC is in margin high, margin low,
or no margin state. This pin has a 50k internal pull-down
resistor.
ION (Pin 7/Pin 10): On-Time Current Input. Tie a resistor
from this pin to ground to set the one-shot timer current
and thereby set the switching frequency.
VFB (Pin 2/Pin 5): Error Amplifier Feedback Input. This pin
connects the error amplifier input to an external resistive
VREFIN (Pin 8/Pin 11): Error Amplifier Reference Input.
The voltage at this pin must be greater than 0.5V and less
than 1V.
divider from VOUT
.
ITH (Pin 3/Pin 6): Current Control Threshold and Error
Amplifier Compensation Point. The current comparator
threshold increases with this control voltage. The voltage
ranges from 0V to 2.4V with 0.75V corresponding to zero
sense voltage (zero current). There is an integrated ca-
pacitor of 20pF connected to this pin.
VREFOUT (Pin 9/Pin 12): Buffered Internal 0.6V Reference
Output. The maximum current sinking limit is 50µA at
this pin. Do not put a filter capacitor larger than 100pF on
this pin.
MPGM (Pin 10/Pin 13): Programmable Margining Input.
A resistor from this pin to ground sets the margining
current. This current, together with the resistor between
the VREFOUT and VREFIN pins, determines the margining
voltage offset.
SGND (Pin 4/Pin 7): Signal Ground. All small-signal
components and compensation components should con-
necttothisground, whichinturnconnectstoPGNDatone
point.
MARGIN1 (Pin 5/Pin 8): The MSB Logic Input for the
Margining Function. Together with the MARGIN0 pin
determines whether the IC is in margin high, margin low,
or no margin state. This pin has a 50k internal pull-down
resistor.
TRACK/SS (Pin 11/Pin 14): Output Voltage Tracking and
SoftStartInput.WhentheICisconfiguredtobethemaster
of two outputs, a capacitor to ground at this pin sets the
rampratefortheoutputvoltage.WhentheICisconfigured
3770f
7
LTC3770
U
U
U
PI FU CTIO S (UH Package/G Package)
tobetheslaveoftwooutputs, theVFB voltageofthemaster BG (Pin 21/Pin 22): Bottom Gate Driver Output. This pin
IC is reproduced by a resistor divider and applied to this drives the gate of the bottom N-channel MOSFET between
pin. An internal 1.4µA soft start current is charging this pin ground and INTVCC.
during the soft-start phase.
PGND (Pin 22/Pin 23): Power Ground. Connect this pin
PLLFLTR (Pin 12/Pin 15): The Phase-Locked Loop’s closely to the source of the bottom N-channel MOSFET,
Lowpass Filter is Tied to This Pin. The voltage at this pin the (–) terminal of CVCC and the (–) terminal of CIN.
defaults to 1.18V when the IC is not synchronized with an
external clock at the PLLIN pin.
SENSE– (Pin23)UHPackage:CurrentSenseComparator
Input. The (–) input to the current comparator is used to
PLLIN (Pin 13/Pin 16): External Synchronization Input to accurately Kelvin sense the bottom side of the sense
Phase Detector. This pin is internally terminated to SGND resistor or MOSFET. This pin is co-bonded with PGND
with a 50k resistor.
internally in the SSOP package.
VIN (Pin 14/Pin 17): Main Input Supply. Decouple this pin SENSE+ (Pin24)UHPackage:CurrentSenseComparator
to PGND with a capacitor (0.1µF to 1µF).
Input. The (+) input to the current comparator is normally
connected to the SW node unless using a sense resistor.
This pin is co-bonded with SW internally in the SSOP
package.
VINSNS (Pin 15) UH Package: VIN Voltage Sense Input.
Normally this pin is tied to VIN. However, in certain
applications when the IC is powered from a separate
supply,VINSNS istiedtotheupperMOSFETsupplytosense SW (Pin 25/Pin 24): Switch Node. The (–) terminal of the
the VIN voltage. The pin is co-bonded with VIN in the SSOP boot-strap capacitor CB connects here. This pin swings
package.
from a diode voltage drop below ground up to VIN.
ZVIN (Pin 16/Pin 18): Post-Package Zener-Trim Voltage TG (Pin 26/Pin 25): Top Gate Drive Output. This pin drives
Input. Under normal conditions this pin should always be the top N-channel MOSFET with a voltage swing equal to
connected to INTVCC.
INTVCC, superimposed on the switch node voltage SW.
Z1 (Pin 17/Pin 19): Post-Package Zener-Trim Control. BOOST (Pin 27/Pin 26): Boosted Floating Driver Supply.
This pin is a multifunctional pin used in production for The (+) terminal of the boot-strap capacitor CB connects
post-package trimming and tracking. Ground this pin here. This pin swings from a diode voltage drop below
under normal soft-start operation. Connecting this pin to INTVCC up to VIN + INTVCC.
INTVCC will turn off the soft-start current during tracking.
Z0 (Pin 28/Pin 27): Dead Time Control Input. Applying a
Z2 (Pin 18/Pin 20): Post-Package Zener-Trim Control. DC voltage will vary the dead time between TG-Low and
This pin is used in production for Post-Package trimming. BG-High transition. Do not force a voltage higher than 5V
Ground this pin or tie to INTVCC under normal operation. on this pin.
INTVCC (Pin 19/Pin 21): Internal 5V Regulator Output. The FCB (Pin 29/Pin 28): Forced Continuous Input. Connect
control circuits are powered from this voltage. Decouple this pin to SGND to force continuous synchronization
this pin to PGND with a minimum of 10µF low ESR operation at low load, to INTVCC to enable discontinuous
tantalum or ceramic capacitor.
mode operation at low load or to a resistive divider from a
secondary output when using a secondary winding.
DRVCC (Pin 20) UH Package Gate: Driver Voltage Input.
Normally connected to the INTVCC regulated output. Do RUN (Pin 30/Pin 1): Run Control Input. A voltage above
not exceed 7V at this pin. This pin is co-bonded to INTVCC 1.5V turns on the IC. Forcing this pin below 1.5V shuts
internally in the SSOP package.
down the device.
3770f
8
LTC3770
U
U
U
PI FU CTIO S (UH Package/G Package)
VON (Pin 31/Pin 2): On-Time Voltage Input. Connecting
this pin to the output voltage makes the on-time propor-
tionaltoVOUT.Thecomparatorinputdefaultsto0.6Vwhen
the pin is grounded and defaults to 4.8V when the pin is
tied to INTVCC.
logic output that is pulled to ground when the output
voltageisnotwithin±10%oftheregulationpoint, afterthe
internal 25µs power bad mask timer expires.
Exposed Pad (Pin 33) UH Package: Signal Ground. Must
be soldered to the PCB ground for electrical contact and
optimum thermal performance.
PGOOD (Pin 32/Pin 3): Power Good Output. Open drain
U
U W
FU CTIO AL DIAGRA
(UH Package)
R
ON
V
OUT
PLLFLTR
12
V
IN
31
V
ON
4.8V
14
V
IN
7
I
ON
29 FCB
INTV
CC
+
0.6V
C
IN
1
µA
5V
REG
R
15
Z
VIN
16
V
INSNS
R
0.6V
Z0
28
INTV
CC
PLL-SYNC
+
–
R
Z1
Z2
17
18
19
F
BOOST
27
V
I
VON
ION
13
PLLIN
t
ON
=
(10pF)
R
S
C
B
TG
26
Q
FCNT
ON
M1
SW
25
SWITCH
LOGIC
AND
20k
R4
+
–
+
–
+
SENSE
24
L1
D
B
ANTI-
I
I
V
CMP
REV
OUT
MPGM
10
1.18V
SHOOT
THROUGH
–
SENSE
23
+
–
RUN
OV
DRV
CC
+
C
2.0V
20
BG
21
OUT
V
M2
RNG
1
FOLDBACK
DISABLED
AT START-UP*
×
C
MARGIN0
6
R
VCC
SENSE
(0.5~2)
(OPTIONAL)*
PGND
22
0.5V
0.25V
MARGIN1
5
32
3.3µA
PGOOD
+
–
V
IN
1
240k
0.6V
REF
R2
–
+
Q2 Q4
OV
UV
V
FB
10K
I
THB
Q6
2
R1
SGND
4
Q1
–
+
10K
90K
SW
+
SENSE
BG
–
+
RUN
INTV
CC
SS
M2
–
–
+
+
–
SENSE
1.4µA
EA
PGND
+
–
+
80% • V
REFIN
1.5V
*CONNECTION W/O
SENSE RESISTOR
12K
V
V
REFIN
REFOUT
C
C1
C
SS
9
8
3
I
TH
RUN 30
11 TRACK/SS
R
C
R3
3770f
9
LTC3770
U
OPERATIO
Main Control Loop
For applications with stringent constant frequency re-
quirements, the LTC3770 can be synchronized with an
external clock. By programming the nominal frequency of
the LTC3770 the same as the external clock frequency, the
LTC3770behavesasaconstantfrequencypartagainstthe
load and supply variations.
The LTC3770 is a current mode controller for DC/DC
step-down converters. In normal operation, the top
MOSFET is turned on for a fixed interval determined by a
one-shot timer OST. When the top MOSFET is turned off,
the bottom MOSFET is turned on until the current com-
parator ICMP trips, restarting the one-shot timer and initi-
ating the next cycle. Inductor current is determined by
sensing the voltage between the SENSE– (PGND on G
Package) and SENSE+ (SW on G Package) pins using a
sense resistor or the bottom MOSFET on-resistance . The
voltage on the ITH pin sets the comparator threshold
corresponding to inductor valley current. The error ampli-
fier EA adjusts this voltage by comparing the feedback
signal VFB from a reference voltage set by the VREFIN pin.
If the load current increases, it causes a drop in the
feedback voltage relative to the reference. The ITH voltage
thenrisesuntiltheaverageinductorcurrentagainmatches
the load current.
Overvoltage and undervoltage comparators OV and UV
pull the PGOOD output low if the output feedback voltage
exits a±10% window around the regulation point after the
internal25µspowerbadmasktimerexpires.Furthermore,
in an overvoltage condition, M1 is turned off and M2 is
turned on immediately and held on until the overvoltage
condition clears.
Foldback current limiting is provided if the output is
shorted to ground. As VFB drops, the buffered current
threshold voltage ITHB is pulled down and clamped to
0.9V. This reduces the inductor valley current level to one
tenthofitsmaximumvalueasVFB approaches0V.Foldback
current limiting is disabled at start-up.
At low load currents, the inductor current can drop to zero
and become negative. This is detected by current reversal
comparator IREV which then shuts off M2, resulting in
discontinuous operation. Both switches will remain off
with the output capacitor supplying the load current until
the ITH voltage rises above the zero current level (0.75V)
to initiate another cycle. Discontinuous mode operation is
disabled by comparator F when the FCB pin is brought
below 0.6V, forcing continuous synchronous operation.
Pulling the RUN pin low forces the controller into its
shutdown state, turning off both M1 and M2. Forcing a
voltage above 1.5V will turn on the device.
INTVCC Power
Power for the top and bottom MOSFET drivers and most
of the internal controller circuitry is derived from the
INTVCC pin. The top MOSFET driver is powered from a
floating bootstrap capacitor CB. This capacitor is re-
chargedfromINTVCC throughanexternalSchottkydiode
DB whenthetopMOSFETisturnedoff.Iftheinputvoltage
is low and INTVCC drops below 3.2V, undervoltage
lockout circuitry prevents the power switches from
turning on.
The operating frequency is determined implicitly by the
top MOSFET on-time and the duty cycle required to
maintain regulation. The one-shot timer generates an on-
time that is proportional to the ideal duty cycle, thus
holding frequency approximately constant with changes
in VIN. The nominal frequency can be adjusted with an
external resistor RON.
3770f
10
LTC3770
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APPLICATIO S I FOR ATIO
The basic LTC3770 application circuit is shown in
Figure 12. External component selection is primarily de-
termined by the maximum load current and begins with
the selection of the sense resistance and power MOSFET
switches.TheLTC3770useseitherasenseresistororthe
on-resistance of the synchronous power MOSFET for
determining the inductor current. The desired amount of
ripple current and operating frequency largely deter-
mines the inductor value. Finally, CIN is selected for its
ability to handle the large RMS current into the converter
and COUT is chosen with low enough ESR to meet the
output voltage ripple and transient specification.
the bottom MOSFET as the current sense element by
simply connecting the SENSE+ pin to the SW pin and
SENSE– pin to PGND. This improves efficiency, but one
must carefully choose the MOSFET on-resistance as dis-
cussed below.
Power MOSFET Selection
The LTC3770 requires two external N-channel power
MOSFETs, one for the top (main) switch and one for the
bottom (synchronous) switch. Important parameters for
the power MOSFETs are the breakdown voltage V(BR)DSS
threshold voltage V(GS)TH, on-resistance RDS(ON), reverse
transfercapacitanceCRSS andmaximumcurrentIDS(MAX)
,
.
Maximum Sense Voltage and VRNG Pin
The gate drive voltage is set by the 5V INTVCC supply.
Consequently, logic-level threshold MOSFETs must be
used in LTC3770 applications. If the input voltage is
expected to drop below 5V, then sub-logic level threshold
MOSFETs should be considered.
Inductor current is determined by measuring the voltage
acrossasenseresistancethatappearsbetweentheSENSE–
(PGND on G Package) and SENSE+ (SW on G Package)
pins. The maximum sense voltage is set by the voltage
applied to the VRNG pin and is equal to approximately
(0.133)VRNG. The current mode control loop will not allow
When the bottom MOSFET is used as the current sense
element, particular attention must be paid to its on-
resistance. MOSFET on-resistance is typically specified
with a maximum value RDS(ON)(MAX) at 25°C. In this case,
additional margin is required to accommodate the rise in
MOSFET on-resistance with temperature:
theinductorcurrentvalleystoexceed(0.133)VRNG/RSENSE
.
In practice, one should allow some margin for variations
intheLTC3770andexternalcomponentvaluesandagood
guide for selecting the sense resistance is:
VRNG
10 •IOUT(MAX)
RSENSE
=
RSENSE
RDS(ON)(MAX)
=
ρT
An external resistive divider from INTVCC can be used to
set the voltage of the VRNG pin between 0.5V and 2V
resulting in nominal sense voltages of 50mV to 200mV.
Additionally, the VRNG pin can be tied to SGND or INTVCC
in which case the nominal sense voltage defaults to 50mV
or 200mV, respectively. The maximum allowed sense
voltage is about 1.33 times this nominal value.
The ρT term is a normalization factor (unity at 25°C)
accounting for the significant variation in on-resistance
2.0
1.5
1.0
0.5
0
Connecting the SENSE+ and SENSE– Pins
The LTC3770 comes in UH and G packages. The UH
package IC can be used with or without a sense resistor.
When using a sense resistor, place it between the source
of the bottom MOSFET, M2, and PGND. Connect the
SENSE+ and SENSE– pins to the top and bottom of the
sense resistor. Using a sense resistor provides a well
definedcurrentlimit,butaddscostandreducesefficiency.
Alternatively, one can eliminate the sense resistor and use
50
100
–50
150
0
JUNCTION TEMPERATURE (°C)
3770 F01
Figure 1. RDS(ON) vs Temperature
3770f
11
LTC3770
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APPLICATIO S I FOR ATIO
with temperature, typically about 0.4%/°C as shown in
Figure 1. For a maximum junction temperature of 100°C,
using a value ρT = 1.3 is reasonable.
time inversely proportional to 1/3 VIN. The current out of
the ION pin is:
V
3RON
IN
I
=
ION
The power dissipated by the top and bottom MOSFETs
strongly depends upon their respective duty cycles and
the load current. When the LTC3770 is operating in
continuous mode, the duty cycles for the MOSFETs are:
For a step-down converter, this results in approximately
constant frequency operation as the input supply varies:
VOUT
f =
[HZ]
VOUT
V
IN
DTOP
DBOT
=
=
VVON • 3RON(10pF)
Toholdfrequencyconstantduringoutputvoltagechanges,
tie the VON pin to VOUT. The VON pin has internal clamps
that limit its input to the one-shot timer. If the pin is tied
below 0.6V, the input to the one-shot is clamped at 0.6V.
Similarly, if the pin is tied above 4.8V, the input is clamped
at 4.8V. In high VOUT applications, tie VON to INTVCC.
Figures 2a and 2b show how RON relates to switching
frequency for several common output voltages.
V – VOUT
IN
V
IN
The resulting power dissipation in the MOSFETs at maxi-
mum output current are:
PTOP = DTOP OUT(MAX)
I
2 ρT(TOP) RDS(ON)(MAX)
+ k VIN IOUT(MAX) CRSS
PBOT = DBOT OUT(MAX)
2 ρT(BOT) RDS(ON)(MAX)
2
f
1000
I
V
= 3.3V
OUT
Both MOSFETs have I2R losses and the top MOSFET
includesanadditionaltermfortransitionlosses,whichare
largest at high input voltages. The constant k = 1.7A–1 can
be used to estimate the amount of transition loss. The
bottomMOSFETlossesaregreatestwhenthebottomduty
cycle is near 100%, during a short-circuit or at high input
voltage.
V
= 2.5V
OUT
V
= 1.5V
OUT
100
100
1000
Operating Frequency
R
(kΩ)
3770 F02a
ON
Figure 2a. Switching Frequency vs RON
(VON = 0V)
The choice of operating frequency is a tradeoff between
efficiency and component size. Low frequency operation
improvesefficiencybyreducingMOSFETswitchinglosses
but requires larger inductance and/or capacitance in order
to maintain low output ripple voltage.
1000
V
= 12V
V
OUT
TheoperatingfrequencyofLTC3770applicationsisdeter-
mined implicitly by the one-shot timer that controls the
on-time tON of the top MOSFET switch. The on-time is set
by the current out of the ION pin and the voltage at the VON
pin according to:
= 5V
OUT
V
= 3.3V
OUT
100
10
100
(kΩ)
1000
3770 F02b
V
tON
=
VON (10pF)
R
ON
I
ION
Figure 2b. Switching Frequency vs RON
(VON = INTVCC
)
TyingaresistorRON toSGNDfromtheION pinyieldsanon-
3770f
12
LTC3770
U
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APPLICATIO S I FOR ATIO
MOSFET back off. This time is generally about 250ns. The
minimum off-time limit imposes a maximum duty cycle of
tON/(tON +tOFF(MIN)).Ifthemaximumdutycycleisreached,
due to a dropping input voltage for example, then the
output will drop out of regulation. The minimum input
voltage to avoid dropout is:
WhenthereisnoRON resistorconnectedtotheION pin, the
on-time tON is theoretically infinite, which in turn could
damage the converter. To prevent this, the LTC3770 will
detect this fault condition and provide a minimum ION
current of 5µA to 10µA.
Changes in the load current magnitude will cause fre-
quency shift. Parasitic resistance in the MOSFET switches
andinductorreducetheeffectivevoltageacrosstheinduc-
tance, resulting in increased duty cycle as the load current
increases. By lengthening the on-time slightly as current
increases, constant frequency operation can be main-
tained. This is accomplished with a resistive divider from
theITH pintotheVON pinandVOUT.Thevaluesrequiredwill
dependontheparasiticresistancesinthespecificapplica-
tion. A good starting point is to feed about 25% of the
voltage change at the ITH pin to the VON pin as shown in
Figure 3a. Place capacitance on the VON pin to filter out the
ITH variationsattheswitchingfrequency. Theresistorload
on ITH reduces the DC gain of the error amp and degrades
load regulation, which can be avoided by using the PNP
emitter follower of Figure 3b.
t
ON + tOFF(MIN)
V
= VOUT
IN(MIN)
tON
A plot of maximum duty cycle vs frequency is shown in
Figure 4.
2.0
1.5
DROPOUT
REGION
1.0
0.5
0
0
0.25
0.50
0.75
1.0
DUTY CYCLE (V /V
)
OUT IN
Minimum Off-Time and Dropout Operation
3770 F04
The minimum off-time tOFF(MIN) is the smallest amount of
time that the LTC3770 is capable of turning on the bottom
MOSFET, tripping the current comparator and turning the
Figure 4. Maximum Switching Frequency vs Duty Cycle
Inductor Selection
Given the desired input and output voltages, the inductor
value and operating frequency determine the ripple
current:
R
VON1
30k
V
V
ON
OUT
C
VON
R
VON2
100k
0.01µF
LTC3770
TH
R
⎛
⎞
C
⎛
⎞
VOUT
f L
VOUT
I
∆IL =
1−
⎜
⎝
⎟
⎠
⎜
⎟
C
C
V
IN
⎝
⎠
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors and output voltage
ripple. Highest efficiency operation is obtained at low
frequency with small ripple current. However, achieving
this requires a large inductor. There is a tradeoff between
component size, efficiency and operating frequency.
(3a)
R
VON1
3k
V
V
ON
OUT
C
R
VON
VON2
10k
0.01µF
10k
LTC3770
TH
INTV
CC
R
C
Q1
2N5087
I
C
C
3770 F03
A reasonable starting point is to choose a ripple current
that is about 40% of IOUT(MAX). The largest ripple current
occurs at the highest VIN. To guarantee that ripple current
does not exceed a specified maximum, the inductance
3770f
(3b)
Figure 3. Correcting Frequency Shift with Load Current Changes
13
LTC3770
U
W U U
APPLICATIO S I FOR ATIO
should be chosen according to:
The selection of COUT is primarily determined by the ESR
required to minimize voltage ripple and load step
transients. The output ripple ∆VOUT is approximately
bounded by:
⎛
⎞⎛
⎞
VOUT
f ∆I
VOUT
L =
1−
⎜
⎟⎜
⎟
V
⎝
⎠⎝
⎠
L(MAX)
IN(MAX)
⎛
⎞
1
Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
afford the core loss found in low cost powdered iron
cores, forcing the use of more expensive ferrite, molyper-
malloyorKoolMµ® cores. Avarietyofinductorsdesigned
for high current, low voltage applications are available
from manufacturers such as Sumida, Panasonic, Coil-
tronics, Coilcraft and Toko.
∆VOUT ≤ ∆IL ESR +
⎜
⎟
8fCOUT
⎝
⎠
Since ∆IL increases with input voltage, the output ripple is
highestatmaximuminputvoltage.Typically,oncetheESR
requirement is satisfied, the capacitance is adequate for
filtering and has the necessary RMS current rating.
Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, special polymer, aluminum electrolytic and
ceramic capacitors are all available in surface mount
packages. Special polymer capacitors offer very low ESR
but have lower capacitance density than other types.
Tantalum capacitors have the highest capacitance density
but it is important to only use types that have been surge
tested for use in switching power supplies. Aluminum
electrolytic capacitors have significantly higher ESR, but
can be used in cost-sensitive applications providing that
consideration is given to ripple current ratings and long
term reliability. Ceramic capacitors have excellent low
ESRcharacteristicsbutcanhaveahighvoltagecoefficient
and audible piezoelectric effects. The high Q of ceramic
capacitors with trace inductance can also lead to signifi-
cant ringing. When used as input capacitors, care must be
taken to ensure that ringing from inrush currents and
switching does not pose an overvoltage hazard to the
power switches and controller. To dampen input voltage
transients, add a small 5µF to 50µF aluminum electrolytic
capacitor with an ESR in the range of 0.5Ω to 2Ω. High
performance through-hole capacitors may also be used,
but an additional ceramic capacitor in parallel is recom-
mended to reduce the effect of their lead inductance.
Schottky Diode D1 Selection
The Schottky diode D1 shown in Figure 12 conducts
during the dead time between the conduction of the power
MOSFET switches. It is intended to prevent the body diode
ofthebottomMOSFETfromturningonandstoringcharge
during the dead time, which can cause a modest (about
1%) efficiency loss. The diode can be rated for about one
half to one fifth of the full load current since it is on for only
a fraction of the duty cycle. In order for the diode to be
effective, the inductance between it and the bottom MOS-
FET must be as small as possible, mandating that these
components be placed adjacently. The diode can be omit-
ted if the efficiency loss is tolerable.
CIN and COUT Selection
The input capacitance CIN is required to filter the square
wave current at the drain of the top MOSFET. Use a low
ESR capacitor sized to handle the maximum RMS current.
VOUT
V
IN
V
IN
IRMS ≅ IOUT(MAX)
– 1
VOUT
This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT(MAX)/2. This simple worst-case condition is
commonly used for design because even significant
deviations do not offer much relief. Note that ripple
current ratings from capacitor manufacturers are often
basedononly2000hoursoflifewhichmakesitadvisable
to derate the capacitor.
Top MOSFET Driver Supply (CB, DB)
AnexternalbootstrapcapacitorCBconnectedtotheBOOST
pinsuppliesthegatedrivevoltageforthetopsideMOSFET.
This capacitor is charged through diode DB from INTVCC
when the switch node is low. When the top MOSFET turns
Kool Mµ is a registered trademark of Magnetics, Inc.
3770f
14
LTC3770
U
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APPLICATIO S I FOR ATIO
on, the switch node rises to VIN and the BOOST pin rises
to approximately VIN + INTVCC. The boost capacitor needs
to store about 100 times the gate charge required by the
topMOSFET. Inmostapplications0.1µFto0.47µF, X5Ror
X7R dielectric capacitor is adequate.
transformer. However, if the controller goes into discon-
tinuous mode and halts switching due to a light primary
load current, then VOUT2 will droop. An external resistor
divider from VOUT2 to the FCB pin sets a minimum voltage
VOUT2(MIN) below which continuous operation is forced
until VOUT2 has risen above its minimum.
Discontinuous Mode Operation and FCB Pin
R4
R3
⎛
⎝
⎞
⎟
⎠
VOUT2(MIN) = 0.6V 1+
The FCB pin determines whether the bottom MOSFET
remains on when current reverses in the inductor. Tying
this pin above its 0.6V threshold enables discontinuous
operation where the bottom MOSFET turns off when
inductor current reverses. The load current at which
current reverses and discontinuous operation begins de-
pends on the amplitude of the inductor ripple current and
will vary with changes in VIN. Tying the FCB pin below the
0.6Vthresholdforcescontinuoussynchronousoperation,
allowing current to reverse at light loads and maintaining
high frequency operation. To prevent forcing current back
into the main power supply, potentially boosting the input
supply to a dangerous voltage level, forced continuous
modeofoperationisdisabledwhentheTRACK/SSvoltage
is 20% below the reference voltage during soft-start or
tracking up. Forced continuous mode of operation is also
disabledwhentheTRACK/SSvoltageisbelow0.1Vduring
tracking down operation. During these two periods, the
PGOOD signal is forced low.
⎜
Fault Conditions: Current Limit and Foldback
The maximum inductor current is inherently limited in a
currentmodecontrollerbythemaximumsensevoltage.In
the LTC3770, the maximum sense voltage is controlled by
the voltage on the VRNG pin. With valley current control,
the maximum sense voltage and the sense resistance
determine the maximum allowed inductor valley current.
The corresponding output current limit is:
VSNS(MAX)
1
2
ILIMIT
=
+ ∆IL
RDS(ON) ρT
The current limit value should be checked to ensure that
ILIMIT(MIN) >IOUT(MAX).Theminimumvalueofcurrentlimit
generally occurs with the largest VIN at the highest ambi-
ent temperature, conditions that cause the largest power
loss in the converter. Note that it is important to check for
self-consistency between the assumed MOSFET junction
temperature and the resulting value of ILIMIT which heats
the MOSFET switches.
In addition to providing a logic input to force continuous
operation, the FCB pin provides a mean to maintain a
flyback winding output when the primary is operating in
discontinuous mode. The secondary output VOUT2 is nor-
mally set as shown in Figure 5 by the turns ratio N of the
Caution should be used when setting the current limit
based upon the RDS(ON) of the MOSFETs. The maximum
current limit is determined by the minimum MOSFET on-
resistance. Data sheets typically specify nominal and
maximum values for RDS(ON), but not a minimum. A
reasonable assumption is that the minimum RDS(ON) lies
the same percentage below the typical value as the maxi-
mum lies above it. Consult the MOSFET manufacturer for
further guidelines.
V
C
IN
+
IN
V
IN
1N4148
V
TG
OUT2
OUT1
•
+
LTC3770
C
OUT2
SW
1µF
V
R4
R3
•
T1
1:N
+
C
FCB
OUT
To further limit current in the event of a short circuit to
ground, the LTC3770 includes foldback current limiting. If
the output falls by more than 60%, then the maximum
sense voltage is progressively lowered to about one tenth
of its full value.
BG
SGND
PGND
3770 F05
Figure 5. Secondary Output Loop
3770f
15
LTC3770
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APPLICATIO S I FOR ATIO
INTVCC Regulator
Soft-Start and Tracking
An internal P-channel low dropout regulator produces the
5V supply that powers the drivers and internal circuitry
within the LTC3770. The INTVCC pin can supply up to
50mA RMS and must be bypassed to ground with a
minimumof10µFlowESRtantalumcapacitororotherlow
ESR capacitor. Good bypassing is necessary to supply the
high transient currents required by the MOSFET gate
drivers. Applications using large MOSFETs with a high
input voltage and high frequency of operation may cause
theLTC3770toexceeditsmaximumjunctiontemperature
rating or RMS current rating. Most of the supply current
drives the MOSFET gates. In continuous mode operation,
thiscurrentisIGATECHG =f(Qg(TOP) +Qg(BOT)).Thejunction
temperature can be estimated from the equations given in
Note 2 of the Electrical Characteristics. For example, the
LTC3770EG is limited to less than 14mA from a 30V
supply:
TheLTC3770hastheabilitytoeithersoftstartbyitselfwith
acapacitorortracktheoutputofanothersupply.Whenthe
device is configured to soft start by itself, a capacitor
should be connected to the TRACK/SS pin. The LTC3770
is put in a low quiescent current shutdown state (IQ <
30µA)iftheRUNpinvoltageisbelow1.5V. TheTRACK/SS
pin is actively pulled to ground in this shutdown state.
Once the RUN pin voltage is above 1.5V, the LTC3770 is
powered up. A soft-start current of 1.4µA then starts to
charge the soft-start capacitor CSS. Pin Z1 must be
grounded for soft-start operation. Note that soft-start is
achieved not by limiting the maximum output current of
thecontrollerbutbycontrollingtheramprateoftheoutput
voltage. Current foldback is disabled during this soft-start
phase. During the soft-start phase, the LTC3770 is ramp-
ing the reference voltage until it is 20% below the voltage
set by the VREFIN pin. The force continuous mode is also
disabled and PGOOD signal is forced low during this
phase. The total soft-start time can be calculated as:
TJ = 70°C + (14mA)(30V)(130°C/W) = 125°C
ForapplicationswheremorecurrentisneededthanINTVCC
could supply, INTVCC could be driven by an external
supply with a voltage higher than 5.3V. However, the
INTVCC pin should not exceed its absolute maximum
voltage of 7V.
tSOFTSTART = 0.8 • VREFIN • CSS/1.4µA
When the device is configured to track another supply, the
feedback voltage of the other supply is duplicated by a
resistor divider and applied to the TRACK/SS pin. Pin Z1
should be tied to INTVCC to turn off the soft-start current
in this mode. Therefore, the voltage ramp rate on this pin
is determined by the ramp rate of the other supply output
voltage.
External Gate Drive Buffers
The LTC3770 drivers are adequate for driving up to about
BOOST
INTV
CC
Q1
Q3
Output Voltage Tracking
FMMT619
GATE
OF M1
FMMT619
10Ω
10Ω
GATE
OF M2
The LTC3770 allows the user to program how its output
ramps up and down by means of the TRACK/SS pin.
Through this pin, the output can be set up to either
coincidentallyorratiometricallytrackwithanothersupply’s
output, as shown in Figure 7. In the following discussions,
VOUT1 refers to the master LTC3770’s output and VOUT2
refers to the slave LTC3770’s output.
TG
BG
Q2
FMMT720
Q4
FMMT720
SW
PGND
3770 F06
Figure 6. Optional External Gate Driver
50nC into MOSFET switches with RMS currents of 50mA.
Applications with larger MOSFET switches or operating at
frequencies requiring greater RMS currents will benefit
fromusingexternalgatedrivebufferssuchastheLTC1693.
Alternately, the external buffer circuit shown in Figure 6
can be used.
ToimplementthecoincidenttrackinginFigure7a,connect
an additional resistive divider to VOUT1 and connect its
midpoint to the TRACK/SS pin of the slave IC. The ratio of
thisdividershouldbeselectedthesameasthatoftheslave
IC’s feedback divider shown in Figure 8. In this tracking
3770f
16
LTC3770
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APPLICATIO S I FOR ATIO
V
V
V
OUT1
OUT1
V
OUT2
OUT2
3770 F07
TIME
TIME
(7a) Coincident Tracking
(7b) Ratiometric Tracking
Figure 7. Two Different Modes of Output Voltage Tracking
V
OUT1
V
OUT1
V
V
OUT2
OUT2
R3
R4
R1
R2
R3
R4
R1
R2
R3
R4
TO
TO
TO
FB1
PIN
TO
FB2
PIN
TO
FB2
PIN
TO
V
TRACK/SS2
PIN
TRACK/SS2
PIN
V
V
V
FB1
PIN
3770 F08
(8a) Coincident Tracking Setup
(8b) Ratiometric Tracking Setup
Figure 8. Setup for Coincident and Ratiometric Tracking
there do exist some tradeoffs. The ratiometric mode saves
a pair of resistors, but the coincident mode offers better
output regulation. This can be better understood with the
help of Figure 9. At the input stage of the slave IC’s error
amplifier, two common anode diodes are used to clamp
the equivalent reference voltage and an additional diode is
used to match the shifted common mode voltage. The top
two current sources are of the same amplitude. In the
coincident mode, the TRACK/SS voltage is substantially
higher than 0.6V at steady state and effectively turns off
D1. D2andD3willthereforeconductthesamecurrentand
offer tight matching between VFB2 and the internal preci-
sion 0.6V reference. In the ratiometric mode, however,
TRACK/SS equals 0.6V at steady state. D1 will divert part
of the bias current to make VFB2 slightly lower than 0.6V.
Although this error is minimized by the exponential I-V
characteristic of the diode, it does impose a finite amount
ofoutputvoltagedeviation.Furthermore,whenthemaster
IC’s output experiences dynamic excursion (under load
transient, for example), the slave IC output will be affected
as well. For better output regulation, use the coincident
tracking mode instead of ratiometric.
I
I
+
–
D1
D2
EA2
TRACK/SS2
0.6V
D3
3770 F09
V
FB2
Figure 9. Equivalent Input Circuit of Error Amplifier
mode,VOUT1 mustbesethigherthanVOUT2.Toimplement
the ratiometric tracking, the ratio of the divider should be
exactly the same as the master IC’s feedback divider. Note
that the pin Z1 of the slave IC should be tied to INTVCC so
that the internal soft-start current is disabled in both
tracking modes or it will introduce a small error on the
tracking voltage depending on the absolute values of the
tracking resistive divider.
By selecting different resistors, the LTC3770 can achieve
different modes of tracking including the two in Figure 7.
So which mode should be programmed? While either
mode in Figure 7 satisfies most practical applications,
3770f
17
LTC3770
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APPLICATIO S I FOR ATIO
Margining
clock on the PLLIN pin. In turn, it will turn on the phase-
locked loop function. The pulse width of the clock has to
be greater than 400ns and the amplitude of the clock
should be greater than 2V.
Margining is a way to program the reference voltage to the
error amplifier to a voltage different from the default 0.6V.
Marginingisusefulforcustomerswhowanttostresstheir
systems by varying supply voltages during testing. The
reference voltage to the error amplifier is set according to
the following equation when the margining function is
enabled:
During the start-up phase, phase-locked loop function is
disabled. When LTC3770 is not in synchronization mode,
PLLFLTR pin voltage is set to around 1.18V. Frequency
synchronization is accomplished by changing the internal
on-time current according to the voltage on the PLLFLTR
pin.
V
REFIN = 0.6V ±(1.18V/R4) • R3
Referring to the functional diagram, 0.6V is the buffered
system reference at the VREFOUT pin. R3 and R4 are
resistorsusedforprogrammingtheamountofmargining.
The phase detector used is an edge sensitive digital type
which provides zero degrees phase shift between the
external and internal pulses. This type of phase detector
will not lock up on input frequencies close to the harmon-
ics of the VCO center frequency. The PLL hold-in range,
∆fH, is equal to the capture range, ∆fC:
V
REFIN should be a voltage between 0.5V and 1V.
Therearetwologiccontrolpins,MARGIN1andMARGIN0,
to determine whether the margining function is enabled,
Margin up(+) or Margin down(–). Table 1 summarizes the
configurations:
∆fH = ∆fC = ±0.3 fO
The output of the phase detector is a complementary pair
of current sources charging or discharging the external
filter network on the PLLFLTR pin. A simplified block
diagram is shown in Figure 10.
Table 1: Margining Function
MARGIN1
LOW
MARGIN0
LOW
Mode
No Margining
Margin Up
LOW
HIGH
HIGH
LOW
Margin Down
No Margining
If the external frequency (fPLLIN) is greater than the oscil-
lator frequency fO, current is sourced continuously, pull-
ing up the PLLFLTR pin. When the external frequency is
less than fO, current is sunk continuously, pulling down
the PLLFLTR pin. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. Thus the voltage on the PLLFLTR
pin is adjusted until the phase and frequency of the
external and internal oscillators are identical. At this stable
HIGH
HIGH
The buffered reference at VREFOUT has the ability to source
a large amount of current. However, it can only sink a
maximum of 50µA of current. To increase the sinking
capability of this reference, connect a resistor to ground at
this pin. One may also be tempted to connect a large
capacitor to this pin to filter out the noise. However, it is
recommended that no larger than 100pF of capacitance
should be connected to this pin.
R
LP
2.4V
C
LP
Phase-Locked Loop and Frequency Synchronization
PLLFLTR
VCO
The LTC3770 has a phase-locked loop comprised of an
internal voltage controlled oscillator and phase detector.
This allows the top MOSFET turn-on to be locked to the
rising edge of an external source. The frequency range of
the voltage controlled oscillator is ±30% around the
center frequency fO. The center frequency is the operating
frequencydiscussedintheprevioussection.TheLTC3770
incorporates a pulse detection circuit that will detect a
DIGITAL
PLLIN
PHASE/
FREQUENCY
DETECTOR
3770 F10
Figure 10. Phase-Locked Loop Block Diagram
3770f
18
LTC3770
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APPLICATIO S I FOR ATIO
operating point the phase comparator output is open and
the filter capacitor CLP holds the voltage. The LTC3770
PLLIN pin must be driven from a low impedance source
such as a logic gate located close to the pin.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Although all dissipative
elements in the circuit produce losses, four main sources
account for most of the losses in LTC3770 circuits:
1. DC I2R losses. These arise from the resistances of the
MOSFETs, inductor and PC board traces and cause the
efficiency to drop at high output currents. In continuous
mode the average output current flows through L, but is
chopped between the top and bottom MOSFETs. If the two
MOSFETs have approximately the same RDS(ON), then the
resistanceofoneMOSFETcansimplybesummedwiththe
resistances of L and the board traces to obtain the DC I2R
loss.Forexample,ifRDS(ON) =0.01ΩandRL =0.005Ω,the
loss will range from 15mW to 1.5W as the output current
varies from 1A to 10A.
The loop filter components (CLP, RLP) smooth out the
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
components CLP and RLP determine how fast the loop
acquires lock. Typically RLP =10kΩ and CLP is 0.01µF to
0.1µF.
Dead Time Control
To further optimize the efficiency, the LTC3770 gives
users some control over the dead time of the Top gate low
and Bottom gate high transition. By applying a DC voltage
on the Z0 pin, the TG low BG high dead time can be
programmed. Because the dead time is a strong function
of the load current and the type of MOSFET used, users
need to be careful to optimize the dead time for their
particular applications. Figure 11 shows the relation be-
tween the TG Low BG High Dead time by varying the Z0
voltages. For an application using LTC3770 with load
currentof5AandIR7811WMOSFETs,thedeadtimecould
be optimized. To make sure that there is no shoot-through
under all conditions, a dead time of 70ns is selected. This
corresponds to a DC voltage about 2.6V on Z0 pin. This
voltage can easily be generated with a resistor divider off
INTVCC.
2. Transition loss. This loss arises from the brief amount
of time the top MOSFET spends in the saturated region
duringswitchnodetransitions.Itdependsupontheinput
voltage, load current, driver strength and MOSFET
capacitance, among other factors. The loss is significant
at input voltages above 20V and can be estimated from:
Transition Loss ≅ (1.7A–1) VIN IOUT CRSS
f
2
3. INTVCC current. This is the sum of the MOSFET driver
and control currents.
180
160
140
120
100
80
4. CIN loss. The input capacitor has the difficult job of
filtering the large RMS input current to the regulator. It
must have a very low ESR to minimize the AC I2R loss and
sufficient capacitance to prevent the RMS current from
causing additional upstream losses in fuses or batteries.
60
Other losses, including COUT ESR loss, Schottky diode D1
conduction loss during dead time and inductor core loss
generally account for less than 2% additional loss.
40
20
I
= 5A
0
OUT
IRT811W FETs
–20
2
3
4
0
5
1
When making adjustments to improve efficiency, the
input current is the best indicator of changes in efficiency.
Z0 VOLTAGE (V)
3770 F11
Figure 11. TG Low BG High Dead Time vs Z0 Voltage
3770f
19
LTC3770
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APPLICATIO S I FOR ATIO
Ifyoumakeachangeandtheinputcurrentdecreases,then
the efficiency has increased. If there is no change in input
current, then there is no change in efficiency.
TyingVRNG to1.1V willsetthecurrentsensevoltagerange
for a nominal value of 110mV with current limit occurring
at 146mV. To check if the current limit is acceptable,
assume a junction temperature of about 80°C above a
70°C ambient with ρ150°C = 1.5:
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
equal to ∆ILOAD (ESR), where ESR is the effective series
resistance of COUT. ∆ILOAD also begins to charge or
dischargeCOUT generatingafeedbackerrorsignalusedby
the regulator to return VOUT to its steady-state value.
During this recovery time, VOUT can be monitored for
overshoot or ringing that would indicate a stability prob-
lem. The ITH pin external components shown in Figure 12
will provide adequate compensation for most applica-
tions. For a detailed explanation of switching control loop
theory see Application Note 76.
146mV
1.5 0.010Ω
1
2
ILIMIT
≥
+
2.8A = 11A
(
)
(
)(
)
and double check the assumed TJ in the MOSFET:
28 V –2.5V
28 V
2
PBOT
=
11A 1.5 0.010Ω = 1.65W
( ) ( )(
)
TJ = 70°C + (1.65W)(40°C/W) = 136°C
Because the top MOSFET is on for such a short time, an
Si4884 RDS(ON)(MAX) = 0.0165Ω, CRSS = 100pF, θJA
40°C/W will be sufficient. Checking its power dissipation
at current limit with ρ100°C = 1.4:
=
2.5V
28V
2
PTOP
=
11A 1.4 0.0165Ω +
) ( )(
(
)
Design Example
2
1.7 28V 11A 100pF 250kHz
)( ) ( )( )(
(
)
As a design example, take a supply with the following
specifications:VIN =5Vto28V(15Vnominal), VOUT =2.5V
±5%, IOUT(MAX) = 10A, f = 450kHz. First, calculate the
= 0.25W + 0.37W = 0.62W
TJ = 70°C + (0.62W)(40°C/W) = 95°C
timing resistor with VON = VOUT
:
The junction temperature will be significantly less at
nominal current, but this analysis shows that careful
attention to heat sinking on the board will be necessary in
this circuit.
2.5V
RON
=
= 74kΩ
3 2.5V 450kHz 10pF
)( )(
and choose the inductor for about 40% ripple current at
the maximum VIN:
(
)
CIN is chosen for an RMS current rating of about 3A at
85°C. The output capacitors are chosen for a low ESR of
0.013Ω to minimize output voltage changes due to induc-
tor ripple current and load steps. The ripple voltage will be
only:
2.5V
450kHz 0.4 10A
2.5V
28V
⎛
⎜
⎝
⎞
⎟
⎠
L =
1−
= 1.3µH
(
)( )(
)
Selecting a standard value of 1.8µH results in a maximum
ripple current of:
∆VOUT(RIPPLE) = ∆IL(MAX) (ESR)
= (2.8A) (0.013Ω) = 36mV
2.5V
450kHz 1.8µH
2.5V
28V
⎛
⎜
⎝
⎞
⎟
⎠
∆IL =
1–
= 2.8A
However, a 0A to 10A load step will cause an output
change of up to:
(
)(
)
Next, choose the synchronous MOSFET switch. Choosing
a Si4874 (RDS(ON) = 0.0083Ω (NOM) 0.010Ω (MAX),
θJA = 40°C/W) yields a nominal sense voltage of:
∆VOUT(STEP) =∆ILOAD (ESR)=(10A)(0.013Ω)=130mV
An optional 22µF ceramic output capacitor is included to
minimize the effect of ESL in the output ripple. The
VSNS(NOM) = (10A)(1.3)(0.0083Ω) = 108mV
complete circuit is shown in Figure 12.
3770f
20
LTC3770
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APPLICATIO S I FOR ATIO
INTV
5V
CC
R
PG
100k
R7
47k
V
IN
5V TO 28V
LTC3770EG
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RUN
RUN
FCB
Z0
R8
51k
M1
V
ON
C
IN
R5
39k
Si4884
3
10µF
50V
x3
PGOOD
BOOST
TG
4
V
RNG
5
V
FB
SW
R6
11k
L1
1.8µH
6
+
+
I
TH
PGND
BG
CB
7
0.22µF
V
2.5V
10A
SGND
OUT
8
MARGIN1
MARGIN0
INTV
CC
9
DB
CMDSH-3
Z1
+
D1
10
11
12
13
14
C
OUT1-2
B340A
I
ON
Z2
180µF
4V
R
V
V
Z
VIN
C
REFIN
x2
R3
10k
20k
V
REFOUT
IN
PLLIN
TRACK/SS PLLFLTR
CC2
100pF
M2
Si4874
C
OUT3
MPGM
23µF
x5R
x2
CV
IN
0.1µF
R
CC1
500pF
CV
CC
10µF
ON
75k
C
SS
0.1µF
R2
95.3k
L1: SUMIDA CEP125-1R8MC-H
R1
30.1k
R4
82k
C
C
: CORNELL DUBILIER ESRE181E04B
OUT
: UNITED CHEMICON THCR60E1H106ZT
IN
3770 F12
Figure 12. Design Example: 2.5V/10A at 450kHz
To set a ±25% margining, select the resistors R3, R4 such
that
it should be as close as possible to the layer with power
MOSFETs.
VREFIN = 0.6 ±25% • 0.6
• Place CIN, COUT, MOSFETs, D1 and inductor all in one
compactarea.Itmayhelptohavesomecomponentson
the bottom side of the board.
or
1.18 •R3
= 25%• 0.6
R4
•
Use an immediate via to connect the components to
ground plane including SGND and PGND of LTC3770.
Use several bigger vias for power components.
R4 ≈ 8R3
• Use compact plane for switch node (SW) to improve
cooling of the MOSFETs and to keep EMI down.
Choose R3 to be 10k, R4 to be 82k for this application.
PC Board Layout Checklist
• Use planes for VIN and VOUT to maintain good voltage
filtering and to keep power losses low.
When laying out a PC board follow one of two suggested
approaches. The simple PC board layout requires a dedi-
cated ground plane layer. Also, for higher currents, it is
recommended to use a multilayer board to help with heat
sinking power components.
• Flood all unused areas on all layers with copper. Flood-
ing with copper will reduce the temperature rise of
powercomponent.Youcanconnectthecopperareasto
any DC net (VIN, VOUT, GND or to any other DC rail in
your system).
• The ground plane layer should not have any traces and
3770f
21
LTC3770
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APPLICATIO S I FOR ATIO
When laying out a printed circuit board, without a ground
plane, use the following checklist to ensure proper opera-
tion of the controller.
MOSFETs. This capacitor carries the MOSFET AC
current.
• Keep the high dV/dt SW, BOOST and TG nodes away
from sensitive small-signal nodes.
• Segregate the signal and power grounds. All small
signal components should return to the SGND pin at
onepointwhichisthentiedtothePGNDpinclosetothe
source of M2.
• Connect the INTVCC decoupling capacitor CVCC closely
to the INTVCC and PGND pins.
• Connect the top driver boost capacitor CB closely to the
BOOST and SW pins.
• Place M2 as close to the controller as possible, keeping
the PGND, BG and SW traces short.
• Connect the VIN pin decoupling capacitor CF closely to
the VIN and PGND pins.
•
Connect the input capacitor(s) CIN close to the power
U
PACKAGE DESCRIPTIO
G Package
28-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
9.90 – 10.50*
(.390 – .413)
28 27 26 25 24 23 22 21 20 19 18
16 15
17
1.25 ±0.12
7.8 – 8.2
5.3 – 5.7
7.40 – 8.20
(.291 – .323)
0.42 ±0.03
0.65 BSC
5
7
8
1
2
3
4
6
9 10 11 12 13 14
RECOMMENDED SOLDER PAD LAYOUT
2.0
(.079)
MAX
5.00 – 5.60**
(.197 – .221)
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.25
0.55 – 0.95
(.0035 – .010)
(.022 – .037)
0.05
0.22 – 0.38
(.009 – .015)
TYP
(.002)
NOTE:
MIN
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
G28 SSOP 0204
3. DRAWING NOT TO SCALE
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
3770f
22
LTC3770
U
PACKAGE DESCRIPTIO
UH Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693)
BOTTOM VIEW—EXPOSED PAD
0.23 TYP
(4 SIDES)
0.75 ± 0.05
R = 0.115
TYP
5.00 ± 0.10
(4 SIDES)
0.00 – 0.05
31 32
0.70 ±0.05
0.40 ± 0.10
5.50 ±0.05
PIN 1
TOP MARK
(NOTE 6)
1
2
3.45 ±0.05
(4 SIDES)
3.45 ± 0.10
(4-SIDES)
4.10 ±0.05
PACKAGE
OUTLINE
(UH) QFN 0603
0.200 REF
0.25 ± 0.05
0.50 BSC
0.25 ± 0.05
0.50 BSC
NOTE:
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
RECOMMENDED SOLDER PAD LAYOUT
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
U
TYPICAL APPLICATIO
1.8V/5A at 450kHz with Tracking
L1: BI TECH 1.8µH HM65-H1R8-TB
M1, M2: PHILIPS PH3230
R
C
C
: TDK C4532X5R1H685M
PG
IN
OUT
100k
: PANASONIC EEFUE0G181R
PGOOD
RUN
FCB
V
IN
4V TO 28V
R7
47k
32
31
30
29
28
27
26
25
M1
PH3230
PGOOD
V
RUN FCB Z0 BOOST TG
SW
ON
R8
51k
R
RUN
51k
24
23
22
21
20
19
18
17
1
2
SENSE+
V
V
RNG
L1
1.8µH
SENSE–
PGND
BG
1000pF
FB
CB
V
1.8V
5A
OUT
3
4
5
6
7
8
0.22µF
I
TH
SGND
LTC3770EUH
R
10k
C
DRV
MARGIN1
MARGIN0
MARGIN1
MARGIN0
CC
CC
Z2
Z1
DB
D1
R2
C
F
CMDSH-3 B340A
60.4k
INTV
220pF
I
ON
CC2
100pF
M2
PH3230
+
R1
V
REFIN
R
C
ON
OUT
30.1k
75k
180µF
CC1
1000pF
4V
x2
V
MPGM TRACK/SS PLLFLTR PLLIN
V
V
ZV
REFOUT
IN
14
INSNS
IN
INTV
CC
R5
10k
9
10
11
12
13
15
16
+
CV
CC
10µF
C
C
OUT3
IN
22µF
X5R
x2
6.8µF
TRACK/SS
50V
x3
V
5V
R6
200k
CC
3770 TA02a
3770f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will notinfringe onexisting patent rights.
23
LTC3770
U
TYPICAL APPLICATIO
Typical Application 2.5V/10A Synchronized at 450kHz
L1: BI TECH 1.8µH HM65-H1R8-TB
M1, M2: PHILIPS PH3230
R
PG
100k
C
C
: TDK C4532X5R1H685M
IN
OUT
: PANASONIC EEFUE0G181R
PGOOD
RUN
FCB
V
IN
5V TO 28V
R7
47k
32
31
30
29
28
27
26
25
M1
PH3230
R8
51k
PGOOD
V
RUN FCB Z0 BOOST TG
SW
R4
R
RUN
51k
ON
39k
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
V
V
SENSE+
RNG
L1
1.8µH
SENSE–
PGND
BG
1000pF
FB
R3
CB
V
2.5V
10A
OUT
11k
0.22µF
I
TH
SGND
LTC3770EUH
R
C
DRV
MARGIN1
MARGIN0
MARGIN1
MARGIN0
CC
CC
Z2
Z1
10k
DB
D1
R2
C
F
CMDSH-3 B340A
95.3k
INTV
220pF
I
ON
CC2
100pF
M2
+
V
REFIN
C
PH3230
OUT
R1
30.1k
R
180µF
ON
75k
4V
x2
CC1
1000pF
INTV
CC
V
MPGM TRACK/SS PLLFLTR PLLIN
V
V
ZV
IN
REFOUT
IN
INSNS
R5
10k
9
10
11
12
13
14
15
16
CV
CC
10µF
C
C
OUT3
IN
22µF
X5R
x2
10µF
PLLIN
R
PL
10k
50V
x3
0.1µF
RV
IN
R6
C
CV
IN
0.01µF
C
C
P
1000pF
SS
PL
0.01µF
10Ω
82k 0.1µF
3770 TA02b
RELATED PARTS
PART NUMBER
LTC1622
DESCRIPTION
550kHz Step-Down Controller
No R Current Mode Synchronous Step-Down Controller
COMMENTS
8-Pin MSOP; Synchronizable; Soft-Start; Current Mode
97% Efficiency; No Sense Resistor; 16-Pin SSOP
Power Good Output; Minimum Input/Output Capacitors;
LTC1625/LTC1775
LTC1628/LTC3728
SENSE
Dual, 2-Phase Synchronous Step-Down Controller
3.5V ≤ V ≤ 36V
IN
LTC1735
High Efficiency, Synchronous Step-Down Controller
Burst Mode® Operation; 16-Pin Narrow SSOP;
3.5V ≤ V ≤ 36V
IN
LTC1736
LTC1772
LTC1773
High Efficiency, Synchronous Step-Down Controller with 5-Bit VID Mobile VID; 0.925V ≤ V
≤ 2V; 3.5V ≤ V ≤ 36V
OUT IN
SOT-23 Step-Down Controller
Current Mode; 550kHz; Very Small Solution Size
Up to 95% Efficiency, 550kHz, 2.65V ≤ V ≤ 8.5V,
Synchronous Step-Down Controller
IN
0.8V ≤ V
≤ V , Synchronizable to 750kHz
OUT
IN
LTC1778
LTC1876
Wide Range, No R
Synchronous Step-Down Controller
GN16-Pin, 0.8V Reference
FB
SENSE
2-Phase, Dual Synchronous Step-Down Controller with
Step-Up Regulator
3.5V ≤ V ≤ 36V, Power Good Output, 300kHz Operation
IN
LTC3708
Dual, 2-Phase, No R
Output Tracking
Synchronous Step-Down Controller with Fast Transient Response Reduces C ; 4V ≤ V ≤ 36V,
SENSE OUT IN
0.6V ≤ V
≤ 6V; 2-Phase Operation Reduces C
OUT
IN
LTC3713
LTC3731
LTC3778
Low V High Current Synchronous Step-Down Controller
1.5V ≤ V ≤ 36V, 0.8V ≤ V
≤ (0.9)V , I Up to 20A
IN OUT
IN
IN
OUT
3-Phase Synchronous Step-Down Controller
600kHz; Up to 60A Output
Low V , No R
Synchronous Step-Down Controller
0.6V ≤ V
≤ (0.9)V , 4V ≤ V ≤ 36V, I
Up to 20A
OUT
SENSE
OUT
IN
IN
OUT
Burst Mode is a registered trademark of Linear Technology Corporation.
3770f
LT/TP 1104 1K • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
©LINEAR TECHNOLOGY CORPORATION 2004
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