LTC3717EUH-1#TRPBF [Linear]
LTC3717-1 - Wide Operating Range, No RSENSE Step-Down Controller for DDR/QDR Memory Termination; Package: QFN; Pins: 32; Temperature Range: -40°C to 85°C;
| 型号： | LTC3717EUH-1#TRPBF |
| 厂家： | 
Linear |
| 描述： | LTC3717-1 - Wide Operating Range, No RSENSE Step-Down Controller for DDR/QDR Memory Termination; Package: QFN; Pins: 32; Temperature Range: -40°C to 85°C 双倍数据速率 开关 |
| 文件： | 总20页 (文件大小：269K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3717-1
Wide Operating Range,
No RSENSETM Step-Down Controller
for DDR/QDR Memory Termination
U
DESCRIPTIO
FEATURES
The LTC®3717-1 is a synchronous step-down switching
regulator controller for double data rate (DDR) and Quad
Data RateTM (QDRTM) memory termination. The controller
uses a valley current control architecture to deliver very
lowdutycycleswithorwithoutasenseresistor. Operating
frequency is selected by an external resistor and is com-
■
VOUT = 1/2 VREF
■
Adjustable and Symmetrical Sink/Source
Current Limit up to 20A
■
True Current Mode Control with Optional Use of
Sense Resistor
■
VON and ION Pins Allow Constant Frequency
Operation During Input and Output Voltage Changes
±0.65% Output Voltage Accuracy
Up to 97% Efficiency
pensated for variations in VIN and VOUT
.
■
■
■
■
■
■
■
■
■
■
■
■
Forced continuous operation reduces noise and RF inter-
ference. Output voltage is internally set to half of VREF
which is user programmable.
,
Ultrafast Transient Response
2% to 90% Duty Cycle at 200kHz
t
ON(MIN) ≤ 100ns
Fault protection is provided by an output overvoltage
comparator and optional short-circuit shutdown timer.
Soft-start capability for supply sequencing is accom-
plished using an external timing capacitor. The regulator
current limit level is symmetrical and user programmable.
Wide supply range allows operation from 4V to 36V at the
VCC input.
Stable with Ceramic COUT
Power Good Output Voltage Monitor
Wide VIN Range: 4V to 36V
Adjustable Switching Frequency up to 1.5MHz
Output Overvoltage Protection
Optional Short-Circuit Shutdown Timer
Available in a 5mm × 5mm QFN Package
U
, LTC and LT are registered trademarks of Linear Technology Corporation.
No RSENSE is a trademark of Linear Technology Corporation.
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress
Semiconductor, Hitachi, IDT, Micron Technology, Inc. and Samsung.
APPLICATIO S
■
Bus Termination: DDR and QDR Memory, SSTL,
HSTL, ...
■
Notebook Computers, Desktop Servers
■
Tracking/Margining Power Supply
U
TYPICAL APPLICATIO
V
CC
5V TO 28V
Efficiency vs Load Current
715k
1µF
V
CC
V
IN
I
ON
2.5V TO 5.5V
100
90
80
70
60
50
40
30
20
10
0
V = 1.25V
OUT
+
+
150µF
6.3V
×2
0.1µF
V
DD
= 2.5V
V
REF
Si7840DP
Si7840DP
RUN/SS
TG
B320A
V
= 5V
IN
LTC3717-1
SW
V
OUT
470pF
V
IN
= 2.5V
+
20k
SENSE
BOOST
1.25V
0.22µF
0.68µH
I
TH
±10A
180µF
4V
×2
CMDSH-3
DRV
SGND INTV
CC
CC
V
ON
BG
B320A
+
4.7µF
PGOOD PGND
–
SENSE
37171 F01a
V
FB
0
2
4
6
8
10
12
14
LOAD CURRENT (A)
37171 F01b
Figure 1. High Efficiency DDR Memory Termination Supply
sn37171 37171fs
1
LTC3717-1
W W
U W
U W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
TOP VIEW
Boosted Topside Driver Supply Voltage
(BOOST) ............................................... 42V to –0.3V
VIN, ION, SW, SENSE+ Voltage .................. 36V to –0.3V
EXTVCC, DRVCC, RUN/SS, PGOOD,
(BOOST – SW) Voltages ............................ 7V to –0.3V
VON, VREF, VRNG Voltages .......(INTVCC + 0.3V) to –0.3V
ITH, VFB Voltages...................................... 2.7V to –0.3V
TG, BG, INTVCC, EXTVCC, DRVCC Peak Currents ....... 2A
TG, BG, INTVCC, EXTVCC, DRVCC RMS Currents.. 50mA
Operating Ambient Temperature
Range (Note 4) ................................... –40°C to 85°C
Junction Temperature (Note 2)............................ 125°C
Storage Temperature Range ................. –65°C to 125°C
Reflow Peak Body Temperature............................ 260°C
32 31 30 29 28 27 26 25
V
1
2
3
4
5
6
7
8
24 SW
ON
+
–
PGOOD
23 SENSE
V
NC
22
21
RNG
I
SENSE
TH
33
SGND
20 PGND
BG
I
19
18 DRV
ON
V
FB
CC
NC
17 INTV
CC
9
10 11 12 13 14 15 16
UH PACKAGE
32-LEAD (5mm × 5mm) PLASTIC QFN
TJMAX = 125°C, θJA = 34°C/ W
EXPOSED PAD IS SGND (PIN 33) MUST BE SOLDERED TO PCB
ORDER PART NUMBER
LTC3717EUH-1
QFN PART MARKING
37171
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VIN = 15V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Buck Regulator
I
Input DC Supply Current (V )
Normal
Shutdown Supply Current
Q(VIN)
IN
1000
15
2000
30
µA
µA
V
= 0V
RUN/SS
V
Feedback Voltage Accuracy
Feedback Voltage Line Regulation
Feedback Voltage Load Regulation
Error Amplifier Transconductance
On-Time
I
= 1.2V (Note 3), V = 2.4V
REF
●
●
–0.65
0.93
0.1
0.65
%
%/V
%
FB
TH
∆V
∆V
V
= 4V to 36V, I = 1.2V (Note 3)
0.002
–0.05
1.13
FB(LINE)
IN
TH
TH
TH
I
I
= 0.5V to 1.9V (Note 3)
= 1.2V (Note 3)
–0.3
1.33
FB(LOAD)
g
mS
m(EA)
t
I
I
= 30µA, V = 0V
186
95
233
115
280
135
ns
ns
ON
ON
ON
ON
= 60µA, V = 0V
ON
t
t
Minimum On-Time
I
= 180µA
50
100
400
ns
ns
ON(MIN)
OFF(MIN)
ON
Minimum Off-Time
300
V
Maximum Current Sense Threshold
V
V
V
= 1V, V = V /2 – 50mV
●
●
●
108
76
148
135
95
185
162
114
222
mV
mV
mV
SENSE(MAX)
RNG
RNG
RNG
FB
REF
V
– V (Source)
= 0V, V = V /2 – 50mV
PGND
SW
FB REF
= INTV , V = V /2 – 50mV
CC FB
REF
V
Minimum Current Sense Threshold
– V (Sink)
V
V
V
= 1V, V = V /2 + 50mV
●
●
●
–140
–97
–200
–165
–115
–235
–190
–133
–270
mV
mV
mV
SENSE(MIN)
RNG
RNG
RNG
FB
REF
V
= 0V, V = V /2 + 50mV
PGND
SW
FB REF
= INTV , V = V /2 + 50mV
CC FB
REF
sn37171 37171fs
2
LTC3717-1
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VIN = 15V, unless otherwise noted.
SYMBOL
∆V
PARAMETER
CONDITIONS
MIN
TYP
10
MAX
UNITS
%
Output Overvoltage Fault Threshold
Output Undervoltage Threshold
RUN Pin Start Threshold
RUN Pin Latchoff Enable
RUN Pin Latchoff Threshold
Soft-Start Charge Current
Soft-Start Discharge Current
8
12
FB(OV)
V
V
V
V
–25
1.5
4
%
FB(UV)
●
0.8
2
V
RUN/SS(ON)
RUN/SS(LE)
RUN/SS(LT)
RUN/SS(C)
RUN/SS(D)
RUN/SS Pin Rising
RUN/SS Pin Falling
4.5
4.2
–3
3
V
3.5
–1.2
1.8
V
I
I
V
V
= 0V
–0.5
0.8
µA
µA
RUN/SS
RUN/SS
= 4.5V, V = 0V
FB
V
V
Undervoltage Lockout
V
V
Falling
Rising
●
●
3.4
3.5
3.9
4.0
V
V
IN(UVLO)
IN
IN
IN
TG R
TG R
BG R
BG R
TG Driver Pull-Up On Resistance
TG Driver Pull-Down On Resistance
BG Driver Pull-Up On Resistance
BG Driver Pull-Down On Resistance
TG Rise Time
TG High (Note 5)
TG Low (Note 5)
BG High (Note 5)
BG Low (Note 5)
2
2
Ω
Ω
UP
DOWN
UP
3
Ω
1
Ω
DOWN
TG t
TG t
C
C
C
C
= 3300pF
= 3300pF
= 3300pF
= 3300pF
20
20
20
20
ns
ns
ns
ns
r
f
LOAD
LOAD
LOAD
LOAD
TG Fall Time
BG t
BG t
BG Rise Time
r
BG Fall Time
f
Internal V Regulator
CC
V
Internal V Voltage
6V < V < 30V, V = 4V
EXTVCC
●
●
4.7
4.5
5
5.3
V
%
INTVCC
CC
CC
∆V
Internal V Load Regulation
I
I
I
= 0mA to 20mA, V = 4V
EXTVCC
–0.1
4.7
±2
LDO(LOADREG)
CC
CC
CC
CC
V
EXTV Switchover Voltage
= 20mA, V
= 20mA, V
Rising
= 5V
V
EXTVCC
CC
EXTVCC
EXTVCC
∆V
∆V
EXTV Switch Drop Voltage
150
200
300
mV
mV
EXTVCC
CC
EXTV Switchover Hysteresis
EXTVCC(HYS)
CC
PGOOD Output
∆V
∆V
∆V
PGOOD Upper Threshold
PGOOD Lower Threshold
PGOOD Hysteresis
V
V
V
Rising (0% = 1/3 V
Falling (0% = 1/3 V
)
8
10
–10
1
12
–12
2
%
%
%
V
FBH
FB
REF
)
–8
FBL
FB
REF
Returning (0% = 1/3 V )
REF
FB(HYS)
FB
V
PGOOD Low Voltage
I
= 5mA
0.15
0.4
PGL
PGOOD
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 4: The LTC3717EUH-1 is guaranteed to meet performance
specifications from 0°C to 70°C. Specifications over the –40°C to 85°C
operating temperature range are assured by design, characterization and
correlation with statistical process controls.
Note 2: T is calculated from the ambient temperature T and power
J
A
dissipation P as follows:
D
Note 5: R
test.
limit guaranteed by design and/or correlation to static
LTC3717EUH-1: T = T + (P • 34°C/W)
Note 3: The LTC3717EUH-1 is tested in a feedback loop that adjusts V to
DS(ON)
J
A
D
FB
achieve a specified error amplifier output voltage (I ).
TH
sn37171 37171fs
3
LTC3717-1
U W
TYPICAL PERFOR A CE CHARACTERISTICS
VOUT/VIN Tracking Ratio
vs Input Voltage
Efficiency vs Load Current
Frequency vs Input Voltage
100
90
80
70
60
50
40
30
20
10
0
50.00
49.95
49.90
49.85
49.80
49.75
49.70
49.65
450
400
350
300
250
200
150
100
50
V
IN
V
OUT
= 2.5V
= 1.25V
LOAD = 0A
LOAD = 10A
LOAD = 1A
LOAD = 0A
LOAD = 10A
V
= 1.25V
FIGURE 1 CIRCUIT
OUT
FIGURE 1 CIRCUIT
10 100
FIGURE 1 CIRCUIT
0
0.01
0.1
1
1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9
INPUT VOLTAGE (V)
1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9
INPUT VOLTAGE (V)
LOAD CURRENT (A)
37171 G01
37171 G02
37171 G03
Load-Step Transient
Start-Up Response
VOUT
200mV/DIV
VOUT
1V/DIV
IL
IL
5A/DIV
2A/DIV
VIN = 2.5V
20µs/DIV
37171 G05
VIN = 2.5V
4ms/DIV
37171 G06
VOUT = 1.25V
LOAD = 500mA TO 10A STEP
FIGURE 1 CIRCUIT
VOUT = 1.25V
LOAD = 0.2Ω
FIGURE 1 CIRCUIT
On-Time vs VON Voltage
Load Regulation
On-Time vs Temperature
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
300
250
200
150
1000
800
600
400
200
0
I
= 30µA
V
V
= 2.5V
I
= 30µA
ION
IN
OUT
ION
= 1.25V
100
50
0
FIGURE 1 CIRCUIT
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
–50 –25
0
25
50
75
100 125
LOAD CURRENT (A)
V
VOLTAGE (V)
TEMPERATURE (°C)
ON
37171 G04
37171 G07
37171 G08
sn37171 37171fs
4
LTC3717-1
U W
TYPICAL PERFOR A CE CHARACTERISTICS
RUN/SS Latchoff Thresholds
vs Temperature
On-Time vs ION Current
INTVCC Load Regulation
10k
1k
0
–0.1
–0.2
–0.3
–0.4
–0.5
3
2
V
= 0V
VON
PULL-DOWN CURRENT
1
0
100
10
PULL-UP CURRENT
–1
–2
1
10
100
0
10
20
30
40
50
–50 –25
0
25
50
75 100 125
I
CURRENT (µA)
ON
TEMPERATURE (°C)
INTV LOAD CURRENT (mA)
CC
37171 G09
37171 G10
37171 G11
RUN/SS Latchoff Thresholds
vs Temperature
Undervoltage Lockout Threshold
vs Temperature
Maximum Current Sense Threshold
vs VRNG Voltage
300
250
200
150
100
50
5.0
4.5
4.0
3.5
4.0
3.5
3.0
2.5
LATCHOFF ENABLE
LATCHOFF THRESHOLD
0
3.0
2.0
0.50
1.00 1.25 1.50
(V)
1.75 2.00
0.75
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
V
TEMPERATURE (°C)
TEMPERATURE (C)
RNG
37171 G14
37171 G12
37171 G13
Error Amplifier gm
vs Temperature
Maximum Current Sense Threshold
vs Temperature, VRNG = 1V
Maximum Current Sense Threshold
vs RUN/SS Voltage, VRNG = 1V
180
160
140
120
100
80
1.50
1.40
1.30
1.20
1.10
1.00
0.90
0.80
0.70
160
140
120
100
80
60
60
40
40
20
20
0
0
2.4
2.0 2.2
2.6 2.8 3.0 3.2 3.4 3.6
110
110
130
–50
10 30 50
90
130
–50
10 30 50
90
–30 –10
70
–30 –10
70
RUN/SS (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
37171 G15
37171 G16
37171 G17
sn37171 37171fs
5
LTC3717-1
U
U
U
PI FU CTIO S
VON (Pin 1): On-Time Voltage Input. Voltage trip point for
the on-time comparator. Tying this pin to the output
voltage makes the on-time proportional to VOUT. The
comparatorinputdefaultsto0.7Vwhenthepinisgrounded,
2.4V when the pin is tied to INTVCC.
goodthreshold, andshort-circuitshutdownthreshold. Do
not apply more than 3V on VREF. If higher voltages are
used, connect an external resistor (R1 ≥ 160k) from
voltage reference to VREF
.
EXTVCC (Pin 15): External VCC Input. When EXTVCC
exceeds 4.7V, an internal switch connects this pin to
INTVCC and shuts down the internal regulator so that
controller and gate drive power is drawn from EXTVCC. Do
not exceed 7V at this pin and ensure that EXTVCC < VIN.
PGOOD (Pin 2): Power Good Output. Open-drain logic
output that is pulled to ground when the output voltage is
not within ±10% of the regulation point.
V
RNG (Pin 3): Sense Voltage Range Input. The voltage at
this pin is ten times the nominal sense voltage at maxi-
mum output current and can be set from 0.5V to 2V by a
resistive divider from INTVCC. The nominal sense voltage
defaults to 70mV when this pin is tied to ground, 140mV
when tied to INTVCC.
VIN (Pin 16): Main Input Supply. Decouple this pin to
PGND with an RC filter (1Ω, 0.1µF).
INTVCC (Pin 17): Internal Regulator Output. The control
circuits are powered from this voltage when VIN is greater
than 5V. Decouple this pin to power ground with a mini-
mum of 4.7µF low ESR tantalum or ceramic capacitor.
ITH (Pin 4): Current Control Threshold and Error Amplifier
Compensation Point. The current comparator threshold
increases with this control voltage. The voltage ranges
from 0V to 2.4V with 0.8V corresponding to zero sense
voltage (zero current).
DRVCC (Pin 18): Voltage Supply to Bottom Gate Driver.
Normally connected to the INTVCC pin through a decoup-
lingRCfilter(1Ω/0.1µF).Decouplethispintopowerground
with a minimum of 4.7µF low ESR tantalum or ceramic
capacitor. Do not exceed 7V at this pin.
SGND (Pin 5)/Exposed Pad (Pin 33): Signal Ground. All
small-signalcomponentsandcompensationcomponents
should connect to this ground, which in turn connects to
PGND at one point. Pin 5 is electrically connected to the
exposed pad. Exposed pad must be soldered to PCB.
BG (Pin 19): Bottom Gate Drive. Drives the gate of the
bottom N-channel MOSFET between ground and DRVCC.
PGND(Pin20):PowerGround.Connectthesepinsclosely
to the source of the bottom N-channel MOSFET, the (–)
terminal of CVCC and the (–) terminal of CIN.
SENSE– (Pin 21): Negative Current Sense Comparator
Input. The (–) input to the current comparator is normally
connected to power ground unless using a resistive di-
vider from INTVCC (see Applications Information).
SENSE+ (Pin 23): Positive Current Sense Comparator
Input. The (+) input to the current comparator is normally
connected to the SW node unless using a sense resistor
(see Applications Information).
ION (Pin 6): On-Time Current Input. Tie a resistor from VIN
tothispintosettheone-shottimercurrentandtherebyset
the switching frequency.
VFB (Pin 7): Error Amplifier Feedback Input. This pin
connects to VOUT and divides its voltage to 2/3 • VFB
through precision internal resistors before it is applied to
the input of the error amplifier. Do not apply more than
1.5V on VFB. For higher output voltages, attach an external
resistor R2 (1/2 • R1 at VREF) from VOUT to VFB.
NC (Pins 8, 9, 11, 12, 13, 14, 22, 25, 26, 29, 30, 32): Do
Not Connect.
SW (Pin 24): Switch Node. The (–) terminal of the boot-
strap capacitor CB connects here. This pin swings from a
diode voltage drop below ground up to VIN.
VREF (Pin 10): Positive Input of Internal Error Amplifier.
This pin connects to an external reference and divides its
voltage to 1/3 VREF through precision internal resisters
before it is applied to the positive input of the error
amplifier. Reference voltage for output voltage, power
TG (Pin 27): Top Gate Drive. Drives the top N-channel
MOSFET with a voltage swing equal to INTVCC superim-
posed on the switch node voltage SW.
sn37171 37171fs
6
LTC3717-1
U
U
U
PI FU CTIO S
BOOST (Pin 28): Boosted Floating Driver Supply. The (+)
terminal of the bootstrap capacitor CB connects here. This
pin swings from a diode voltage drop below INTVCC up to
VIN + INTVCC.
RUN/SS (Pin 31): Run Control and Soft-Start Input. A
capacitor to ground at this pin sets the ramp time to full
output current (approximately 3s/µF) and the time delay
for overcurrent latchoff (see Applications Information).
Forcing this pin below 0.8V shuts down the device.
U
U
W
FU CTIO AL DIAGRA
R
ON
V
IN
V
ON
+
1
6
I
ON
15 EXTV
16
V
IN
CC
C
IN
4.7V
+
–
0.8V
REF
0.7V
2.4V
5V
REG
BOOST
28
C
TG
27
B
V
I
VON
ION
M1
t
ON
=
(10pF)
R
S
Q
I
SW
24
ON
+
L1
SENSE
23
20k
V
OUT
+
–
+
–
D
B
SWITCH
LOGIC
I
INTV
17
CMP
REV
CC
C
VCC
DRV
18
CC
SHDN
OV
+
C
OUT
1.4V
RNG
BG
19
M2
V
PGND
20
3
×
–
SENSE
21
0.7V
PGOOD
2
5.7µA
1
3/10V
240k
+
REF
Q2
UV
OV
–
R3
20k
I
V
THB
FB
7
R4
40k
Q1
+
–
SGND
5
Q5
11/30V
REF
RUN
SHDN
SS
–
+
1.2µA
EA
–
+
6V
0.6V
R2
80k
37171 FD01
C
C
SS
V
REF
C1
I
RUN/SS
31
10
4
TH
0.6V
R
C
R1
40k
sn37171 37171fs
7
LTC3717-1
U
OPERATIO
Furthermore, in an overvoltage condition, M1 is turned off
and M2 is turned on and held on until the overvoltage
condition clears.
Main Control Loop
The LTC3717-1 is a current mode controller for DC/DC
step-down converters. In normal operation, the top
MOSFET is turned on for a fixed interval determined by a
one-shot timer OST. When the top MOSFET is turned off,
the bottom MOSFET is turned on until the current com-
parator ICMP trips, restarting the one-shot timer and initi-
ating the next cycle. Inductor current is determined by
sensingthevoltagebetweentheSENSE+ andSENSE– pins
using the bottom MOSFET on-resistance . The voltage on
the ITH pin sets the comparator threshold corresponding
to inductor valley current. The error amplifier EA adjusts
this ITH voltage by comparing 2/3 of the feedback signal
VFB from the output voltage with a reference equal to 1/3
of the VREF voltage. If the load current increases, it causes
adropinthefeedbackvoltagerelativetothereference. The
ITH voltage then rises until the average inductor current
again matches the load current. As a result in normal DDR
operation VOUT is equal to 1/2 of the VREF voltage.
Pulling the RUN/SS pin low forces the controller into its
shutdown state, turning off both M1 and M2. Releasing
the pin allows an internal 1.2µA current source to charge
up an external soft-start capacitor CSS. When this voltage
reaches 1.5V, the controller turns on and begins switch-
ing, but with the ITH voltage clamped at approximately
0.6V below the RUN/SS voltage. As CSS continues to
charge, the soft-start current limit is removed.
INTVCC/EXTVCC Power
Power for the top and bottom MOSFET drivers and most
of the internal controller circuitry is derived from the
INTVCC pin. The top MOSFET driver is powered from a
floating bootstrap capacitor CB. This capacitor is re-
chargedfromINTVCC throughanexternalSchottkydiode
DB when the top MOSFET is turned off. When the EXTVCC
pin is grounded, an internal 5V low dropout regulator
supplies the INTVCC power from VCC. If EXTVCC rises
above 4.7V, the internal regulator is turned off, and an
internal switch connects EXTVCC to INTVCC. This allows
ahighefficiencysourceconnectedtoEXTVCC, suchasan
external 5V supply or a secondary output from the
converter, to provide the INTVCC power. Voltages up to
7V can be applied to EXTVCC for additional gate drive. If
the VCC voltage is low and INTVCC drops below 3.4V,
undervoltage lockout circuitry prevents the power
switches from turning on.
The operating frequency is determined implicitly by the
top MOSFET on-time and the duty cycle required to
maintain regulation. The one-shot timer generates an on-
time that is proportional to the ideal duty cycle, thus
holding frequency approximately constant with changes
in VIN. The nominal frequency can be adjusted with an
external resistor RON.
Overvoltage and undervoltage comparators OV and UV
pull the PGOOD output low if the output feedback voltage
exits a ±10% window around the regulation point.
sn37171 37171fs
8
LTC3717-1
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APPLICATIO S I FOR ATIO
U
A typical LTC3717-1 application circuit is shown in
Figure 1. External component selection is primarily de-
termined by the maximum load current and begins with
the selection of the sense resistance and power MOSFET
switches. The LTC3717-1 uses the on-resistance of the
synchronous power MOSFET for determining the induc-
tor current. The desired amount of ripple current and
operatingfrequencylargelydeterminestheinductorvalue.
Finally, CIN is selected for its ability to handle the large
RMS current into the converter and COUT is chosen with
low enough ESR to meet the output voltage ripple and
transient specification.
the source of the bottom MOSFET M2 and ground. Con-
nect the SENSE+ and SENSE– pins as a Kelvin connection
to the sense resistor with SENSE+ at the source of the
bottom MOSFET and the SENSE– pin to PGND. Using a
sense resistor provides a well defined current limit, but
adds cost and reduces efficiency. Alternatively, one can
eliminate the sense resistor and use the bottom MOSFET
as the current sense element by simply connecting the
SENSE+ pin to the drain and the SENSE– pin to the source
of the bottom MOSFET. This improves efficiency, but one
must carefully choose the MOSFET on-resistance as dis-
cussed in a later section.
Maximum Sense Voltage and VRNG Pin
Power MOSFET Selection
Inductor current is determined by measuring the voltage
across a sense resistance that appears between the
SENSE+ and SENSE– pins. The maximum sense voltage
is set by the voltage applied to the VRNG pin and is equal
to approximately (0.13)VRNG for sourcing current and
(0.17)VRNG forsinkingcurrent.Thecurrentmodecontrol
loop will not allow the inductor current valleys to exceed
(0.13)VRNG/RSENSE for sourcing current and (0.17)VRNG
for sinking current. In practice, one should allow some
margin for variations in the LTC3717-1 and external
component values and a good guide for selecting the
sense resistance is:
The LTC3717-1 requires two external N-channel power
MOSFETs, one for the top (main) switch and one for the
bottom (synchronous) switch. Important parameters for
the power MOSFETs are the breakdown voltage V(BR)DSS
threshold voltage V(GS)TH, on-resistance RDS(ON), reverse
transfercapacitanceCRSS andmaximumcurrentIDS(MAX)
,
.
The gate drive voltage is set by the 5V INTVCC supply.
Consequently, logic-level threshold MOSFETs must be
used in LTC3717-1 applications.
When the bottom MOSFET is used as the current sense
element, particular attention must be paid to its
on-resistance. MOSFET on-resistance is typically speci-
fied with a maximum value RDS(ON)(MAX) at 25°C. In this
case, additional margin is required to accommodate the
rise in MOSFET on-resistance with temperature:
VRNG
10•IOUT(MAX)
RSENSE
=
when VRNG = 0.5 – 2V.
An external resistive divider from INTVCC can be used to
set the voltage of the VRNG pin between 0.5V and 2V
resulting in nominal sense voltages of 50mV to 200mV.
Additionally, the VRNG pin can be tied to SGND or INTVCC
in which case the nominal sense voltage defaults to 70mV
or 140mV, respectively. The maximum allowed sense
voltage is about 1.3 times this nominal value for positive
output current and 1.7 times the nominal value for nega-
tive output current.
RSENSE
RDS(ON)(MAX)
=
ρT
The ρT term is a normalization factor (unity at 25°C)
accounting for the significant variation in on-resistance
with temperature, typically about 0.4%/°C as shown in
Figure 2. For a maximum junction temperature of 100°C,
using a value ρT = 1.3 is reasonable.
The power dissipated by the top and bottom MOSFETs
strongly depends upon their respective duty cycles and
the load current. During normal operation, the duty cycles
for the MOSFETs are:
Connecting the SENSE+ and SENSE– Pins
The LTC3717-1 can be used with or without a sense
resistor. When using a sense resistor, it is placed between
sn37171 37171fs
9
LTC3717-1
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APPLICATIO S I FOR ATIO
2.0
setbythecurrentintotheION pinandthevoltageattheVON
pin according to:
1.5
1.0
0.5
0
V
tON
=
VON (10pF)
I
ION
Tying a resistor RON from VIN to the ION pin yields an on-
time inversely proportional to VIN. For a step-down
converter, this results in approximately constant fre-
quency operation as the input supply varies:
50
100
–50
150
0
JUNCTION TEMPERATURE (°C)
VOUT
VVONRON(10pF)
f =
Hz
[ ]
37171 F02
Figure 2. RDS(ON) vs. Temperature
Toholdfrequencyconstantduringoutputvoltagechanges,
tie the VON pin to VOUT. The VON pin has internal clamps
that limit its input to the one-shot timer. If the pin is tied
below 0.7V, the input to the one-shot is clamped at 0.7V.
Similarly, if the pin is tied above 2.4V, the input is clamped
at 2.4V.
VOUT
DTOP
DBOT
=
=
V
IN
V – VOUT
IN
V
IN
Because the voltage at the ION pin is about 0.7V, the
currentintothispinisnotexactlyinverselyproportionalto
VIN, especially in applications with lower input voltages.
To account for the 0.7V drop on the ION pin, the following
equation can be used to calculate frequency:
The resulting power dissipation in the MOSFETs at maxi-
mum output current are:
PTOP = DTOP OUT(MAX)
I
2 ρT(TOP) RDS(ON)(MAX)
+ k VIN IOUT(MAX) CRSS
PBOT = DBOT OUT(MAX)
2 ρT(BOT) RDS(ON)(MAX)
2
f
V − 0.7V •V
(
)
I
IN
OUT
f =
VVON •V •RON(10pF)
Both MOSFETs have I2R losses and the top MOSFET
includesanadditionaltermfortransitionlosses,whichare
largest at high input voltages. The constant k = 1.7A–1 can
be used to estimate the amount of transition loss. The
bottomMOSFETlossesaregreatestwhenthebottomduty
cycle is near 100%, during a short-circuit or at high input
voltage.
IN
To correct for this error, an additional resistor RON2
connected from the ION pin to the 5V INTVCC supply will
further stabilize the frequency.
5V
0.7V
RON2
=
RON
Changes in the load current magnitude will also cause
frequency shift. Parasitic resistance in the MOSFET
switches and inductor reduce the effective voltage across
the inductance, resulting in increased duty cycle as the
loadcurrentincreases.Bylengtheningtheon-timeslightly
as current increases, constant frequency operation can be
maintained. This is accomplished with a resistive divider
from the ITH pin to the VON pin and VOUT. The values
required will depend on the parasitic resistances in the
Operating Frequency
The choice of operating frequency is a tradeoff between
efficiency and component size. Low frequency operation
improvesefficiencybyreducingMOSFETswitchinglosses
but requires larger inductance and/or capacitance in order
to maintain low output ripple voltage.
The operating frequency of LTC3717-1 applications is
determined implicitly by the one-shot timer that controls
the on-time tON of the top MOSFET switch. The on-time is
specific application. A good starting point is to feed about
sn37171 37171fs
10
LTC3717-1
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APPLICATIO S I FOR ATIO
U
R
R
VON1
VON1
3k
30k
V
V
ON
V
V
OUT
ON
OUT
C
R
VON
C
VON2
VON
R
0.01µF
VON2
100k
10k
10k
0.01µF
LTC3717-1
LTC3717-1
INTV
CC
R
R
C
C
Q1
2N5087
I
I
TH
TH
C
C
C
C
37171 F03
(3a)
(3b)
Figure 3. Adjusting Frequency Shift with Load Current Changes
orKoolMµ® cores.Avarietyofinductorsdesignedforhigh
current, lowvoltageapplicationsareavailablefrommanu-
facturers such as Sumida, Panasonic, Coiltronics, Coil-
craft and Toko.
25% of the voltage change at the ITH pin to the VON pin as
shown in Figure 3a. Place capacitance on the VON pin to
filter out the ITH variations at the switching frequency. The
resistor load on ITH reduces the DC gain of the error amp
and degrades load regulation, which can be avoided by
using the PNP emitter follower of Figure 3b.
Schottky Diode D1, D2 Selection
The Schottky diodes, D1 and D2, shown in Figure 1
conduct during the dead time between the conduction of
the power MOSFET switches. It is intended to prevent the
body diodes of the top and bottom MOSFETs from turning
on and storing charge during the dead time, which can
causeamodest(about1%)efficiencyloss. Thediodescan
beratedforaboutonehalftoonefifthofthefullloadcurrent
since they are on for only a fraction of the duty cycle. In
order for the diode to be effective, the inductance between
it and the bottom MOSFET must be as small as possible,
mandating that these components be placed adjacently.
The diodes can be omitted if the efficiency loss is tolerable.
Inductor L1 Selection
Given the desired input and output voltages, the inductor
value and operating frequency determine the ripple
current:
VOUT
fL
VOUT
V
IN
∆IL =
1−
Lower ripple current reduces cores losses in the inductor,
ESR losses in the output capacitors and output voltage
ripple. Highest efficiency operation is obtained at low
frequency with small ripple current. However, achieving
this requires a large inductor. There is a tradeoff between
component size, efficiency and operating frequency.
CIN and COUT Selection
The input capacitance CIN is required to filter the square
wave current at the drain of the top MOSFET. Use a low
ESR capacitor sized to handle the maximum RMS current.
A reasonable starting point is to choose a ripple current
that is about 40% of IOUT(MAX). The largest ripple current
occurs at the highest VIN. To guarantee that ripple current
does not exceed a specified maximum, the inductance
should be chosen according to:
VOUT
V
IN
V
IN
VOUT
IRMS IOUT(MAX)
– 1
VOUT
f∆IL(MAX)
VOUT
V
IN(MAX)
This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT(MAX)/2. This simple worst-case condition is
commonly used for design because even significant
deviations do not offer much relief. Note that ripple
current ratings from capacitor manufacturers are often
L =
1−
Once the value for L is known, the type of inductor must be
selected. High efficiency converters generally cannot af-
ford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite, molypermalloy
Kool Mµ is a registered trademark of Magnetics, Inc.
sn37171 37171fs
11
LTC3717-1
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APPLICATIO S I FOR ATIO
basedononly2000hoursoflifewhichmakesitadvisable
to derate the capacitor.
on, the switch node rises to VIN and the BOOST pin rises
to approximately VIN + INTVCC. The boost capacitor needs
to store about 100 times the gate charge required by the
top MOSFET. In most applications a 0.1µF to 0.47µF X5R
or X7R dielectric capacitor is adequate.
The selection of COUT is primarily determined by the ESR
required to minimize voltage ripple and load step
transients. The output ripple ∆VOUT is approximately
bounded by:
Fault Condition: Current Limit
1
The maximum inductor current is inherently limited in a
currentmodecontrollerbythemaximumsensevoltage.In
the LTC3717-1, the maximum sense voltage is controlled
bythevoltageontheVRNG pin. Withvalleycurrentcontrol,
the maximum sense voltage and the sense resistance
determine the maximum allowed inductor valley current.
The corresponding output current limit is:
∆VOUT ≤ ∆IL ESR +
8fCOUT
Since ∆IL increases with input voltage, the output ripple is
highestatmaximuminputvoltage.Typically,oncetheESR
requirement is satisfied, the capacitance is adequate for
filtering and has the necessary RMS current rating.
Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, special polymer, aluminum electrolytic and
ceramic capacitors are all available in surface mount
packages. Special polymer capacitors offer very low ESR
but have lower capacitance density than other types.
Tantalumcapacitorshavethehighestcapacitancedensity
but it is important to only use types that have been surge
tested for use in switching power supplies. Aluminum
electrolytic capacitors have significantly higher ESR, but
can be used in cost-sensitive applications providing that
consideration is given to ripple current ratings and long
term reliability. Ceramic capacitors have excellent low
ESR characteristics but can have a high voltage coeffi-
cient and audible piezoelectric effects. The high Q of
ceramic capacitors with trace inductance can also lead to
significant ringing. When used as input capacitors, care
must be taken to ensure that ringing from inrush currents
and switching does not pose an overvoltage hazard to the
power switches and controller. To dampen input voltage
transients, add a small 5µF to 50µF aluminum electrolytic
capacitor with an ESR in the range of 0.5Ω to 2Ω. High
performance through-hole capacitors may also be used,
but an additional ceramic capacitor in parallel is recom-
mended to reduce the effect of their lead inductance.
VSNS(MAX)
1
ILIMITPOSITIVE
ILIMITNEGATIVE
=
+ ∆IL
2
RDS(ON)ρT
VSNS(MIN)
1
=
− ∆IL
2
RDS(ON)ρT
The current limit value should be checked to ensure that
ILIMIT(MIN) >IOUT(MAX).Theminimumvalueofcurrentlimit
generally occurs with the largest VIN at the highest ambi-
ent temperature, conditions that cause the largest power
loss in the converter. Note that it is important to check for
self-consistency between the assumed MOSFET junction
temperature and the resulting value of ILIMIT which heats
the MOSFET switches.
Caution should be used when setting the current limit
based upon the RDS(ON) of the MOSFETs. The maximum
current limit is determined by the minimum MOSFET on-
resistance. Data sheets typically specify nominal and
maximum values for RDS(ON), but not a minimum. A
reasonable assumption is that the minimum RDS(ON) lies
the same amount below the typical value as the maximum
liesaboveit.ConsulttheMOSFETmanufacturerforfurther
guidelines.
Minimum Off-time and Dropout Operation
Top MOSFET Driver Supply (CB, DB)
The minimum off-time tOFF(MIN) is the smallest amount of
time that the LTC3717-1 is capable of turning on the
bottom MOSFET, tripping the current comparator and
turning the MOSFET back off. This time is generally about
sn37171 37171fs
AnexternalbootstrapcapacitorCBconnectedtotheBOOST
pinsuppliesthegatedrivevoltageforthetopsideMOSFET.
This capacitor is charged through diode DB from INTVCC
when the switch node is low. When the top MOSFET turns
12
LTC3717-1
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APPLICATIO S I FOR ATIO
250ns. The minimum off-time limit imposes a maximum
duty cycle of tON/(tON + tOFF(MIN)). If the maximum duty
cycle is reached, due to a dropping input voltage for
example, then the output will drop out of regulation. The
minimum input voltage to avoid dropout is:
U
BOOST
DRV
CC
Q1
Q3
FMMT619
FMMT619
10Ω
10Ω
GATE
OF M1
GATE
OF M2
TG
BG
Q2
FMMT720
Q4
FMMT720
t
ON + tOFF(MIN)
SW
PGND
37171 F05
V
= VOUT
IN(MIN)
tON
Figure 5. Optional External Gate Driver
Output Voltage Programming
Soft-Start and Latchoff with the RUN/SS Pin
When VFB is connected to VOUT, the output voltage is
regulated to one half of the voltage at the VREF pin. A
resistor connected between VFB and VOUT can be used to
further adjust the output voltage according to the follow-
ing equation:
The RUN/SS pin provides a means to shut down the
LTC3717-1 as well as a timer for soft-start and overcur-
rent latchoff. Pulling the RUN/SS pin below 0.8V puts the
LTC3717-1 into a low quiescent current shutdown
(IQ < 30µA). Releasing the pin allows an internal 1.2µA
current source to charge up the external timing capacitor
CSS. If RUN/SS has been pulled all the way to ground,
there is a delay before starting of about:
60k + RFB
VOUT = VREF
120k
If VREF exceeds 3V, resistors should be placed in series
with the VREF pin and the VFB pin to avoid exceeding the
input common mode range of the internal error amplifier.
To maintain the VOUT = VREF/2 relationship, the resistor in
series with the VREF pin should be made twice as large as
the resistor in series with the VFB pin.
1.5V
1.2µA
tDELAY
=
CSS = 1.3s/µF CSS
(
)
When the voltage on RUN/SS reaches 1.5V, the LTC3717-
1 begins operating with a clamp on ITH of approximately
0.9V. As the RUN/SS voltage rises to 3V, the clamp on ITH
is raised until its full 2.4V range is available. This takes an
additional 1.3s/µF, during which the load current is folded
back. During start-up, the maximum load current is re-
duced until either the RUN/SS pin rises to 3V or the output
reaches 75% of its final value. The pin can be driven from
logic as shown in Figure 6. Diode D1 reduces the start
delay while allowing CSS to charge up slowly for the soft-
start function.
R
FB
249k
V
OUT
V
FB
LTC3717-1
R
FB
499k
V
V
REF
REF
37171 F04
Figure 4
INTV
CC
R
*
External Gate Drive Buffers
SS
V
IN
RUN/SS
3.3V OR 5V
RUN/SS
*
D2*
The LTC3717-1 drivers are adequate for driving up to
about 30nC into MOSFET switches with RMS currents of
50mA. ApplicationswithlargerMOSFETswitchesoroper-
ating at frequencies requiring greater RMS currents will
benefit from using external gate drive buffers such as the
LTC1693. Alternately, the external buffer circuit shown in
Figure 5 can be used. Note that the bipolar devices reduce
the signal swing at the MOSFET gate.
R
SS
D1
C
SS
C
SS
37171 F06
*OPTIONAL TO OVERRIDE
OVERCURRENT LATCHOFF
(6a)
(6b)
Figure 6. RUN/SS Pin Interfacing with Latchoff Defeated
sn37171 37171fs
13
LTC3717-1
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APPLICATIO S I FOR ATIO
high frequency of operation may cause the LTC3717-1 to
exceed its maximum junction temperature rating or RMS
After the controller has been started and given adequate
time to charge up the output capacitor, CSS is used as a
short-circuit timer. After the RUN/SS pin charges above current rating. Most of the supply current drives the
4V, if the output voltage falls below 75% of its regulated
value, then a short-circuit fault is assumed. A 1.8µA cur-
rent then begins discharging CSS. If the fault condition f(Qg(TOP) + Qg(BOT)). The junction temperature can be
MOSFET gates unless an external EXTVCC source is used.
In continuous mode operation, this current is IGATECHG
=
estimated from the equations given in Note 2 of the
ElectricalCharacteristics.Forexample,theLTC3717EUH-1
persists until the RUN/SS pin drops to 3.5V, then the con-
troller turns off both power MOSFETs, shutting down the
converter permanently. The RUN/SS pin must be actively is limited to less than 14mA from a 30V supply:
pulled down to ground in order to restart operation.
TJ = 70°C + (14mA)(30V)(34°C/W) = 84.3°C
The overcurrent protection timer requires that the soft-
Forlargercurrents, considerusinganexternalsupplywith
start timing capacitor CSS be made large enough to guar-
the EXTVCC pin.
antee that the output is in regulation by the time CSS has
reachedthe4Vthreshold.Ingeneral,thiswilldependupon
EXTVCC Connection
the size of the output capacitance, output voltage and load
The EXTVCC pin can be used to provide MOSFET gate drive
currentcharacteristic.Aminimumsoft-startcapacitorcan
and control power from the output or another external
be estimated from:
source during normal operation. Whenever the EXTVCC
pin is above 4.7V the internal 5V regulator is shut off and
CSS > COUT VOUT RSENSE (10–4 [F/V s])
an internal 50mA P-channel switch connects the EXTVCC
pintoINTVCC.INTVCC powerissuppliedfromEXTVCC until
this pin drops below 4.5V. Do not apply more than 7V to
theEXTVCC pinandensurethatEXTVCC ≤ VCC. Thefollow-
ing list summarizes the possible connections for EXTVCC:
Generally 0.1µF is more than sufficient.
Overcurrent latchoff operation is not always needed or
desired. The feature can be overridden by adding a pull-
up current greater than 5µA to the RUN/SS pin. The
additional current prevents the discharge of CSS during a
fault and also shortens the soft-start period. Using a
resistortoVIN asshowninFigure6aissimple, butslightly
increases shutdown current. Connecting a resistor to
INTVCC as shown in Figure 6b eliminates the additional
shutdowncurrent, butrequiresadiodetoisolateCSS. Any
pull-up network must be able to pull RUN/SS above the
4.2V maximum threshold of the latchoff circuit and over-
come the 4µA maximum discharge current.
1. EXTVCC grounded. INTVCC is always powered from the
internal 5V regulator.
2. EXTVCC connected to an external supply. A high effi-
ciency supply compatible with the MOSFET gate drive
requirements (typically 5V) can improve overall
efficiency.
3. EXTVCC connected to an output derived boost network.
The low voltage output can be boosted using a charge
pump or flyback winding to greater than 4.7V. The system
will start-up using the internal linear regulator until the
boosted output supply is available.
INTVCC Regulator
An internal P-channel low dropout regulator produces the
5V supply that powers the drivers and internal circuitry
within the LTC3717-1. The INTVCC pin can supply up to
50mA RMS and must be bypassed to ground with a
minimum of 4.7µF tantalum or other low ESR capacitor.
Good bypassing is necessary to supply the high transient
currents required by the MOSFET gate drivers. Applica-
tions using large MOSFETs with a high input voltage and
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
sn37171 37171fs
14
LTC3717-1
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U
Checking Transient Response
what is limiting the efficiency and which change would
produce the most improvement. Although all dissipative
elements in the circuit produce losses, four main sources
account for most of the losses in LTC3717-1 circuits:
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
aloadstepoccurs,VOUT immediatelyshiftsbyanamount
equal to ∆ILOAD (ESR), where ESR is the effective series
resistance of COUT. ∆ILOAD also begins to charge or
discharge COUT generating a feedback error signal used
by the regulator to return VOUT to its steady-state value.
During this recovery time, VOUT can be monitored for
overshoot or ringing that would indicate a stability
problem. The ITH pin external components shown in
Figure 1 will provide adequate compensation for most
applications. For a detailed explanation of switching
control loop theory see Application Note 76.
1. DC I2R losses. These arise from the resistances of the
MOSFETs, inductor and PC board traces and cause the
efficiency to drop at high output currents. In continuous
mode the average output current flows through L, but is
chopped between the top and bottom MOSFETs. If the two
MOSFETs have approximately the same RDS(ON), then the
resistanceofoneMOSFETcansimplybesummedwiththe
resistances of L and the board traces to obtain the DC I2R
loss.Forexample,ifRDS(ON) =0.01ΩandRL =0.005Ω,the
loss will range from 1% up to 10% as the output current
varies from 1A to 10A for a 1.5V output.
2. Transition loss. This loss arises from the brief amount
of time the top MOSFET spends in the saturated region
during switch node transitions. It depends upon the input
voltage, load current, driver strength and MOSFET capaci-
tance, among other factors. The loss is significant at input
voltages above 20V and can be estimated from:
Design Example
As a design example, take a supply with the following
specifications: VIN = VREF = 2.5V, VEXTVCC = 5V, VOUT
=
1.25V ±5%, IOUT(MAX) = 10A, f = 250kHz. First, calculate
the timing resistor with VON = VOUT
:
2
Transition Loss (1.7A–1) VIN IOUT CRSS
f
1.25V(2.5V – 0.7V)
(0.7V)(250kHz)(10pF)2.5V
RON
=
= 514kΩ
3. INTVCC current. This is the sum of the MOSFET driver
and control currents.
and choose the inductor for about 40% ripple current at
the maximum VIN:
4. CIN loss. The input capacitor has the difficult job of
filtering the large RMS input current to the regulator. It
must have a very low ESR to minimize the AC I2R loss and
sufficient capacitance to prevent the RMS current from
causing additional upstream losses in fuses or batteries.
1.25V
(250kHz)(0.4)(10A)
1.25V
2.5V
L =
1−
= 0.63µH
Selectingastandardvalueof0.68µHresultsinamaximum
Other losses, including COUT ESR loss, Schottky diode D1
conduction loss during dead time and inductor core loss
generally account for less than 2% additional loss.
ripple current of:
1.25V
(250kHz)(0.68µH)
1.25V
2.5V
Whenmakingadjustmentstoimproveefficiency,theinput
current is the best indicator of changes in efficiency. If you
make a change and the input current decreases, then the
efficiency has increased. If there is no change in input
current, then there is no change in efficiency.
∆IL =
1–
= 3.7A
Next, choose the synchronous MOSFET switch. Choosing
a Si4874 (RDS(ON) = 0.0083Ω (NOM) 0.010Ω (MAX),
θJA = 40°C/W) yields a nominal sense voltage of:
VSNS(NOM) = (10A)(1.3)(0.0083Ω) = 108mV
sn37171 37171fs
15
LTC3717-1
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TyingVRNG to1.1V willsetthecurrentsensevoltagerange
for a nominal value of 110mV with current limit occurring
at 143mV. To check if the current limit is acceptable,
assume a junction temperature of about 40°C above a
70°C ambient with ρ110°C = 1.4:
0.013Ω to minimize output voltage changes due to induc-
tor ripple current and load steps. For current sinking
applicationswherecurrentflowsbacktotheinputthrough
the top transistor, outputcapacitors with asimilaramount
of bulk C and ESR should be placed on the input as well.
(This is typically the case, since VIN is derived from
another DC/DC converter.) The ripple voltage will be only:
143mV
(1.4)(0.010Ω) 2
1
ILIMIT
≥
+ (3.7A) = 12.1A
∆VOUT(RIPPLE) = ∆IL(MAX) (ESR)
= (4A) (0.013Ω) = 52mV
and double check the assumed TJ in the MOSFET:
However, a 0A to 10A load step will cause an output
change of up to:
2.5V –1.25V
PBOT
=
(12.1A)2(1.4)(0.010Ω) = 1.02W
2.5V
∆VOUT(STEP) =∆ILOAD (ESR)=(10A)(0.013Ω)=130mV
TJ = 70°C + (1.02W)(40°C/W) = 111°C
An optional 22µF ceramic output capacitor is included to
minimize the effect of ESL in the output ripple. The
complete circuit is shown in Figure 7.
Because the top MOSFET is on roughly the same amount
of time as the bottom MOSFET, the same Si4874 can be
used as the synchronous MOSFET.
PC Board Layout Checklist
The junction temperatures will be significantly less at
nominal current, but this analysis shows that careful
attention to heat sinking will be necessary in this circuit.
When laying out a PC board follow one of the two sug-
gested approaches. The simple PC board layout requires
a dedicated ground plane layer. Also, for higher currents,
it is recommended to use a multilayer board to help with
heat sinking power components.
CIN is chosen for an RMS current rating of about 5A at
85°C. The output capacitors are chosen for a low ESR of
C
SS
0.1µF
D
B
CMDSH-3
V
V
= 2.5V
RUN/SS BOOST
IN
C
C
IN
+
IN
R3
R
PG
100k
R4
C
B
D2
22µF
6.3V
X7R
180µF
4V
11k
39k
0.22µF
M1
B320A
PGOOD
LTC3717-1
TG
Si4874
×2
OUT
1.25V
L1
0.68µH
V
RNG
SW
+
±10A
C
C1
C
C
OUT3
R
C
20k
OUT1-2
470pF
+
SENSE
270µF
2V
22µF
6.3V
X7R
M2
Si4874
D1
B320A
I
TH
PGND
×2
C
–
C2
SENSE
100pF
SGND
BG
C
VCC
C
0.01µF
V
ON
ON
+
4.7µF
I
INTV
DRV
V
ON
CC
CC
CC
R
F
1Ω
V
V
5V
FB
EXT
C
F
0.1µF
V
REF
EXTV
CC
(OPT)
0.1µF
R
ON
511k
10Ω
37171 F07
C
, C
: CORNELL DUBILIER ESRE181E04B
IN OUT1-2
L1: SUMIDA CEP125-0R68MC-H
Figure 7. Design Example: 1.25V/±10A at 250kHz
sn37171 37171fs
16
LTC3717-1
W U U
APPLICATIO S I FOR ATIO
U
• The ground plane layer should not have any traces and
it should be as close as possible to the layer with power
MOSFETs.
When laying out a printed circuit board, without a ground
plane, use the following checklist to ensure proper opera-
tion of the controller. These items are also illustrated in
Figure 8.
• Place CIN, COUT, MOSFETs, D1 and inductor all in one
compactarea.Itmayhelptohavesomecomponentson
the bottom side of the board.
• Segregate the signal and power grounds. All small
signal components should return to the SGND pin at
onepointwhichisthentiedtothePGNDpinclosetothe
source of M2.
• Place LTC3717-1 chip with Pins 15 to 28 facing the
power components. Keep the components connected
to Pins 1 to 10 close to LTC3717-1 (noise sensitive
components).
• Place M2 as close to the controller as possible, keeping
the PGND, BG and SW traces short.
•
Use an immediate via to connect the components to
groundplaneincludingSGNDandPGNDofLTC3717-1.
Use several bigger vias for power components.
• Connect the input capacitor(s) CIN close to the power
MOSFETs. This capacitor carries the MOSFET AC cur-
rent.
• Use compact plane for switch node (SW) to improve
cooling of the MOSFETs and to keep EMI down.
• Keep the high dV/dT SW, BOOST and TG nodes away
from sensitive small-signal nodes.
• Use planes for VIN and VOUT to maintain good voltage
filtering and to keep power losses low.
• Connect the INTVCC and DRVCC decoupling capacitor
CVCC closely to the INTVCC, DRVCC and PGND pins.
• Flood all unused areas on all layers with copper. Flood-
ing with copper will reduce the temperature rise of
powercomponent.Youcanconnectthecopperareasto
any DC net (VIN, VOUT, GND or to any other DC rail in
your system).
• Connect the top driver boost capacitor CB closely to the
BOOST and SW pins.
• Connect the VCC pin decoupling capacitor CF closely to
the VCC and PGND pins.
C
C
B
SS
L
RUN/SS BOOST
PGOOD
LTC3717-1
TG
D
B
V
SW
+
+
RNG
M1
C
C1
SENSE
R
C
I
PGND
TH
–
V
SENSE
IN
D2
D1
C
C2
C
M2
SGND
BG
IN
C
C
ION
VCC
V
ON
–
–
+
I
INTV
DRV
ON
CC
C
FB
CC
V
C
OUT
OUT
C
V
V
V
F
FB
CC
R
F
EXTV
REF
CC
R
ON
37171 F08
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 8. LTC3717-1 Layout Diagram
sn37171 37171fs
17
LTC3717-1
TYPICAL APPLICATIO S
U
1.5V/±10A at 300kHz from 5V to 28V Input
C
SS
D
B
0.1µF
CMDSH-3
V
IN
RUN/SS BOOST
5V TO 28V
C
IN
R
R
R
C
PG
R1
R2
B
10µF
35V
×3
100k
11k
39k
0.22µF
B320A
L1
M1
PGOOD
LTC3717-1
TG
IRF7811W
V
OUT
1.5V
V
SW
+
±10A
RNG
C
C1
1.2µH
C
OUT
R
C
20k
680pF
+
SENSE
270µF
2V
M2
IRF7822
D1
B320A
I
PGND
TH
×2
–
C
C2
SENSE
100pF
SGND
BG
C
C 0.01µF
ON
VCC
V
ON
4.7µF
I
INTV
DRV
V
ON
CC
CC
CC
V
V
FB
EXTV
V
3V
REF
CC
REF
10µF
6.3V
X7R
R
ON
510k
37171 TA01
C
: CORNELL DUBILIER ESRE271M02B
OUT
High Voltage Half (VIN) Power Supply
C
SS
D
B
0.1µF
CMDSH-3
V
IN
RUN/SS BOOST
5V TO 25V
C
R
IN
C
PG
B
10µF
100k
0.22µF
M1
25V
×2
PGOOD
LTC3717-1
TG
FDS6680S
V
V
±6A
OUT
IN
/2
L1
1.8µH
V
SW
+
RNG
C
C1
470pF
R
C
20k
+
C
C
SENSE
OUT1
OUT2
270µF
10µF
M2
FDS6680S
I
PGND
TH
16V
15V
–
C
C2
SENSE
100pF
SGND
BG
C
VCC
4.7µF
C
0.01µF
V
ON
ON
I
INTV
DRV
V
ON
CC
CC
CC
R
F
1Ω
V
V
FB
C
F
0.1µF
EXTV
REF
CC
R
ON
510k
R2
1M
R1 2M
C2
2200pF
37171 TA02
C
C
C
: TAIYO YUDEN TMK432BJ106MM
IN
: SANYO, OS-CON 16SP270
OUT1
OUT2
: TAIYO YUDEN JMK316BJ106ML
L1: TOKO 919AS-1R8N
sn37171 37171fs
18
LTC3717-1
U
PACKAGE DESCRIPTIO
UH Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693)
0.57 ±0.05
5.35 ±0.05
4.20 ±0.05
3.45 ±0.05
(4 SIDES)
PACKAGE OUTLINE
0.23 ± 0.05
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
BOTTOM VIEW—EXPOSED PAD
R = 0.115
TYP
0.75 ± 0.05
0.40 ± 0.10
5.00 ± 0.10
(4 SIDES)
31 32
0.00 – 0.05
PIN 1
TOP MARK
1
2
3.45 ± 0.10
(4-SIDES)
(UH) QFN 0102
0.200 REF
0.23 ± 0.05
0.50 BSC
NOTE:
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
sn37171 37171fs
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will notinfringe onexisting patent rights.
19
LTC3717-1
U
TYPICAL APPLICATIO
Typical Application 1.25V/±3A at 1.4MHz
C
SS
D
B
0.1µF
CMDSH-3
V
IN
RUN/SS BOOST
2.5V
+
+
R
C
PG
C
B
IN
100k
0.22µF
120µF
M1
L1
0.7µH
PGOOD
LTC3717-1
TG
4V
1/2 Si9802
V
OUT
1.25V
V
SW
+
±3A
RNG
C
C1
470pF
R
C
33k
C
SENSE
OUT
120µF
M2
1/2 Si9802
I
PGND
TH
4V
–
C
C2
SENSE
100pF
SGND
BG
C
VCC
C
, 0.01µF
ON
V
ON
4.7µF
I
INTV
ON
CC
DRV
V
CC
V
V
5V
FB
CC
EXTV
REF
CC
1µF
R
ON
92k
3717 TA03
C
, C : CORNELL DUBILIER ESRD121M04B
IN OUT
L1: TOKO A921CY-0R7M
RELATED PARTS
PART NUMBER
LTC1625/LTC1775
LTC1628-PG
DESCRIPTION
No R
TM Current Mode Synchronous Step-Down Controller
COMMENTS
97% Efficiency; No Sense Resistor; 99% Duty Cycle
SENSE
Dual, 2-Phase Synchronous Step-Down Controller
Power Good Output; Minimum Input/Output Capacitors;
3.5V ≤ V ≤ 36V
IN
LTC1628-SYNC
LTC1709-7
Dual, 2-Phase Synchronous Step-Down Controller
Synchronizable 150kHz to 300kHz
High Efficiency, 2-Phase Synchronous Step-Down Controller
with 5-Bit VID
Up to 42A Output; 0.925V ≤ V
≤ 2V
OUT
LTC1709-8
LTC1735
High Efficiency, 2-Phase Synchronous Step-Down Controller
High Efficiency, Synchronous Step-Down Controller
Up to 42A Output; VRM 8.4; 1.3V ≤ V
Burst ModeTM Operation; 16-Pin Narrow SSOP;
≤ 3.5V
OUT
3.5V ≤ V ≤ 36V
IN
LTC1736
LTC1772
LTC1773
High Efficiency, Synchronous Step-Down Controller with 5-Bit VID
SOT-23 Step-Down Controller
Mobile VID; 0.925V ≤ V
≤ 2V; 3.5V ≤ V ≤ 36V
OUT IN
Current Mode; 550kHz; Very Small Solution Size
Up to 95% Efficiency, 550kHz, 2.65V ≤ V ≤ 8.5V,
Synchronous Step-Down Controller
IN
0.8V ≤ V
≤ V , Synchronizable to 750kHz
OUT
IN
LTC1778/LTC3778
Wide Operating Range, No R
Dual, Step-Down Controller
Step-Down Synchronous Controllers 4V ≤ V ≤ 36V, True Current Mode Control,
SENSE
IN
2% to 90% Duty Cycle
LTC1874
LTC1876
Current Mode; 550kHz; Small 16-Pin SSOP, V < 9.8V
IN
2-Phase, Dual Synchronous Step-Down Controller with
Step-Up Regulator
2.6V ≤ V ≤ 36V, Power Good Output,
IN
300kHz Operation
LTC3413
LTC3717
Monolithic DDR Memory Termination Regulator
90% Efficiency, ±3A Output, 2MHz Operation
Wide Operating Range, No R
Step-Down Synchronous Controllers 4V ≤ V ≤ 36V, True Current Mode Control,
IN
SENSE
for DDR Memory Termination
2% to 90% Duty Cycle, 16-Pin SSOP, No R
SENSE
Burst Mode is a registered trademark of Linear Technology Corporation.
sn37171 37171fs
LT/TP 0603 1K • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2003
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