LTC3718EG [Linear]
Low Input Voltage DC/DC Controller for DDR/QDR Memory Termination; 低输入电压DC / DC控制器，用于DDR / QDR存储器终端
| 型号： | LTC3718EG |
| 厂家： | 
Linear |
| 描述： | Low Input Voltage DC/DC Controller for DDR/QDR Memory Termination |
| 文件： | 总20页 (文件大小：243K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3718
Low Input Voltage
DC/DC Controller for
DDR/QDR Memory Termination
U
FEATURES
DESCRIPTIO
The LTC®3718 is a high current, high efficiency synchro-
nous switching regulator controller for DDR and QDRTM
memory termination. It operates from an input as low as
1.5V and provides a regulated output voltage equal to
(0.5)VIN. The controller uses a valley current control
architecture to enable high frequency operation with very
lowon-timeswithoutrequiringasenseresistor.Operating
frequency is selected by an external resistor and is com-
pensatedforvariationsinVIN andVOUT.TheLTC3718uses
a pair of standard 5V logic level N-channel external
MOSFETs, eliminating the need for expensive P-channel
or low threshold devices.
■
Very Low VIN(MIN): 1.5V
■
Ultrafast Transient Response
■
True Current Mode Control
■
5V Drive for N-Channel MOSFETs Eliminates
Auxillary 5V Supply
No Sense Resistor Required
■
■
Uses Standard 5V Logic-Level N-Channel MOSFETs
■
VOUT(MIN): 0.4V
VOUT Tracks 1/2 VIN or External VREF
■
■
Symmetrical Source and Sink Output Current Limit
■
Adjustable Switching Frequency
tON(MIN) <100ns
■
■
Power Good Output Voltage Monitor
Forced continuous operation reduces noise and RF inter-
ference. Fault protection is provided by internal foldback
current limiting, an output overvoltage comparator and an
optional short-circuit timer. Soft-start capability for sup-
ply sequencing can be accomplished using an external
timing capacitor. OPTI-LOOP® compensation allows the
transient response to be optimized over a wide range of
loads and output capacitors.
■
Programmable Soft-Start
■
Output Overvoltage Protection
■
Optional Short-Circuit Shutdown Timer
■
Small 24-Lead SSOP Package
U
APPLICATIO S
■
Bus Termination: DDR/QDR Memory, SSTL, HSTL, ...
■
Servers, RAID Systems
, LTC and LT are registered trademarks of Linear Technology Corporation.
OPTI-LOOP is a registered trademark of Linear Technology Corporation. No RSENSE is a
trademark of Linear Technology Corporation. QDR RAMs and Quad Data Rate RAMs comprise a
new family of products developed by Cypress Semiconductor, IDT and Micron Technology, Inc.
■
Distributed Power Systems
Synchronous Buck with General Purpose Boost
■
U
TYPICAL APPLICATIO
V
IN
2.5V
C
IN1
D
B
22µF
CMDSH-3
×2
SHDN
BOOST
C
B
Efficiency vs Load Current
0.33µF
D1
M1
V
TG
REF
B340A
R
Si7440DP
ON
237k
100
90
80
70
60
50
40
30
20
10
0
LTC3718
V
V
= 2.5V
IN
OUT
I
ON
SW1
+
= 1.25V
V
OUT
V
FB1
SENSE
L1 0.8µH
V
OUT
1.25V
PGOOD
RUN/SS
PGND1
C
SS
0.1µF
±10A
–
C
+
OUT
SENSE
470µF
×2
M2
Si7440DP
D2
B340A
BG
C1 820pF X7R
INTV
CC
IN1
IN2
R
4.75k
C
I
V
V
TH
SGND1
V
IN
C
IN2
4.7µF
L2
4.7µH
SGND2
PGND2
SW2
FIGURE 1 CIRCUIT
10 100
V
FB2
0.01
0.1
1
D3
MBR0520
C
VCC1
10µF
LOAD CURRENT (A)
R
12.1k
R
37.4k
F2
F1
3718 G05/TA01a
C
OUT
: SANYO POSCAP 4TPB470M
L1: SUMIDA CEP125-0R8MC
L2: PANASONIC ELJPC4R7MF
3718 TA01
Figure 1. High Efficiency Bus Termination Supply without Auxiliary 5V Supply
3718fa
1
LTC3718
W W U W
U W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
ORDER PART
NUMBER
Input Supply Voltage (VIN2) .......................10V to –0.3V
Boosted Topside Driver Supply Voltage
TOP VIEW
1
2
BOOST
TG
24
23
22
21
20
19
18
17
16
15
14
13
RUN/SS
(BOOST) ............................................... 42V to –0.3V
V
ON
LTC3718EG
V
IN1, ION, SW1 Voltage ............................. 36V to –0.3V
3
SW1
PGOOD
+
RUN/SS, PGOOD Voltages......................... 7V to –0.3V
VON, VREF, VRNG Voltages .......(INTVCC + 0.3V) to –0.3V
ITH, VFB1 Voltages .................................... 2.7V to –0.3V
SW2 Voltage ............................................. 36V to –0.4V
4
SENSE
SENSE
V
RNG
–
5
I
TH
6
PGND1
BG
SGND1
7
I
ON
8
INTV
CC
V
FB1
V
FB2 Voltage .................................................VIN2 + 0.3V
9
V
V
IN1
REF
SHDN Voltage ......................................................... 10V
TG, BG, INTVCC Peak Currents.................................. 2A
TG, BG, INTVCC RMS Currents ............................ 50mA
Operating Ambient Temperature
10
11
12
V
SHDN
IN2
PGND2
SW2
SGND2
V
FB2
G PACKAGE
24-LEAD PLASTIC SSOP
Range (Note 4) ................................... –40°C to 85°C
Junction Temperature (Note 2)............................ 125°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
TJMAX = 125°C, θJA = 130°C/ W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VIN1 = 15V, VIN2 = 1.5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Buck Regulator
I
Input DC Supply Current (V
Normal
Shutdown Supply Current
Feedback Voltage Accuracy
)
IN1
Q(VIN1)
1000
15
2000
30
µA
µA
V
= 0V
RUN/SS
V
I
= 1.2V (Note 3)
TH
●
●
–0.65
0.93
0.1
0.65
%
%/V
%
FB1
∆V
∆V
Feedback Voltage Line Regulation
Feedback Voltage Load Regulation
Error Amplifier Transconductance
On-Time
V
= 4V to 36V, I = 1.2V (Note 3)
0.002
–0.05
1.13
FB1(LINE)
FB1(LOAD)
IN1
TH
I
I
= 0.5V to 1.9V (Note 3)
= 1.2V (Note 3)
–0.3
1.33
TH
TH
g
mS
m(EA)
t
I
I
= 60µA, V = 1.5V
= 30µA, V = 1.5V
200
400
250
500
300
600
ns
ns
ON
ON
ON
ON
ON
t
t
Minimum On-Time
I
= 180µA
50
100
400
ns
ns
ON(MIN)
OFF(MIN)
ON
Minimum Off-Time
300
V
Maximum Current Sense Threshold
V
V
V
= 1V, V = V /2 – 50mV
●
●
●
108
76
148
135
95
185
162
114
222
mV
mV
mV
SENSE(MAX)
RNG
RNG
RNG
FB1
REF
V
– V
(Source)
= 0V, V = V /2 – 50mV
PGND
SW1
FB1 REF
= INTV , V = V /2 – 50mV
CC FB1
REF
V
Minimum Current Sense Threshold
– V (Sink)
V
V
V
= 1V, V = V /2 + 50mV
–140
–97
–200
–165
–115
–235
–190
–133
–270
mV
mV
mV
SENSE(MIN)
RNG
RNG
RNG
FB1
REF
V
= 0V, V = V /2 + 50mV
PGND
SW1
FB1 REF
= INTV , V = V /2 + 50mV
CC FB1
REF
∆V
∆V
Output Overvoltage Fault Threshold
Output Undervoltage Fault Threshold
RUN Pin Start Threshold
8
10
–25
1.5
4
12
%
%
V
FB1(OV)
FB1(UV)
V
V
●
0.8
2
RUN/SS(ON)
RUN/SS(LE)
RUN Pin Latchoff Enable
RUN/SS Pin Rising
4.5
V
3718fa
2
LTC3718
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VIN1 = 15V, VIN2 = 1.5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
3.5
MAX
4.2
–3
3
UNITS
V
V
RUN Pin Latchoff Threshold
Soft-Start Charge Current
Soft-Start Discharge Current
RUN/SS Pin Falling
RUN/SS(LT)
RUN/SS(C)
RUN/SS(D)
I
I
V
V
= 0V
–0.5
0.8
–1.2
1.8
µA
RUN/SS
RUN/SS
= 4.5V, V = 0V
µA
FB
V
V
Undervoltage Lockout
V
V
Falling
Rising
●
●
3.4
3.5
3.9
4.0
V
V
IN(UVLO)
IN1
IN
IN
TG R
TG R
BG R
BG R
TG Driver Pull-Up On Resistance
TG Driver Pull-Down On Resistance
BG Driver Pull-Up On Resistance
BG Driver Pull-Down On Resistance
TG Rise Time
TG High
TG Low
BG High
BG Low
2
2
3
3
4
2
Ω
Ω
UP
DOWN
UP
3
Ω
1
Ω
DOWN
TG t
TG t
C
C
C
C
= 3300pF
= 3300pF
= 3300pF
= 3300pF
20
20
20
20
ns
ns
ns
ns
r
f
LOAD
LOAD
LOAD
LOAD
TG Fall Time
BG t
BG t
BG Rise Time
r
BG Fall Time
f
Internal V Regulator
CC
V
Internal V Voltage
6V < V <30V
●
4.7
5
5.3
V
INTVCC
CC
IN1
∆V
LDO(LOAD)
Internal V Load Regulation
I = 0mA to 20mA
CC
–0.1
±2
%
CC
PGOOD Output
∆V
∆V
∆V
PGOOD Upper Threshold
PGOOD Lower Threshold
PGOOD Hysterisis
V
V
V
= Rising
8
10
–10
1
12
–12
2
%
%
%
V
FB1H
FB1
FB1
= Falling
–8
FB1L
= Returning
FB1(HYS)
FB1
V
PGOOD Low Voltage
I
= 5mA
0.15
0.4
PGL
PGOOD
Boost Regulator
V
V
Minimum Operating Voltage
Maximum Operating Voltage
0.9
1.5
10
V
V
IN2(MIN)
IN2(MAX)
Q(VIN2)
I
Input DC Supply Current (V
)
IN2
Normal
Shutdown Supply Current
3
0.01
4.5
1
mA
µA
V
=0V
SHDN
V
V
V
Feedback Voltage
0°C < T < 70°C
1.205
1.20
1.23
1.23
1.255
1.26
V
V
FB2
FB2
●
●
I
Pin Bias Current
27
80
nA
VFB2
FB2
∆V
Boost Reference Line Regulation
BOOST Switching Frequency
1.5V < V < 10V
0.02
0.2
%/V
FB2(LINE)
IN2
f
0°C < T < 70°C
1.0
0.9
1.4
1.4
1.8
1.9
MHz
MHz
BOOST
●
DC
BOOST Maximum Duty Cycle
BOOST Switch Current Limit
82
86
%
mA
mV
µA
V
BOOST(MAX)
I
(Note 5)
500
800
300
0.01
LIM(BOOST)
V
BOOST Switch V
I
SW
= 300mA
= 5V
350
1
CESAT(BOOST)
CESAT
I
BOOST Switch Leakage Current
SHDN Input Voltage High
SHDN Input Voltage Low
SHDN Pin Bias Current
V
SWLKG(BOOST)
SW
V
V
1
SHDN(HIGH)
SHDN(LOW)
SHDN
0.3
V
I
V
V
= 3V
= 0V
25
0.01
50
0.1
µA
µA
SHDN
SHDN
3718fa
3
LTC3718
ELECTRICAL CHARACTERISTICS
Note 1: Absolute Maximum Ratings are those values beyond which the life
Note 3: The LTC3718 is tested in a feedback loop that adjusts V to
FB1
of a device may be impaired.
achieve a specified error amplifier output voltage (I ).
TH
Note 2: T is calculated from the ambient temperature T and power
Note 4: The LTC3718 is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
J
A
dissipation P as follows:
D
LTC3718EG: T = T + (P • 130°C/W)
J
A
D
Note 5: Current limit guaranteed by design and/or correlation to static test.
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Boost Converter Oscillator
Frequency vs Temperature
Boost Converter Current Limit
vs Duty Cycle
SHDN Pin Current vs VSHDN
1000
900
800
700
600
500
400
300
200
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
50
40
30
20
10
0
T
= 25°C
A
V
= 5V
IN
70°C
25°C
V
IN
= 1.5V
–40°C
0
1
2
3
4
5
–50
–25
0
25
50
75
100
10
20
30
40
50
60
70
80
SHDN PIN VOLTAGE (V)
TEMPERATURE (°C)
DUTY CYCLE (%)
3718 G02
3718 G01
3718 G03
V
OUT/VIN Tracking Ratio vs Input
VFB2, Feedback Pin Voltage
Efficiency vs Load Current
Voltage
100
90
80
70
60
50
40
30
20
10
0
50.00
49.95
49.90
49.85
49.80
49.75
49.70
49.65
1.25
1.24
1.23
1.22
1.21
1.20
V
IN
V
OUT
= 2.5V
= 1.25V
LOAD = 0A
LOAD = 1A
LOAD = 10A
FIGURE 1 CIRCUIT
10
FIGURE 1 CIRCUIT
FIGURE 1 CIRCUIT
0.01
0.1
1
100
1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9
INPUT VOLTAGE (V)
–50
–25
0
25
50
75
100
LOAD CURRENT (A)
TEMPERATURE (°C)
3718 G05/TA01a
3718 G06
3718 G04
3718fa
4
LTC3718
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Frequency vs Input Voltage
Load Regulation
450
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
V
V
= 2.5V
IN
OUT
400
= 1.25V
LOAD = 10A
350
300
250
LOAD = 0A
200
150
100
V
= 1.25V
FIGURE 1 CIRCUIT
OUT
50
0
FIGURE 1 CIRCUIT
1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9
INPUT VOLTAGE (V)
0
1
2
3
4
5
6
7
8
9
10
LOAD CURRENT (A)
3718 G07
3718 G08
Load-Step Transient
Start-Up Response
VOUT
200mV/DIV
VOUT
1V/DIV
IL
IL
5A/DIV
2A/DIV
VIN = 2.5V
20µs/DIV
3718 G10.eps
VIN = 2.5V
4ms/DIV
3718 G09.eps
VOUT = 1.25V
LOAD = 500mA TO 10A STEP
FIGURE 1 CIRCUIT
VOUT = 1.25V
LOAD = 0.2Ω
FIGURE 1 CIRCUIT
On-Time vs VON Voltage
On-Time vs Temperature
On-Time vs ION Current
10k
300
250
200
150
1000
800
600
400
200
0
V = 0V
VON
I
= 30µA
I
= 30µA
ION
ION
1k
100
10
100
50
0
1
10
100
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
1
2
3
0
I
ON
CURRENT (µA)
V
VOLTAGE (V)
ON
3718 G13
3718 G12
3718 G11
3718fa
5
LTC3718
U W
TYPICAL PERFOR A CE CHARACTERISTICS
RUN/SS Latchoff Thresholds
vs Temperature
RUN/SS Latchoff Thresholds
vs Temperature
INTVCC Load Regulation
3
2
5.0
4.5
4.0
3.5
0
–0.1
–0.2
–0.3
–0.4
–0.5
PULL-DOWN CURRENT
LATCHOFF ENABLE
1
0
PULL-UP CURRENT
–1
LATCHOFF THRESHOLD
–2
3.0
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
0
10
20
30
40
50
TEMPERATURE (°C)
TEMPERATURE (°C)
INTV LOAD CURRENT (mA)
CC
3718 G15
3718 G16
3718 G14
Undervoltage Lockout Threshold
vs Temperature
Maximum Current Sense Threshold
vs VRNG Voltage
Maximum Current Sense Threshold
vs RUN/SS Voltage, VRNG = 1V
300
250
200
150
100
50
4.0
3.5
3.0
2.5
160
140
120
100
80
60
40
20
0
2.0
0
2.4
–50 –25
0
25
50
75 100 125
0.50
1.00 1.25 1.50
(V)
1.75 2.00
2.0 2.2
2.6 2.8 3.0 3.2 3.4 3.6
RUN/SS (V)
0.75
TEMPERATURE (C)
V
RNG
3718 G17
3718 G18
2718 G19
Error Amplifier gm
vs Temperature
Maximum Current Sense Threshold
vs Temperature, VRNG = 1V
1.50
1.40
1.30
1.20
1.10
1.00
0.90
0.80
0.70
180
160
140
120
100
80
60
40
20
0
110
130
–50
10 30 50
90
–30 –10
70
110
130
–50
10 30 50
90
–30 –10
70
TEMPERATURE (°C)
TEMPERATURE (°C)
3718 G21
3718 G20
3718fa
6
LTC3718
U
U
U
PI FU CTIO S
RUN/SS (Pin 1): Run Control and Soft-Start Input. A
capacitor to ground at this pin sets the ramp time to full
output current (approximately 3s/µF) and the time delay
for overcurrent latchoff (see Applications Information).
Forcing this pin below 0.8V shuts down the device.
V
FB2 (Pin 12): Boost Converter Feedback. The VFB2 pin is
connected to INTVCC through a resistor divider to set the
voltage on INTVCC. Set INTVCC voltage according to:
V
INTVCC = 1.23V(1 + RF2/RF1)
SW2 (Pin 13): Boost Converter Switch Pin. Connect
inductor/diode for boost converter portion here. Minimize
trace area at this pin to keep EMI down.
V
ON (Pin 2): On-Time Voltage Input. Voltage trip point for
the on-time comparator. Tying this pin to the output
voltage makes the on-time proportional to VOUT. The
comparatorinputdefaultsto0.7Vwhenthepinisgrounded,
2.4V when the pin is tied to INTVCC.
PGND (Pins 14, 19): Power Ground. Connect these pins
closely to the source of the bottom N-channel MOSFET,
the (–) terminal of CVCC and the (–) terminal of CIN.
PGOOD (Pin 3): Power Good Output. Open-drain logic
output that is pulled to ground when the output voltage of
thebucksectionisnotwithin±10%oftheregulationpoint.
VIN2 (Pin 15): Input Supply Pin for Boost Converter
Portion of LTC3718. Must be locally bypassed.
VIN1 (Pin 16): Main Input Supply. Decouple this pin to
PGND with at least a 1µF ceramic capacitor.
VRNG (Pin 4): Sense Voltage Range Input. The voltage at
this pin is ten times the nominal sense voltage at maxi-
mum output current and can be set from 0.5V to 2V by a
resistive divider from INTVCC. The nominal sense voltage
defaults to 70mV when this pin is tied to ground, 140mV
when tied to INTVCC.
INTVCC (Pin17):InternalRegulatorOutput.Thedriverand
control circuits are powered from this voltage when VIN is
greater than 5V. Decouple this pin to power ground with a
minimumof4.7µFlowESRtantalumorceramiccapacitor.
ITH (Pin 5): Current Control Threshold and Error Amplifier
Compensation Point. The current comparator threshold
increases with this control voltage. The voltage ranges
from 0V to 2.4V with 1.2V corresponding to zero sense
voltage (zero current).
BG (Pin 18): Bottom Gate Drive. Drives the gate of the
bottom N-channel MOSFET between ground and INTVCC.
SENSE– (Pin 20): Negative Current Sense Comparator
Input. The (–) input to the current comparator is normally
connected to power ground unless using a resistive di-
vider from INTVCC (see Applications Information).
SENSE+ (Pin 21): Positive Current Sense Comparator
Input. The (+) input to the current comparator is normally
connected to the SW node unless using a sense resistor
(see Applications Information).
SGND (Pins 6, 11): Signal Ground. All small-signal com-
ponentsandcompensationcomponentsshouldconnectto
this ground, which in turn connects to PGND at one point.
ION (Pin 7): On-Time Current Input. Tie a resistor from VIN
tothispintosettheone-shottimercurrentandtherebyset
the switching frequency.
SW1 (Pin 22): Switch Node. The (–) terminal of the
bootstrap capacitor CB connects here. This pin swings
from a diode voltage drop below ground up to VIN.
VFB1 (Pin 8): Error Amplifier Feedback Input. This pin
connects the negative error amplifier input to VOUT
.
VREF (Pin 9): Positive Input of Internal Error Amplifier.
Reference voltage for output voltage, power good thresh-
old, and short-circuit shutdown threshold. The output
voltage is set to VREF/2.
TG (Pin 23): Top Gate Drive. Drives the top N-channel
MOSFET with a voltage swing equal to INTVCC superim-
posed on the switch node voltage SW.
BOOST (Pin 24): Boosted Floating Driver Supply. The (+)
terminal of the bootstrap capacitor CB connects here. This
pin swings from a diode voltage drop below INTVCC up to
VIN + INTVCC.
SHDN (Pin 10): Shutdown, Active Low. Tie to 1V or more
to enable boost converter portion of the LTC3718. Ground
to shut down.
3718fa
7
LTC3718
U
U
W
FU CTIO AL DIAGRA S
R
ON
V
V
ON
IN
2
7
I
ON
16
V
IN1
+
C
IN
0.7V
2.4V
0.8V
REF
5V
REG
BOOST
24
V
I
VON
ION
t
ON
=
(10pF)
R
S
C
TG
23
B
Q
I
M1
SW1
22
ON
20k
+
–
+
–
+
L1
SENSE
21
SWITCH
LOGIC
I
V
CMP
REV
OUT
D
B
INTV
17
CC
SHDN
OV
+
C
C
OUT
1.4V
RNG
VCC
BG
18
M2
V
PGND1
19
4
×
–
SENSE
20
0.7V
PGOOD
3
5.7µA
1
3/10V
240k
+
REF
Q2
UV
OV
–
R3
20k
I
V
THB
FB1
8
R4
40k
Q1
+
–
SGND1
6
Q5
11/30V
REF
RUN
SHDN
SS
–
+
1.2µA
EA
–
+
6V
0.6V
R2
80k
C
C1
C
SS
V
REF
I
TH
RUN/SS
1
9
5
0.6V
R
C
R1
40k
3718 FD01
V
IN2
15
R5
40k
R6
40k
V
13 SW2
Q3
OUT2
+
–
COMPARATOR
A2
–
+
A1
m
R7
DRIVER
g
(EXTERNAL)
V
FF
S
R
Q
R
FB2
C2
C
RAMP
Q1
Q2
Σ
FB2 12
GENERATOR
x10
+
–
C2
R9
30k
R8
(EXTERNAL)
0.15Ω
1.4MHz
OSCILLATOR
R10
140k
SHDN
10
SHUTDOWN
SGND2
11
14 PGND2
3718 FD02
3718fa
8
LTC3718
U
OPERATIO
Main Control Loop
INTVCC Power
The LTC3718 is a current mode controller for DC/DC
step-down converters designed to operate from low input
voltages. It incorporates a boost converter with a buck
regulator.
Power for the top and bottom MOSFET drivers and most
of the internal controller circuitry is derived from the
INTVCC pin. The top MOSFET driver is powered from a
floating bootstrap capacitor CB. This capacitor is re-
chargedfromINTVCC throughanexternalSchottkydiode
DB when the top MOSFET is turned off.
Buck Regulator Operation
In normal operation, the top MOSFET is turned on for a
fixed interval determined by a one-shot timer OST. When
the top MOSFET is turned off, the bottom MOSFET is
turned on until the current comparator ICMP trips, restart-
ing the one-shot timer and initiating the next cycle. Induc-
tor current is determined by sensing the voltage between
the SENSE+ and SENSE– pins using the bottom MOSFET
on-resistance . The voltage on the ITH pin sets the com-
parator threshold corresponding to inductor valley cur-
rent. The error amplifier EA adjusts this voltage by com-
paring the feedback signal VFB1 from the output voltage
with an internal reference generated from one half of the
voltage on VREF. If the load current increases, it causes a
drop in the feedback voltage relative to the reference. The
ITH voltage then rises until the average inductor current
again matches the load current.
Boost Regulator Operation
The 5V power source for INTVCC can be provided by a
current mode, internally compensated fixed frequency
step-up switching regulator that has been incorporated
into the LTC3718.
Operation can be best understood by referring to the
Functional Diagrams. Q1 and Q2 form a bandgap refer-
ence core whose loop is closed around the output of the
regulator. The voltage drop across R5 and R6 is low
enough such that Q1 and Q2 do not saturate, even when
VIN2 is1V. Whenthereisnoload, VFB2 risesslightlyabove
1.23V, causing VC (the error amplifier’s output) to de-
crease.ComparatorA2’soutputstayshigh,keepingswitch
Q3intheoffstate. Asincreasedoutputloadingcausesthe
VFB2 voltage to decrease, A1’s output increases. Switch
current is regulated directly on a cycle-by-cycle basis by
the VC node. The flip-flop is set at the beginning of each
switch cycle, turning on the switch. When the summation
of a signal representing switch current and a ramp gen-
erator (introduced to avoid subharmonic oscillations at
duty factors greater than 50%) exceeds the VC signal,
comparator A2 changes state, resetting the flip-flop and
turning off the switch. More power is delivered to the
output as switch current is increased. The output voltage,
attenuated by external resistor divider R7 and R8, appears
at the VFB2 pin, closing the overall loop. Frequency com-
pensation is provided internally by RC and CC. Transient
response can be optimized by the addition of a phase lead
capacitor CPL in parallel with R7 in applications where
large value or low ESR output capacitors are used.
The operating frequency is determined implicitly by the
top MOSFET on-time and the duty cycle required to
maintain regulation. The one-shot timer generates an on-
time that is proportional to the ideal duty cycle, thus
holding frequency approximately constant with changes
in VIN. The nominal frequency can be adjusted with an
external resistor RON.
Overvoltage and undervoltage comparators OV and UV
pull the PGOOD output low if the output feedback voltage
exits a ±10% window around the regulation point.
Furthermore, in an overvoltage condition, M1 is turned off
and M2 is turned on and held on until the overvoltage
condition clears.
Pulling the RUN/SS pin low forces the controller into its
shutdownstate,turningoffbothM1andM2.Releasingthe
pinallowsaninternal1.2µAcurrentsourcetochargeupan
externalsoft-startcapacitorCSS.Whenthisvoltagereaches
1.5V, the controller turns on and begins switching, but
with the ITH voltage clamped at approximately 0.6V below
the RUN/SS voltage. As CSS continues to charge, the soft-
start current limit is removed.
As the load current is decreased, the switch turns on for
a shorter period each cycle. If the load current is further
decreased, the boost converter will skip cycles to main-
tain output voltage regulation. If the VFB2 pin voltage is
increased significantly above 1.23V, the boost converter
will enter a low power state.
3718fa
9
LTC3718
W U U
U
APPLICATIO S I FOR ATIO
theSENSE+ andSENSE– pinsasaKelvinconnectiontothe
sense resistor with SENSE+ at the source of the bottom
MOSFET and the SENSE– pin to PGND1. Using a sense
resistorprovidesawelldefinedcurrentlimit,butaddscost
andreducesefficiency.Alternatively,onecaneliminatethe
sense resistor and use the bottom MOSFET as the current
senseelementbysimplyconnectingtheSENSE+pintothe
drain and the SENSE– pin to the source of the bottom
MOSFET. This improves efficiency, but one must carefully
choose the MOSFET on-resistance as discussed in a later
section.
A typical LTC3718 application circuit is shown in
Figure 1. External component selection is primarily de-
termined by the maximum load current and begins with
the selection of the sense resistance and power MOSFET
switches. The LTC3718 uses the on-resistance of the
synchronous power MOSFET for determining the induc-
tor current. The desired amount of ripple current and
operatingfrequencylargelydeterminestheinductorvalue.
Finally, CIN is selected for its ability to handle the large
RMS current into the converter and COUT is chosen with
low enough ESR to meet the output voltage ripple and
transient specification.
Power MOSFET Selection
Maximum Sense Voltage and VRNG Pin
The LTC3718 requires two external N-channel power
MOSFETs, one for the top (main) switch and one for the
bottom (synchronous) switch. Important parameters for
Inductor current is determined by measuring the voltage
across a sense resistance that appears between the
SENSE+ and SENSE– pins. The maximum sense voltage
is set by the voltage applied to the VRNG pin and is equal
to approximately (0.13)VRNG for sourcing current and
(0.17)VRNG forsinkingcurrent.Thecurrentmodecontrol
loop will not allow the inductor current valleys to exceed
(0.13)VRNG/RSENSE for sourcing current and (0.17)VRNG
for sinking current. In practice, one should allow some
margin for variations in the LTC3718 and external com-
ponent values and a good guide for selecting the sense
resistance is:
the power MOSFETs are the breakdown voltage V(BR)DSS
threshold voltage V(GS)TH, on-resistance RDS(ON), reverse
transfercapacitanceCRSS andmaximumcurrentIDS(MAX)
,
.
The gate drive voltage is set by the 5V INTVCC supply.
Consequently, logic-level threshold MOSFETs must be
used in LTC3718 applications.
When the bottom MOSFET is used as the current sense
element, particular attention must be paid to its
on-resistance. MOSFET on-resistance is typically speci-
fied with a maximum value RDS(ON)(MAX) at 25°C. In this
case, additional margin is required to accommodate the
rise in MOSFET on-resistance with temperature:
VRNG
10•IOUT(MAX)
RSENSE
=
when VRNG = 0.5 – 2V.
RSENSE
RDS(ON)(MAX)
=
An external resistive divider from INTVCC can be used to
set the voltage of the VRNG pin between 0.5V and 2V
resulting in nominal sense voltages of 50mV to 200mV.
Additionally, the VRNG pin can be tied to SGND or INTVCC
in which case the nominal sense voltage defaults to 70mV
or 140mV, respectively. The maximum allowed sense
voltage is about 1.3 times this nominal value for positive
output current and 1.7 times the nominal value for nega-
tive output current.
ρT
The ρT term is a normalization factor (unity at 25°C)
accounting for the significant variation in on-resistance
with temperature, typically about 0.4%/°C as shown in
Figure 2. For a maximum junction temperature of 100°C,
using a value ρT = 1.3 is reasonable.
The power dissipated by the top and bottom MOSFETs
strongly depends upon their respective duty cycles and
the load current. During normal operation, the duty cycles
for the MOSFETs are:
Connecting the SENSE+ and SENSE– Pins
TheLTC3718canbeusedwithorwithoutasenseresistor.
When using a sense resistor, it is placed between the
source of the bottom MOSFET M2 and ground. Connect
3718fa
10
LTC3718
W U U
APPLICATIO S I FOR ATIO
U
2.0
1.5
1.0
0.5
0
V
tON
=
VON (10pF)
I
ION
Tying a resistor RON from VIN to the ION pin yields an on-
time inversely proportional to VIN. For a step-down
converter, this results in approximately constant fre-
quency operation as the input supply varies:
VOUT
R (10pF)
f =
Hz
[ ]
VVON ON
50
100
–50
150
0
JUNCTION TEMPERATURE (°C)
Toholdfrequencyconstantduringoutputvoltagechanges,
tie the VON pin to VOUT. The VON pin has internal clamps
that limit its input to the one-shot timer. If the pin is tied
below 0.7V, the input to the one-shot is clamped at 0.7V.
Similarly, if the pin is tied above 2.4V, the input is clamped
at 2.4V.
3718 F02
Figure 2. RDS(ON) vs Temperature
VOUT
V
IN
DTOP
DBOT
=
=
V – VOUT
IN
Because the voltage at the ION pin is about 0.7V, the
currentintothispinisnotexactlyinverselyproportionalto
VIN, especially in applications with lower input voltages.
To account for the 0.7V drop on the ION pin, the following
equation can be used to calculate frequency:
V
IN
The resulting power dissipation in the MOSFETs at maxi-
mum output current are:
PTOP = DTOP OUT(MAX)
I
2 ρT(TOP) RDS(ON)(MAX)
+ k VIN IOUT(MAX) CRSS
PBOT = DBOT OUT(MAX)
2 ρT(BOT) RDS(ON)(MAX)
2
f
V − 0.7V •V
(
)
IN
OUT
f =
I
VVON •V •RON(10pF)
IN
Both MOSFETs have I2R losses and the top MOSFET
includesanadditionaltermfortransitionlosses,whichare
largest at high input voltages. The constant k = 1.7A–1 can
be used to estimate the amount of transition loss. The
bottomMOSFETlossesaregreatestwhenthebottomduty
cycle is near 100%, during a short-circuit or at high input
voltage.
To correct for this error, an additional resistor RON2
connected from the ION pin to the 5V INTVCC supply will
further stabilize the frequency.
5V
0.7V
RON2
=
RON
Changes in the load current magnitude will also cause
frequency shift. Parasitic resistance in the MOSFET
switches and inductor reduce the effective voltage across
the inductance, resulting in increased duty cycle as the
loadcurrentincreases.Bylengtheningtheon-timeslightly
as current increases, constant frequency operation can be
maintained. This is accomplished with a resistive divider
from the ITH pin to the VON pin and VOUT. The values
required will depend on the parasitic resistances in the
specific application. A good starting point is to feed about
25% of the voltage change at the ITH pin to the VON pin as
shown in Figure 3a. Place capacitance on the VON pin to
Operating Frequency
The choice of operating frequency is a tradeoff between
efficiency and component size. Low frequency operation
improvesefficiencybyreducingMOSFETswitchinglosses
but requires larger inductance and/or capacitance in order
to maintain low output ripple voltage.
TheoperatingfrequencyofLTC3718applicationsisdeter-
mined implicitly by the one-shot timer that controls the
on-time tON of the top MOSFET switch. The on-time is set
by the current into the ION pin and the voltage at the VON
pin according to:
3718fa
11
LTC3718
APPLICATIO S I FOR ATIO
W U U
U
R
VON1
R
VON1
3k
30k
V
V
ON
V
V
OUT
ON
OUT
C
R
VON
C
VON2
VON
R
0.01µF
VON2
100k
10k
10k
0.01µF
LTC3718
TH
LTC3718
TH
INTV
CC
R
R
C
C
Q1
2N5087
I
I
C
C
C
C
3718 F03
(3a)
(3b)
Figure 3. Adjusting Frequency Shift with Load Current Changes
filter out the ITH variations at the switching frequency. The
resistor load on ITH reduces the DC gain of the error amp
and degrades load regulation, which can be avoided by
using the PNP emitter follower of Figure 3b.
available from manufacturers such as Sumida, Pana-
sonic, Coiltronics, Coilcraft and Toko.
Schottky Diode D1, D2 Selection
The Schottky diodes, D1 and D2, shown in Figure 1
conduct during the dead time between the conduction of
the power MOSFET switches. It is intended to prevent the
body diodes of the top and bottom MOSFETs from turning
on and storing charge during the dead time, which can
causeamodest(about1%)efficiencyloss. Thediodescan
beratedforaboutonehalftoonefifthofthefullloadcurrent
since they are on for only a fraction of the duty cycle. In
order for the diode to be effective, the inductance between
it and the bottom MOSFET must be as small as possible,
mandating that these components be placed adjacently.
The diodes can be omitted if the efficiency loss is tolerable.
Inductor L1 Selection
Given the desired input and output voltages, the inductor
value and operating frequency determine the ripple
current:
VOUT
fL
VOUT
V
IN
∆IL =
1−
Lower ripple current reduces cores losses in the inductor,
ESR losses in the output capacitors and output voltage
ripple. Highest efficiency operation is obtained at low
frequency with small ripple current. However, achieving
this requires a large inductor. There is a tradeoff between
component size, efficiency and operating frequency.
CIN and COUT Selection
The input capacitance CIN is required to filter the square
wave current at the drain of the top MOSFET. Use a low
ESR capacitor sized to handle the maximum RMS current.
A reasonable starting point is to choose a ripple current
that is about 40% of IOUT(MAX). The largest ripple current
occurs at the highest VIN. To guarantee that ripple current
does not exceed a specified maximum, the inductance
should be chosen according to:
VOUT
V
IN
V
IN
VOUT
IRMS IOUT(MAX)
– 1
VOUT
f∆IL(MAX)
VOUT
V
IN(MAX)
This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT(MAX)/2. This simple worst-case condition is
commonly used for design because even significant
deviations do not offer much relief. Note that ripple
current ratings from capacitor manufacturers are often
basedononly2000hoursoflifewhichmakesitadvisable
to derate the capacitor.
L =
1−
Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
afford the core loss found in low cost powdered iron
cores, forcing the use of more expensive ferrite,
molypermalloy or Kool Mµ® cores. A variety of inductors
designed for high current, low voltage applications are
The selection of COUT is primarily determined by the ESR
required to minimize voltage ripple and load step
Kool Mµ is a registered trademark of Magnetics, Inc.
3718fa
12
LTC3718
W U U
APPLICATIO S I FOR ATIO
U
transients. The output ripple ∆VOUT is approximately
bounded by:
top MOSFET. In most applications a 0.1µF to 0.47µF X5R
or X7R dielectric capacitor is adequate.
1
Fault Condition: Current Limit
∆VOUT ≤ ∆IL ESR +
8fCOUT
The maximum inductor current is inherently limited in a
currentmodecontrollerbythemaximumsensevoltage.In
the LTC3718, the maximum sense voltage is controlled by
the voltage on the VRNG pin. With valley current control,
the maximum sense voltage and the sense resistance
determine the maximum allowed inductor valley current.
The corresponding output current limit is:
Since ∆IL increases with input voltage, the output ripple is
highestatmaximuminputvoltage.Typically,oncetheESR
requirement is satisfied, the capacitance is adequate for
filtering and has the necessary RMS current rating.
Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, special polymer, aluminum electrolytic and
ceramic capacitors are all available in surface mount
packages. Special polymer capacitors offer very low ESR
but have lower capacitance density than other types.
Tantalumcapacitorshavethehighestcapacitancedensity
but it is important to only use types that have been surge
tested for use in switching power supplies. Aluminum
electrolytic capacitors have significantly higher ESR, but
can be used in cost-sensitive applications providing that
consideration is given to ripple current ratings and long
term reliability. Ceramic capacitors have excellent low
ESR characteristics but can have a high voltage coeffi-
cient and audible piezoelectric effects. The high Q of
ceramic capacitors with trace inductance can also lead to
significant ringing. When used as input capacitors, care
must be taken to ensure that ringing from inrush currents
and switching does not pose an overvoltage hazard to the
power switches and controller. To dampen input voltage
transients, add a small 5µF to 50µF aluminum electrolytic
capacitor with an ESR in the range of 0.5Ω to 2Ω. High
performance through-hole capacitors may also be used,
but an additional ceramic capacitor in parallel is recom-
mended to reduce the effect of their lead inductance.
VSNS(MAX)
1
ILIMITPOSITIVE
ILIMITNEGATIVE
=
+ ∆IL
2
RDS(ON)ρT
VSNS(MIN)
1
=
− ∆IL
2
RDS(ON)ρT
The current limit value should be checked to ensure that
ILIMIT(MIN) >IOUT(MAX).Theminimumvalueofcurrentlimit
generally occurs with the largest VIN at the highest ambi-
ent temperature, conditions that cause the largest power
loss in the converter. Note that it is important to check for
self-consistency between the assumed MOSFET junction
temperature and the resulting value of ILIMIT which heats
the MOSFET switches.
Caution should be used when setting the current limit
based upon the RDS(ON) of the MOSFETs. The maximum
current limit is determined by the minimum MOSFET on-
resistance. Data sheets typically specify nominal and
maximum values for RDS(ON), but not a minimum. A
reasonable assumption is that the minimum RDS(ON) lies
the same amount below the typical value as the maximum
liesaboveit.ConsulttheMOSFETmanufacturerforfurther
guidelines.
Top MOSFET Driver Supply (CB, DB)
Minimum Off-time and Dropout Operation
AnexternalbootstrapcapacitorCBconnectedtotheBOOST
pinsuppliesthegatedrivevoltageforthetopsideMOSFET.
This capacitor is charged through diode DB from INTVCC
when the switch node is low. When the top MOSFET turns
on, the switch node rises to VIN and the BOOST pin rises
to approximately VIN + INTVCC. The boost capacitor needs
to store about 100 times the gate charge required by the
The minimum off-time tOFF(MIN) is the smallest amount of
time that the LTC3718 is capable of turning on the bottom
MOSFET, tripping the current comparator and turning the
MOSFET back off. This time is generally about 250ns. The
minimum off-time limit imposes a maximum duty cycle of
tON/(tON +tOFF(MIN)).Ifthemaximumdutycycleisreached,
3718fa
13
LTC3718
W U U
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APPLICATIO S I FOR ATIO
due to a dropping input voltage for example, then the
output will drop out of regulation. The minimum input
voltage to avoid dropout is:
Alternately, the external buffer circuit shown in Figure 5
can be used. Note that the bipolar devices reduce the
signal swing at the MOSFET gate.
t
ON + tOFF(MIN)
Soft-Start and Latchoff with the RUN/SS Pin
V
= VOUT
IN(MIN)
tON
The RUN/SS pin provides a means to shut down the
LTC3718 as well as a timer for soft-start and overcurrent
latchoff. Pulling the RUN/SS pin below 0.8V puts the
LTC3718 into a low quiescent current shutdown
(IQ < 30µA). Releasing the pin allows an internal 1.2µA
current source to charge up the external timing capacitor
CSS. If RUN/SS has been pulled all the way to ground,
there is a delay before starting of about:
Output Voltage Programming
When VFB is connected to VOUT, the output voltage is
regulated to one half of the voltage at the VREF pin. A
resistor connected between VFB and VOUT can be used to
further adjust the output voltage according to the follow-
ing equation:
60k + RFB
1.5V
1.2µA
VOUT = VREF
tDELAY
=
CSS = 1.3s/µF CSS
(
)
120k
If VREF exceeds 3V, resistors should be placed in series
with the VREF pin and the VFB pin to avoid exceeding the
input common mode range of the internal error amplifier.
To maintain the VOUT = VREF/2 relationship, the resistor in
series with the VREF pin should be made twice as large as
the resistor in series with the VFB pin.
When the voltage on RUN/SS reaches 1.5V, the LTC3718
begins operating with a clamp on ITH of approximately
0.9V. As the RUN/SS voltage rises to 3V, the clamp on ITH
is raised until its full 2.4V range is available. This takes an
additional 1.3s/µF, during which the load current is folded
back. During start-up, the maximum load current is re-
duced until either the RUN/SS pin rises to 3V or the output
reaches 75% of its final value. The pin can be driven from
logic as shown in Figure 6. Diode D1 reduces the start
delay while allowing CSS to charge up slowly for the soft-
start function.
R
FB
249k
V
OUT
V
FB1
LTC3718
R
FB
499k
V
V
REF
REF
3718 F04
INTV
CC
Figure 4
R
*
SS
V
IN
RUN/SS
External Gate Drive Buffers
3.3V OR 5V
RUN/SS
*
D2*
R
SS
D1
The LTC3718 drivers are adequate for driving up to about
30nC into MOSFET switches with RMS currents of 50mA.
Applications with larger MOSFET switches or operating at
frequencies requiring greater RMS currents will benefit
fromusingexternalgatedrivebufferssuchastheLTC1693.
C
SS
C
SS
3718 F06
*OPTIONAL TO OVERRIDE
OVERCURRENT LATCHOFF
(6a)
(6b)
BOOST
INTV
CC
Figure 6. RUN/SS Pin Interfacing with Latchoff Defeated
Q1
FMMT619
Q3
FMMT619
After the controller has been started and given adequate
time to charge up the output capacitor, CSS is used as a
short-circuit timer. After the RUN/SS pin charges above
4V, if the output voltage falls below 75% of its regulated
value, then a short-circuit fault is assumed. A 1.8µA cur-
10Ω
10Ω
GATE
OF M1
GATE
TG
BG
OF M2
Q2
Q4
FMMT720
FMMT720
SW
PGND
3718 F05
rent then begins discharging CSS. If the fault condition
Figure 5. Optional External Gate Driver
3718fa
14
LTC3718
W U U
APPLICATIO S I FOR ATIO
persists until the RUN/SS pin drops to 3.5V, then the con-
troller turns off both power MOSFETs, shutting down the
converter permanently. The RUN/SS pin must be actively
pulled down to ground in order to restart operation.
U
Inductor Selection for Boost Converter
For the boost converter, the inductance should be 4.7µH
for input voltages less then 3.3V and 10µH for inputs
above 3.3V. The inductor should have a saturation current
rating of approximately 0.5A or greater. A guide for select-
inganinductorfortheboostconverteristochoosearipple
current that is 40% of the current supplied by the boost
converter.Toensurethattheripplecurrentdoesn’texceed
a specified amount, the inductance can be chosen accord-
ing to the following equation:
The overcurrent protection timer requires that the soft-
start timing capacitor CSS be made large enough to guar-
antee that the output is in regulation by the time CSS has
reachedthe4Vthreshold.Ingeneral,thiswilldependupon
the size of the output capacitance, output voltage and load
currentcharacteristic.Aminimumsoft-startcapacitorcan
be estimated from:
V
SS > COUT VOUT RSENSE (10–4 [F/V s])
IN2(MAX)
C
V
1–
IN2(MIN)
VOUT(BOOST)
∆I• f
Diode D3 Selection
Generally 0.1µF is more than sufficient.
L =
Overcurrent latchoff operation is not always needed or
desired. The feature can be overridden by adding a pull-
up current greater than 5µA to the RUN/SS pin. The
additional current prevents the discharge of CSS during a
fault and also shortens the soft-start period. Using a
resistortoVIN asshowninFigure6aissimple, butslightly
increases shutdown current. Connecting a resistor to
INTVCC as shown in Figure 6b eliminates the additional
shutdowncurrent, butrequiresadiodetoisolateCSS. Any
pull-up network must be able to pull RUN/SS above the
4.2V maximum threshold of the latchoff circuit and over-
come the 4µA maximum discharge current.
A Schottky diode is recommended for use in the boost
converter section. The Motorola MBR0520 is a very good
choice.
Boost Converter Output Capacitor
Because the LTC3718’s boost converter is internally com-
pensated,loopstabilitymustbecarefullyconsideredwhen
choosing its output capacitor. Small, low cost tantalum
capacitors have some ESR, which aids stability. However,
ceramic capacitors are becoming more popular, having
attractivecharacteristicssuchasnear-zeroESR,smallsize
and reasonable cost. Simply replacing a tantalum output
capacitorwithaceramicunitwilldecreasethephasemargin,
in some cases to unacceptable levels. With the addition of
a phase-lead capacitor and isolating resistor, the boost
converter portion of the LTC3718 can be used success-
fully with ceramic output capacitors.
INTVCC Supply
The 5V supply that powers the drivers and internal cir-
cuitry within the LTC3718 can be supplied by either an
internal P-channel low dropout regulator if VIN is greater
than5VortheinternalboostregulatorifVIN islessthan5V.
The INTVCC pin can supply up to 50mA RMS and must be
bypassed to ground with a minimum of 4.7µF tantalum or
other low ESR capacitor. Good bypassing is necessary to
supplythehightransientcurrentsrequiredbytheMOSFET
gate drivers. Applications using large MOSFETs with a
high input voltage and high frequency of operation may
cause the LTC3718 to exceed its maximum junction tem-
peratureratingorRMScurrentrating.Incontinuousmode
operation, this current is IGATECHG = f(Qg(TOP) + Qg(BOT)).
The junction temperature can be estimated from the
equations given in Note 2 of the Electrical Characteristics.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Although all dissipative
elements in the circuit produce losses, four main sources
account for most of the losses in LTC3718 circuits:
3718fa
15
LTC3718
W U U
U
APPLICATIO S I FOR ATIO
1. DC I2R losses. These arise from the resistances of the
MOSFETs, inductor and PC board traces and cause the
efficiency to drop at high output currents. In continuous
mode the average output current flows through L, but is
chopped between the top and bottom MOSFETs. If the two
MOSFETs have approximately the same RDS(ON), then the
resistanceofoneMOSFETcansimplybesummedwiththe
resistances of L and the board traces to obtain the DC I2R
loss.Forexample,ifRDS(ON) =0.01ΩandRL =0.005Ω,the
loss will range from 1% up to 10% as the output current
varies from 1A to 10A for a 1.5V output.
discharge COUT generating a feedback error signal used
by the regulator to return VOUT to its steady-state value.
During this recovery time, VOUT can be monitored for
overshoot or ringing that would indicate a stability
problem. The ITH pin external components shown in
Figure 1 will provide adequate compensation for most
applications. For a detailed explanation of switching
control loop theory see Application Note 76.
Design Example
As a design example, take a supply with the following
specifications: VIN = 2.5V, VOUT = 1.25V ±100mV,
IOUT(MAX) = ±6A, f = 300kHz. First, calculate the timing
2. Transition loss. This loss arises from the brief amount
of time the top MOSFET spends in the saturated region
during switch node transitions. It depends upon the input
voltage, load current, driver strength and MOSFET capaci-
tance, among other factors. The loss is significant at input
voltages above 20V and can be estimated from:
resistor with VON = VOUT
:
2.5V − 0.7V
(2.5V)(300kHz)(10pF)
RON
=
= 240k
2
Transition Loss (1.7A–1) VIN IOUT CRSS
f
Next,useastandardvalueof237kandchoosetheinductor
for about 40% ripple current at the maximum VIN:
3. INTVCC current. This is the sum of the MOSFET driver
and control currents.
1.25V
(300kHz)(0.4)(6A)
1.25V
2.5V
L =
1–
= 0.87µH
4. CIN loss. The input capacitor has the difficult job of
filtering the large RMS input current to the regulator. It
must have a very low ESR to minimize the AC I2R loss and
sufficient capacitance to prevent the RMS current from
causing additional upstream losses in fuses or batteries.
Selecting a standard value of 1µH results in a maximum
ripple current of:
1.25V
(300kHz)(1µH)
1.25V
2.5V
Other losses, including COUT ESR loss, Schottky diode D1
conduction loss during dead time and inductor core loss
generally account for less than 2% additional loss.
∆IL =
1–
= 2.1A
Next,choosethesynchronousMOSFETswitch.Choosing
an IRF7811A (RDS(ON) = 0.013Ω, CRSS = 60pF, θJA
50°C/W) yields a nominal sense voltage of:
Whenmakingadjustmentstoimproveefficiency,theinput
current is the best indicator of changes in efficiency. If you
make a change and the input current decreases, then the
efficiency has increased. If there is no change in input
current, then there is no change in efficiency.
=
VSNS(NOM) = (6A)(1.3)(0.013Ω) = 101.4mV
Tying VRNG to 1V will set the current sense voltage range
for a nominal value of 100mV with current limit occurring
at 133mV. To check if the current limit is acceptable,
assume a junction temperature of about 10°C above a
50°C ambient with ρ60°C = 1.15:
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
aloadstepoccurs,VOUT immediatelyshiftsbyanamount
equal to ∆ILOAD (ESR), where ESR is the effective series
resistance of COUT. ∆ILOAD also begins to charge or
133mV
(1.15)(0.013Ω) 2
1
ILIMIT
≥
+ (2.1A) = 9.9A
3718fa
16
LTC3718
W U U
APPLICATIO S I FOR ATIO
U
ESR of 0.005Ω to minimize output voltage changes due to
inductor ripple current and load steps. The ripple voltage
will be only:
and double check the assumed TJ in the MOSFET:
2
2.5V – 1.25V 9.9A
P
BOT
=
(1.15)(0.013Ω)
∆VOUT(RIPPLE) = ∆IL(MAX) (ESR)
= (2.6A) (0.005Ω) = 13mV
2.5V
= 0.18W
2
However, a 0A to 6A load step will cause an output change
of up to:
TJ = 50°C + (0.18W)(50°C/W) = 59°C
Now check the power dissipation of the top MOSFET at
current limit with ρ90°C = 1.35:
∆VOUT(STEP) = ∆ILOAD (ESR) = (6A) (0.005Ω) = 30mV
The inductor for the boost converter is selected by first
choosing an allowable ripple current. The boost converter
willbeoperatingindiscontinousmode.Ifweselectaripple
current of 170mA for the boost converter, then:
2
) (
1.25V
2.5V
PTOP
=
9.9A 1.35 0.013Ω
(
)(
)
2
+ 1.7 2.5V 9.9A 60pF 300kHz
(
)(
)(
) (
)(
)
3.3V
5V
= 0.87W
3.3V 1−
L =
= 4.7µH
TJ = 50°C + (0.87W)(50°C/W) = 93.5°C
(170mA)(1.4MHz)
CIN is chosen for an RMS current rating of about 6A at
temperature. The output capacitors are chosen for a low
The complete circuit is shown in Figure 7.
V
IN
2.5V
C
22µF
×2
IN1
C
IN2
330µF
C
SS
0.1µF
R
PG
100k
R
R2
39.2k
D
B
CMDSH-3
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
17
16
15
14
13
RUN/SS
BOOST
TG
C
B
0.33µF
D1
M1
V
ON
B340A
IRF7811A
PGOOD
PGOOD
SW1
R
R1
10k
+
V
RNG
SENSE
L1
1µH
R
C
V
4.75k
OUT
–
1.25V
I
SENSE
TH
C2
100pF
±6A
C1 820pF
C
OUT
SGND1
PGND1
270µF
R
ON
237k
×2
LTC3718
M2
IRF7811A
D2
B340A
I
BG
ON
V
V
INTV
FB1
CC
IN1
IN2
V
V
REF
10
11
12
SHDN
C
IN2
4.7µF
L2
4.7µH
SGND2
PGND2
SW2
V
FB2
R
F3
10k
C
D3
MBR0520
VCC1
10µF
R
F1
12.1k
R
F2
37.4k
3718 F07
C
F4
1000pF
Figure 7. Design Example: 1.25V/±6A at 300kHz from 2.5V
3718fa
17
LTC3718
W U U
U
APPLICATIO S I FOR ATIO
PC Board Layout Checklist
• Flood all unused areas on all layers with copper.
Flooding with copper will reduce the temperature rise
of power component. You can connect the copper
areas to any DC net (VIN, VOUT, GND or to any other DC
rail in your system).
When laying out a PC board follow one of the two
suggested approaches. The simple PC board layout
requires a dedicated ground plane layer. Also, for higher
currents, it is recommended to use a multilayer board to
help with heat sinking power components.
When laying out a printed circuit board, without a ground
plane,usethefollowingchecklisttoensureproperopera-
tion of the controller. These items are also illustrated in
Figure 8.
• The ground plane layer should not have any traces and
itshouldbeascloseaspossibletothelayerwithpower
MOSFETs.
• Segregate the signal and power grounds. All small
signal components should return to the SGND pin at
one point which is then tied to the PGND pin close to
the source of M2.
• Place CIN, COUT, MOSFETs, D1 and inductor all in one
compact area. It may help to have some components
on the bottom side of the board.
• Place LTC3718 chip with Pins 13 to 24 facing the
power components. Keep the components connected
to Pins 1 to 12 close to LTC3718 (noise sensitive
components).
• Place M2 as close to the controller as possible, keep-
ing the PGND, BG and SW traces short.
• Connect the input capacitor(s) CIN close to the power
MOSFETs. This capacitor carries the MOSFET AC
current.
• Use an immediate via to connect the components to
ground plane including SGND and PGND of LTC3718.
Use several bigger vias for power components.
• Keep the high dV/dt SW, BOOST and TG nodes away
from sensitive small-signal nodes.
• Use compact plane for switch node (SW) to improve
cooling of the MOSFETs and to keep EMI down.
• ConnecttheINTVCC decouplingcapacitorCVCC closely
to the INTVCC and PGND pins.
• Use planes for VIN and VOUT to maintain good voltage
filtering and to keep power losses low.
• Connect the top driver boost capacitor CB closely to
the BOOST and SW pins.
V
IN
C
SS
+
1
2
24
23
22
21
20
19
18
17
16
15
14
13
RUN/SS
BOOST
TG
C
B
M1
C
IN
V
ON
D
B
3
PGOOD
SW1
L1
4
+
V
OUT
V
SENSE
RNG
C1
R
C
5
–
I
SENSE
TH
C
OUT
6
M2
D2
SGND1
PGND1
C2
LTC3718
R
ON
7
I
BG
ON
8
C
VCC
V
V
INTV
FB1
REF
CC
IN1
IN2
–
9
V
V
10
11
12
SHDN
3718 F08
C
IN2
L2
BOLD LINES INDICATE HIGH CURRENT PATHS
SGND2
PGND2
SW2
D3
V
FB2
R
F5
R
F3
R
F4
Figure 8. LTC3718 Layout Diagram
3718fa
18
LTC3718
U
TYPICAL APPLICATIO
One Half VIN, ±10A Bus Terminator
V
IN
2.5V
C
IN1
22µF X5R
×2
C
****
C
IN2
SS
R
D
B
PG
330µF
0.1µF X7R
100k
CMDSH-3
1
2
24
RUN/SS
BOOST
TG
C
0.33µF
B
X7R
23
22
21
20
19
18
17
16
15
14
13
D1
B340A
M1
Si7440DP
V
ON
3
PGOOD
PGOOD
SW1
C1
820pF
X7R
4
+
V
SENSE
L1**
0.8µH
RNG
R
4.75k
V
OUT
C
5
–
1.25V
I
SENSE
TH
C2
100pF
±10A
C
*
+
6
OUT
SGND1
PGND1
470µF
×2
R
ON
237k
22µF
X5R
LTC3718
7
M2
Si7440DP
D2
B340A
I
BG
ON
8
V
V
INTV
FB1
REF
CC
IN1
IN2
9
V
V
10
11
12
SHDN
4.7µF
6.3V X7R
L2***
4.7µH
SGND2
PGND2
SW2
V
FB2
C
R
F3
10k
VCC1
D3
MBR0520
R
F1
12.1k
R
10µF 6.3V
F2
37.4k
X5R
3718 TA02
C
F4
1000pF X7R
*SANYO POSCAP 4TPB470M
**SUMIDA CEP125-0R8MC
***PANASONIC ELJPC4R7MF
****SANYO POSCAP 6TPB330M
U
PACKAGE DESCRIPTIO
G Package
24-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
7.90 – 8.50*
(.311 – .335)
24 23 22 21 20 19 18 17 16 15 14
1.25 ±0.12
13
7.8 – 8.2
5.3 – 5.7
7.40 – 8.20
(.291 – .323)
0.42 ±0.03
0.65
BSC
RECOMMENDED SOLDER PAD LAYOUT
5
7
8
1
2
3
4
6
9
10 11 12
2.0
(.079)
5.00 – 5.60**
(.197 – .221)
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.25
0.55 – 0.95
(.0035 – .010)
(.022 – .037)
0.22 – 0.38
(.009 – .015)
0.05
(.002)
G24 SSOP 0802
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
3. DRAWING NOT TO SCALE
3718fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will notinfringe onexisting patent rights.
19
LTC3718
U
TYPICAL APPLICATIO
Dual Output 2.5V, ±10A Buck Converter and 5V to 12V/130mA Boost Converter
V
IN
6V TO 24V
C
****
IN1
C
SS
0.1µF X7R
R
33µF
×2
D
PG
100k
B
CMDSH-3
1
2
24
23
22
21
20
19
18
17
16
15
14
13
25V
RUN/SS
BOOST
TG
C
X7R
0.33µF
B
D1
M1
V
ON
B340A
Si7440DP
3
PGOOD
PGOOD
SW1
C1
4
+
3300pF
X7R
V
SENSE
L1**
1.8µH
RNG
R
10k
V
OUT1
2.5V
C
5
–
I
SENSE
TH
C2
100pF
±10A
+
C
*
6
OUT
R
SGND1
PGND1
F
470µF
R
237k
ON
1Ω
×2
LTC3718
7
M2
Si7440DP
D2
B340A
I
BG
ON
R
FB
249k
8
V
V
INTV
FB1
REF
CC
IN1
IN2
C
R
499k
F
REF
0.1µF
9
V
V
C
VCC2
4.7µF
10
11
12
V
IN2
5V
SHDN
C
IN2
22µF X5R
L2***
10µH
SGND2
PGND2
SW2
V
FB2
C
R
F3
10k
VCC1
D3
R
R
4.7µF
F1
12.3k
F2
MBR0520
V
OUT2
107k
X5R
12V
130mA
C
F4
*SANYO POSCAP 4TPB470M
**TOKO D104C
200pF X7R
***PANASONIC ELJPC4R7MF
****KEMET T495X336K025AS
3718 TA03
RELATED PARTS
PART NUMBER
LT®1613
DESCRIPTION
COMMENTS
1.4MHz, 1.1V < V < 10V
ThinSOTTM Step-Up DC/DC Converter
IN
LTC1735
High Efficiency Synchronous Switching Regulator
ThinSOT Current Mode Step-Down Controller
Synchronous Current Mode Step-Down Controller
4V ≤ V ≤ 36V, 0.8V ≤ V
≤ 6V, SSOP-16
OUT
IN
LTC1772
Small Solution, 2.5V ≤ V ≤ 9.8V, 0.8V ≤ V
≤ V
IN
OUT IN
LTC1773
2.65V ≤ V ≤ 8.5V, 0.8V ≤ V
≤ V ,
OUT IN
IN
550kHz Operation, >90% Efficiency
LTC1778
No R
TM Synchronous Step-Down Controller
SENSE
No Sense Resistor Required, 4V ≤ V ≤ 36V,
IN
0.8V ≤ V
≤ V
IN
OUT
LTC1876
LTC3413
LTC3711
LTC3713
LTC3717
2-Phase, Dual Synchronous Step-Down Controller with Step-Up Regulator
3A Monolithic DDR Memory Termination Regulator
2.6V ≤ V ≤ 36V, Dual Output: 0.8V ≤ V
≤ (0.9)V
IN
OUT IN
±3A Output Current, 2.25V ≤ V ≤ 5.5V
IN
5-Bit, Adjustable, No R
Synchronous Step-Down Controller
0.925V ≤ V ≤ 2V, 4V ≤ V ≤ 36V
OUT IN
SENSE
Low Input Voltage, High Power, No R
Synchronous Controller
No Sense Resistor Required, V
= 1.5V
IN(MIN)
SENSE
High Power DDR Memory Termination Regulator
4V ≤ V ≤ 36V, V
Tracks V or V
,
REF
IN
OUT
IN
I
from 1A to 20A
OUT
LTC3778
LTC3831
No R Synchronous Step-Down Controller
Optional Sense Resistor, 4V ≤ V ≤ 36V,
IN
SENSE
0.6V ≤ V
≤ V
OUT
IN
High Power DDR Memory Termination Regulator
V
I
Tracks 1/2 V or V , 3V ≤ V ≤ 8V,
from 1A to 20A
OUT
OUT
IN
REF
IN
No R
and ThinSOT are trademarks of Linear Technology Corporation.
SENSE
3718fa
LT/TP 1103 1K REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2002
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