LTC3556 [Linear]
High Effi ciency USB Power Manager with Dual Buck and Buck-Boost DC/DCs; 与双通道降压和降压 - 升压型DC / DC高效率艾菲USB电源管理器
| 型号： | LTC3556 |
| 厂家： | 
Linear |
| 描述： | High Effi ciency USB Power Manager with Dual Buck and Buck-Boost DC/DCs |
| 文件： | 总36页 (文件大小：342K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3556
High Efficiency USB Power
Manager with Dual Buck
and Buck-Boost DC/DCs
FEATURES
POWER MANAGER
DESCRIPTION
The LTC®3556 is a highly integrated power management
and battery charger IC for Li-Ion/Polymer battery applica-
tions.Itincludesahighefficiencycurrentlimitedswitching
PowerPath manager with automatic load prioritization, a
battery charger, an ideal diode, and three synchronous
switching regulators (two bucks and one buck-boost).
Designed specifically for USB applications, the LTC3556’s
switching power manager automatically limits input cur-
rent to a maximum of either 100mA or 500mA for USB
applications or 1A for adapter-powered applications.
High Efficiency Switching PowerPathTM Controller
n
with Bat-TrackTM Adaptive Output Control
n
Programmable USB or Wall Current Limit
(100mA/500mA/1A)
n
Full Featured Li-Ion/Polymer Battery Charger
n
Instant-On Operation with a Discharged Battery
n
1.5A Maximum Charge Current
n
Internal 180mΩ Ideal Diode Plus External Ideal Diode
Controller Powers Load in Battery Mode
n
Low No-Load I when Powered from BAT (<30μA)
Q
TheLTC3556’sswitchinginputstagetransmitsnearlyallof
the 2.5W available from the USB port to the system load
with minimal power wasted as heat. This feature allows
the LTC3556 to provide more power to the application and
easestheconstraintofthermalbudgetinginsmallspaces.
The two buck regulators can provide up to 400mA each
and the buck-boost can deliver 1A.
DC/DCs
n
n
n
n
n
n
n
Dual High Efficiency Buck DC/DCs (400mA/400mA I
)
OUT
High Efficiency Buck-Boost DC/DC (1A I
All Regulators Operate at 2.25MHz
)
OUT
Dynamic Voltage Scaling on Two Buck Outputs
2
I C Control of Enables, Mode, Two V
Settings
OUT
ENALL Pin with Power-Up Sequence Control
Low No-Load Quiescent Current: 20μA Each
The LTC3556 is available in the low profile 28-pin (4mm
× 5mm × 0.75mm) QFN surface mount package.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. PowerPath
and Bat-Track are trademarks of Linear Technology Corporation. All other trademarks are the
property of their respective owners. Protected by U.S. Patents including 6522118 and 6404251.
APPLICATIONS
n
HDD-Based MP3 Players, PDAs, GPS, PMPs
n
Other USB-Based Handheld Products
TYPICAL APPLICATION
Battery Charge Current
vs Battery Voltage
High Efficiency PowerPath Manager, Dual Buck, Buck-Boost and LDO
USB/WALL
4.5V TO 5.5V
TO OTHER
LOADS
USB COMPLIANT
STEP-DOWN
REGULATOR
700
600
500
400
300
200
100
0
BATTERY CHARGE CURRENT
EXTRA CURRENT
FOR FASTER CHARGING
CC/CV
BATTERY
CHARGER
0V
OPTIONAL
Li-Ion
500mA USB CURRENT LIMIT
CHARGE
+
T
LTC3556
3.3V/25mA
RTC/LOW
POWER LOGIC
ALWAYS ON LDO
1
V
= 5V
BUS
5X MODE
0.8V TO 3.6V/400mA
0.8V TO 3.6V/400mA
MEMORY
CORE
μP
BATTERY CHARGER PROGRAMMED FOR 1A
DUAL HIGH EFFICIENCY
ENALL
BUCKS
2
3
2.8
3.2 3.4 3.6
3.8
4
4.2
3
BATTERY VOLTAGE (V)
HIGH EFFICIENCY
BUCK-BOOST
SEQ
2.5V to 3.3V/1A
PGOODALL
3556 TA01b
HDD/IO
3
2
2
I C
I C PORT
3556 TA01
3556f
1
LTC3556
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
TOP VIEW
(Note 1)
V
V
(Transient) t < 1ms, Duty Cycle < 1%.. –0.3V to 7V
BUS
, V , V , V
(Static), DV ,
IN1 IN2 IN3 BUS
CC
FB1, FB2, NTC, BAT, ENALL, SCL, SDA,
28 27 26 25 24 23
LDO3V3
CLPROG
NTC
1
2
3
4
5
6
7
8
22
21
20
19
18
17
16
15
GATE
CHRG
PROG
SW2
PGOODALL, CHRG....................................... –0.3V to 6V
SEQ....................–0.3V to Lesser of 6V or (V
+ 0.3V)
OUT
FB3, V ..............–0.3V to Lesser of 6V or (V + 0.3V)
C3
IN3
SW1
29
I
I
I
I
I
....................................................................3mA
CLPROG
PGOODALL CHRG
PROG
LDO3V3
SW1 SW2
I , I , I
V
V
IN1
IN2
, I
....................................................50mA
FB1
FB3
FB2
........................................................................2mA
SDA
V
C3
PGOODALL
...................................................................30mA
9
10 11 12 13 14
UFD PACKAGE
, I
............................................................600mA
.............................................................2A
SW BAT VOUT
I
, I
, I
.............................................2.5A
SWAB3 SWCD3 VOUT3
28-LEAD (4mm s 5mm) PLASTIC QFN
Operating Temperature Range (Note 2).... –40°C to 85°C
Junction Temperature (Note 3) ............................. 125°C
Storage Temperature Range................... –65°C to 125°C
T
= 125°C, θ = 37°C/W
JMAX
JA
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
28-Lead (4mm × 5mm) Plastic QFN
TEMPERATURE RANGE
–40°C to 85°C
LTC3556EUFD#PBF
LTC3556EUFD#TRPBF
3556
Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VBUS = 5V, VIN1 = VIN2 = VIN3 = VOUT3 = 3.8V, BAT = 3.8V, DVCC = 3.3V,
RPROG = 1k, RCLPROG = 3.01k, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
PowerPath Switching Regulator
V
Input Supply Voltage
Total Input Current
4.35
5.5
V
BUS
l
l
l
l
I
1x Mode, V
5x Mode, V
= BAT
= BAT
OUT
87
95
100
500
1000
0.50
mA
mA
mA
mA
BUSLIM
OUT
OUT
436
800
0.31
460
860
0.38
10x Mode, V
= BAT
Suspend Mode, V
= BAT
OUT
I
V
Quiescent Current
1x Mode, I
5x Mode, I
= 0mA
= 0mA
7
15
mA
mA
mA
mA
VBUSQ
BUS
OUT
OUT
10x Mode, I
= 0mA
15
OUT
Suspend Mode, I
= 0mA
0.044
OUT
h
(Note 4) Ratio of Measured V
Current to
1x Mode
224
1133
2140
11.3
mA/mA
mA/mA
mA/mA
mA/mA
CLPROG
BUS
CLPROG Program Current
5x Mode
10x Mode
Suspend Mode
3556f
2
LTC3556
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VBUS = 5V, VIN1 = VIN2 = VIN3 = VOUT3 = 3.8V, BAT = 3.8V, DVCC = 3.3V,
RPROG = 1k, RCLPROG = 3.01k, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I
V
Current Available Before Loading 1x Mode, BAT = 3.3V
5x Mode, BAT = 3.3V
135
672
1251
0.32
mA
mA
mA
mA
OUT(POWERPATH)
OUT
BAT
10x Mode, BAT = 3.3V
Suspend Mode
V
V
V
V
CLPROG Servo Voltage in Current
Limit
1x, 5x, 10x Modes
Suspend Mode
1.188
100
V
CLPROG
mV
V
Undervoltage Lockout
Rising Threshold
Falling Threshold
4.30
4.00
4.35
4.7
V
V
UVLO_VBUS
UVLO_VBUS-BAT
OUT
BUS
3.95
3.4
V
to BAT Differential Undervoltage Rising Threshold
200
50
mV
mV
BUS
Lockout
Falling Threshold
V
Voltage
1x, 5x, 10x Modes, 0V < BAT < 4.2V,
BAT +
0.3
V
OUT
I
= 0mA, Battery Charger Off
OUT
USB Suspend Mode, I
= 250μA
4.5
1.8
4.6
4.7
2.7
V
MHz
Ω
OUT
l
f
Switching Frequency
PMOS On-Resistance
NMOS On-Resistance
Peak Switch Current Limit
2.25
0.18
0.30
OSC
R
R
PMOS_POWERPATH
NMOS_POWERPATH
PEAK_POWERPATH
Ω
I
1x, 5x Modes
10x Mode
2
3
A
A
Battery Charger
V
BAT Regulated Output Voltage
4.179
4.165
4.200
4.200
4.221
4.235
V
V
FLOAT
l
I
I
Constant Current Mode Charge
Current
980
185
1022
204
1065
223
mA
mA
CHG
R
= 5k
PROG
Battery Drain Current
V
BUS
V
BUS
> V
, Battery Charger Off, I = 0μA
OUT
OUT
2
3.5
27
5
38
μA
μA
BAT
UVLO
= 0V, I
= 0μA (Ideal Diode Mode)
V
V
PROG Pin Servo Voltage
1.000
0.100
V
V
PROG
PROG Pin Servo Voltage in Trickle
Charge
BAT < V
PROG_TRKL
TRKL
V
C/10 Threshold Voltage at PROG
100
1022
100
2.85
135
–100
4
mV
mA/mA
mA
C/10
PROG
TRKL
h
Ratio of I to PROG Pin Current
BAT
I
Trickle Charge Current
BAT < V
TRKL
V
TRKL
Trickle Charge Threshold Voltage
Trickle Charge Hysteresis Voltage
Recharge Battery Threshold Voltage
Safety Timer Termination
BAT Rising
2.7
3.0
V
mV
ΔV
TRKL
RECHRG
TERM
V
Threshold Voltage Relative to V
–75
3.3
–125
5
mV
FLOAT
t
t
Timer Starts When BAT = V
BAT < V
Hour
Hour
mA/mA
mV
FLOAT
Bad Battery Termination Time
0.42
0.088
0.5
0.63
0.112
100
1
BADBAT
TRKL
h
C/10
End of Charge Indication Current Ratio (Note 5)
0.1
V
CHRG Pin Output Low Voltage
CHRG Pin Leakage Current
Battery Charger Power FET
I
= 5mA
= 5V
65
CHRG
CHRG
CHRG
I
V
μA
CHRG
R
0.18
110
Ω
ON_CHG
On-Resistance (Between V
and BAT)
OUT
T
LIM
Junction Temperature in Constant
Temperature Mode
°C
3556f
3
LTC3556
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VBUS = 5V, VIN1 = VIN2 = VIN3 = VOUT3 = 3.8V, BAT = 3.8V, DVCC = 3.3V,
RPROG = 1k, RCLPROG = 3.01k, unless otherwise noted.
SYMBOL
NTC
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
V
Cold Temperature Fault Threshold
Voltage
Rising Threshold
Hysteresis
75.0
33.4
0.7
76.5
1.5
78.0
36.4
2.7
%V
%V
COLD
HOT
DIS
BUS
BUS
Hot Temperature Fault Threshold
Voltage
Falling Threshold
Hysteresis
34.9
1.5
%V
%V
BUS
BUS
NTC Disable Threshold Voltage
Falling Threshold
Hysteresis
1.7
50
%V
BUS
mV
I
NTC Leakage Current
V
= V = 5V
BUS
–50
50
nA
NTC
NTC
Ideal Diode
V
FWD
Forward Voltage
V
= 0V, I = 10mA
OUT
= 10mA
2
15
mV
mV
BUS
OUT
I
R
Internal Diode On-Resistance, Dropout V
= 0V
0.18
Ω
A
DROPOUT
BUS
I
Internal Diode Current Limit
1.6
3.1
MAX_DIODE
Always On 3.3V Supply
V
Regulated Output Voltage
0mA < I
< 25mA
3.3
4
3.5
0.4
V
Ω
Ω
LDO3V3
LDO3V3
R
R
Closed-Loop Output Resistance
Dropout Output Resistance
CL_LDO3V3
23
OL_LDO3V3
Logic (ENALL, PGOODALL)
V
V
Logic Low Input Voltage
Logic High Input Voltage
Pull-Down Resistance
ENALL Pin
ENALL Pin
ENALL Pin
V
V
IL
1.2
1.6
IH
R
4.5
MΩ
V
PD
OL
V
Logic Low Output Voltage
Logic High Leakage Current
PGOODALL Assertion Delay
PGOODALL Pin, I
= 5mA
0.07
0.2
1
PULL-UP
I
t
PGOODALL Pin, V
= 5V
PGOODALL
μA
ms
OH
230
PGOODALL
2
I C Port (Note 9)
DV
Input Supply Voltage
5.5
1
V
μA
V
CC
I
DV Current
CC
SCL/SDA = 0kHz
0.3
1.0
DVCC
V
DV UVLO
CC
DVCC_UVLO
2
ADDRESS
I C Address
0001 001[0]
V
V
SDA, SCL
SDA, SCL
Input High Voltage
Input Low Voltage
70
–1
%DV
IH
IL
CC
CC
30
1
%DV
I , I SDA, SCL Input High/Low Current
IH IL
0
μA
V
V
SDA
SDA Output Low Voltage
Clock Operating Frequency
I
= 3mA
0.4
400
OL
SCL
BUF
SDA
f
t
kHz
μs
Bus Free Time Between Stop and Start
Condition
1.3
0.6
t
Hold Time After (Repeated) Start
Condition
μs
HD_STA
t
t
t
Repeated Start Condition Setup Time
Stop Condition Setup Time
Data Hold Time Output
0.6
0.6
0
μs
μs
ns
SU_STA
SU_STO
900
HD_DAT(O)
3556f
4
LTC3556
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VBUS = 5V, VIN1 = VIN2 = VIN3 = VOUT3 = 3.8V, BAT = 3.8V, DVCC = 3.3V,
RPROG = 1k, RCLPROG = 3.01k, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
0
TYP
MAX
UNITS
ns
t
t
t
t
t
t
t
Data Hold Time Input
Data Setup Time
HD_DAT(I)
100
ns
SU_DAT
SCL Clock Low Period
SCL Clock High Period
Clock/Data Fall Time
Clock/Data Rise Time
Input Spike Suppression Pulse Width
1.3
μs
LOW
0.6
μs
HIGH
C = Capacitance of One BUS Line (pF)
B
20 + 0.1C
20 + 0.1C
300
300
50
ns
f
B
B
C = Capacitance of One BUS Line (pF)
B
ns
r
ns
SP
Switching Regulators 1, 2 and 3
V
V
Input Supply Voltage
2.7
2.5
5.5
2.9
2.7
V
IN1,2,3
V
V
UVLO—V
UVLO—V
Falling
Rising
V
Connected to V Through Low
OUT
2.6
2.8
V
V
OUTUVLO
OUT
OUT
OUT
OUT
IN1,2,3
Impedance. Switching Regulators are
Disabled in UVLO
l
f
Oscillator Frequency
1.8
2.25
MHz
OSC
Switching Regulator 1 (Buck)
I
Pulse Skip Mode Input Current
Burst Mode® Input Current
Forced Burst Mode Input Current
LDO Mode Input Current
I
I
I
I
I
= 0μA (Note 6)
= 0μA (Note 6)
= 0μA (Note 6)
= 0μA (Note 6)
= 0μA, FB1 = 0V
225
35
400
60
35
35
1
μA
μA
μA
μA
μA
VIN1
OUT1
OUT1
OUT1
OUT1
OUT1
20
20
Shutdown Input Current
I
I
PMOS Switch Current Limit
Available Output Current
Pulse Skip/Burst Mode Operation
600
800
1100
mA
LIM1
OUT1
Pulse Skip/Burst Mode Operation (Note 9)
Forced Burst Mode Operation (Note 9)
LDO Mode (Note 9)
400
60
50
mA
mA
mA
l
l
V
V
V
Maximum Servo Voltage
Minimum Servo Voltage
Full Scale (1, 1, 1, 1) (Note 7)
Zero Scale (0, 0, 0, 0) (Note 7)
0.780
0.405
0.800
0.425
25
0.820
0.445
V
V
FBHIGH1
FBLOW1
LSB1
V
Servo Voltage Step Size
mV
Ω
FB1
R
R
R
R
PMOS R
NMOS R
0.6
P1
DS(ON)
DS(ON)
0.7
Ω
N1
LDO Mode Closed-Loop R
0.25
2.5
Ω
LDO_CL1
LDO_OL1
OUT
LDO Mode Open-Loop R
FB1 Input Current
(Note 8)
Ω
OUT
I
V
= 0.85V
–50
100
50
nA
%
FB1
FB1
l
D1
Maximum Duty Cycle
R
SW1 Pull-Down in Shutdown
Switching Regulator 2 (Buck)
10
kΩ
SW1
I
Pulse Skip Mode Input Current
Burst Mode Input Current
Forced Burst Mode Input Current
LDO Mode Input Current
I
I
I
I
I
= 0μA (Note 6)
= 0μA (Note 6)
= 0μA (Note 6)
= 0μA (Note 6)
= 0μA, FB2 = 0V
225
35
400
60
35
35
1
μA
μA
μA
μA
μA
VIN2
OUT2
OUT2
OUT2
OUT2
OUT2
20
20
Shutdown Input Current
I
I
PMOS Switch Current Limit
Available Output Current
Pulse Skip/Burst Mode Operation
600
800
1100
mA
LIM2
OUT2
Pulse Skip/Burst Mode Operation (Note 9)
Forced Burst Mode Operation (Note 9)
LDO Mode (Note 9)
400
60
50
mA
mA
mA
Burst Mode is a registered trademark of Linear Technology Corporation.
3556f
5
LTC3556
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VBUS = 5V, VIN1 = VIN2 = VIN3 = VOUT3 = 3.8V, BAT = 3.8V, DVCC = 3.3V,
RPROG = 1k, RCLPROG = 3.01k, unless otherwise noted.
SYMBOL
PARAMETER
Servo Voltage
CONDITIONS
MIN
TYP
0.800
0.6
MAX
UNITS
V
l
V
V
(Note 7)
0.780
0.820
FB2
FB2
R
R
R
R
PMOS R
NMOS R
Ω
P2
DS(ON)
DS(ON)
0.7
Ω
N2
LDO Mode Closed-Loop R
0.25
2.5
Ω
LDO_CL2
LDO_OL2
OUT
LDO Mode Open-Loop R
FB2 Input Current
(Note 8)
Ω
OUT
I
V
= 0.85V
FB2
–50
100
50
nA
%
FB2
l
D2
Maximum Duty Cycle
R
SW2
SW2 Pull-Down in Shutdown
10
kΩ
Switching Regulator 3 (Buck-Boost)
I
Input Current
PWM Mode, I
= 0μA
OUT3
220
13
0
400
20
1
μA
μA
μA
VIN3
Burst Mode Operation, I
Shutdown
= 0μA
OUT3
V
V
Minimum Regulated Output Voltage
For Burst Mode Operation or Synchronous
PWM Operation
2.65
2.75
V
OUT3(LOW)
Maximum Regulated Output Voltage
Forward Current Limit (Switch A)
5.50
2
5.60
2.5
275
0
V
A
OUT3(HIGH)
LIMF3
l
l
l
I
I
I
I
PWM Mode
3
Forward Burst Current Limit (Switch A) Burst Mode Operation
Reverse Burst Current Limit (Switch D) Burst Mode Operation
200
–30
50
350
30
mA
mA
mA
PEAK3(BURST)
ZERO3(BURST)
MAX3(BURST)
Maximum Deliverable Output Current 2.7V ≤ V ≤ 5.5V, 2.75V ≤ V
≤ 5.5V
OUT3
IN3
in Burst Mode Operation
Maximum Servo Voltage
Minimum Servo Voltage
(Note 9)
l
l
V
V
V
Full Scale (1, 1, 1, 1)
Zero Scale (0, 0, 0, 0)
0.780
0.405
0.800
0.425
25
0.820
0.445
V
V
FBHIGH3
FBLOW3
LSB3
V
Servo Voltage Step Size
mV
nA
Ω
FB3
I
FB3 Input Current
V
= 0.8V
FB3
–50
50
FB3
R
R
PMOS R
NMOS R
Switches A, D
Switches B, C
Switches A, D
Switches B, C
0.22
0.17
DS(ON)P
DS(ON)N
LEAK(P)
LEAK(N)
DS(ON)
DS(ON)
Ω
I
I
PMOS Switch Leakage
NMOS Switch Leakage
–1
–1
1
1
μA
μA
kΩ
%
R
V
Pull-Down in Shutdown
OUT3
10
VOUT3
l
D
D
Maximum Buck Duty Cycle
Maximum Boost Duty Cycle
Soft-Start Time
PWM Mode
PWM Mode
100
BUCK(MAX)
75
%
BOOST(MAX)
t
0.5
ms
SS3
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3556E is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 3: The LTC3556E includes overtemperature protection that is
intended to protect the device during momentary overload conditions.
Junction temperature will exceed 125°C when overtemperature protection
is active. Continuous operation above the specified maximum operating
junction temperature may impair device reliability.
Note 4: Total input current is the sum of quiescent current, I
measured current given by:
, and
VBUSQ
V
/R
• (h
+1)
CLPROG CLPROG
CLPROG
Note 5: h
is expressed as a fraction of measured full charge current
C/10
with indicated PROG resistor.
Note 6: FBx above regulation such that regulator is in sleep. Specification
does not include resistive divider current reflected back to V
.
INx
Note 7: Applies to Pulse Skip, Burst Mode operation and Forced Burst
Mode operation only.
Note 8: Inductor series resistance adds to open-loop R
Note 9: Guaranteed by design.
.
OUT
3556f
6
LTC3556
TYPICAL PERFORMANCE CHARACTERISTICS
Ideal Diode Resistance
vs Battery Voltage
Output Voltage vs Load Current
(Battery Charger Disabled)
Ideal Diode V-I Characteristics
1.0
0.8
0.6
0.4
0.2
0
0.25
0.20
0.15
0.10
0.05
0
4.50
4.25
4.00
3.75
3.50
3.25
V
= 5V
INTERNAL IDEAL DIODE
WITH SUPPLEMENTAL
EXTERNAL VISHAY
Si2333 PMOS
BUS
BAT = 4V
5x MODE
INTERNAL IDEAL
DIODE
INTERNAL IDEAL
DIODE ONLY
BAT = 3.4V
INTERNAL IDEAL DIODE
WITH SUPPLEMENTAL
EXTERNAL VISHAY
Si2333 PMOS
V
V
= 0V
= 5V
BUS
BUS
0
0.04
0.08
0.12
0.16
0.20
2.7
3.0
3.3
3.6
3.9
4.2
0
200
400
600
800
1000
FORWARD VOLTAGE (V)
BATTERY VOLTAGE (V)
LOAD CURRENT (mA)
3556 G01
3556 G02
3556 G03
USB Limited Battery Charge
Current vs Battery Voltage
USB Limited Battery Charge
Current vs Battery Voltage
Battery Drain Current
vs Battery Voltage
700
600
150
125
25
20
15
10
5
I
= 0μA
VOUT
V
= 0V
BUS
V
R
R
= 5V
BUS
500
400
300
200
100
0
V
R
R
= 5V
BUS
= 1k
PROG
CLPROG
100
75
= 1k
PROG
CLPROG
= 3.01k
= 3.01k
50
25
0
V
= 5V
BUS
(SUSPEND MODE)
1x USB SETTING,
BATTERY CHARGER SET FOR 1A
5x USB SETTING,
BATTERY CHARGER SET FOR 1A
0
3.0
3.3
3.6
4.2
2.7
3.9
2.7 3.0 3.3 3.6
BATTERY VOLTAGE (V)
3.9
4.2
2.7
3.0
3.3
3.6
3.9
4.2
BATTERY VOLTAGE (V)
BATTERY VOLTAGE (V)
3556 G04
3556 G05
3556 G06
Battery Charging Efficiency vs
PowerPath Switching Regulator
Efficiency vs Load Current
VBUS Current vs VBUS Voltage
(Suspend)
Battery Voltage with No External
Load (PBAT/PBUS
)
100
90
80
70
60
50
40
100
90
80
70
60
50
40
30
20
10
0
BAT = 3.8V
R
R
VOUT
= 3.01k
BAT = 3.8V
VOUT
CLPROG
PROG
5x, 10x MODE
= 1k
I
= 0mA
1x MODE
I
= 0mA
1x CHARGING
EFFICIENCY
5x CHARGING
EFFICIENCY
0.01
0.1
1
2.7
3.0
3.3
3.6
3.9
4.2
0
1
3
4
5
2
LOAD CURRENT (A)
BATTERY VOLTAGE (V)
BUS VOLTAGE (V)
3556 G07
3556 G08
3556 G09
3556f
7
LTC3556
TYPICAL PERFORMANCE CHARACTERISTICS
Output Voltage vs Load Current
in Suspend
VBUS Current vs Load Current
in Suspend
3.3V LDO Output Voltage
vs Load Current, VBUS = 0V
5.0
4.5
4.0
3.5
3.0
2.5
3.4
3.2
3.0
2.8
2.6
0.5
0.4
0.3
0.2
0.1
0
BAT = 3.5V
V
BUS
= 5V
BAT = 3.9V, 4.2V
BAT = 3.4V
BAT = 3.3V
= 3.01k
BAT = 3.6V
R
CLPROG
BAT = 3V
BAT = 3.1V
BAT = 3.2V
V
= 5V
BUS
BAT = 3.3V
= 3k
R
CLPROG
BAT = 3.3V
0
0.1
0.2
0.3
0.4
0.5
0
5
10
15
20
25
0
0.1
0.2
0.3
0.4
0.5
LOAD CURRENT (mA)
LOAD CURRENT (mA)
LOAD CURRENT (mA)
3556 G10
3556 G12
3556 G11
Battery Charge Current
vs Temperature
Battery Charger Float Voltage
vs Temperature
Low-Battery (Instant On) Output
Voltage vs Temperature
4.21
4.20
4.19
4.18
4.17
3.68
3.66
3.64
3.62
3.60
600
500
400
300
200
100
0
BAT = 2.7V
I
= 100mA
VOUT
5x MODE
THERMAL REGULATION
R
= 2k
PROG
10x MODE
60 80
20 40
TEMPERATURE (°C)
–40 –20
0
100 120
–40
–15
10
35
60
85
–40
–15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
3556 G13
3556 G14
3556 G15
Oscillator Frequency
vs Temperature
VBUS Quiescent Current
vs Temperature
VBUS Quiescent Current in
Suspend vs Temperature
2.6
2.4
2.2
2.0
1.8
15
12
9
70
60
50
40
30
V
VOUT
= 5V
= 0μA
I
= 0μA
BUS
VOUT
I
5x MODE
BAT = 3.6V
= 0V
V
= 5V
BUS
V
BUS
BAT = 3V
= 0V
1x MODE
V
BUS
6
BAT = 2.7V
= 0V
V
BUS
3
–40
–15
10
35
60
85
–40
–15
10
35
60
85
–40
–15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3556 G16
3556 G17
3556 G18
3556f
8
LTC3556
TYPICAL PERFORMANCE CHARACTERISTICS
PGOODALL, CHRG Pin Current
vs Voltage (Pull-Down State)
3.3V LDO Step Response
(5mA to 15mA)
Battery Drain Current
vs Temperature
100
80
60
40
20
0
50
40
30
20
10
0
V
= 5V
BAT = 3.8V
BUS
BAT = 3.8V
V
= 0V
BUS
ALL REGULATORS OFF
I
LDO3V3
5mA/DIV
0mA
V
LDO3V3
20mV/DIV
AC COUPLED
3556 G20
BAT = 3.8V
20μs/DIV
0
1
2
3
4
5
–40
–15
10
35
60
85
PGOODALL, CHRG PIN VOLTAGE (V)
TEMPERATURE (°C)
3556 G19
3556 G21
Switching Regulators 1, 2
Burst Mode Efficiency
Switching Regulators 1, 2 Pulse
Skip Mode Quiescent Currents
Switching Regulators 1, 2
Pulse Skip Mode Efficiency
325
300
275
250
225
200
1.95
100
90
80
70
60
50
40
30
20
10
0
100
90
V
= 3.8V
V
= 2.5V
OUT1,2
IN1,2
V
= 2.5V
OUT1,2
1.90
1.85
1.80
1.75
1.70
V
= 1.2V
80
OUT1,2
V
= 1.2V
V
= 2.5V
OUT1,2
V
= 1.8V
OUT1,2
OUT1,2
70
(CONSTANT FREQUENCY)
V
= 1.8V
OUT1,2
60
50
40
30
20
10
0
V
= 1.25V
OUT1,2
(PULSE SKIPPING)
V
= 3.8V
V
= 3.8V
IN1,2
IN1,2
–40
–15
10
35
60
85
0.1
1
10
100
1000
1
10
100
1000
LOAD CURRENT (mA)
TEMPERATURE (°C)
LOAD CURRENT (mA)
3556 G24
3556 G22
3556 G23
Switching Regulators 1, 2 Load
Regulation at VOUT1,2 = 1.2V
Switching Regulators 1, 2 Load
Regulation at VOUT1,2 = 1.8V
Switching Regulators 1, 2
Forced Burst Mode Efficiency
1.230
1.215
1.200
100
90
80
70
60
50
40
30
20
10
0
1.845
1.823
1.800
V
= 3.8V
V
= 2.5V
V
= 3.8V
BUS
OUT1,2
BUS
Burst Mode
OPERATION
Burst Mode OPERATION
PULSE SKIP MODE
V
= 1.2V
OUT1,2
V
= 1.8V
OUT1,2
FORCED
Burst Mode
OPERATION
PULSE SKIP
MODE
1.185
1.170
1.778
1.755
FORCED
Burst Mode
OPERATION
V
= 3.8V
IN1,2
0.1
1
10
100
1000
0.1
1
10
100
1000
0.1
1
10
100
1000
LOAD CURRENT (mA)
LOAD CURRENT (mA)
LOAD CURRENT (mA)
3556 G26
3556 G27
3556 G25
3556f
9
LTC3556
TYPICAL PERFORMANCE CHARACTERISTICS
Switching Regulator 3 Burst Mode
Operation Input Quiescent Current
Switching Regulator 3 Forward
Current Limit vs Temperature
Switching Regulators 1, 2 Load
Regulation at VOUT1,2 = 2.5V
2.56
2.53
2.50
2600
2550
2500
2450
2400
2350
2300
14.0
13.5
13.0
12.5
12.0
11.5
11.0
V
= 3.8V
V
A
= 3.3V
BUS
OUT3
V
= 3V
IN3
T
= 27°C
V
= 4.5V
IN3
Burst Mode OPERATION
PULSE SKIP MODE
V
= 3.6V
= 4.5V
IN3
V
= 3.6V
IN3
V
= 3V
IN3
V
IN3
FORCED
Burst Mode
OPERATION
2.47
2.44
0.1
1
10
100
1000
–15
5
25 45 65 85
125
105
–15
5
25 45 65 85
125
105
–55 –35
–55 –35
LOAD CURRENT (mA)
TEMPERATURE (°C)
TEMPERATURE (°C)
3556 G28
3556 G30
3556 G29
RDS(ON)’s for Switching Regulator 3
vs Temperature
Switching Regulator 3 Efficiency
vs Load Current
0.30
0.25
0.20
0.15
0.10
0.05
0
0.40
0.35
0.30
0.25
0.20
0.15
0.10
100
90
80
Burst Mode
PWM MODE
OPERATION
CURVES
PMOS
70
CURVES
V
= V
= 3V
OUT3
IN3
60
50
V
= V
= 3.6V
OUT3
IN3
V
= V
= 4.5V
OUT3
IN3
40
30
20
10
0
V
A
= 3.3V
OUT3
T
= 27°C
NMOS
V
= 3V
IN3
V
V
V
= 3V
= 3.6V
= 4.5V
IN3
IN3
IN3
V
= 3.6V
IN3
V
= 4.5V
IN3
–15
5
25 45 65 85
125
105
0.1
1
10
100
1000
–55 –35
LOAD CURRENT (mA)
TEMPERATURE (°C)
3556 G31
3556 G32
Switching Regulator 3 PWM Mode
Efficiency vs Input Voltage
Switching Regulator 3 Reduction in
Current Deliverability at Low VIN3
100
90
300
250
200
150
100
50
I
= 50mA
V
A
= 3.3V
OUT3
OUT3
T
= 27°C
80
I
= 200mA
OUT3
I
= 1000mA
OUT3
70
60
50
40
30
20
10
0
STEADY STATE LOAD
START-UP WITH A
RESISTIVE LOAD
START-UP WITH A
CURRENT SOURCE LOAD
V
A
= 3.3V
OUT3
T
= 27°C
0
2.7
3.5
3.9
(V)
4.3
4.7
3.1
2.7
3.5
3.9
(V)
4.3
4.7
3.1
V
V
IN3
IN3
3556 G33
3556 G34
3556f
10
LTC3556
TYPICAL PERFORMANCE CHARACTERISTICS
Start-Up Sequencing with SEQ = 0V
Switching Regulator 3 Step
Response (0mA to 300mA)
VIN1 = VIN2 = VIN3 = 4.2V
All Outputs Loaded with 5mA
V
OUT3
V
V
= 3.8V
OUT3
IN3
100mV/DIV
AC
= 3.3V
ENALL
COUPLED
V
OUT3
= 3.3V
1V/DIV
V
V
= 1.8V
= 1.6V
OUT2
OUT1
300mA
I
OUT3
200mA/
DIV
0
3556 G36
3556 G35
200μs/DIV
100μs/DIV
PIN FUNCTIONS
LDO3V3 (Pin 1): 3.3V LDO Output Pin. This pin provides
V
(Pin 5): Power Input for (Buck) Switching Regula-
IN1
a regulated, always-on, 3.3V supply voltage. LDO3V3
tor 1. This pin will generally be connected to V . A 1μF
OUT
gets its power from V . It may be used for light loads
MLCC capacitor is recommended on this pin.
OUT
such as a watchdog microprocessor or real time clock.
A 1μF capacitor is required from LDO3V3 to ground. If
the LDO3V3 output is not used it should be disabled by
FB1 (Pin 6): Feedback Input for (Buck) Switching Regula-
tor 1. When regulator 1’s control loop is complete, this
pin servos to 1 of 16 possible set-points based on the
connecting it to V
.
OUT
2
commanded value from the I C serial port. See Table 4.
CLPROG (Pin 2): USB Current Limit Program and Moni-
tor Pin. A resistor from CLPROG to ground determines
FB3 (Pin 7): Feedback Input for (Buck-Boost) Switching
Regulator 3. When regulator 3’s control loop is complete,
this pin servos to 1 of 16 possible set-points based on the
the upper limit of the current drawn from the V
pin.
BUS
A fraction of the V
current is sent to the CLPROG pin
BUS
2
commanded value from the I C serial port. See Table 4.
when the synchronous switch of the PowerPath switching
regulatorison.Theswitchingregulatordeliverspoweruntil
V
(Pin 8): Output of the Error Amplifier and Voltage
C3
theCLPROGpinreaches1.188V.SeveralV currentlimit
Compensation Node for (Buck-Boost) Switching Regula-
tor 3. External Type I or Type III compensation (to FB3)
connects to this pin. See Applications Information section
for selecting buck-boost compensation components.
BUS
settings are available via user input which will typically
correspond to the 500mA and 100mA USB specifications.
A multilayer ceramic averaging capacitor or R-C network
is required at CLPROG for filtering.
SWAB3 (Pin 9): Switch Node for (Buck-Boost) Switching
Regulator 3. Connected to internal power switches A and B.
External inductor connects between this node and SWCD3.
NTC (Pin 3): Input to the Thermistor Monitoring Circuits.
The NTC pin connects to a battery’s thermistor to deter-
mine if the battery is too hot or too cold to charge. If the
battery’s temperature is out of range, charging is paused
until it re-enters the valid range. A low drift bias resistor
2
DV (Pin 10): Logic Supply for the I C Serial Port.
CC
V
(Pin 11): Power Input for (Buck-Boost) Switching
IN3
is required from V
to NTC and a thermistor is required
BUS
Regulator3. ThispinwillgenerallybeconnectedtoV . A
OUT
from NTC to ground. If the NTC function is not desired,
the NTC pin should be grounded.
1μF (min) MLCC capacitor is recommended on this pin.
V
(Pin12):RegulatedOutputVoltagefor(Buck-Boost)
OUT3
SW1 (Pin 4): Power Transmission Pin for (Buck) Switch-
ing Regulator 1.
Switching Regulator 3.
3556f
11
LTC3556
PIN FUNCTIONS
2
SCL (Pin 13): Clock Input Pin for the I C Serial Port. The
to BAT. If the external ideal diode FET is not used, GATE
should be left floating.
2
I C logic levels are scaled with respect to DV .
CC
SWCD3 (Pin 14): Switch Node for (Buck-Boost) Switch-
ing Regulator 3. Connected to internal power switches
C and D. External inductor connects between this node
and SWAB3.
BAT (Pin 23): Single Cell Li-Ion Battery Pin. Depending on
available V
power, a Li-Ion battery on BAT will either
BUS
deliverpowertoV throughtheidealdiodeorbecharged
OUT
from V
via the battery charger.
OUT
V
(Pin 24): Output Voltage of the Switching Power-
PGOODALL (Pin 15): Logic Output. This in an open-drain
output which indicates that all enabled switching regula-
tors have settled to their final value. It can be used as a
power-on reset for the primary microprocessor.
OUT
Path Controller and Input Voltage of the Battery Charger.
The majority of the portable product should be powered
from V . The LTC3556 will partition the available power
between the external load on V
OUT
and the internal battery
OUT
2
SDA (Pin 16): Data Input Pin for the I C Serial Port. The
charger. Priority is given to the external load and any extra
power is used to charge the battery. An ideal diode from
2
I C logic levels are scaled with respect to DV .
CC
BAT to V
ensures that V
is powered even if the load
FB2 (Pin 17): Feedback Input for (Buck) Switching Regu-
lator 2. When regulator 2’s control loop is complete, this
pin servos to a fixed voltage of 0.8V.
OUT
OUT
exceeds the allotted power from V
or if the V
power
BUS
BUS
source is removed. V
should be bypassed with a low
OUT
impedance ceramic capacitor.
V
(Pin 18): Power Input for (Buck) Switching Regula-
IN2
V
(Pin 25): Primary Input Power Pin. This pin delivers
BUS
tor 2. This pin will generally be connected to V . A 1μF
OUT
powertoV viatheSWpinbydrawingcontrolledcurrent
OUT
MLCC capacitor is recommended on this pin.
from a DC source such as a USB port or wall adapter.
SW2 (Pin 19): Power Transmission Pin for (Buck) Switch-
ing Regulator 2.
SW (Pin 26): Power Transmission Pin for the USB Power
Path. The SW pin delivers power from V
step-down switching regulator. A 3.3μH inductor should
be connected from SW to V
to V
via the
OUT
BUS
PROG (Pin 20): Charge Current Program and Charge
Current Monitor Pin. Connecting a resistor from PROG
to ground programs the charge current. If sufficient in-
put power is available in constant-current mode, this pin
servos to 1V. The voltage on this pin always represents
the actual charge current.
.
OUT
SEQ (Pin 27): Sequence Select Logic Input. Three-state
input which determines start-up sequence after ENALL
is asserted.
If tied to GND, start-up sequence is:
CHRG (Pin 21): Open-Drain Charge Status Output. The
CHRG pin indicates the status of the battery charger. Four
possible states are represented by CHRG: charging, not
charging, unresponsive battery and battery temperature
out of range. CHRG is modulated at 35kHz and switches
between a low and a high duty cycle for easy recogni-
tion by either humans or microprocessors. See Table 1.
CHRG requires a pull-up resistor and/or LED to provide
indication.
Buck 1 → Buck 2 → Buck-Boost
If tied to V , start-up sequence is:
OUT
Buck 1 → Buck-Boost → Buck 2
If left floating, start-up sequence is:
Buck-Boost → Buck 1 → Buck 2
ENALL (Pin 28): Enable All Logic Input. Enables all three
switching regulators in sequence according to the state of
the SEQ pin. Active high. Has a 5.5M internal pull-down
resistor. Alternately, all switching regulators can be indi-
GATE (Pin 22): Analog Output. This pin controls the gate
2
vidually enabled via the I C serial port.
of an optional external P-channel MOSFET transistor used
to supplement the ideal diode between V
and BAT. The
OUT
Exposed Pad (Pin 29): Ground. The Exposed Pad should
be connected to a continuous ground plane on the second
layer of the printed circuit board by several vias directly
external ideal diode operates in parallel with the internal
ideal diode. The source of the P-channel MOSFET should
be connected to V
and the drain should be connected
under the LTC3556.
OUT
3556f
12
LTC3556
BLOCK DIAGRAM
V
25
BUS
2.25MHz
PowerPath
SWITCHING
REGULATOR
SW
26
1
LDO3V3
3.3V LDO
SUSPEND
LDO
500μA
V
24
22
OUT
+
–
+
–
+
+
GATE
IDEAL
CC/CV
CLPROG
NTC
2
3
–
CHARGER
–
+
15mV
0.3V
–
+
BATTERY
TEMPERATURE
MONITOR
BAT
23
20
5
1.188V
3.6V
PROG
V
IN1
EN1
CHRG 21
CHARGE
STATUS
4
6
SW1
FB1
400mA
2.25MHz
(BUCK)
D/A
SWITCHING
REGULATOR 1
4
V
18
IN2
EN2
EN3
400mA
2.25MHz
19 SW2
PGOODALL 15
POWER
GOOD
(BUCK)
SWITCHING
REGULATOR 2
FB2
17
11
V
IN3
A
9
SWAB3
MASTER LOGIC
AND
SEQUENCER
B
1A
SEQ 27
2.25MHz
D/A
(BUCK-BOOST)
SWITCHING
REGULATOR 3
V
OUT3
12
D
C
4
14 SWCD3
ENALL 28
FB3
7
8
DV 10
CC
V
2
C3
SDA 16
SCL 13
I C PORT
29
3556 BD
GND
3556f
13
LTC3556
TIMING DIAGRAM
I2C Timing Diagram
DATA BYTE A
DATA BYTE B
ADDRESS
WR
0
0
0
0
1
0
0
1
1
A7
1
A6
2
A5
3
A4
A3
A2
6
A1
7
A0
8
B7
1
B6
2
B5
3
B4
B3
B2
6
B1
7
B0
8
START
STOP
SDA
SCL
0
0
0
1
0
0
0
8
ACK
9
ACK
9
ACK
9
1
2
3
4
5
6
7
4
5
4
5
SDA
t
t
t
BUF
SU, DAT
SU, STA
t
t
t
t
LOW
HD, STA
SU, STO
HD, DAT
3556 TD
SCL
t
t
t
SP
HD, STA
HIGH
START
CONDITION
REPEATED START
CONDITION
STOP
CONDITION
START
CONDITION
t
r
t
f
OPERATION
Introduction
The three switching regulators can be enabled together
in any desired sequence via the ENALL and SEQ pins
The LTC3556 is a highly integrated power management IC
which includes a high efficiency switch mode PowerPath
controller, a battery charger, an ideal diode, an always-on
LDO,two400mAbuckswitchingregulatorsanda1Abuck-
boost switching regulator. The entire chip is controllable
2
or can be independently enabled via the I C serial port.
2
Under I C control, one of the 400mA bucks and the 1A
buck-boost have adjustable set-points so that voltages
can be reduced when high processor performance is not
needed. Along with constant frequency PWM mode, all
three switching regulators have a low power burst-only
mode setting for significantly reduced quiescent current
underlightloadconditions.Additionally,the400mAbucks
can be configured for automatic Burst Mode operation or
LDO mode.
2
via an I C serial port.
DesignedspecificallyforUSBapplications,thePowerPath
controller incorporates a precision average input current
step-down switching regulator to make maximum use of
the allowable USB power. Because power is conserved,
the LTC3556 allows the load current on V
to exceed
OUT
the current drawn by the USB port without exceeding the
USB load specifications.
High Efficiency Switching PowerPath Controller
Whenever V
is available and the PowerPath switch-
BUS
The PowerPath switching regulator and battery charger
communicatetoensurethattheinputcurrentneverviolates
the USB specifications.
ing regulator is enabled, power is delivered from V
to
BUS
V
OUT
via SW. V
drives the combination of the external
OUT
load (including switching regulators 1, 2 and 3) and the
battery charger.
The ideal diode from BAT to V
guarantees that ample
even if there is insuf-
OUT
power is always available to V
OUT
.
IfthecombinedloaddoesnotexceedthePowerPathswitching
ficient or absent power at V
BUS
regulator’s programmed input current limit, V
will track
OUT
0.3V above the battery (Bat-Track). By keeping the voltage
acrossthebatterychargerlow,efficiencyisoptimizedbecause
power lost to the linear battery charger is minimized. Power
An “always-on” LDO provides a regulated 3.3V from avail-
able power at V . Drawing very little quiescent current,
OUT
this LDO will be on at all times and can be used to supply
up to 25mA.
available to the external load is therefore optimized.
3556f
14
LTC3556
OPERATION
If the combined load at V
4.5
4.2
3.9
3.6
3.3
3.0
2.7
2.4
is large enough to cause the
OUT
switching power supply to reach the programmed input
currentlimit,thebatterychargerwillreduceitschargecur-
rent by that amount necessary to enable the external load
to be satisfied. Even if the battery charge current is set to
exceed the allowable USB current, the USB specification
will not be violated. The switching regulator will limit the
averageinputcurrentsothattheUSBspecificationisnever
violated. Furthermore, load current at V
prioritizedandonlyremainingavailablepowerwillbeused
to charge the battery.
NO LOAD
300mV
will always be
OUT
3.6
4.2
2.4
2.7
3.0
3.3
3.9
BAT (V)
3556 F01
If the voltage at BAT is below 3.3V, or the battery is not
present and the load requirement does not cause the
Figure 1. VOUT vs BAT
switching regulator to exceed the USB specification, V
OUT
willregulateat3.6V,therebyprovidinginstant-onoperation.
Ideal Diode from BAT to V
OUT
If the load exceeds the available power, V will drop to
OUT
The LTC3556 has an internal ideal diode as well as a con-
troller for an optional external ideal diode. The ideal diode
controller is always on and will respond quickly whenever
a voltage between 3.6V and the battery voltage. If there
is no battery present when the load exceeds the available
USB power, V
can drop toward ground.
OUT
V
drops below BAT.
OUT
The power delivered from V
to V
is controlled
OUT
BUS
If the load current increases beyond the power allowed
from the switching regulator, additional power will be
pulled from the battery via the ideal diode. Furthermore,
by a 2.25MHz constant-frequency step-down switching
regulator. To meet the USB maximum load specification,
the switching regulator includes a control loop which
ensures that the average input current is below the level
programmed at CLPROG.
if power to V
(USB or wall power) is removed, then all
BUS
of the application power will be provided by the battery via
the ideal diode. The transition from input power to battery
–1
ThecurrentatCLPROGisafraction(h
)oftheV
power at V
will be quick enough to allow only the 10μF
OUT
CLPROG
BUS
current. When a programming resistor and an averaging
capacitorareconnectedfromCLPROGtoGND,thevoltage
on CLPROG represents the average input current of the
switching regulator. When the input current approaches
capacitor to keep V
from drooping. The ideal diode
OUT
consists of a precision amplifier that enables a large on-
chipP-channelMOSFETtransistorwheneverthevoltageat
2200
the programmed limit, CLPROG reaches V
, 1.188V
VISHAY Si2333
CLPROG
2000
OPTIONAL EXTERNAL
and power out is held constant. The input current limit is
1800
1600
1400
1200
1000
800
IDEAL DIODE
2
programmed by the B1 and B0 bits of the I C serial port.
It can be configured to limit average input current to one
of several possible settings as well as be deactivated (USB
LTC3556
IDEAL DIODE
Suspend).TheinputcurrentlimitwillbesetbytheV
CLPROG
servo voltage and the resistor on CLPROG according to
600
ON
SEMICONDUCTOR
MBRM120LT3
the following expression:
400
200
VCLPROG
RCLPROG
0
IVBUS = IVBUSQ
+
• h
(
+ 1
)
CLPROG
0
120 180 240 300 360 420 480
60
FORWARD VOLTAGE (mV) (BAT – V
)
OUT
3556 F02
Figure 1 shows the range of possible voltages at V
a function of battery voltage.
as
OUT
Figure 2. Ideal Diode Operation
3556f
15
LTC3556
OPERATION
V
is approximately 15mV (V ) below the voltage at
If the load on V
exceeds the suspend current limit,
OUT
OUT
FWD
BAT. The resistance of the internal ideal diode is approxi-
mately180mΩ. Ifthisissufficientfortheapplication, then
no external components are necessary. However, if more
conductance is needed, an external P-channel MOSFET
the additional current will come from the battery via the
ideal diode.
3.3V Always-On Supply
transistor can be added from BAT to V
.
OUT
TheLTC3556includesalowquiescentcurrentlowdropout
regulator that is always powered. This LDO can be used to
provide power to a system pushbutton controller, standby
microcontroller or real time clock. Designed to deliver up
to 25mA, the always-on LDO requires at least a 1μF low
impedance ceramic bypass capacitor for compensation.
WhenanexternalP-channelMOSFETtransistorispresent,
the GATE pin of the LTC3556 drives its gate for automatic
ideal diode control. The source of the external P-chan-
nel MOSFET should be connected to V
and the drain
OUT
should be connected to BAT. Capable of driving a 1nF load,
the GATE pin can control an external P-channel MOSFET
transistor having an on-resistance of 40mΩ or lower.
The LDO is powered from V , and therefore will enter
OUT
dropout at loads less than 25mA as V
falls near 3.3V.
OUT
If the LDO3V3 output is not used, it should be disabled
by connecting it to V
.
Suspend LDO
OUT
If the LTC3556 is configured for USB suspend mode, the
switching regulator is disabled and the suspend LDO
V
Undervoltage Lockout (UVLO)
BUS
AninternalundervoltagelockoutcircuitmonitorsV and
keeps the PowerPath switching regulator off until V
rises above 4.30V and is about 200mV above the battery
voltage. Hysteresis on the UVLO turns off the regulator if
BUS
provides power to the V
pin (presuming there is power
OUT
BUS
available to V ). This LDO will prevent the battery from
BUS
running down when the portable product has access to
a suspended USB port. Regulating at 4.6V, this LDO only
becomes active when the switching converter is disabled
(suspended). ToremaincompliantwiththeUSBspecifica-
tion, the input to the LDO is current limited so that it will
not exceed the 500μA low power suspend specification.
V
drops below 4.00V or to within 50mV of BAT. When
BUS
this happens, system power at V
the battery via the ideal diode.
will be drawn from
OUT
3.5V TO
TO USB
OR WALL
ADAPTER
V
BUS
SW
26
(BAT + 0.3V)
TO SYSTEM
LOAD
25
V
OUT
PWM AND
GATE DRIVE
24
22
IDEAL
DIODE
I
/
SWITCH
OPTIONAL
EXTERNAL
IDEAL DIODE
PMOS
h
CLPROG
+
–
GATE
BAT
CONSTANT CURRENT
CONSTANT VOLTAGE
BATTERY CHARGER
–
+
15mV
–
+
–
+
+
0.3V
CLPROG
1.188V
2
+
–
23
3.6V
AVERAGE INPUT
CURRENT LIMIT
CONTROLLER
AVERAGE OUTPUT
VOLTAGE LIMIT
CONTROLLER
+
SINGLE CELL
Li-Ion
3556 F03
Figure 3. PowerPath Block Diagram
3556f
16
LTC3556
OPERATION
Battery Charger
the battery is always topped off, a charge cycle will auto-
matically begin when the battery voltage falls below 4.1V.
In the event that the safety timer is running when the
battery voltage falls below 4.1V, it will reset back to zero.
To prevent brief excursions below 4.1V from resetting the
safety timer, the battery voltage must be below 4.1V for
more than 1.3ms. The charge cycle and safety timer will
The LTC3556 includes a constant-current/constant-volt-
age battery charger with automatic recharge, automatic
termination by safety timer, low voltage trickle charging,
bad cell detection and thermistor sensor input for out-of-
temperature charge pausing.
also restart if the V
UVLO cycles low and then high
BUS
Battery Preconditioning
(e.g., V
is removed and then replaced), or if the battery
charger is cycled on and off by the I C port.
BUS
When a battery charge cycle begins, the battery charger
first determines if the battery is deeply discharged. If the
batteryvoltageisbelowV
trickle charge feature sets the battery charge current to
10% of the programmed value. If the low voltage persists
for more than 1/2 hour, the battery charger automatically
terminates and indicates via the CHRG pin that the battery
was unresponsive.
2
,typically2.85V,anautomatic
TRKL
Charge Current
The charge current is programmed using a single resis-
tor from PROG to ground. 1/1022th of the battery charge
current is sent to PROG which will attempt to servo to
1.000V. Thus, the battery charge current will try to reach
1022 times the current in the PROG pin. The program
resistor and the charge current are calculated using the
following equations:
Oncethebatteryvoltageisabove2.85V,thebatterycharger
begins charging in full power constant-current mode. The
current delivered to the battery will try to reach 1022V/
1022V
ICHRG
1022V
RPROG
R
. Depending on available input power and external
PROG
RPROG
=
, ICHRG =
load conditions, the battery charger may or may not be
able to charge at the full programmed rate. The external
load will always be prioritized over the battery charge
current. The USB current limit programming will always
be observed and only additional power will be available to
charge the battery. When system loads are light, battery
charge current will be maximized.
Ineithertheconstant-currentorconstant-voltagecharging
modes, the voltage at the PROG pin will be proportional to
the actual charge current delivered to the battery. There-
fore, the actual charge current can be determined at any
time by monitoring the PROG pin voltage and using the
following equation:
Charge Termination
VPROG
RPROG
IBAT
=
•1022
The battery charger has a built-in safety timer. When
the voltage on the battery reaches the pre-programmed
float voltage of 4.200V, the battery charger will regulate
the battery voltage and the charge current will decrease
naturally. Once the battery charger detects that the battery
has reached 4.200V, the four hour safety timer is started.
After the safety timer expires, charging of the battery will
discontinue and no more current will be delivered.
In many cases, the actual battery charge current, I , will
BAT
belowerthanI
duetolimitedinputpoweravailableand
CHRG
prioritization with the system load drawn from V
.
OUT
Charge Status Indication
The CHRG pin indicates the status of the battery charger.
Four possible states are represented by CHRG which in-
clude charging, not charging, unresponsive battery, and
battery temperature out of range.
Automatic Recharge
After the battery charger terminates, it will remain off
drawing only microamperes of current from the battery.
If the portable product remains in this state long enough,
the battery will eventually self discharge. To ensure that
The signal at the CHRG pin can be easily recognized as
one of the above four states by either a human or a mi-
croprocessor. An open-drain output, the CHRG pin can
3556f
17
LTC3556
OPERATION
drive an indicator LED through a current limiting resistor
for human interfacing or simply a pull-up resistor for
microprocessor interfacing.
pingivesthebatteryfaultindication.Forthisfault,ahuman
would easily recognize the frantic 6.1Hz “fast” blink of the
LEDwhileamicroprocessorwouldbeabletodecodeeither
the 12.5% or 87.5% duty cycles as a bad battery fault.
To make the CHRG pin easily recognized by both humans
and microprocessors, the pin is either Low for charging,
High for not charging, or it is switched at high frequency
(35kHz) to indicate the two possible faults, unresponsive
battery and battery temperature out of range.
Note that the LTC3556 is a 3-terminal PowerPath prod-
uct where system load is always prioritized over battery
charging. Due to excessive system load, there may not be
sufficient power to charge the battery beyond the trickle
charge threshold voltage within the bad battery timeout
period. Inthiscase, thebatterychargerwillfalselyindicate
a bad battery. System software may then reduce the load
and reset the battery charger to try again.
When charging begins, CHRG is pulled low and remains
lowforthedurationofanormalchargecycle.Whencharg-
ing is complete, i.e., the BAT pin reaches 4.200V and the
chargecurrenthasdroppedtoonetenthoftheprogrammed
value, the CHRG pin is released (Hi-Z). If a fault occurs,
the pin is switched at 35kHz. While switching, its duty
cycle is modulated between a high and low value at a very
low frequency. The low and high duty cycles are disparate
enough to make an LED appear to be on or off thus giving
the appearance of “blinking”. Each of the two faults has
its own unique “blink” rate for human recognition as well
as two unique duty cycles for machine recognition.
Although very improbable, it is possible that a duty cycle
reading could be taken at the bright-dim transition (low
duty cycle to high duty cycle). When this happens the
duty cycle reading will be precisely 50%. If the duty cycle
reading is 50%, system software should disqualify it and
take a new duty cycle reading.
NTC Thermistor
The CHRG pin does not respond to the C/10 threshold if
The battery temperature is measured by placing a nega-
tive temperature coefficient (NTC) thermistor close to the
battery pack.
the LTC3556 is in V
current limit. This prevents false
BUS
end of charge indications due to insufficient power avail-
able to the battery charger.
To use this feature, connect the NTC thermistor, R , be-
NTC
Table 1 illustrates the four possible states of the CHRG
pin when the battery charger is active.
tween the NTC pin and ground and a resistor, R
, from
NOM
V
BUS
to the NTC pin. R
should be a 1% resistor with
NOM
a value equal to the value of the chosen NTC thermistor
at 25°C (R25). A 100k thermistor is recommended since
thermistor current is not measured by the LTC3556 and
will have to be budgeted for USB compliance.
Table 1. CHRG Signal
MODULATION
STATUS
FREQUENCY (BLINK) FREQUENCY
DUTY CYCLES
100%
Charging
0Hz
0Hz
35kHz
35kHz
0Hz (Lo-Z)
0Hz (Hi-Z)
1.5Hz at 50%
6.1Hz at 50%
Not Charging
NTC Fault
Bad Battery
0%
The LTC3556 will pause charging when the resistance of
the NTC thermistor drops to 0.54 times the value of R25
or approximately 54k. For Vishay “Curve 1” thermistor,
this corresponds to approximately 40°C. If the battery
charger is in constant-voltage (float) mode, the safety
timer also pauses until the thermistor indicates a return
to a valid temperature. As the temperature drops, the
resistance of the NTC thermistor rises. The LTC3556 is
also designed to pause charging when the value of the
NTC thermistor increases to 3.25 times the value of R25.
For Vishay “Curve 1” this resistance, 325k, corresponds
to approximately 0°C. The hot and cold comparators each
3556f
6.25%, 93.75%
12.5%, 87.5%
An NTC fault is represented by a 35kHz pulse train whose
duty cycle alternates between 6.25% and 93.75% at a
1.5Hz rate. A human will easily recognize the 1.5Hz rate
as a “slow” blinking which indicates the out-of-range
battery temperature while a microprocessor will be able
to decode either the 6.25% or 93.75% duty cycles as an
NTC fault.
If a battery is found to be unresponsive to charging (i.e.,
its voltage remains below 2.85V for 1/2 hour), the CHRG
18
LTC3556
OPERATION
haveapproximately3°Cofhysteresistopreventoscillation
about the trip point. Grounding the NTC pin disables the
NTC charge pausing function.
Bus Speed
2
The I C port is designed to be operated at speeds of up
to 400kHz. It has built-in timing delays to ensure correct
2
operation when addressed from an I C compliant master
device. It also contains input filters designed to suppress
glitches should the bus become corrupted.
Thermal Regulation
To optimize charging time, an internal thermal feedback
loop may automatically decrease the programmed charge
current. This will occur if the die temperature rises to
approximately 110°C. Thermal regulation protects the
LTC3556 from excessive temperature due to high power
operation or high ambient thermal conditions and allows
the user to push the limits of the power handling capability
with a given circuit board design without risk of damag-
ing the LTC3556 or external components. The benefit
of the LTC3556 thermal regulation loop is that charge
current can be set according to actual conditions rather
than worst-case conditions with the assurance that the
battery charger will automatically reduce the current in
worst-case conditions.
Start and Stop Condition
A bus master signals the beginning of a communication
to a slave device by transmitting a Start condition. A Start
condition is generated by transitioning SDA from high
to low while SCL is high. When the master has finished
communicating with the slave, it issues a Stop condition
by transitioning SDA from low to high while SCL is high.
2
The bus is then free for communication with another I C
device.
Byte Format
Each byte sent to the LTC3556 must be eight bits long
followed by an extra clock cycle for the Acknowledge bit
to be returned by the LTC3556. The data should be sent
to the LTC3556 most significant bit (MSb) first.
2
I C Interface
The LTC3556 may receive commands from a host (mas-
ter) using the standard I C 2-wire interface. The Timing
2
Diagram shows the timing relationship of the signals on
the bus. The two bus lines, SDA and SCL, must be high
when the bus is not in use. External pull-up resistors or
Acknowledge
The Acknowledge signal is used for handshaking between
the master and the slave. An Acknowledge (active low)
generated by the slave (LTC3556) lets the master know
that the latest byte of information was received. The
Acknowledge related clock pulse is generated by the
master. The master releases the SDA line (high) during
the Acknowledge clock cycle. The slave receiver must pull
down the SDA line during the Acknowledge clock pulse
so that it remains a stable Low during the High period of
this clock pulse.
2
current sources, such as the LTC1694 I C accelerator, are
required on these lines. The LTC3556 is a receive-only
2
(slave) device. The I C control signals, SDA and SCL are
scaled internally to the DV supply. DV should be con-
CC
CC
nected to the same power supply as the microcontroller
2
generating the I C signals.
2
The I C port has an undervoltage lockout on the DV
CC
2
pin. When DV is below approximately 1V, the I C serial
CC
port is cleared and switching regulators 1 and 3 are set
to full scale.
Slave Address
The LTC3556 responds to only one 7-bit address which
has been factory programmed to 0001001. The LSb of the
address byte is 1 for Read and 0 for Write. This device is
write only corresponding to an address byte of 00010010
(0×12). If the correct seven bit address is given but the
R/W bit is 1, the LTC3556 will not respond.
3556f
19
LTC3556
OPERATION
Table 2. I2C Serial Port Mapping (Defaults to 0xFF00 in Reset State or if DVCC = 0V)
A7
A6
A5
A4
A3
A2
A1
A0
B7
B6
B5
B4
B3
B2
Enable Input Current Limit
(See Table 3)
B1
B0
Switching Regulator 1
Voltage (See Table 4)
Switching Regulator 3
Voltage (See Table 4)
Disable Switching Regulator
Enable
Enable
Battery Modes (See Table 5) Regulator Regulator Regulator
Charger
1
2
3
Bus Write Operation
Table 3. USB Current Limit Settings
The master initiates communication with the LTC3556
with a Start condition and a 7-bit address followed by
the Write Bit R/W = 0. If the address matches that of the
LTC3556,theLTC3556returnsanAcknowledge.Themaster
should then deliver the most significant data byte. Again
the LTC3556 acknowledges and the cycle is repeated for
a total of one address byte and two data bytes. Each data
byte is transferred to an internal holding latch upon the
return of an Acknowledge. After both data bytes have been
transferred to the LTC3556, the master may terminate the
communication with a Stop condition. Alternatively, a
Repeat-Start condition can be initiated by the master and
B1
0
B0
1
USB SETTING
10x Mode (Wall 1A Limit)
5x Mode (USB 500mA Limit)
1x Mode (USB 100mA Limit)
Suspend
1
1
0
0
1
0
Table 4. Switching Regulator Servo Voltage
A7
A3
0
A6
A2
0
A5
A1
0
A4 SWITCHING REGULATOR 1 SERVO VOLTAGE
A0 SWITCHING REGULATOR 3 SERVO VOLTAGE
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0.425V
0.450V
0.475V
0.500V
0.525V
0.550V
0.575V
0.600V
0.625V
0.650V
0.675V
0.700V
0.725V
0.750V
0.775V
0.800V
0
0
0
2
0
0
1
another chip on the I C bus can be addressed. This cycle
0
0
1
can continue indefinitely and the LTC3556 will remember
thelastinputofvaliddatathatitreceived. Onceallchipson
the bus have been addressed and sent valid data, a global
Stop condition can be sent and the LTC3556 will update its
command latch with the data that it had received.
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
2
In certain circumstances the data on the I C bus may
1
0
0
become corrupted. In these cases the LTC3556 responds
appropriately by preserving only the last set of complete
datathatithasreceived.Forexample,assumetheLTC3556
has been successfully addressed and is receiving data
when a Stop condition mistakenly occurs. The LTC3556
will ignore this stop condition and will not respond until
a new Start condition, correct address, new set of data
and Stop condition are transmitted.
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
Table 5. Switching Regulator Modes
MODE OF (BUCK) SWITCHING MODE OF (BUCK-BOOST)
B6 B5 REGULATORS 1 AND 2
Likewise, with only one exception, if the LTC3556 was
previously addressed and sent valid data but not updated
with a Stop, it will respond to any Stop that appears on
the bus, independent of the number of Repeat-Starts that
have occurred. If a Repeat-Start is given and the LTC3556
successfully acknowledges its address and first byte, it
will not respond to a Stop until both bytes of the new data
have been received and acknowledged.
SWITCHING REGULATOR 3
0
1
0
1
0
1
1
0
Pulse Skip Mode
PWM Mode
Burst Mode Operation
Forced Burst Mode Operation Burst Mode Operation
LDO Mode
3556f
20
LTC3556
OPERATION
2
Disabling the I C Port
the least noise switching solution. At lighter loads, either
Burst Mode operation, forced Burst Mode operation or
LDO mode may be selected. The buck regulators include
soft-start to limit inrush current when powering on, short-
circuit current protection and switch node slew limiting
circuitrytoreduceradiatedEMI.Noexternalcompensation
componentsarerequired. Theoperatingmodeofthebuck
2
The I C serial port can be disabled by grounding the
DV pin. In this mode, control automatically passes to
CC
the individual logic input pins ENALL and SEQ. However,
considerablefunctionalityisnotavailableinthismodesuch
as the ability to independently enable the three switching
regulators and disable the battery charger. In addition,
2
regulators can be set by I C control and defaults to pulse
2
with the I C port disabled, both programmable switching
2
skip mode if the I C port is not used. Both buck converters
regulators default to a fixed servo voltage of 0.8V, both
400mA bucks default to pulse skip mode, the 1A buck-
boost defaults to PWM mode, and the USB input current
limit defaults to 1x mode (100mA Limit).
are enabled (along with the buck-boost) when the ENALL
pin is asserted or each may be individually enabled by the
2
I C port. Buck regulator 1 has a programmable feedback
2
servo voltage via I C control (which defaults to 800mV if
2
the I C port is not used) whereas buck regulator 2 has a
PGOODALL Pin
fixedfeedbackservovoltageof800mV. Thebuckregulator
The PGOODALL pin is an open-drain output used to in-
dicate that all enabled switching regulators have reached
their final voltage. PGOODALL remains low impedance
until the last enabled regulator in the sequence reaches
92% of its regulation value. A 230ms delay is included
to allow a system microcontroller ample time to reset
itself. PGOODALL may be used as a power-on reset to the
microprocessor powered by one (or more) of the three
regulated outputs. PGOODALL is an open-drain output
and requires a pull-up resistor to the input voltage of
the monitoring microprocessor or another appropriate
power source.
input supplies V and V will generally be connected
IN1
IN2
to the system load pin V
.
OUT
Buck Regulator Output Voltage Programming
Both buck regulators can be programmed for output
voltages greater than 0.8V. The full-scale output voltage
for each buck regulator is programmed using a resistor
divider from the buck regulator output connected to the
feedback pins (FB1 and FB2) such that:
R1
R2
⎛
⎞
⎠
VOUTX = VFBX
+ 1
⎜
⎝
⎟
400mA Step-Down Switching Regulators
where V ranges from 0.425V to 0.8V for buck regula-
FBX
tor 1 and V
Figure 4.
is fixed at 0.8V for buck regulator 2. See
The LTC3556 contains two 2.25MHz step-down (buck)
constant-frequency current mode switching regulators.
Each buck regulator can provide up to 400mA of output
current. Both buck regulators can be programmed for a
minimumoutputvoltageof0.8Vandcanbeusedtopower
a microcontroller core, microcontroller I/O, memory, disk
drive or other logic circuitry. One of the buck regulators
FBX
Typical values for R1 are in the range of 40k to 1M. The
capacitor, C , cancels the pole created by feedback resis-
FB
torsandtheinputcapacitanceoftheFBxpinandalsohelps
to improve transient response for output voltages much
2
has I C programmable set-points for on-the-fly power
V
INx
L
savings. Both buck converters support 100% duty cycle
operation (low dropout mode) when their input voltage
drops very close to their output voltage. To suit a variety
of applications, selectable mode functions can be used to
trade off noise for efficiency. Four modes are available to
control the operation of the LTC3556’s buck regulators.
At moderate to heavy loads, the pulse skip mode provides
V
SWx
LTC3556
FBx
OUTx
C
R1
C
OUT
FB
R2
GND
3556 F04
Figure 4. Buck Converter Application Circuit
3556f
21
LTC3556
OPERATION
greater than 0.8V. A variety of capacitor sizes can be used
in forced Burst Mode operation, the output capacitor is
charged to a voltage slightly higher than the regulation
point.Thestep-downconverterthengoesintosleepmode,
during which the output capacitor provides the load cur
rent. In sleep mode, most of the regulator’s circuitry is
powered down, helping conserve battery power. When
theoutputvoltagedropsbelowapredeterminedvalue, the
buck regulator circuitry is powered on and another burst
cycle begins. The duration for which the buck regulator
operates in sleep mode depends on the load current. The
sleep time decreases as the load current increases. The
maximum output current in forced Burst Mode operation
is about 100mA for buck regulators 1 and 2. The buck
regulatorswillnotentersleepmodeifthemaximumoutput
current is exceeded in forced Burst Mode operation and
the output will drop out of regulation. Forced Burst Mode
operationprovidesasignificantimprovementinefficiency
at light loads at the expense of higher output ripple when
compared to pulse skip mode. For many noise-sensitive
systems,forcedBurstModeoperationmightbeundesirable
at certain times (i.e., during a transmit or receive cycle
of a wireless device), but highly desirable at others (i.e.,
for C but a value of 10pF is recommended for most ap-
FB
plications. Experimentation with capacitor sizes between
2pF and 22pF may yield improved transient response.
Buck Regulator Operating Modes
The LTC3556’s buck regulators include four possible op-
erating modes to meet the noise/power needs of a variety
of applications.
In pulse skip mode, an internal latch is set at the start of
every cycle which turns on the main P-channel MOSFET
switch.Duringeachcycle,acurrentcomparatorcompares
thepeakinductorcurrenttotheoutputofanerroramplifier.
The output of the current comparator resets the internal
latch which causes the main P-channel MOSFET switch to
turn off and the N-channel MOSFET synchronous rectifier
to turn on. The N-channel MOSFET synchronous rectifier
turns off at the end of the 2.25MHz cycle or if the current
through the N-channel MOSFET synchronous rectifier
drops to zero. Using this method of operation, the error
amplifier adjusts the peak inductor current to deliver the
required output power. All necessary compensation is
internal to the switching regulator requiring only a single
ceramicoutputcapacitorforstability.AtlightloadsinPWM
mode, the inductor current may reach zero on each pulse
which will turn off the N-channel MOSFET synchronous
rectifier. In this case, the switch node (SW) goes high
impedance and the switch node voltage will “ring.” This
is discontinuous mode operation and is normal behavior
for a switching regulator. At very light loads in pulse skip
mode, the buck regulators will automatically skip pulses
as needed to maintain output regulation.
2
when the device is in low power standby mode). The I C
port can be used to enable or disable forced Burst Mode
operation at any time, offering both low noise and low
power operation when they are needed.
In Burst Mode operation, the buck regulator automati-
cally switches between fixed frequency PWM operation
and hysteretic control as a function of the load current.
At light loads, the buck regulators operate in hysteretic
mode in much the same way as described for the forced
Burst Mode operation. Burst Mode operation provides
slightly less output ripple at the expense of slightly lower
efficiency than forced Burst Mode operation. At heavy
loads, the buck regulator operates in the same manner
as pulse skip operation does at high loads. For applica-
tions that can tolerate some output ripple at low output
currents, Burst Mode operation provides better efficiency
than pulse skip at light loads while still providing the full
specified output current of the buck regulator.
At high duty cycles (V
> V /2) it is possible for the
INx
OUTx
inductor current to reverse, causing the buck regulator
to operate continuously at light loads. This is normal and
regulationismaintained,butthesupplycurrentwillincrease
to several milliamperes due to continuous switching.
In forced Burst Mode operation, the buck regulators use a
constant-currentalgorithmtocontroltheinductorcurrent.
By controlling the inductor current directly and using a
hysteretic control loop, both noise and switching losses
areminimized. Inthismodeoutputpowerislimited. While
Finally, the buck regulators have an LDO mode that gives
a DC option for regulating their output voltages. In LDO
mode, the buck regulators are converted to linear regula-
3556f
22
LTC3556
OPERATION
tors and deliver continuous power from their SWx pins
through their respective inductors. This mode gives the
lowest possible output noise as well as low quiescent
current at light loads.
Buck Regulator Switching Slew Rate Control
The buck regulators contain new patent pending circuitry
to limit the slew rate of the switch node (SW1 and SW2).
Thisnewcircuitryisdesignedtotransitiontheswitchnode
over a period of a couple of nanoseconds, significantly
reducing radiated EMI and conducted supply noise.
The buck regulators allow mode transition on the fly,
providing seamless transition between modes even under
load.Thisallowstheusertoswitchbackandforthbetween
modes to reduce output ripple or increase low current
efficiency as needed.
Low Supply Operation
TheLTC3556incorporatesanundervoltagelockoutcircuit
on V
which shuts down both buck regulators (as well
OUT
Buck Regulator in Shutdown
as the buck-boost) when V
drops below V
.
OUT
OUTUVLO
The buck regulators are in shutdown when not enabled for
operation. In shutdown, all circuitry in the buck regulator
is disconnected from the buck regulator input supply
leaving only a few nanoamperes of leakage current. The
buck regulator outputs are individually pulled to ground
through a 10k resistor on the switch pins (SW1 and SW2)
when in shutdown.
This UVLO prevents unstable operation.
Buck-Boost DC/DC Switching Regulator
TheLTC3556containsa2.25MHzconstant-frequencyvolt-
age mode buck-boost switching regulator. The regulator
provides up to 1A of output load current. The buck-boost
can be programmed to a minimum output voltage of 2.5V
and can be used to power a microcontroller core, micro-
controller I/O, memory, disk drive or other logic circuitry.
Buck Regulator Dropout Operation
2
It is possible for a buck regulator’s input voltage, V , to
WhencontrolledbyI C,thebuck-boosthasprogrammable
INX
approach its programmed output voltage (e.g., a battery
voltageof3.4Vwithaprogrammedoutputvoltageof3.3V).
Whenthishappens,thePMOSswitchdutycycleincreases
until it is turned on continuously at 100%. In this dropout
condition, the respective output voltage equals the buck
regulator’s input voltage minus the voltage drops across
the internal P-channel MOSFET and the inductor.
set-pointsforon-the-flypowersavings. Tosuitavarietyof
applications, aselectablemodefunctionallowstheuserto
trade off noise for efficiency. Two modes are available to
control the operation of the LTC3556’s buck-boost regula-
tor. At moderate to heavy loads, the constant frequency
PWMmodeprovidestheleastnoiseswitchingsolution. At
lighter loads Burst Mode operation may be selected. The
full-scaleoutputvoltageisprogrammedbyauser-supplied
resistive divider returned to the FB3 pin. An error amplifier
compares the divided output voltage with a reference and
adjuststhecompensationvoltageaccordinglyuntiltheFB3
has stabilized to the selected reference voltage (0.425V to
0.8V).Thebuck-boostregulatoralsoincludesasoft-startto
limit inrush current and voltage overshoot when powering
on, short circuit current protection, and switch node slew
limiting circuitry for reduced radiated EMI.
Buck Regulator Soft-Start Operation
Soft-start is accomplished by gradually increasing the
peak inductor current for each buck regulator over a
500ꢀs period. This allows each output to rise slowly,
helping minimize the battery surge current. A soft-start
cycle occurs whenever a given buck regulator is enabled,
or after a fault condition has occurred (thermal shutdown
or UVLO). A soft-start cycle is not triggered by changing
operating modes. This allows seamless output operation
when transitioning between forced Burst Mode, Burst
Mode, pulse skip mode or LDO operation.
3556f
23
LTC3556
OPERATION
Input Current Limit
Buck-Boost Regulator Burst Mode Operation
The input current limit comparator will shut the input
PMOS switch off once current exceeds 2.5A (typical).
The 2.5A input current limit also protects against a
grounded VOUT3 node.
In Burst Mode operation, the buck-boost regulator uses
a hysteretic FB3 voltage algorithm to control the output
voltage. By limiting FET switching and using a hysteretic
control loop, switching losses are greatly reduced. In this
mode output current is limited to 50mA typical. While
operating in Burst Mode operation, the output capacitor
is charged to a voltage slightly higher than the regulation
point. The buck-boost converter then goes into a sleep
state, during which the output capacitor provides the load
current. The output capacitor is charged by charging the
inductor until the input current reaches 250mA typical
andthendischargingtheinductoruntilthereversecurrent
reaches 0mA typical. This process is repeated until the
feedbackvoltagehaschargedto6mVabovetheregulation
point. In the sleep state, most of the regulator’s circuitry is
powered down, helping to conserve battery power. When
the feedback voltage drops 6mV below the regulation
point, the switching regulator circuitry is powered on and
another burst cycle begins. The duration for which the
regulator sleeps depends on the load current and output
capacitor value. The sleep time decreases as the load cur-
rent increases. The maximum load current in Burst Mode
operation is 50mA typical. The buck-boost regulator will
not go to sleep if the current is greater than 50mA, and
if the load current increases beyond this point while in
BurstModeoperationtheoutputwillloseregulation.Burst
Mode operation provides a significant improvement in ef-
ficiencyatlightloadsattheexpenseofhigheroutputripple
when compared to PWM mode. For many noise-sensitive
systems, Burst Mode operation might be undesirable at
certain times (i.e., during a transmit or receive cycle of a
wireless device), but highly desirable at others (i.e., when
the device is in low power standby mode). The B6 and
Output Overvoltage Protection
If the FB3 node were inadvertently shorted to ground, then
the output would increase indefinitely with the maximum
current that could be sourced from V . The LTC3556
IN3
protects against this by shutting off the input PMOS if
the output voltage exceeds 5.6V (typical).
Low Output Voltage Operation
When the output voltage is below 2.65V (typical) during
startup, Burst Mode operation is disabled and switch D
is turned off (allowing forward current through the well
diode and limiting reverse current to 0mA).
Buck-Boost Regulator PWM Operating Mode
In PWM mode the voltage seen at FB3 is compared to the
selectedreferencevoltage(0.425Vto0.8V).FromtheFB3
voltage an error amplifier generates an error signal seen
at VC3. This error signal commands PWM waveforms
that modulate switches A, B, C and D. Switches A and B
operate synchronously as do switches C and D. If VIN3 is
significantlygreaterthantheprogrammedVOUT3,thenthe
converter will operate in buck mode. In this case switches
A and B will be modulated, with switch D always on (and
switch C always off), to step down the input voltage to
the programmed output. If VIN3 is significantly less than
the programmed VOUT3, then the converter will operate in
boostmode. InthiscaseswitchesCandDaremodulated,
with switch A always on (and switch B always off), to step
up the input voltage to the programmed output. If VIN3 is
close to the programmed VOUT3, then the converter will
operate in 4-switch mode. In this mode the switches se-
quencethroughthepatternofAD,AC,BDtoeitherstepthe
input voltage up or down to the programmed output.
2
B5 bits of the I C port are used to enable or disable Burst
Mode operation at any time, offering both low noise and
low power operation when they are needed.
3556f
24
LTC3556
OPERATION
Buck-Boost Regulator Soft-Start Operation
condition has occurred (thermal shutdown or UVLO). A
soft-start cycle is not triggered by changing operating
modes.Thisallowsseamlessoperationwhentransitioning
between Burst Mode operation and PWM mode.
Soft-start is accomplished by gradually increasing the
reference voltage input to the error amplifier over a 0.5ms
(typical)period.Thislimitstransientinrushcurrentsduring
start-up because the output voltage is always “in regula-
tion.” Ramping the reference voltage input also limits the
rate of increase in the V voltage which helps minimize
output overshoot during start-up. A soft-start cycle oc-
Low Supply Operation
TheLTC3556incorporatesanundervoltagelockoutcircuit
on V
(connected to V ) which shuts down the buck-
C3
OUT
IN3
boost regulator when V
drops below 2.6V. This UVLO
OUT
curs whenever the buck-boost is enabled, or after a fault
prevents unstable operation.
APPLICATIONS INFORMATION
CLPROG Resistor and Capacitor
row, the LTC3556 was designed for a specific inductance
value of 3.3μH. Some inductors which may be suitable
for this application are listed in Table 6.
As described in the High Efficiency Switching PowerPath
Controller section, the resistor on the CLPROG pin deter-
mines the average input current limit when the switching
regulator is set to either the 1x mode (USB 100mA), the
5x mode (USB 500mA) or the 10x mode. The input cur-
rent will be comprised of two components, the current
Table 6. Recommended Inductors for PowerPath Controller
MAX MAX
INDUCTOR
TYPE
L
I
DCR
(Ω)
SIZE IN mm
(L × W × H) MANUFACTURER
DC
(μH) (A)
LPS4018
3.3 2.2
0.08
Coilcraft
www.coilcraft.com
3.9 × 3.9 × 1.7
that is used to drive V
and the quiescent current of the
OUT
switching regulator. To ensure that the USB specification
is strictly met, both components of input current should
be considered. The Electrical Characteristics table gives
values for quiescent currents in either setting as well as
current limit programming accuracy. To get as close to
the 500mA or 100mA specifications as possible, a 1%
D53LC
3.3 2.26 0.034
3.3 1.55 0.070
Toko
5.0 × 5.0 × 3.0
3.8 × 3.8 × 1.8
DB318C
www.toko.com
WE-TPC
Type M1
3.3 1.95 0.065
Würth Elektronik
www.we-online.com
4.8 × 4.8 × 1.8
CDRH6D12 3.3 2.2 0.0625
CDRH6D38 3.3 3.5 0.020
Sumida
www.sumida.com
6.7 × 6.7 × 1.5
7.0 × 7.0 × 4.0
resistor should be used. Recall that I
= I
+
VBUS
VBUSQ
V
and V
Bypass Capacitors
BUS
OUT
V
/R
• (h
+1).
CLPROG CLPPROG
CLPROG
The style and value of capacitors used with the LTC3556
determineseveralimportantparameterssuchasregulator
control-loop stability and input voltage ripple. Because
the LTC3556 uses a step-down switching power supply
An averaging capacitor or an R-C combination is required
in parallel with the CLPROG resistor so that the switching
regulator can determine the average input current. This
network also provides the dominant pole for the feedback
loop when current limit is reached. To ensure stability,
the capacitor on CLPROG should be 0.47μF or larger.
Alternatively, faster transient response may be achieved
with 0.1μF in series with 8.2Ω.
from V
to V , its input current waveform contains
BUS
OUT
high frequency components. It is strongly recommended
that a low equivalent series resistance (ESR) multilayer
ceramic capacitor be used to bypass V . Tantalum and
BUS
aluminum capacitors are not recommended because of
their high ESR. The value of the capacitor on V
directly
BUS
Choosing the PowerPath Inductor
controls the amount of input ripple for a given load cur-
rent. Increasing the size of this capacitor will reduce the
input ripple.
Because the input voltage range and output voltage range
of the power path switching regulator are both fairly nar-
3556f
25
LTC3556
APPLICATIONS INFORMATION
maximize efficiency, choose an inductor with a low DC
resistance. For a 1.2V output, efficiency is reduced about
2% for 100mΩ series resistance at 400mA load current,
and about 2% for 300mΩ series resistance at 100mA load
current. Choose an inductor with a DC current rating at
least 1.5 times larger than the maximum load current to
ensure that the inductor does not saturate during normal
operation. If output short-circuit is a possible condition,
the inductor should be rated to handle the maximum peak
current specified for the buck converters.
To prevent large V
voltage steps during transient load
OUT
conditions, it is also recommended that a ceramic capaci-
tor be used to bypass V . The output capacitor is used
OUT
in the compensation of the switching regulator. At least
4ꢀF of actual capacitance with low ESR are required on
V
. Additional capacitance will improve load transient
OUT
performance and stability.
Multilayer ceramic chip capacitors typically have excep-
tional ESR performance. MLCCs combined with a tight
board layout and an unbroken ground plane will yield very
good performance and low EMI emissions.
Different core materials and shapes will change the
size/current and price/current relationship of an induc-
tor. Toroid or shielded pot cores in ferrite or Permalloy
materials are small and don’t radiate much energy, but
generally cost more than powdered iron core inductors
with similar electrical characteristics. Inductors that are
very thin or have a very small volume typically have much
higher core and DCR losses, and will not give the best ef-
ficiency. The choice of which style inductor to use often
depends more on the price vs size, performance and any
radiated EMI requirements than on what the LTC3556
requires to operate.
There are several types of ceramic capacitors available,
each having considerably different characteristics. For
example, X7R ceramic capacitors have the best voltage
and temperature stability. X5R ceramic capacitors have
apparentlyhigherpackingdensitybutpoorerperformance
over their rated voltage and temperature ranges. Y5V
ceramic capacitors have the highest packing density,
but must be used with caution, because of their extreme
nonlinear characteristic of capacitance vs voltage. The
actualin-circuitcapacitanceofaceramiccapacitorshould
be measured with a small AC signal (ideally less than
200mV) as is expected in-circuit. Many vendors specify
The inductor value also has an effect on forced burst
and Burst Mode operations. Lower inductor values will
cause the Burst Mode and forced Burst Mode switching
frequencies to increase.
thecapacitancevsvoltagewitha1V
ACtestsignaland
RMS
as a result overstate the capacitance that the capacitor will
present in the application. Using similar operating condi-
tions as the application, the user must measure or request
from the vendor the actual capacitance to determine if the
selected capacitor meets the minimum capacitance that
the application requires.
Table 7 shows several inductors that work well with the
LTC3556’s buck regulators. These inductors offer a good
compromise in current rating, DCR and physical size.
Consult each manufacturer for detailed information on
their entire selection of inductors.
400mA Step-Down Switching Regulator Inductor
Selection
Table 7. Recommended Inductors for 400mA Step-Down
Switching Regulators
Many different sizes and shapes of inductors are avail-
able from numerous manufacturers. Choosing the right
inductor from such a large selection of devices can be
overwhelming, but following a few basic guidelines will
make the selection process much simpler.
NDUCTOR
TYPE
L
(μH)
MAX
I (A) DCR(Ω) (L × W × H) MANUFACTURER
DC
MAX
SIZE IN mm
DE2818C
DE2812C
4.7
4.7
1.25
1.15
0.9
0.072*
0.13*
0.11
Toko
3.0 × 2.8 × 1.8
3.0 × 2.8 × 1.2
4.0 × 4.0 × 1.8
www.toko.com
CDRH3D16 4.7
Sumida
www.sumida.com
Thebuckconvertersaredesignedtoworkwithinductorsin
the range of 2.2μH to 10μH. For most applications a 4.7μH
inductor is suggested for both buck regulators. Larger
value inductors reduce ripple current which improves
outputripplevoltage.Lowervalueinductorsresultinhigher
ripple current and improved transient response time. To
SD3118
SD3112
4.7
4.7
1.3
0.8
0.162
0.246
Cooper
www.cooperet.
com
3.1 × 3.1 × 1.8
3.1 × 3.1 × 1.2
LPS3015
4.7
1.1
0.2
Coilcraft
www.coilcraft.com
3.0 × 3.0 × 1.5
*Typical DCR
3556f
26
LTC3556
APPLICATIONS INFORMATION
400mA Step-Down Switching Regulator Input/Output
Capacitor Selection
Table 9. Recommended Inductors for Buck-Boost Regulator
MAX MAX
DC
(μH) (A)
INDUCTOR
TYPE
L
I
DCR
(Ω)
SIZE IN mm
(L × W × H) MANUFACTURER
Low ESR (equivalent series resistance) MLCC capacitors
shouldbeusedatbothbuckregulatoroutputsaswellasat
LPS4018
3.3 2.2
2.2 2.5
0.08
0.07
Coilcraft
www.coilcraft.com
3.9 × 3.9 × 1.7
3.9 × 3.9 × 1.7
eachbuckregulatorinputsupply(V andV ).OnlyX5R
IN1
IN2
or X7R ceramic capacitors should be used because they
retaintheircapacitanceoverwidervoltageandtemperature
ranges than other ceramic types. A 10ꢀF output capaci-
tor is sufficient for most applications. For good transient
response and stability the output capacitor should retain
at least 4ꢀF of capacitance over operating temperature
and bias voltage. Each buck regulator input supply should
be bypassed with a 1ꢀF capacitor. Consult with capacitor
manufacturers for detailed information on their selection
and specifications of ceramic capacitors. Many manufac-
turers now offer very thin (<1mm tall) ceramic capacitors
ideal for use in height-restricted designs. Table 8 shows a
list of several ceramic capacitor manufacturers.
D53LC
2.0 3.25 0.02
Toko
5.0 × 5.0 × 3.0
4.8 × 4.8 × 2.8
4.7 × 4.7 × 2.4
www.toko.com
7440430022 2.2 2.5 0.028
Würth-Elektronik
www.we-online.com
CDRH4D22/ 2.2 2.4 0.044
HP
Sumida
www.sumida.com
SD14
2.0 2.56 0.045
Cooper
www.cooperet.com
5.2 × 5.2 ×
1.45
Buck-Boost Regulator Input/Output Capacitor
Selection
LowESRMLCCcapacitorsshouldalsobeusedatboththe
buck-boost regulator output (V
) and the buck-boost
OUT3
regulator input supply (V ). Again, only X5R or X7R ce-
IN3
ramic capacitors should be used because they retain their
capacitance over wider voltage and temperature ranges
than other ceramic types. A 22μF output capacitor is suf-
ficient for most applications. The buck-boost regulator
input supply should be bypassed with a 2.2μF capacitor.
Refer to Table 8 for recommended ceramic capacitor
manufacturers.
Table 8. Recommended Ceramic Capacitor Manufacturers
AVX
www.avxcorp.com
www.murata.com
www.t-yuden.com
www.vishay.com
www.tdk.com
Murata
Taiyo Yuden
Vishay Siliconix
TDK
Buck-Boost Regulator Inductor Selection
Buck-Boost Regulator Output Voltage Programming
Inductorselectioncriteriaforthebuck-boostaresimilarto
thosegivenforthe400mAstep-downswitchingregulators.
The buck-boost converter is designed to work with induc-
tors in the range of 1μH to 5μH. For most applications a
2.2μH inductor will suffice. Choose an inductor with a DC
current rating at least 2 times larger than the maximum
load current to ensure that the inductor does not saturate
during normal operation. If output short circuit is a pos-
sible condition, the inductor should be rated to handle
the maximum peak current specified for the buck-boost
converter.
The buck-boost regulator can be programmed for output
voltages greater than 2.75V and less than 5.5V. The full-
scaleoutputvoltageisprogrammedusingaresistordivider
from the V
pin connected to the FB3 pin such that:
OUT3
R1
R2
⎛
⎞
⎠
VOUT3 = V
+ 1
FB3
⎜
⎝
⎟
where V ranges from 0.425V to 0.8V.
FB3
Table 9 shows several inductors that work well with the
LTC3556’s buck-boost regulator. These inductors offer a
good compromise in current rating, DCR and physical
size. Consult each manufacturer for detailed information
on their entire selection of inductors.
3556f
27
LTC3556
APPLICATIONS INFORMATION
Closing the Feedback Loop
The unity-gain frequency of the error amplifier with the
Type I compensation is given by:
TheLTC3556incorporatesvoltagemodePWMcontrol.The
control to output gain varies with operation region (buck,
boost, buck-boost), but is usually no greater than 20. The
output filter exhibits a double-pole response given by:
1
fUG
=
Hz
2 • π •R1•CP1
Mostapplicationsdemandanimprovedtransientresponse
toallowasmalleroutputfiltercapacitor.Toachieveahigher
bandwidth, Type III compensation is required. Two zeros
are required to compensate for the double-pole response.
1
fFILTER_POLE
=
Hz
2 • π • L •COUT
is the output filter capacitor.
where C
OUT
Type III compensation also reduces any V
at start-up.
overshoot
OUT3
The output filter zero is given by:
1
The compensation network depicted in Figure 6 yields the
transfer function:
fFILTER_ZERO
=
Hz
2 • π •RESR •COUT
is the capacitor equivalent series resistance.
where R
VC3
1
ESR
=
VOUT3 R1(C1+ C2)
Atroublesomefeatureinboostmodeistheright-halfplane
zero (RHP), and is given by:
(1+ sR2C2)[1+ s(R1+ R3)C3]
•
2
s 1+ sR2(C1||C2) (1+ sR3C3)
V
⎡
⎤
IN
⎣
⎦
fRHPZ
=
Hz
2 • π •IOUT •L • VOUT
A Type III compensation network attempts to introduce
a phase bump at a higher frequency than the LC double
pole. This allows the system to cross unity gain after the
LC double pole, and achieve a higher bandwidth. While
attempting to cross over after the LC double pole, the
system must still cross over before the boost right-half
plane zero. If unity gain is not reached sufficiently before
the right-half plane zero, then the –180° of phase lag from
The loop gain is typically rolled off before the RHP zero
frequency.
A simple Type I compensation network (as shown in
Figure 5) can be incorporated to stabilize the loop but
at the cost of reduced bandwidth and slower transient
response. To ensure proper phase margin, the loop must
cross unity-gain a decade before the LC double pole.
V
OUT3
R3
C3
0.8V
+
–
R1
V
OUT3
ERROR
AMP
FB3
7
0.8V
+
–
ERROR
AMP
R1
FB3
7
C2
R
FB
V
C3
R2
C1
8
C
R2
P1
3556 F06
V
C3
8
3556 F05
Figure 5. Error Amplifier with Type I Compensation
Figure 6. Error Amplifier with Type III Compensation
3556f
28
LTC3556
APPLICATIONS INFORMATION
the LC double pole combined with the –90° of phase lag
from the right-half plane zero will result in negating the
phase bump of the compensator.
Over-Programming the Battery Charger
The USB high power specification allows for up to 2.5W to
bedrawnfromtheUSBport(5V×500mA).ThePowerPath
switching regulator transforms the voltage at V
to just
The compensator zeros should be placed either before
or only slightly after the LC double pole such that their
positive phase contributions offset the –180° that occurs
at the filter double pole. If they are placed at too low of a
frequency, theywillintroducetoomuchgaintothesystem
and the crossover frequency will be too high. The two high
frequency poles should be placed such that the system
crosses unity gain during the phase bump introduced
by the zeros and before the boost right-half plane zero
and such that the compensator bandwidth is less than
the bandwidth of the error amp (typically 900kHz). If the
gain of the compensation network is ever greater than
the gain of the error amplifier, then the error amplifier no
longer acts as an ideal op amp, and another pole will be
introduced at the same point.
BUS
abovethevoltageatBATwithhighefficiency,whilelimiting
power to less than the amount programmed at CLPROG.
In some cases the battery charger may be programmed
(withthePROGpin)todeliverthemaximumsafecharging
current without regard to the USB specifications. If there
is insufficient current available to charge the battery at the
programmed rate, the PowerPath regulator will reduce
charge current until the system load on V
is satisfied
OUT
and the V
current limit is satisfied. Programming the
BUS
battery charger for more current than is available will
not cause the average input current limit to be violated.
It will merely allow the battery charger to make use of
all available power to charge the battery as quickly as
possible, and with minimal power dissipation within the
battery charger.
Recommended Type III compensation components for a
3.3V output:
Alternate NTC Thermistors and Biasing
R1: 324kꢁ
The LTC3556 provides temperature qualified charging if
a grounded thermistor and a bias resistor are connected
to NTC. By using a bias resistor whose value is equal to
the room temperature resistance of the thermistor (R25)
the upper and lower temperatures are pre-programmed
to approximately 40°C and 0°C, respectively (assuming
a Vishay “Curve 1” thermistor).
R : 105kꢁ
FB
C1: 10pF
R2: 15kꢁ
C2: 330pF
R3: 121kΩ
C3: 33pF
The upper and lower temperature thresholds can be ad-
justed by either a modification of the bias resistor value
or by adding a second adjustment resistor to the circuit.
If only the bias resistor is adjusted, then either the upper
or the lower threshold can be modified but not both. The
other trip point will be determined by the characteristics
of the thermistor. Using the bias resistor in addition to an
adjustmentresistor,boththeupperandthelowertempera-
ture trip points can be independently programmed with
the constraint that the difference between the upper and
lower temperature thresholds cannot decrease. Examples
of each technique follow.
C
: 22μF
OUT
L : 2.2μH
OUT
NTC thermistors have temperature characteristics which
areindicatedonresistance-temperatureconversiontables.
TheVishay-DalethermistorNTHS0603N011-N1003F,used
3556f
29
LTC3556
APPLICATIONS INFORMATION
in the following examples, has a nominal value of 100k
and follows the Vishay “Curve 1” resistance-temperature
characteristic.
to the nonlinear behavior of the thermistor. The following
equations can be used to easily calculate a new value for
the bias resistor:
rHOT
0.536
In the explanation below, the following notation is used.
R25 = Value of the thermistor at 25°C
RNOM
RNOM
=
•R25
•R25
rCOLD
3.25
R
R
= Value of thermistor at the cold trip point
NTC|COLD
=
= Value of thermistor at the hot trip point
NTC|HOT
where r
and r
are the resistance ratios at the de-
r
r
= Ratio of R
to R25
HOT
COLD
COLD
NTC|COLD
sired hot and cold trip points. Note that these equations
are linked. Therefore, only one of the two trip points can
be chosen, the other is determined by the default ratios
designed in the IC. Consider an example where a 60°C
hot trip point is desired.
= Ratio of R
to R25
HOT
NTC|COLD
R
=Primarythermistorbiasresistor(seeFigure7a)
NOM
R1 = Optional temperature range adjustment resistor
(see Figure 7b)
FromtheVishayCurve1R-Tcharacteristics,r is0.2488
ThetrippointsfortheLTC3556’stemperaturequalification
HOT
should be set
at 60°C. Using the above equation, R
are internally programmed at 0.349 • V
for the hot
NOM
BUS
to 46.4k. With this value of R
, the cold trip point is
NOM
threshold and 0.765 • V
for the cold threshold.
BUS
about 16°C. Notice that the span is now 44°C rather than
the previous 40°C. This is due to the decrease in “tem-
perature gain” of the thermistor as absolute temperature
increases.
Therefore, the hot trip point is set when:
RNTC|HOT
• VBUS = 0.349 • VBUS
RNOM +RNTC|HOT
The upper and lower temperature trip points can be inde-
pendentlyprogrammedbyusinganadditionalbiasresistor
asshowninFigure7b. Thefollowingformulascanbeused
and the cold trip point is set when:
RNTC|COLD
to compute the values of R
and R1:
• VBUS = 0.765 • VBUS
RNOM +RNTC|COLD
NOM
rCOLD –rHOT
RNOM
=
•R25
2.714
SolvingtheseequationsforR
in the following:
andR
results
NTC|COLD
NTC|HOT
R1= 0.536 •RNOM –rHOT •R25
R
= 0.536 • R
NTC|HOT
NOM
For example, to set the trip points to 0°C and 45°C with
a Vishay Curve 1 thermistor choose:
and
R
= 3.25 • R
NTC|COLD
NOM
3.266 – 0.4368
RNOM
=
•100k = 104.2k
By setting R
equal to R25, the above equations result
NOM
= 0.536 and r
2.714
in r
= 3.25. Referencing these ratios
HOT
COLD
The nearest 1% value is 105k.
to the Vishay Resistance-Temperature Curve 1 chart gives
a hot trip point of about 40°C and a cold trip point of about
0°C. The difference between the hot and cold trip points
is approximately 40°C.
R1 = 0.536 • 105k – 0.4368 • 100k = 12.6k
The nearest 1% value is 12.7k. The final solution is shown
in Figure 7b and results in an upper trip point of 45°C and
a lower trip point of 0°C.
By using a bias resistor, R
, different in value from
NOM
R25, the hot and cold trip points can be moved in either
direction.Thetemperaturespanwillchangesomewhatdue
3556f
30
LTC3556
APPLICATIONS INFORMATION
LTC3556
NTC BLOCK
V
V
BUS
BUS
0.765 • V
BUS
R
NOM
–
+
100k
TOO_COLD
TOO_HOT
NTC
3
R
NTC
T
100k
–
+
0.349 • V
BUS
+
–
NTC_ENABLE
0.017V • V
BUS
3556 F07a
(7a)
V
V
LTC3556
NTC BLOCK
BUS
BUS
0.765 • V
BUS
R
NOM
–
+
105k
TOO_COLD
TOO_HOT
NTC
3
R1
12.7k
–
+
0.349 • V
BUS
R
NTC
T
100k
+
–
NTC_ENABLE
0.017 • V
BUS
3556 F07b
(7b)
Figure 7. NTC Circuits
3556f
31
LTC3556
APPLICATIONS INFORMATION
USB Inrush Limiting
Printed Circuit Board Layout Considerations
When a USB cable is plugged into a portable product,
the inductance of the cable and the high-Q ceramic input
capacitor form an L-C resonant circuit. If the cable does
not have adequate mutual coupling or if there is not much
impedance in the cable, it is possible for the voltage at
the input of the product to reach as high as twice the USB
voltage (~10V) before it settles out. To prevent excessive
voltagefromdamagingtheLTC3556duringahotinsertion,
it is best to have a low voltage coefficient capacitor at the
In order to be able to deliver maximum current under
all conditions, it is critical that the Exposed Pad on the
backside of the LTC3556 package be soldered to the PC
board ground. Failure to make thermal contact between
the Exposed Pad on the backside of the package and the
copper board will result in higher thermal resistances.
Furthermore, duetoitshighfrequencyswitchingcircuitry,
it is imperative that the input capacitors, inductors and
output capacitors be as close to the LTC3556 as possible
and that there be an unbroken ground plane under the
LTC3556 and all of its external high frequency compo-
V
pintotheLTC3556. Thisisachievablebyselectingan
BUS
MLCC capacitor that has a higher voltage rating than that
requiredfortheapplication. Forexample, a16V, X5R, 10μF
capacitor in a 1206 case would be a more conservative
choice than a 6.3V, X5R, 10μF capacitor in a smaller 0805
case. The size of the input overshoot will be determined
nents. High frequency currents such as the V , V
,
BUS IN1
V
and V currents on the LTC3556, tend to find their
IN2
IN3
way along the ground plane in a myriad of paths ranging
from directly back to a mirror path beneath the incident
path on the top of the board. If there are slits or cuts
in the ground plane due to other traces on that layer,
the current will be forced to go around the slits. If high
frequency currents are not allowed to flow back through
their natural least-area path, excessive voltage will build
up and radiated emissions will occur. There should be a
group of vias under the grounded backside of the pack-
age leading directly down to an internal ground plane. To
minimize parasitic inductance, the ground plane should
be on the second layer of the PC board.
by the “Q” of the resonant tank circuit formed by C and
IN
the input lead inductance. It is recommended to measure
the input ringing with the selected components to verify
compliance with the Absolute Maximum specifications.
Alternatively, the following soft connect circuit (Figure 8)
can be employed. In this circuit, capacitor C1 holds MP1
off when the cable is first connected. Eventually C1 begins
to charge up to the USB input voltage applying increasing
gate support to MP1. The long time constant of R1 and
C1 prevent the current from building up in the cable too
fast thus dampening out any resonant overshoot.
MP1
Si2333
V
BUS
C1
100nF
5V USB
INPUT
C2
10μF
LTC3556
USB CABLE
R1
40k
GND
3556 F08
Figure 8. USB Soft Connect Circuit
3556f
32
LTC3556
APPLICATIONS INFORMATION
The GATE pin for the external ideal diode controller has
extremely limited drive current. Care must be taken to
minimize leakage to adjacent PC board traces. 100nA of
leakage from this pin will introduce an offset to the 15mV
ideal diode of approximately 10mV. To minimize leakage,
the trace can be guarded on the PC board by surrounding
lead length, however, may add enough series inductance
to require a bypass capacitor of at least 1μF from BAT to
GND. Furthermore, when the battery is disconnected, a
100μF OSCON B6 capacitor in series with a 0Ω jumper
from BAT to GND is required to keep ripple voltage low.
High value, low ESR multilayer ceramic chip capacitors
reduce the constant-voltage loop phase margin, possibly
resulting in instability. Ceramic capacitors up to 22μF may
beusedinparallelwithabattery,butlargerceramicsshould
be decoupled with 0.2Ω to 1Ω of series resistance.
it with V
connected metal, which should generally be
OUT
less that one volt higher than GATE.
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3556.
In constant-current mode, the PROG pin is in the feed-
back loop rather than the battery voltage. Because of the
additional pole created by any PROG pin capacitance,
capacitance on this pin must be kept to a minimum. With
no additional capacitance on the PROG pin, the battery
charger is stable with program resistor values as high
as 25k. However, additional capacitance on this node
reduces the maximum allowed program resistor. The pole
frequency at the PROG pin should be kept above 100kHz.
Therefore, if the PROG pin has a parasitic capacitance,
1. Are the capacitors at V , V , V and V as close
BUS IN1 IN2
IN3
as possible to the LTC3556? These capacitors provide
the AC current to the internal power MOSFETs and their
drivers. Minimizing inductance from these capacitors
to the LTC3556 is a top priority.
2. Are C and L1 closely connected? The (–) plate of C
OUT
OUT
IN
returns current to the GND plane, and then back to C .
3. Keep sensitive components away from the SW pins.
C
, the following equation should be used to calculate
PROG
Battery Charger Stability Considerations
the maximum resistance value for R
:
PROG
The LTC3556’s battery charger contains both a constant-
voltageandaconstant-currentcontrolloop.Theconstant-
voltage loop is stable without any compensation when a
battery is connected with low impedance leads. Excessive
1
RPROG
≤
2π •100kHz •CPROG
3556 F09
Figure 9. Higher Frequency Ground Currents Follow Their Incident Path.
Slices in the Ground Plane Cause High Voltage and Increased Emissions
3556f
33
LTC3556
TYPICAL APPLICATION
Watchdog Microcontroller Operation
L1
3.3μH
25
26
USB/WALL
4.5V TO 5.5V
TO OTHER
LOADS
SW
OUT
V
BUS
24
22
23
C1
V
100k
10μF
3
20
2
510Ω
C2
22μF
GATE
BAT
NTC
MP1
PROG
CLPROG
T
8.25Ω
0.1μF
+
Li-Ion
2k
RED
29
GND
3.01k
2.5V TO
3.3V
1A
21
12
CHRG
V
HDD
OUT3
10pF
121k
33pF
330pF
15k
8
324k
1
V
C3
LDO3V3
22μF
7
10
FB3
1μF
DV
CC
14
2.2μF
SWCD3
105k
L2
2.2μH
9
SWAB3
11
PUSHBUTTON
MICROCONTROLLER
V
IN3
L3
4.7μH
1.8V
400mA
LTC3555
19
17
SW2
FB2
I/O
1.02M
806k
10pF
2
13,16
2
I C (SCL, SDA)
1μF
10μF
MICROPROCESSOR
C1: MURATA GRM21BR61A106KE19
C2: TDK C2012X5R0J226M
L1: COILCRAFT LPS4018-332LM
L2: COILCRAFT LPS4018-222MLC
L3, L4: TOKO 1098AS-4R7M
MP1: SILICONIX Si2333
18
4
V
0.8V TO
1.6V
IN2
L4
4.7μH
400mA
SW1
FB1
CORE
POR
806k
806k
28
27
10pF
ENALL
SEQ
6
1μF
10k
10μF
5
V
IN1
15
3556 TA02
PGOODALL
3556f
34
LTC3556
PACKAGE DESCRIPTION
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev B)
0.70 0.05
4.50 0.05
3.10 0.05
2.50 REF
2.65 0.05
3.65 0.05
PACKAGE OUTLINE
0.25 0.05
0.50 BSC
3.50 REF
4.10 0.05
5.50 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH
R = 0.20 OR 0.35
s 45° CHAMFER
2.50 REF
R = 0.115
TYP
R = 0.05
TYP
0.75 0.05
4.00 0.10
(2 SIDES)
27
28
0.40 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
5.00 0.10
(2 SIDES)
3.50 REF
3.65 0.10
2.65 0.10
(UFD28) QFN 0506 REV B
0.25 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3556f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
35
LTC3556
TYPICAL APPLICATION
Pushbutton Start with Automatic Sequencing, Reverse Input Voltage Protection and 10 Second Push and Hold Hard Shutdown
MP1
25
12
8
USB
CONNECTOR
V
MEMORY
V
OUT3
BUS
10μF
V
C3
7
14
FB3
SWCD3
10
DV
CC
9
15
0.1μF
SWAB3
PGOODALL
1
CORE
LDO3V3
4
6
1μF
SW1
4.7k
1k
LTC3556
FB1
1M
28
27
MN1
ENALL
SEQ
2
SDA
SCL
2
13,16
19
I C (SCL, SDA)
I/O
10μF
10μF
SW2
FB2
10k
29
17
GND
2
SEND I C CODE: “0x12FF1C”
ONCE POWER IS DETECTED
MN1: 2N7002
MP1: SILICONIX Si2333DS
3556 TA03
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LTC3455
LTC3456
LTC3552
Dual DC/DC Converter with USB Power
Manager and Li-Ion Battery Charger
Seamless Transition Between Input Power Sources: Li-Ion Battery, USB and 5V Wall
Adapter. Two High Efficiency DC/DC Converters: Up to 96%. Full Featured Li-Ion Battery
Charger with Accurate USB Current Limiting (500mA/100mA). Pin Selectable Burst Mode
Operation. Hot SwapTM Output for SDIO and Memory Cards. 24-Lead 4mm × 4mm QFN
Package
2-Cell, Multi-Output DC/DC Converter
with USB Power Manager
Seamless Transition Between 2-Cell Battery, USB and AC Wall Adapter Input Power
Sources. Main Output: Fixed 3.3V Output, Core Output: Adjustable from 0.8V to V
.
BATT(MIN)
Hot Swap Output for Memory Cards. Power Supply Sequencing: Main and Hot Swap
Accurate USB Current Limiting. High Frequency Operation: 1MHz. High Efficiency: Up to
92%. 24-Lead 4mm × 4mm QFN Package
Standalone Linear Li-Ion Battery
Charger with Adjustable Output Dual
Synchronous Buck Converter
Synchronous Buck Converter, Efficiency: >90%, Adjustable Outputs at 800mA and 400mA,
Charge Current Programmable up to 950mA, USB Compatible, 16-Lead 5mm × 3mm DFN
Package
LTC3555/
LTC3555-1
High Efficiency USB Power Manager Plus Maximizes Available Power from USB Port, Bat-Track, “Instant On” Operation, 1.5A Max
Triple Step-Down DC/DC
Charge Current, 180mΩ Ideal Diode with <50mΩ Option, 3.3V/25mA Always-On LDO,
Three Synchronous Buck Regulators (400mA/400mA/1A), 4mm × 5mm QFN28 Package
LTC3557/
LTC3557-1
Linear USB Power Manager with Li-Ion/
Complete Multifunction ASSP: Linear Power Manager and Three Buck Regulators
Polymer Charger and Triple Synchronous Charge Current Programmable up to 1.5A from Wall Adapter Input, Thermal Regulation,
Buck Converter
Synchronous Buck Efficiency: >95%, ADJ Outputs: 0.8V to 3.6V at 400mA/400mA/600mA
Bat-Track Adaptive Output Control, 200mΩ Ideal Diode, 4mm × 4mm QFN28 Package
LTC4085
Linear USB Power Manager with Ideal
Diode Controller and Li-Ion Charger
Charges Single Cell Li-Ion Batteries Directly from a USB Port, Thermal Regulation, 200mΩ
Ideal Diode with <50mΩ option, 4mm × 3mm DFN14 Package
LTC4088/
LTC4088-1
High Efficiency USB Power Manager and Maximizes Available Power from USB Port, Bat-Track, “Instant On” Operation, 1.5A Max
Battery Charger
Charge Current, 180mΩ Ideal Diode with <50mΩ Option, 3.3V/25mA Always-On LDO,
4mm × 3mm DFN14 Package
Hot Swap is a trademark of Linear Technology Corporation.
3556f
LT 0208 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
36
●
●
© LINEAR TECHNOLOGY CORPORATION 2008
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
相关型号：
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LTC3556 - High Efficiency USB Power Manager with Dual Buck and Buck-Boost DC/DCs; Package: QFN; Pins: 28; Temperature Range: -40°C to 85°C
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LTC3557EUF#PBF
LTC3557/LTC3557-1 - USB Power Manager with Li-Ion Charger and Three Step-Down Regulators; Package: QFN; Pins: 28; Temperature Range: -40°C to 85°C
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