LTC3425EUH#TR [Linear]
LTC3425 - 5A, 8MHz, 4-Phase Synchronous Step-Up DC/DC Converter; Package: QFN; Pins: 32; Temperature Range: -40°C to 85°C;型号: | LTC3425EUH#TR |
厂家: | Linear |
描述: | LTC3425 - 5A, 8MHz, 4-Phase Synchronous Step-Up DC/DC Converter; Package: QFN; Pins: 32; Temperature Range: -40°C to 85°C 开关 |
文件: | 总24页 (文件大小:305K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC3425
5A, 8MHz, 4-Phase
Synchronous Step-Up
DC/DC Converter
U
FEATURES
DESCRIPTIO
■
High Efficiency: Up to 95%
The LTC®3425 is a synchronous, 4-phase boost converter
with output disconnect capable of operation below 1V
input. It includes four N-channel MOSFET switches and
four P-channel synchronous rectifiers for an effective
RDS(ON) of 0.045Ω and 0.05Ω, respectively. 4-phase
operation greatly reduces peak inductor currents, and
capacitor ripple current, and increases effective switching
frequency, minimizing inductor and capacitor sizes. True
output disconnect eliminates inrush current and allows
zero load current in shutdown. External Schottky diodes
arenotrequiredinmostapplications(VOUT <4.3V).Power
saving Burst Mode operation can be user controlled or left
in automatic mode.
■
Up to 3A Continuous Output Current
■
4-Phase Operation for Low Output Ripple
and Tiny Solution Size
■
Output Disconnect and Inrush Current Limiting
■
Very Low Quiescent Current: 12µA
0.5V to 4.5V Input Range
■
■
2.4V to 5.25V Adjustable Output Voltage
■
Adjustable Current Limit
■
Adjustable, Fixed Frequency Operation from
100kHz to 2MHz per Phase
■
Synchronizable Oscillator with Sync Output
■
Internal Synchronous Rectifiers
Manual or Automatic Burst Mode® Operation
■
Other features include 1µA shutdown current, program-
mable frequency with sync in and out, programmable
soft-start, antiringing control, thermal shutdown, adjust-
able current limit, reference output and power good
comparator.
■
Power Good Comparator
■
<1µA Shutdown Current
■
Antiringing Control
■
5mm × 5mm Thermally Enhanced QFN Package
U
APPLICATIO S
The LTC3425 is available in a small, thermally enhanced
32-pin QFN package.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode is a registered trademark of Linear Technology Corporation.
■
Handheld Computers
■
Point-of-Load Regulators
■
3.3V to 5V Conversion
U
TYPICAL APPLICATIO
V
IN
2V TO 3V
2.2µF
2.7µH 2.7µH 2.7µH 2.7µH
100
90
V
SWA
SWB
LTC3425
GNDB
SWC
SWD
IN
V
V
V
V
V
OUTS
OUTA
OUTB
OUTC
SHDN
OFF ON
80
Burst Mode FIXED
REFOUT
CCM
OPERATION FREQUENCY
MODE
70
60
50
40
30
20
10
0
V
3.3V
2A
OUT
OUTD
4.7µF
×4
REFEN
SYNCIN
BURST
1M
10k
22pF
FB
COMP
SS
SYNCOUT
PGOOD
V
V
= 2.4V
IN
OUT
0.01µF
R
T
590k
330pF
= 3.3V
f = 1MHz/PHASE
I
LIM
SGND
15k
75k
L = 2.7µH
33k
GNDA
GNDC GNDD
0.1
1
10
100
1000
10000
0.01µF
20k
LOAD CURRENT (mA)
3425 TA01
3425 TA02
C
C
: TAIYO YUDEN JMK107BJ225MA
OUT
L1-L4: TDK RLF5018T-2R7M1R8
IN
: TAIYO YUDEN JMK212BJ475MG (×4)
3425f
1
LTC3425
W W
U W
U
W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
TOP VIEW
VIN Voltage ................................................. –0.3V to 6V
SWA-D Voltages ..........................................–0.3V to 6V
V
OUTA-D, VOUTS Voltages............................ –0.3V to 6V
32 31 30 29 28 27 26 25
BURST, SHDN, SS, REFEN, SYNCOUT, PGOOD,
REFOUT, CCM, SYNCIN Voltages ............... –0.3V to 6V
Operating Ambient Temperature Range
(Note 5) .............................................. –40°C to 85°C
Storage Temperature Range ................. –65°C to 125°C
Lead Temperature (Soldering, 10 sec).................. 300°C
GNDA
GNDA
SWA
1
2
3
4
5
6
7
8
24 GNDD
23 GNDD
SWD
22
V
OUTA
V
V
21
20
19
OUTD
OUTC
33
V
OUTB
SWB
SWC
GNDB
GNDB
18 GNDC
17 GNDC
9
10 11 12 13 14 15 16
UH PACKAGE
32-LEAD (5mm × 5mm) PLASTIC QFN
TJMAX = 125°C, θJA = 40°C/W 1 LAYER BOARD,
θJA = 35°C/W 4 LAYER BOARD, θJC = 1.1°C/W
EXPOSED PAD IS GND (PIN 33) MUST BE SOLDERED TO PCB
ORDER PART
NUMBER
UH PART
MARKING
3425
LTC3425EUH
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 1.2V, VOUT = 3.3V, RT = 15k, unless otherwise noted.
PARAMETER
CONDITIONS
= 0V, I
MIN
TYP
MAX
1
UNITS
Minimum Start-Up Voltage
Minimum Operating Voltage
Output Voltage Adjust Range
Feedback Regulation Voltage
Feedback Input Current
V
< 1mA
LOAD
0.88
V
V
OUT
(Note 3)
●
●
●
0.5
2.4
5.25
1.244
50
V
1.196
1.220
1
V
nA
V
Quiescent Current—Burst Mode Operation
BURST = 0V, REFEN = 0V, FB = 1.3V (Note 2)
BURST = 0V, REFEN = 2V, FB = 1.3V (Note 2)
12
18
25
35
µA
µA
OUT
V
V
Quiescent Current—Shutdown
SHDN = 0V, V
= 0V, Not Including Switch Leakage
0.1
1.8
1
3
µA
mA
µA
µA
Ω
IN
OUT
Quiescent Current—Active
V = 0V, Nonswitching (Note 2)
C
OUT
NMOS Switch Leakage
PMOS Switch Leakage
NMOS Switch On Resistance
PMOS Switch On Resistance
NMOS Current Limit
V
V
= 5V
0.1
5
SW
SW
= 5V, V
= 0V
0.1
10
OUT
(Note 4)
(Note 4)
0.04
0.05
Ω
I
I
Resistor = 75k (Note 4)
Resistor = 200k (Note 4)
●
●
5.0
1.8
7.0
2.7
A
A
LIM
LIM
3425f
2
LTC3425
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 1.2V, VOUT = 3.3V, RT = 15k, unless otherwise noted.
PARAMETER
CONDITIONS
CCM < 0.4V
CCM > 1.4V
MIN
TYP
–80
0.6
90
MAX
UNITS
mA
A
PMOS Turn-Off Current
PMOS Reverse Current Limit
Max Duty Cycle
●
●
●
83
97
0
%
Min Duty Cycle
%
Frequency Accuracy
SHDN Input High
R = 15k
T
0.8
1
1.2
MHz
V
V
= 0V (Initial Start-Up)
> 2.4V
●
●
1
0.65
V
V
OUT
OUT
SHDN Input Low
●
0.25
1
V
SHDN Input Current
V
V
= 5V or 0V
= 2V
0.01
–0.50
µA
µA
SHDN
SHDN
REFEN, CCM Input High
REFEN, CCM Input Low
REFEN, Input Current
SYNCIN Input High
SYNCIN Input Low
SYNCIN Input Current
CCM Input Current
SYNC Input Pulse Width Range
SYNC Out High
●
●
1.4
2.5
V
V
0.4
1
V
= 5V
0.01
µA
V
REFEN
(Note 7)
(Note 7)
●
●
0.5
1
V
V
V
= 5V
0.3
2
µA
µA
µs
V
SYNCIN
= 5V
4
CCM
●
0.1
3
SYNC Out Low
0.4
V
REFOUT
REFEN > 1.4V, No Load
●
●
1.190
1.184
1.220
1.220
50
1.251
1.252
V
I
< 100µA, I
< 10µA
V
SOURCE
SINK
Error Amp Transconductance
Error Amp Output High
Error Amp Output Low
PGOOD Threshold (Falling Edge)
PGOOD Hysteresis
µS
V
I
Resistor = 75k
2.2
LIM
0.15
–11.4
2.5
V
Referenced to Feedback Voltage
Referenced to Feedback Voltage
●
●
●
●
–9.5
1.5
–13.5
4
%
%
V
PGOOD Low Voltage
I
= 1mA (10mA Max)
0.12
0.01
2.7
0.25
1
SINK
PGOOD Leakage
V
V
= 5.5V
µA
µA
V
PGOOD
SS Current Source
= 1V
SS
Burst Threshold Voltage
Burst Threshold Hysteresis
Falling Edge
●
0.84
0.94
120
1.04
mV
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 5: The LTC3425E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 6: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 2: Current is measured into the V
pin since the supply current is
OUTS
bootstrapped to the output. The current will reflect to the input supply by
/(V • Efficiency). The outputs are not switching.
V
OUT IN
Note 3: Once the output is started, the IC is not dependent on the V
IN
supply.
Note 4: Total with all four FETs in parallel.
Note 7: The typical logic threshold for this input is: V /2
OUT
3425f
3
LTC3425
U W
TYPICAL PERFOR A CE CHARACTERISTICS
SW Pin and Inductor Current in
Discontinous Mode. Antiring
Circuit Eliminates High Frequency
Ringing
SWA, SWB, SWC, SWD
at 1MHz/Phase
SW Pin and Oscillator SYNCOUT
IL
SWA
2V/DIV
0.2A/DIV
SWA TO SWD
5V/DIV
SYNCOUT
2V/DIV
SW
2V/DIV
250ns/DIV
3425 G01
250ns/DIV
3425 G02
VIN = 2.4V
VOUT = 3.3V
COUT = 220µF
250ns/DIV
3425 G03
Output Voltage Ripple at 2.5A
Output Voltage Ripple at 2.5A
Load with Only Four 4.7µF
Ceramic Capacitors
Load with a 47µF Ceramic Bulk
Transient Response 0.5A to 1.5A
Fixed Frequency Mode Operation
Capacitor
VOUT AC
100mV/DIV
V
OUT AC
VOUT AC
10mV/DIV
50mV/DIV
LOAD
CURRENT
0.5A/DIV
V
IN = 2.4V
VOUT = 3.3V
OUT = 220µF
100µs/DIV
3425 G04
VIN = 2.4V
500ns/DIV
3425 G05
VIN = 2.4V
500ns/DIV
3425 G06
VOUT = 3.3V
VOUT = 3.3V
C
FREQUENCY = 1MHz/PHASE
FREQUENCY = 1MHz/PHASE
Soft-Start and Inrush Current
Limiting
Transient Response 10mA to 1A
Automatic Burst Mode Operation
Burst Mode Operation
IOUT
IIN
1A/DIV
0.5A/DIV
SWA
2V/DIV
SS Pin
1V/DIV
BURST PIN
1V/DIV
V
OUT AC
VOUT
2V/DIV
50mV/DIV
VOUT AC
200mV/DIV
VIN = 2.4V
500µs/DIV
3425 G07
VIN = 2.4V
VOUT = 3.3V
COUT = 220µF
25µs/DIV
3425 G08
VIN = 2.4V
1ms/DIV
3425 G10
VOUT = 3.3V
VOUT = 3.3V
CSOFTSTART = 0.015µF
C
OUT = 220µF
3425f
4
LTC3425
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Converter Efficiency for 2-, 3- and
4-Phase Operation
Converter Efficiency
for VOUT = 3.3V
Converter Efficiency
for VOUT = 5V
100
90
80
70
60
50
40
30
20
10
0
98
96
100
90
80
70
60
50
40
30
20
10
0
T
V
V
= 25°C
A
V
= 3.3V
V
V
= 2.4V
IN
IN
= 2.4V
IN
= 3.3V
OUT
= 2.4V
= 3.3V
94 1MHz/PHASE
IN
V
= 1.2V
IN
92
90
88
86
84
82
V
= 2.4V
V
V
= 2.4V
IN
IN
IN
V
= 1.2V
IN
4 PHASE
3 PHASE
2 PHASE
Burst Mode OPERATION
1MHz/PHASE
Burst Mode OPERATION
1MHz/PHASE
T
= 25°C
T
= 25°C
A
A
80
100
1000
10000
0.1
1
10
100
1000 10000
0.1
1
10
100
1000 10000
LOAD (mA)
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
3425 G13
3425 G11
3425 G12
Efficiency Comparison of
Efficiency Comparison of
Discontinuous Mode and Forced
Continuous Mode at Light Loads
for VIN = 2.4V, VOUT = 3.3V
Discontinuous Mode and Forced
Continuous Mode at Light Loads
for VIN = 3.3V, VOUT = 5V
Converter No Load Input Current
vs VIN (Burst Mode Operation)
100
90
100
140
120
100
80
T
= 25°C
T = 25°C
A
T
= 25°C
A
A
1MHz/PHASE
1MHz/PHASE
90
80
70
DISCONTINUOUS
MODE
80
DISCONTINUOUS
MODE
70
FORCED
CONTINUOUS
MODE
V
OUT
= 5V
60
50
60
50
FORCED
CONTINUOUS
MODE
60
40
30
20
10
0
40
30
20
10
0
V
OUT
= 3.3V
40
20
0
1
10
100
1000
1
10
100
1000
1.5
3.0
3.5
4.0
4.5
2.0
2.5
V
CONVERTER OUTPUT CURRENT (mA)
LOAD (mA)
(V)
IN
3425 G14
3425 G15
3425 G16
Oscillator Frequency
Peak Current Limit
Effective RDS(ON)
10
1.8
1.6
1.4
1.2
0.065
0.060
0.055
0.050
0.045
0.040
T
= 25°C
T
= 25°C
T
= 25°C
A
A
A
PMOS
NMOS
1.0
0.8
0.6
1
1
10
100
140
RESISTOR (kΩ)
180 200
60
80 100 120
160
2.5
3
3.5
V
4
4.5
5
R
T
(kΩ)
I
(V)
LIM
OUT
3425 G17
3425 G18
3425 G19
3425f
5
LTC3425
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Maximum Output Current
in Burst Mode Operation
Maximum Start-Up Load vs VIN
(Constant Current Load)
Automatic Burst Mode Current
Thresholds vs RBURST
100
10
1
350
300
0.7
0.6
T
= 25°C
T
= 25°C
T = 25°C
A
A
A
LEAVE
Burst Mode
OPERATION
V
OUT
= 3.3V
V
OUT
= 3.3V
0.5
0.4
0.3
0.2
0.1
250
V
= 5V
OUT
ENTER
Burst Mode
OPERATION
200
150
100
50
V
OUT
= 5V
0
0
1.3
(V)
1.5 1.6
10
100
BURST RESISTOR (kΩ)
1000
0.9 1.0
1.1 1.2
V
1.4
2
2.5
3
3.5
5
1
1.5
4
4.5
V
IN
(V)
IN
3425 G22
3425 G21
3425 G20
Automatic Burst Mode Thresholds
vs VIN
Soft-Start Charging Current
vs Temperature
Shutdown Voltage vs Temperature
3.0
2.5
2.0
1.5
1.0
0.5
0
100
90
80
70
60
50
40
0.450
0.425
0.400
0.375
0.350
0.325
0.300
V
= 5V
OUT
V
> 2.3V
IN
V
= 3.3V
OUT
LEAVE Burst Mode OPERATION
ENTER Burst Mode OPERATION
V
< 2.3V
IN
(START-UP MODE)
V
= 3.3V
V
OUT
T
= 25°C
BURST
= 5V
A
OUT
R
= 33k
–45
–5 15 35 55 75 95 115
–25
1.5
2
2.5
3
3.5
4
–45
–5 15 35 55 75 95 115
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
V
(V)
IN
3425 G24
3425 G23
3425 G25
Minimum Start-Up Voltage
vs Temperature
PMOS Reverse Current in Forced
CCM vs Temperature
PGOOD Threshold vs Temperature
11.8
11.7
11.6
11.5
11.4
11.3
11.2
11.1
11.0
10.9
10.8
800
750
700
650
600
550
500
450
400
350
300
1.00
0.95
0.90
0.85
0.80
0.75
0.70
–45
–5 15 35 55 75 95 115
–45
–5 15 35 55 75 95 115
–25
–25
–45
–5 15 35 55 75 95 115
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3425 G27
3425 G28
3425 G26
3425f
6
LTC3425
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Peak Current Limit
vs Temperature
Oscillator Frequency
vs Temperature
Feedback Voltage vs Temperature
1.230
1.225
1.220
1.215
1.210
1.205
1.200
3
2
2.0
1.5
1.0
1
0.5
0
0
–0.5
–1.0
–1.5
–2.0
–1
–2
–3
–45
–5 15 35 55 75 95 115
–45
–5 15 35 55 75 95 115
–45
–5 15 35 55 75 95 115
–25
–25
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3425 G29
3425 G30
3425 G31
Burst Mode VOUT Quiescent
Current vs Temperature
Error Amplifier gm
vs Temperature
20
15
10
5
55
50
45
40
–45
–5 15 35 55 75 95 115
–45
–5 15 35 55 75 95 115
–25
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
3425 G32
3425 G33
3425f
7
LTC3425
U
U
U
PI FU CTIO S
GNDA–D (Pins 1, 2, 7, 8, 17, 18, 23, 24): Power Ground
for the IC and the Four Internal N-channel MOSFETs.
Connect directly to the power ground plane.
COMP (Pin 13): Error Amp Output. A frequency compen-
sation network is connected from this pin to ground to
compensate the loop. See the section Closing the Feed-
back Loop for guidelines.
SWA–D (Pins 3, 6, 19, 22): Switch Pins. Connect induc-
tors here. Minimize trace length to keep EMI to a mini-
mum. For discontinuous inductor current, a controlled
impedance is internally connected from SW to VIN to
minimize EMI. For applications where VOUT > 4.3V, it is
required to have Schottky diodes from SW to VOUT or a
snubbercircuittostaywithinabsolutemaximumratingon
the SW pins.
BURST (Pin 14): Burst Mode Threshold Adjust Pin. A
resistor/capacitor combination from this pin to ground
programs the average load current at which automatic
Burst Mode operation is entered.
For manual control of Burst Mode operation, ground
BURSTtoforceBurstModeoperationorconnectittoVOUT
to force fixed frequency PWM mode. Note that BURST
must not be pulled higher than VOUT
.
V
OUTA–D (Pins 4, 5, 20, 21): Output of the Four Synchro-
nous Rectifiers. Connect output filter capacitors to these
pins. Connect one low ESR ceramic capacitor directly
from each pin to the ground plane.
REFOUT (Pin 15): Buffered 1.22V Reference Output. This
pin can source up to 100µA and sink up to 10µA (only
active when REFEN is pulled high). This pin must be
decoupled with a 0.1µF capacitor for stability.
REFEN (Pin 9): Pull this pin above 1.4V to enable the REF
output. Grounding this pin turns the REF output off to
reduce quiescent current.
PGOOD (Pin 16): Open-Drain Output of the Power Good
Comparator. This pin will go low when the output voltage
drops 11% below its regulated value. Maximum sink
current should be limited to 10mA.
VOUTS (Pin10):VOUT SensePin. ConnectVOUTS directlyto
an output filter capacitor. The top of the feedback divider
network should also be tied to this point.
SYNCOUT (Pin 25): Sync Output Pin. A clock is provided
at the oscillator frequency, but phase-shifted 180 degrees
to allow for synchronizing two devices for an 8-phase
converter.
SGND (Pin 11): Signal Ground Pin. Connect to ground
plane, near the feedback divider resistor.
FB(Pin12):FeedbackPin.ConnectFBtoaresistordivider,
keeping the trace as short as possible. The output voltage
can be adjusted according to the following formula:
CCM (Pin 26):This pin is used to select forced continuous
conduction mode. Normally this pin is grounded to allow
CCM or DCM operation. To force continuous conduction
mode, tie this pin to VOUT. In this mode, a reverse current
of up to about 0.6A will be allowed before turning off the
synchronous rectifier. This will prevent pulse skipping at
light load when Burst Mode operation is disabled, and will
also improve the large-signal transient response when
going from a heavy load to a light load. For Burst Mode
operation, CCM should be low.
R1+R2
VOUT = 1.22 •
R1
where R1 is connected from FB to SGND and R2 is
connected from FB to VOUTS
.
3425f
8
LTC3425
U
U
U
PI FU CTIO S
ILIM (Pin 27): Current Limit Adjust Pin. Connect a resistor
from ILIM to SGND to set the peak current limit threshold
for the N-channel MOSFETs, according to the formula
(note that this is the peak current in each inductor):
SYNCIN (Pin 30): Oscillator Synchronization Pin. A clock
pulse width of 100ns minimum is required to synchronize
the internal oscillator. If not used, SYNCIN should be
grounded. The typical logic threshold for this input is:
130
R
VOUT
2
ILIM
=
The SYNCIN is ignored in Burst Mode operation.
where I is in Amps and R is in kΩ. Do not use values less
than 75k.
SHDN (Pin 31): Shutdown Pin. Grounding SHDN (or
pulling it below 0.25V) shuts down the IC. Pull pin up to
≥1V to enable. Once enabled, the pin only needs to be
≥0.65V.
RT (Pin28):ConnectaresistorfromRT toSGND(orSGND
plane) to program the oscillator frequency, according to
the formula:
SS (Pin 32): Soft-Start pin. Connect a capacitor from this
pin to ground to set the soft-start time, according to the
formula:
60
RT
fOSC
=
fOSC 15
fSWITCH
=
=
t(ms) = CSS (µF) • 320
4
RT
The nominal soft-start charging current is 2.5µA. The
activerangeofSSisfrom0.8Vto1.6V. Notethatthisisthe
rise time of SS. The actual rise time of VOUT will be a
function of load and output capacitance.
where fOSC is in MHz and RT is in kΩ.
VIN (Pin 29): Input Supply Pin. Connect this to the input
supply and decouple with 1µF minimum low ESR
ceramic capacitor.
Exposed Pad (Pin 33): Additional Power Ground for the
IC. Connect directly to the power ground plane.
OPERATING MODE
BURST PIN
CCM PIN
Low
Automatic Burst (Operating Mode is Load Dependent)
Forced Burst
RC Network to Ground
Low
High
High
Low
Forced Fixed Frequency with Pulse Skipping at Light Load
Forced Fixed Frequency, Low Noise (No Pulse Skipping)
Low
High
3425f
9
LTC3425
W
BLOCK DIAGRA
1V TO 4.5V
+
29
3
6
19
22
V
IN
SWA
SWB SWC
SWD
1 OF 4
V
OUT
V
V
OUTA
4
2.5V TO 5.25V
+
OUTB
FB
5
ANTIRING
V
OUTC
20
21
–
PMOS
P
0.8V
ENABLE
V
OUTD
+
–
PWM LOGIC
AND
DRIVERS
MODE CONTROL
CCM
N
26
I/2000
ZERO
DIVIDER
4-PHASE
GEN
V
10
16
OUTS
+
+
4
4
CLK
SLOPE
Σ
+
+
R
T
PGOOD
IOSC
+
–
Σ
1.086/
1.116
+
–
–
OSC
28
SYNCIN
30
25
SYNC
4
4
4
1.22V
+
+
–
MODE
SLEEP
FB
Burst Mode
CONTROL
0.94V
12
13
–
ERROR
AMP
BURST
COMP
SYNCOUT
COMP
THERMAL SHDN
SHDN
–
+
SHUTDOWN
31
9
OFF ON
V
REF
–3%
UV
REFEN
OFF ON REFOUT
V
REF
1.22V
+
–
+
–
REFOUT
15
START-UP,
SOFT-START
AND
I
LIMIT
I
3%
OV
THERMAL REG
BURST
14
SS
32
GNDA
GNDB
GNDC
17 18
GNDD
SGND
11
LIM
1
2
7
8
23 24
33
27
3425f
10
LTC3425
U
OPERATIO
5
4
3
2
1
0
DETAILED DESCRIPTION
SINGLE
PHASE
The LTC3425 provides high efficiency, low noise power
forhighcurrentboostapplicationssuchascellularphones
and PDAs. The true output disconnect feature eliminates
inrush current and allows VOUT to go to zero during
shutdown. The current mode architecture with adaptive
slope compensation provides ease of loop compensation
FOUR PHASE
with excellent transient load response. The low RDS(ON)
,
low gate charge synchronous switches eliminate the need
foranexternalSchottkyrectifier,andprovideefficienthigh
frequency pulse width modulation (PWM) control. High
efficiency is achieved at light loads when Burst Mode
operation is entered, where the IC’s quiescent current is a
1
1.5
0
0.5
TIME (µs)
3425 F01
Figure 1. Comparison of Output Ripple Current with Single
Phase and 4-Phase Boost Converter in a 2A Load Application
Operating at 50% Duty Cycle
low 12µA typical on VOUT
.
MULTIPHASE OPERATION
Example:
The LTC3425 uses a 4-phase architecture, rather than the
conventional single phase of other boost converters. By
having multiple phases equally spaced (90° apart), not
only is the output ripple frequency increased by a factor of
four, but the output capacitor ripple current is greatly
reduced. Although this architecture requires four induc-
tors, rather than a single inductor, there are a number of
important advantages.
The following example, operating at 50% duty cycle,
illustrates the advantages of multiphase operation over a
conventional single-phase design.
VIN = 1.9V, VOUT = 3.6V, Efficiency = 90% (approx),
IOUT = 2A, Frequency = 1MHz, L = 2.2µH
Table 1
SINGLE
PHASE
FOUR
PHASE
CHANGE FROM
1 TO 4 PHASE
PARAMETER
• Much lower peak inductor current allows the use of
smaller, lower cost inductors.
Peak-Peak Output
Ripple Current
4.227A
0.450A
Reduced by 89%
RMS Output Ripple Current
Peak Inductor Current
2.00A
4.227A
1MHz
0.184A
1.227A
4MHz
Reduced by 91%
Reduced by 71%
Increased by 4×
• Greatly reduced output ripple current minimizes output
capacitance requirement.
Output Ripple Frequency
• Higher frequency output ripple is easier to filter for low
noise applications.
With 4-phase operation, at least one of the phases will be
delivering current to the load whenever VIN is greater than
one quarter VOUT (duty cycles less than 75%). For lower
duty cycles, there can be as many as two or three phases
delivering load current simultaneously. This greatly re-
duces both the output ripple current and the peak current
ineachinductor, comparedwithasingle-phaseconverter.
This is illustrated in the waveforms of Figures 2 and 3.
• Input ripple current is also reduced for lower noise on
VIN.
The peak boost inductor current is given by:
IO
di
2
ILPEAK
=
+
(1–D)•N
Where IO is the average load current, D is the PWM duty
cycle, N is the number of phases and di is the inductor
ripple current. This relationship is shown graphically in
Figure 1 using a single phase and a 4-phase example.
Operation Using Only Two or Three Phases
The LTC3425 can operate as a 2- or 3-phase converter by
simplyeliminatingtheinductorfromtheunusedphase(s).
3425f
11
LTC3425
U
OPERATIO
SWITCH A
VOLTAGE
SWITCH B
VOLTAGE
SWITCH C
VOLTAGE
SWITCH D
VOLTAGE
INDUCTOR A
CURRENT
INDUCTOR B
CURRENT
INDUCTOR C
CURRENT
INDUCTOR D
CURRENT
INPUT CURRENT
RECTIFIER A
CURRENT
RECTIFIER B
CURRENT
RECTIFIER C
CURRENT
RECTIFIER D
CURRENT
OUTPUT RIPPLE
CURRENT
3425 F02
Figure 2. Simplified Voltage and Current Waveforms
for 4-Phase Operation at 50% Duty Cycle
This approach can be used to reduce solution cost and
board area in applications not requiring the full power
capability of the LTC3425, or where peak efficiency may
not be as important as cost and size. In this case, phase A
should always be used, since this is the only phase active
in Burst Mode operation and phase C is recommended as
the second phase for the lowest output ripple, since it is
180° out of phase with phase A. Figure 4 illustrates the
efficiency differences with two, three and four phases in a
typical 2-cell to 3.3V boost application. In this example,
you can see that for maximum loads less than 1A, the
efficiency penalty for using only two or three phases is
fairly small. Keep in mind, however, that this penalty will
grow larger as the input voltage drops. Output ripple will
also increase with each phase that is eliminated.
Low Voltage Start-Up
The LTC3425 includes an independent start-up oscillator
designedtostartupatinputvoltagesaslowas0.88V. The
frequency and peak current limit during start-up are
3425f
12
LTC3425
U
OPERATIO
SWITCH A
VOLTAGE
SWITCH B
VOLTAGE
SWITCH C
VOLTAGE
SWITCH D
VOLTAGE
INDUCTOR A
CURRENT
INDUCTOR B
CURRENT
INDUCTOR C
CURRENT
INDUCTOR D
CURRENT
INPUT CURRENT
RECTIFIER A
CURRENT
RECTIFIER B
CURRENT
RECTIFIER C
CURRENT
RECTIFIER D
CURRENT
OUTPUT RIPPLE
CURRENT
3432 F03
Figure 3. Simplified Voltage and Current Waveforms
for 4-Phase Operation at 75% Duty Cycle
internally controlled. The device can start up under some
load (see the graph Start-Up Current vs Input Voltage).
Soft-start and inrush current limiting is provided during
start-up as well as normal mode. The same soft-start
capacitor is used for each operating mode.
input by 0.3V, the IC powers itself from VOUT instead of
VIN. At this point the internal circuitry has no dependency
on the VIN input voltage, eliminating the requirement for a
large input capacitor. The input voltage can drop as low as
0.5Vwithoutaffectingcircuitoperation.Thelimitingfactor
fortheapplicationbecomestheabilityofthepowersource
to supply sufficient energy to the output at the low volt-
ages, andthemaximumdutycyclethatisclampedat90%.
During start-up, all four phases switch in unison. When
either VIN or VOUT exceeds 2.3V, the IC enters normal
operating mode. Once the output voltage exceeds the
3425f
13
LTC3425
U
OPERATIO
98
T
V
V
= 25°C
A
IN
OUT
60
RT
= 2.4V
fOSC
=
96
= 3.3V
94 1MHz/PHASE
fOSC 15
92
90
88
86
84
82
fSWITCH
=
=
4
RT
4 PHASE
3 PHASE
where fOSC is in MHz and RT is in kΩ.
2 PHASE
The oscillator can be synchronized with an external clock
appliedtoSYNCIN. Whensynchronizingtheoscillator, the
free running frequency must be set to an approximately
30% lower frequency than the desired synchronized fre-
quency. SYNCOUT is provided for synchronizing two or
more devices. The output sync pulse is 180° out of phase
from the internal oscillator, allowing two devices to be
synchronized to create an 8-phase converter. Note that in
Burst Mode operation, the oscillator is turned off and
SYNCOUT is driven low.
80
100
1000
LOAD (mA)
10000
3425 G13
Figure 4. LTC3425 Efficiency vs
Load for 2-, 3- and 4-Phase Operation
Low Noise Fixed Frequency Operation
Shutdown: The part is shut down by pulling SHDN below
0.25V and made active by pulling the pin above 1V. Note
that SHDN can be driven above VIN or VOUT, as long as it
is limited to less than 5.5V.
Infixedfrequencyoperation, theminimumon-timebefore
pulse skipping occurs (at light load) is typically 110ns.
Current Sensing: Lossless current sensing converts the
peak current signal to a voltage to sum in with the internal
slope compensation. This summed signal is compared to
theerroramplifieroutputtoprovideapeakcurrentcontrol
command for the PWM. The internal slope-compensation
is adaptive to the input and output voltage, therefore the
converterprovidestheproperamountofslopecompensa-
tion to ensure stability, but not an excess to cause a loss
of phase margin in the converter.
Soft-Start: The soft-start time is programmed with an
external capacitor to ground on SS. An internal current
sourcechargesitwithanominal2.5µA(1µAwhileinstart-
up mode when VIN and VOUT are both below 2.3V). The
voltage on the soft-start pin (in conjunction with the
externalresistorontheILIM pin)isusedtocontrolthepeak
current limit until the voltage on the capacitor exceeds
1.6V, at which point the external resistor sets the peak
current. In the event of a commanded shutdown or a
thermal shutdown, the capacitor is discharged automati-
cally. Note that Burst Mode operation is inhibited during
the soft-start time.
Error Amp: The error amplifier is a transconductance
amplifier with its positive input internally connected to the
1.22V reference and its negative input connected to FB. A
simple compensation network is placed from COMP to
ground. Internal clamps limit the minimum and maximum
error amp output voltage for improved large-signal tran-
sient response. During Burst Mode operation, the com-
pensationpinishighimpedance,howeverclampslimitthe
voltageontheexternalcompensationnetwork,preventing
the compensation capacitor from discharging to zero.
t(ms) = CSS(µF) • 320
Oscillator: The frequency of operation is set through a re-
sistor from the RT pin to ground. An internally trimmed
timing capacitor resides inside the IC. The internal
oscillator frequency is then divided by four to generate the
four phases, each phase shifted by 90°. The oscillator fre-
quencyandresultingswitchingfrequencyofeachofthefour
phases are calculated using the following formula:
3425f
14
LTC3425
U
OPERATIO
CurrentLimit:Theprogrammablecurrentlimitcircuitsets
the maximum peak current in the NMOS switches. The
current limit level is programmed using a resistor to
ground on the ILIM pin. Do not use values below 75k. In
Burst Mode operation, the current limit is automatically
set to a nominal value of 0.6A peak for optimal efficiency.
the soft-start capacitor will be reset. The part will be
enabled again when the die temperature has dropped
about10°C. Note:Overtemperatureprotectionisintended
to protect the device during momentary overload condi-
tions. Continuous operation above the specified maxi-
mum operating junction temperature may result in device
degradation or failure.
130
ILIM
=
per Phase
Burst Mode Operation
R
BurstModeoperationcanbeautomaticorusercontrolled.
In automatic operation, the IC will automatically enter
Burst Mode operation at light load and return to fixed
frequency PWM mode for heavier loads. The user can
program the average load current at which the mode
transition occurs using a single resistor.
where I is in Amps and R is in kΩ.
Synchronous Rectifier and Zero Current Amp: To pre-
vent the inductor current from running away, the PMOS
synchronous rectifier is only enabled when VOUT > (VIN +
0.3V)andFBis>0.8V.Thezerocurrentamplifiermonitors
the inductor current to the output and shuts off the
synchronous rectifier once the current is below 50mA
typical, preventing negative inductor current. If CCM is
tied high, the amplifier will allow up to 0.6A of negative
current in the synchronous rectifier.
During Burst Mode operation, only Phase A is active and
the other three phases are turned off, reducing quiescent
current and switching losses by 75%. Note that the
oscillator is also shut down in this mode, since the on time
is determined by the time it takes the inductor current to
reach a fixed peak current, and the off time is determined
by the time it takes for the inductor current to return to
zero.
Antiringing Control: The antiringing control connects a
resistor across the inductor to damp the ringing on SW in
discontinuous conduction mode. The LCSW ringing (L =
inductor, CSW = Capacitance on Switch pin) is low energy,
but can cause EMI radiation.
In Burst Mode operation, the IC delivers energy to the
output until it is regulated and then goes into a sleep mode
where the outputs are off and the IC is consuming only
12µA of quiescent current. In this mode, the output ripple
has a variable frequency component with load current and
will be typically 2% peak-peak. This maximizes efficiency
at very light loads by minimizing switching and quiescent
losses. Burst Mode ripple can be reduced slightly by using
more output capacitance (47µF or greater). This capacitor
doesnotneedtobealowESRtypeiflowESRceramicsare
also used. Another method of reducing Burst Mode ripple
is to place a small feedforward capacitor across the upper
resistor in the VOUT feedback divider network.
Power Good: An internal comparator monitors the FB
voltage. If FB drops 11.4% below the regulation value,
PGOOD will pull low (sink current should be limited to
10mA max). The output will stay low until the FB voltage
is within 9.5% of the regulation voltage. A filter prevents
noise spikes from causing nuisance trips.
Reference Output: The internal 1.22V reference is buff-
ered and brought out to REFOUT. It is active when REFEN
is pulled high (above 1.4V). For stability, a minimum of
0.1µF capacitor must be placed on REFOUT. The output
cansourceupto100µAandsinkupto10µA.Forthelowest
possible quiescent current in Burst Mode operation, the
referenceoutputshouldbedisabledbygrounding REFEN.
During Burst Mode operation, COMP is disconnected
from the error amplifier in an effort to hold the voltage on
the external compensation network where it was before
entering Burst Mode operation. To minimize the effects of
leakage current and stray resistance, voltage clamps limit
the min and max voltage on COMP during Burst Mode
Thermal Shutdown: An internal temperature monitor will
start to reduce the programmed peak current limit if the
die temperature exceeds 135°C. If the die temperature
continues to rise and reaches 150°C, the part will go into
thermal shutdown and all switches will be turned off and
operation. This minimizes the transient experienced when
3425f
15
LTC3425
U
OPERATIO
a heavy load is suddenly applied to the converter after
being in Burst Mode operation for an extended period of
time.
to sink up to 2mA. Note that Burst Mode operation is
inhibited during start-up and soft-start.
Note that if VIN is raised to within 200mV or less below
VOUT, the part will exit Burst Mode operation and the
For automatic operation, an RC network should be con-
nected from BURST to ground. The value of the resistor
will control the average load current (IBURST) at which
Burst Mode operation will be entered and exited (there is
hysteresis to prevent oscillation between modes). The
equation given for the capacitor on BURST is for the
minimum value, to prevent ripple on BURST from causing
the part to oscillate in and out of Burst Mode operation at
the current where the mode transition occurs.
synchronous rectifier will be disabled. It will remain in
fixed frequency mode until VIN is at least 300mV below
VOUT
.
If the load applied during forced Burst Mode operation
(BURST = GND) exceeds the current that can be supplied,
the output voltage will start to droop and the part will
automaticallycomeoutofBurstModeoperationandenter
fixed frequency mode, raising VOUT. The part will then
enter Burst Mode operation once again, the cycle will
repeat, resulting in about 4% output ripple. The maximum
current that can be supplied in Burst Mode operation is
given by:
2.75
RBURST
1.7
IBURST
IBURST
=
=
to leave Burst Mode operation
to enter Burst Mode operation
RBURST
0.60
IO(MAX)
=
in Amps
where RBURST is in kΩ and IBURST is in Amps. For load
VOUT – V
IN
currents under 20mA, refer to the curve Automatic Burst
2 • 1+
V
IN
Mode Thresholds vs RBURST
.
COUT • VOUT
Output Disconnect and Inrush Limiting
CBURST
=
10,000
The LTC3425 is designed to allow true output disconnect
by eliminating body diode conduction of the internal
PMOS rectifiers. This allows VOUT to go to zero volts
during shutdown, drawing no current from the input
source.Italsoallowsforinrushcurrentlimitingatturn-on,
minimizing surge currents seen by the input supply. Note
that to obtain the advantages of output disconnect, there
cannot be any external Schottky diodes connected be-
where CBURST(MIN) and COUT are in µF.
When the voltage on BURST drops below 0.94V, the part
will enter Burst Mode operation. When the BURST pin
voltage is above 1.06V, it will be in fixed frequency mode.
In the event that a sudden load transient causes the
feedbackpintodropbymorethan4%fromtheregulation
value, an internal pull-up is applied to BURST, forcing the
part quickly out of Burst Mode operation. For optimum
transient response when going between Burst Mode
operationandPWMmode,themodeshouldbecontrolled
manually by the host. This way PWM mode can be
commanded before the load step occurs, minimizing
output voltage droop. For manual control of Burst Mode
operation, the RC network can be eliminated. To force
fixedfrequencyPWMmode, BURSTshouldbeconnected
toVOUT.ToforceBurstModeoperation,BURSTshouldbe
grounded.ThecircuitconnectedtoBURSTshouldbeable
tween the switch pins and VOUT
.
Note: Board layout is extremely critical to minimize
voltage overshoot on the switch pins due to stray induc-
tance. Keep the output filter capacitors as close as
possible to the VOUT pins, and use very low ESR/ESL
ceramic capacitors tied to a good ground plane.
ForapplicationswithVOUT over4.3V,Schottkydiodesare
required to limit the peak switch voltage to less than 6V.
These must also be very close to minimize stray induc-
tance. See the section Applications Where VOUT > 4.3V.
3425f
16
LTC3425
W U U
APPLICATIO S I FOR ATIO
U
The inductor current ripple is typically set to 20% to 40%
of the maximum inductor current.
R
T
C
IN
L1
C
SS
L4
For high efficiency, choose an inductor with high fre-
quency core material, such as ferrite to reduce core loses.
The inductor should have low ESR (equivalent series
resistance) to reduce the I2R losses, and must be able to
handle the peak inductor current without saturating. To
minimize radiated noise, use a shielded inductor. (Note
that the inductance of shielded types will drop more as
current increases, and will saturate more easily). See
Table 2 for a list of inductor manufacturers.
C
C
C
C
OUT
OUT
OUT
OUT
LTC3425
L2
L3
Table 2. Inductor Vendor Information
3425 F05
SUPPLIER PHONE
FAX
WEB SITE
Coilcraft
Murata
(847) 639-6400
(847) 639-1469
www.coilcraft.com
www.murata.com
Figure 5. Typical Board Layout
USA:
(814) 237-1431
USA:
(814) 238-0490
Sumida
USA:
USA:
www.japanlink.com/
sumida
LTC3425
(847) 956-0666
Japan:
(847) 956-0702
Japan:
81-3-3607-5111 81-3-3607-5144
3425 F06
TDK
(847) 803-6100
(847) 803-6296
www.component.
tdk.com
Figure 6. Example Board Layout for a 10W, 4-Phase Boost
Converter. Total Area = 0.50in2 (with All Components Mounted
on the Topside of Board)
Some example inductor part types are:
Coilcraft DO-1608, DS-1608 and DT-1608 series
Murata LQH3C, LQH4C, LQH32C and LQN6C series
COMPONENT SELECTION
Inductor Selection
Sumida CDRH3D16, CDRH4D18, CDRH4D28, CR32,
CR43 series
The high frequency, multiphase operation of the LTC3425
allows the use of small surface mount inductors. The
minimum inductance value is proportional to the operat-
ing frequency and is limited by the following constraints:
TDK RLF5018T and NLFC453232T series
Output Capacitor Selection
The output voltage ripple has three components to it. The
bulk value of the capacitor is set to reduce the ripple due
tochargeintothecapacitoreachcycle. Themaxrippledue
to charge is given by:
V
• VOUT(MAX) – V
IN(MIN)
(
)
2
f
IN(MIN)
L >
and L >
f •Ripple • VOUT(MAX)
where:
f = Operating frequency in MHz (of each phase)
IP • V
COUT • VOUT • f • 4
IN
VRBULK
where:
=
Ripple = Allowable inductor current ripple (amps
peak-peak)
VIN(MIN) = Minimum input voltage
IP = peak inductor current
VOUT(MAX) = Maximum output voltage
f = switching frequency of one phase
3425f
17
LTC3425
W U U
U
APPLICATIO S I FOR ATIO
voltage from exceeding its maximum rating during the
break-before-make time. Surface mount diodes, such as
the MBR0520L or equivalent, must be used and must be
locatedveryclosetothepinstominimizestrayinductance.
Two example application circuits are shown in Figures 7
and 8, one with output disconnect and one without.
The ESR (equivalent series resistance) is usually the most
dominant factor for ripple in most power converters. The
ripple due to capacitor ESR is given by:
V
RCESR = IP • CESR
where CESR = Capacitor Series Resistance
The ESL (equivalent series inductance) is also an impor-
tant factor for high frequency converters. Using small,
surface mount ceramic capacitors, placed as close as
possible to the VOUT pins, will minimize ESL.
Operating Frequency Selection
T
here are several considerations in selecting the operat-
ing frequency of the converter. The first is, which are the
sensitive frequency bands that cannot tolerate any spec-
tral noise? For example, in products incorporating RF
communications, the 455kHz IF frequency is sensitive to
any noise, therefore switching above 600kHz is desired.
Some communications have sensitivity to 1.1MHz, and
in that case, a 1.5MHz converter frequency may be
employed.
Low ESR/ESL capacitors should be used to minimize
outputvoltageripple.Forsurfacemountapplications,AVX
TPS Series tantalum capacitors, Sanyo POSCAP or X5R
type ceramic capacitors are recommended.
In all applications, a minimum of 1µF, low ESR ceramic
capacitor should be placed as close to each of the four
VOUT pins as possible, and grounded to a local ground
plane.
The second consideration is the physical size of the
converter. As the operating frequency goes up, the induc-
tor and filter capacitors go down in value and size. The
trade off is in efficiency, since the switching losses in-
crease proportionally with frequency.
Input Capacitor Selection
The input filter capacitor reduces peak currents drawn
from the input source and reduces input switching noise.
Since the IC can operate at voltages below 0.5V once the
output is regulated (as long as SHDN is above 0.65V), the
demandontheinputcapacitortolowerrippleismuchless.
Taiyo Yuden offers very low ESR capacitors, for example
the 2.2µF in a 0603 case (JMK107BJ22MA). See Table 3
for a list of capacitor manufacturers for input and output
capacitor selection.
Thermal Considerations
To deliver the power that the LTC3425 is capable of, it is
imperative that a good thermal path be provided to dissi-
pate the heat generated within the package. This can be
accomplished by taking advantage of the large thermal
pad on the underside of the IC. It is recommended that
multiple vias in the printed circuit board be used to
conductheatawayfromtheICandintoacopperplanewith
as much area as possible. In the event that the junction
temperature gets too high, the peak current limit will
automatically be decreased. If the junction temperature
continues to rise, the part will go into thermal shutdown,
and all switching will stop until the temperature drops.
Table 3. Capacitor Vendor Information
SUPPLIER PHONE
FAX
WEB SITE
AVX
(803) 448-9411 (803) 448-1943 www.avxcorp.com
(619) 661-6322 (619) 661-1055 www.sanyovideo.com
(847) 803-6100 (847) 803-6296 www.component.tdk.com
Sanyo
TDK
Murata
USA:
USA:
www.murata.com
(814) 237-1431 (814) 238-0490
(800) 831-9172
Taiyo Yuden (408) 573-4150 (408) 573-4159 www.t-yuden.com
Closing the Feedback Loop
The LTC3425 uses current mode control with internal
adaptiveslopecompensation.Currentmodecontrolelimi-
nates the 2nd order filter, due to the inductor and output
capacitor exhibited in voltage mode controllers, and sim-
plifies it to a single pole filter response. The product of the
3425f
Applications Where VOUT > 4.3V
Due to the very high slew rates associated with the switch
nodes, Schottky diode clamps are required in any applica-
tion where VOUT can exceed 4.3V to prevent the switch
18
LTC3425
W U U
APPLICATIO S I FOR ATIO
U
V
IN
3.3V
C
IN
2.2µF
L1
L2
L3
L4
2.7µH 2.7µH 2.7µH 2.7µH
D1
C
S
D2
0.47µF
×2
D3
D4
V
SWA
SWB
LTC3425
GNDB
SWC
SWD
Q1
IN
V
V
V
V
V
OUTS
OUTA
OUTB
OUTC
SHDN
REFOUT
CCM
V
OUT
5V
2.5A
OUTD
+
C
C
BULK
OUT
REFEN
SYNCIN
BURST
R2
R4
100k
4.7µF
×4
150µF
309k
6.3V
FB
COMP
SS
SYNCOUT
PGOOD
V
OUT
R1
C2
R
T
100k
220pF
R
I
T
LIM
R3
100k
PGOOD
12.1k
C
GNDA
GNDC GNDD
SGND
R
LIM
75k
SS
0.01µF
3425 F07
C
: TAIYO YUDEN JMK107BJ225MA
D1 TO D4: MOTOROLA MBR0520L
L1 TO L4: TDK RLF5018T-2R7M1R8
Q1: ZETEX ZXM61P02F
IN
C : TAIYO YUDEN LMK107BJ474KA
S
C
C
: TAIYO YUDEN JMK212BJ475MG (×4)
: AVX TPSD157M006R0050
OUT
BULK
Figure 7. Application Circuit for VOUT > 4.3V with Inrush Limiting and Output Disconnect
V
IN
3.3V
C
IN
2.2µF
L1
L2
L3
L4
2.7µH 2.7µH 2.7µH 2.7µH
D1
D2
D3
D4
V
SWA
SWB
LTC3425
GNDB
SWC
SWD
IN
V
V
V
V
V
OUTS
OUTA
OUTB
OUTC
SHDN
REFOUT
CCM
V
OUT
5V
OUTD
+
C
C
BULK
OUT
2.5A
REFEN
SYNCIN
BURST
R2
309k
R4
100k
4.7µF
×4
150µF
6.3V
FB
COMP
SS
SYNCOUT
PGOOD
V
OUT
R1
100k
C2
R
T
220pF
R
I
T
LIM
R3
100k
PGOOD
12.1k
C
GNDA
GNDC GNDD
SGND
R
LIM
75k
SS
0.01µF
3425 F08
C
C
C
: TAIYO YUDEN JMK107BJ225MA
D1 TO D4: MOTOROLA MBR0520LT1
L1 TO L4: TDK RLF5018T-2R7M1R8
IN
: TAIYO YUDEN JMK212BJ475MG (×4)
OUT
BULK
: AVX TPSD157M006R0050
Figure 8. Application Circuit for VOUT > 4.3V When Inrush Limiting and Output Disconnect are Not Required
3425f
19
LTC3425
W U U
U
APPLICATIO S I FOR ATIO
2
modulator control to output DC gain, and the error amp
open-loop gain gives the DC gain of the system:
V
IN
FRHPZ
=
2 • π •IOUT •L
At heavy loads this gain increase with phase lag can occur
at a relatively low frequency. The loop gain is typically
rolled off before the RHP zero frequency.
VREF
VOUT
GDC = GCONTROLOUTPUT •GEA
•
8•V
IOUT
GCONTROL
=
IN , GEA ≈ 5,000
The typical error amp compensation is shown in Figure 9.
The equations for the loop dynamics are as follows:
The output filter pole is given by:
1
IOUT
π • VOUT •COUT
FPOLE1
≈
FFILTERPOLE
=
2 • π •100e6 •CC1
where COUT is the output filter capacitor.
The output filter zero is given by:
whichis extremely close toDC
1
FZERO1
=
1
2 • π •RZ •CC1
1
FFILTERZERO
=
2 • π •RESR •COUT
FPOLE2
=
where RESR is the output capacitor equivalent series
resistance.
2 • π •RZ •CC2
V
OUT
A troublesome feature of the boost regulator topology is
the right half plane zero (RHP), and is given by:
+
–
1.25V
FB
ERROR
AMP
R1
R2
V
C
C
C1
R
Z
C
C2
3425 F09
Figure 9
3425f
20
LTC3425
U
TYPICAL APPLICATIO S
Single or Dual Cell to 3.3V Boost with Automatic Burst Mode Operation
V
= 1.1V TO 3V
IN
+
C
IN
2.2µF
L1
L2
L3
L4
2.2µH 2.2µH 2.2µH 2.2µH
V
SWA
SWB
LTC3425
GNDB
SWC
SWD
IN
V
V
V
V
V
OUTS
OUTA
OUTB
OUTC
R5
10k
C1
SHDN
REFOUT
CCM
22pF
V
3.3V
1A
OUT
OUTD
C
+
C
OUT
BULK
REFEN
SYNCIN
BURST
R2
511k
R5
100k
4.7µF
×4
150µF
4V
FB
COMP
SS
C3
R1
301k
C2
R
T
0.056µF
220pF
SYNCOUT
PGOOD
R
I
T
LIM
R3
100k
PGOOD
15k
R
LIM
75k
C
GNDA
GNDC GNDD
SGND
SS
0.01µF
R4
20k
3425 TA03
C
C
: AVX TPSD157M004R0050
C
: TAIYO YUDEN JMK212BJ475MG (×4)
BULK
OUT
: TAIYO YUDEN JMK107BJ225MA
IN
L1 TO L4: MURATA LQH4C2R2M04
3425f
21
LTC3425
U
TYPICAL APPLICATIO S
Application with User Commanded Burst Mode Operation
and Buffered Reference Output Enabled
V
IN
= 1.8V TO 3V
+
C
IN
2.2µF
L1
L2
L3
L4
3.3µH 3.3µH 3.3µH 3.3µH
V
SWA
SWB
LTC3425
GNDB
SWC
SWD
IN
V
V
V
V
V
OUTS
OUTA
OUTB
OUTC
R4
10k
SHDN
C3
REFOUT
CCM
V
REF
22pF
V
3.3V
2A
OUT
C1
0.1µF
OUTD
C
OUT
REFEN
SYNCIN
BURST
V
OUT
R2
511k
R4
100k
4.7µF
×4
FB
COMP
SS
BURST PWM
R1
301k
C2
R
T
330pF
SYNCOUT
PGOOD
R
I
T
LIM
R3
33k
PGOOD
30.1k
C
GNDA
GNDC GNDD
SGND
R
LIM
75k
SS
0.01µF
3425 TA04
C
C
: TAIYO YUDEN JMK107BJ225MA
IN
: TAIYO YUDEN JMK212BJ475MG (×4)
OUT
L1 TO L4: SUMIDA CDRH4D28
3425f
22
LTC3425
U
PACKAGE DESCRIPTIO
UH Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693)
0.57 ±0.05
5.35 ±0.05
4.20 ±0.05
3.45 ±0.05
(4 SIDES)
PACKAGE OUTLINE
0.23 ± 0.05
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
BOTTOM VIEW—EXPOSED PAD
R = 0.115
TYP
0.75 ± 0.05
0.40 ± 0.10
5.00 ± 0.10
(4 SIDES)
31 32
0.00 – 0.05
PIN 1
TOP MARK
1
2
3.45 ± 0.10
(4-SIDES)
(UH) QFN 0102
0.200 REF
0.23 ± 0.05
0.50 BSC
NOTE:
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
3425f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
23
LTC3425
U
TYPICAL APPLICATIO
10MHz, High Current, Very Low Profile, 8-Phase Converter Using Two LTC3425s Operating
in Fixed Frequency Mode with Forced CCM (Max Component Height = 1.6mm)
V
IN
2.5V
C
C
IN1
2.2µF
IN2
2.2µF
L1
1µH
L2
1µH
L3
1µH
L4
1µH
L5
1µH
L6
1µH
L7
1µH
L8
1µH
V
SWA
SWB
SWC
SWD
V
SWA
SWB
SWC
SWD
IN
IN
V
V
V
V
V
V
V
V
V
V
OUTS
OUTA
OUTB
OUTC
OUTS
OUTA
OUTB
OUTC
SHDN
SHDN
REFOUT
CCM
REFOUT
CCM
V
3.3V
5A
OUT
V
V
OUT
OUT
OUTD
OUTD
C
C
OUT2
OUT1
R
F4
REFEN
SYNCIN
BURST
REFEN
SYNCIN
BURST
R
R4
4.7µF
×4
F2
4.7µF
×4
LTC3425
LTC3425
17.4k
17.4k 100k
FB
COMP
SS
SYNCOUT
PGOOD
FB
COMP
SS
SYNCOUT
PGOOD
R
F1
10.2k
C1
R
T
R
T
330pF
R
T1
12.1k
I
I
LIM
LIM
R3
33k
PGOOD
C
SS
0.022µF
GNDA
GNDB
GNDC GNDD
R
F3
R
T2
14.7k
GNDA
GNDB
GNDC GNDD
R5
75k
SGND
R6
75k
SGND
10.2k
C
OUT
: TAIYO YUDEN JMK107BJ225MA
IN1,2
C
: TAIYO YUDEN JMK212BJ475MG (×8)
3425 TA05
L1 TO L8: MURATA LQH32CN1R0M51
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LT1946/LT1946A
LT1961
1A (I ) 1.2MHz/2.2MHz, High Efficiency Step-Up DC/DC High Efficiency, V : 2.6V to 16V, V
: 34V, I : 4.2mA/5.5mA,
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: <1µA, ThinSOT
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1.5A (I ) 1.2MHz/2.7MHz, High Efficiency Step-Up
High Efficiency, V : 2.45V to 16V, V
: 34V, I : 3.2mA,
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SW
IN
DC/DC Converters
I : <1µA, MS8
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1.5A (I ) 1.25MHz, High Efficiency Step-Up DC/DC
90% Efficiency, V : 3V to 25V, V
: 35V, I : 0.9mA,
SW
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I : 6µA, MS8E
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LTC3400/LTC3400B
LTC3401/LTC3402
LTC3701
600mA (I ) 1.2MHz, Synchronous Step-Down DC/DC
92% Efficiency, V : 0.85V to 5V, V
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I : <1µA, ThinSOT
1A/2A (I ) 3MHz, Synchronous Step-Up DC/DC
97% Efficiency, V : 0.5V to 5V, V
: 6V, I : 38µA, I : <1µA,
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MS10
2-Phase, 550kHz, Low Input Voltage, Dual Step-Down
DC/DC Controller
97% Efficiency, V : 2.5V to 10V, I : 460µA, I : <9µA, SSOP-16
IN Q SD
3425f
LT/TP 0803 1K PRINTED IN USA
24 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2003
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