LTC2912CDDB-2#TRPBF [Linear]
LTC2912 - Single UV/OV Voltage Monitor; Package: DFN; Pins: 8; Temperature Range: 0°C to 70°C;型号: | LTC2912CDDB-2#TRPBF |
厂家: | Linear |
描述: | LTC2912 - Single UV/OV Voltage Monitor; Package: DFN; Pins: 8; Temperature Range: 0°C to 70°C 光电二极管 |
文件: | 总14页 (文件大小:230K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC2912
Single UV/OV
Voltage Monitor
FEATURES
DESCRIPTION
TheLTC®2912voltagemonitorisdesignedtodetectpower
supply undervoltage and overvoltage events. The VL and
VH monitor inputs include filtering to reject brief glitches,
thereby ensuring reliable reset operation without false or
noisy triggering. An adjustable timer defines the duration
of the overvoltage and undervoltage reset outputs which
function independently. While the LTC2912 operates
n
Monitors Single Voltage
n
Adjustable UV and OV Trip Values
n
Guaranteed Threshold Accuracy: ±±1.5
n
Power Supply Glitch Immunity
n
Adjustable Reset Timeout with Timeout Disable
n
29µA Quiescent Current
n
Open‑Drain OV and UV Outputs
n
Guaranteed OV and UV for V ≥ 1V
directly from 2.3V to 6V supplies, an internal V shunt
CC
CC
Available in 8‑Lead ThinSOTTM and (3mm × 2mm)
n
regulator coupled with low supply current demand allows
DFN Packages
operation from higher voltages such as 12V, 24V or 48V.
Three output configurations are available: the LTC2912‑1
has a latch control for the OV output; the LTC2912‑2
has an OV and UV output disable feature for margining
applications; the LTC2912‑3 is identical to the LTC2912‑1
but with a noninverting, OV output.
APPLICATIONS
n
Desktop and Notebook Computers
Network Servers
n
n
Core, I/O Voltage Monitors
TheLTC2912providesaprecise,versatile,space‑conscious
micropower solution for voltage monitoring.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners.
TYPICAL APPLICATION
Single OV/UV Supply Monitor, 313V ±±ꢀ5 Tolerance
Reset Time-Out Period vs Capacitance
10000
3.3V
POWER
SUPPLY
0.1µF
1000
100
27.4k
1k
V
CC
SYSTEM
VH
VL
OV
UV
LTC2912-1
4.53k
10
1
LATCH
GND
TMR
2912 TA01a
22nF
0.1
1
10
100
(nF)
1000
TIMEOUT = 200ms
TMR PIN CAPACITANCE, C
TMR
2912 G08
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LTC2912
(Note ±)
ABSOLUTE MAXIMUM RATINGS
Terminal Voltages
Operating Temperature Range
V
CC
(Note 3)............................................. –0.3V to 6V
LTC2912C ................................................ 0°C to 70°C
LTC2912I .............................................–40°C to 85°C
LTC2912H.......................................... –40°C to 125°C
Storage Temperature Range
OV, UV, OV............................................. –0.3V to 16V
TMR..........................................–0.3V to (V + 0.3V)
VH, VL, LATCH, DIS ...............................–0.3V to 7.5V
CC
Terminal Currents
TSOT.................................................. –65°C to 125°C
DFN.................................................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
I
....................................................................10mA
I , I , I ........................................................10mA
VCC
UV OV OV
TSOT.................................................................300°C
PACKAGE/ORDER INFORMATION
LTC2912‑1
LTC2912‑1
TOP VIEW
TOP VIEW
V
1
2
3
4
8
7
6
5
LATCH
UV
CC
LATCH 1
UV 2
OV 3
GND 4
8 V
CC
7 VH
6 VL
5 TMR
VH
VL
9
OV
TMR
GND
TS8 PACKAGE
8-LEAD PLASTIC TSOT-23
DDB PACKAGE
8-LEAD (3mm × 2mm) PLASTIC DFN
T
= 150°C, θ = 195°C/W
JMAX
JA
T
= 125°C, θ = 55°C/W
JA
JMAX
EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB
LTC2912‑2
LTC2912‑2
TOP VIEW
TOP VIEW
V
1
2
3
4
8
7
6
5
DIS
UV
CC
DIS 1
UV 2
OV 3
8 V
CC
7 VH
6 VL
5 TMR
VH
VL
9
OV
TMR
GND
GND 4
TS8 PACKAGE
8-LEAD PLASTIC TSOT-23
DDB PACKAGE
8-LEAD (3mm × 2mm) PLASTIC DFN
T
JMAX
= 125°C, θ = 55°C/W
JA
T
= 125°C, θ = 55°C/W
JA
JMAX
EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB
LTC2912‑3
LTC2912‑3
TOP VIEW
TOP VIEW
8 V
V
1
2
3
4
8
7
6
5
LATCH
UV
CC
LATCH 1
UV 2
OV 3
GND 4
CC
VH
VL
7 VH
6 VL
5 TMR
9
OV
TMR
GND
TS8 PACKAGE
8-LEAD PLASTIC TSOT-23
DDB PACKAGE
8-LEAD (3mm × 2mm) PLASTIC DFN
T
= 125°C, θ = 55°C/W
JA
JMAX
T
= 125°C, θ = 55°C/W
JA
JMAX
EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB
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LTC2912
ORDER INFORMATION
Lead Free Finish
TAPE AND REEL (MINI)
LTC2912CTS8‑1#TRMPBF LTC2912CTS8‑1#TRPBF LTCJW
LTC2912ITS8‑1#TRMPBF LTC2912ITS8‑1#TRPBF LTCJW
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
0°C to 70°C
8‑Lead Plastic TSOT‑23
8‑Lead Plastic TSOT‑23
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
LTC2912HTS8‑1#TRMPBF LTC2912HTS8‑1#TRPBF LTCJW
LTC2912CDDB‑1#TRMPBF LTC2912CDDB‑1#TRPBF LCJZ
LTC2912IDDB‑1#TRMPBF LTC2912IDDB‑1#TRPBF LCJZ
LTC2912HDDB‑1#TRMPBF LTC2912HDDB‑1#TRPBF LCJZ
LTC2912CTS8‑2#TRMPBF LTC2912CTS8‑2#TRPBF LTCJX
8‑Lead Plastic TSOT‑23
8‑Lead (3mm × 2mm) Plastic DFN
8‑Lead (3mm × 2mm) Plastic DFN
8‑Lead (3mm × 2mm) Plastic DFN
8‑Lead Plastic TSOT‑23
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
LTC2912ITS8‑2#TRMPBF LTC2912ITS8‑2#TRPBF
LTCJX
8‑Lead Plastic TSOT‑23
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
LTC2912HTS8‑2#TRMPBF LTC2912HTS8‑2#TRPBF LTCJX
LTC2912CDDB‑2#TRMPBF LTC2912CDDB‑2#TRPBF LCKB
LTC2912IDDB‑2#TRMPBF LTC2912IDDB‑2#TRPBF LCKB
LTC2912HDDB‑2#TRMPBF LTC2912HDDB‑2#TRPBF LCKB
LTC2912CTS8‑3#TRMPBF LTC2912CTS8‑3#TRPBF LTCJY
8‑Lead Plastic TSOT‑23
8‑Lead (3mm × 2mm) Plastic DFN
8‑Lead (3mm × 2mm) Plastic DFN
8‑Lead (3mm × 2mm) Plastic DFN
8‑Lead Plastic TSOT‑23
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
LTC2912ITS8‑3#TRMPBF LTC2912ITS8‑3#TRPBF
LTCJY
8‑Lead Plastic TSOT‑23
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
LTC2912HTS8‑3#TRMPBF LTC2912HTS8‑3#TRPBF LTCJY
LTC2912CDDB‑3#TRMPBF LTC2912CDDB‑3#TRPBF LCKC
LTC2912IDDB‑3#TRMPBF LTC2912IDDB‑3#TRPBF LCKC
LTC2912HDDB‑3#TRMPBF LTC2912HDDB‑3#TRPBF LCKC
8‑Lead Plastic TSOT‑23
8‑Lead (3mm × 2mm) Plastic DFN
8‑Lead (3mm × 2mm) Plastic DFN
8‑Lead (3mm × 2mm) Plastic DFN
–40°C to 85°C
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
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LTC2912
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 2.°C1 VCC = 313V, VL = ꢀ14.V, VH = ꢀ1..V, LATCH = VCC unless otherwise
noted1 (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
V
V
Shunt Regulator Voltage
I
I
= 5mA
= 5mA (H‑Grade)
6.2
6.2
6.6
6.6
7.2
7.3
V
V
SHUNT
CC
CC
CC
l
l
l
l
l
l
l
l
V
Shunt Regulator Load Regulation
I
= 2mA to 10mA
200
300
mV
V
DV
CC
CC
SHUNT
V
V
V
Supply Voltage (Note 3)
2.3
V
SHUNT
CC
Minimum V Output Valid
DIS = 0V
1
V
CCR(MIN)
CC(UVLO)
CC
Supply Undervoltage Lockout
Supply Undervoltage Lockout Hysteresis
Supply Current
DIS = 0V, V Rising
1.9
5
2
2.1
50
V
CC
DIS = 0V
25
mV
µA
mV
µs
DV
CC(UVHYST)
I
CC
V
= 2.3V to 6V
29
70
CC
Hn
V
UOT
Undervoltage/Overvoltage Threshold
492
50
500
125
508
500
t
I
t
Undervoltage/Overvoltage Threshold to
Output Delay
V
= V
– 5mV or V = V
+ 5mV
UOT
UOD
UOT
Ln
l
l
VH, VL Input Current
15
30
nA
nA
VHL
H‑Grade
l
l
UV/OV Time‑Out Period
C
C
= 1nF
= 1nF (H‑Grade)
6
6
8.5
8.5
12.5
14
ms
ms
UOTO
TMR
TMR
l
l
l
l
l
l
V
V
OV Latch Clear Input High
OV Latch Clear Input Low
LATCH Input Current
DIS Input Current
1.2
V
V
LATCH(VIH)
LATCH(VIL)
LATCH
0.8
1
I
I
V
V
> 0.5V
µA
µA
V
LATCH
> 0.5V
1
2
3.3
DIS
DIS
V
V
DIS Input High
1.2
DIS(VIH)
DIS(VIL)
TMR(UP)
DIS Input Low
0.8
V
l
l
I
I
TMR Pull‑Up Current
V
TMR
V
TMR
= 0V
= 0V (H‑Grade)
–1.3
–1.2
–2.1
–2.1
–2.8
–2.8
µA
µA
l
l
TMR Pull‑Down Current
V
TMR
V
TMR
= 1.6V
= 1.6V (H‑Grade)
1.3
1.2
2.1
2.1
2.8
2.8
µA
µA
TMR(DOWN)
l
l
V
V
V
Timer Disable Voltage
Referenced to V
–180
1
–270
mV
V
TMR(DIS)
CC
UV/OV
UV/OV
Output Voltage High UV/OV/OV
Output Voltage Low UV/OV/OV
V
= 2.3V, I
= 2.3V, I
= –1µA
OH
CC
l
l
V
CC
V
CC
= 2.5mA
0.10
0.01
0.30
0.15
V
V
OL
= 1V, I = 100µA
UV
Note ±: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 3: V maximum pin voltage is limited by input current. Since the
CC
V
pin has an internal 6.5V shunt regulator, a low impedance supply that
CC
exceeds 6V may exceed the rated terminal current. Operation from higher
voltage supplies requires a series dropping resistor. See Applications
Information.
Note 2: All currents into pins are positive; all voltages are referenced to
GND unless otherwise noted.
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LTC2912
TIMING DIAGRAMS
VH Monitor Timing
VL Monitor Timing
V
V
VH
VL
UOT
UOT
1V
t
t
t
t
UOTO
UOD
UOTO
UOD
UV
1V
OV
2912 TD01
2912 TD02
VH Monitor Timing (TMR Pin Strapped to VCC
)
VL Monitor Timing (TMR Pin Strapped to VCC
)
V
VH
V
VL
UOT
UOT
t
t
UOD
t
t
UOD
UOD
UOD
UV
1V
OV
1V
2912 TD03
2912 TD04
TYPICAL PERFORMANCE CHARACTERISTICS
Input Threshold Voltage
vs Temperature
VCC Shunt Voltage
vs Temperature
Supply Current vs Temperature
6.8
6.7
6.6
6.5
6.4
6.3
6.2
0.505
0.504
0.503
0.502
0.501
0.500
0.499
0.498
0.497
0.496
0.495
45
40
35
10mA
V
= 5V
CC
5mA
2mA
V
= 3.3V
CC
30
25
20
15
1mA
V
= 2.3V
CC
200µA
50
–50
0
25
75
100
–25
–50
–25
25
50
75
100
–50
–25
0
25
50
75
100
0
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
2912 G03
2912 G01
2912 G02
Typical Transient Duration vs
Comparator Overdrive
VCC Shunt Voltage vs ICC
UV Output Voltage vs VCC
6.75
6.65
6.55
6.45
6.35
6.25
0.8
0.6
0.4
0.2
0
700
600
500
400
300
200
100
50
V
CC
RESET OCCURS
ABOVE CURVE
UV WITH
10k PULL-UP
–40°C
V
= 6V
CC
UV WITHOUT
PULL-UP
25°C
85°C
V
= 2.3V
CC
0
0.2
0.4
0.6
0.8
1
–2
0
2
4
6
8
10
12
0.1
1
10
100
I
(mA)
SUPPLY VOLTAGE, V (V)
COMPARATOR OVERDRIVE PAST THRESHOLD (%)
CC
CC
2912 G05
2912 G06
2912 G04
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LTC2912
TYPICAL PERFORMANCE CHARACTERISTICS
Reset Time-Out Period
vs Capacitance
UV Output Voltage vs VCC
UV, ISINK vs VCC
5
4
3
2
1
0
5
4
3
2
1
0
10000
1000
100
VH = 0.55V
VH = 0.45V
SEL = V
SEL = V
CC
CC
UV AT 150mV
UV AT 50mV
10
1
0
1
2
3
4
5
0
1
2
3
4
5
0.1
1
10
100
(nF)
1000
TMR PIN CAPACITANCE, C
SUPPLY VOLTAGE, V (V)
SUPPLY VOLTAGE, V (V)
CC
TMR
CC
2912 G08
2912 G07
2912 G09
UV/OV, Voltage Output Low
Reset Timeout Period
vs Temperature
vs Output Sink Current
OV/OV Output Voltage vs VCC
12
11
10
9
5
4
3
2
1
0
1.0
0.8
0.6
0.4
C
= 1nF
V
= 0.55V
TMR
L
85°C
25°C
–40°C
OV
8
OV
0.2
0
7
6
–50
0
25
50
75
100
–25
0
1
3
4
5
2
0
10
I
15
(mA)
20
25
30
5
TEMPERATURE (°C)
SUPPLY VOLTAGE, V (V)
UV/OV
CC
2912 G11
2912 G12
1912 G10
PIN FUNCTIONS
(DFN/TSOT Packages)
DIS (Pin 8/Pin ±, LTC29±2-2): Output Disable Input.
Disables the OV and UV output pins. When DIS is pulled
high, the OV and UV pins are not asserted except during a
UVLO condition. Pin has a weak (2µA) internal pull‑down
to GND. Leave pin open if unused.
is cleared. While held high, OV/OV has a similar delay and
output characteristic as UV.
OV (Pin 6/Pin 3, LTC29±2-±, LTC29±2-2): Overvoltage
Logic Output. Asserts low when the VL input voltage is
above threshold. Latched low (LTC2912‑1). Held low for
programmed delay time after VL input is valid (LTC2912‑
Exposed Pad (Pin 9, DDB Package): Exposed Pad may
be left open or connected to device ground.
2). Pin has a weak pull‑up to V and may be pulled above
CC
V
using an external pull‑up. Leave pin open if unused.
CC
GND (Pin ./Pin 4): Device Ground.
LATCH (Pin 8/Pin ±, LTC29±2-±, LTC29±2-3): OV/OV
Latch Clear/Bypass Input. When pulled high, OV/OV latch
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LTC2912
PIN FUNCTIONS
(DFN/TSOT Packages)
V
(Pin ±/Pin 8): Supply Voltage. Bypass this pin to
OV (Pin 6/Pin 3, LTC29±2-3): Overvoltage Logic Output.
CC
GND with a 0.1µF (or greater) capacitor. Operates as a
direct supply input for voltages up to 6V. Operates as a
shunt regulator for supply voltages greater than 6V and
should have a resistance between the pin and the supply
to limit input current to no greater than 10mA. When used
without a current‑limiting resistance, pin voltage must
not exceed 6V.
Asserts high with a weak internal pull‑up to V when the
CC
VL input is above threshold. Latches high. May be pulled
above V using an external pull‑up. Leave pin open if
CC
unused.
TMR (Pin 4/Pin .): Reset Delay Timer. Attach an external
capacitor (C
) of at least 10pF to GND to set a reset
TMR
delay time of 9ms/nF. A 1nF capacitor will generate an
VH (Pin 2/Pin 7): Voltage High Input. When the voltage
8.5ms reset delay time. Tie pin to V to bypass timer.
CC
on this pin is below 0.5V, an undervoltage condition is
UV (Pin 7/Pin 2): Undervoltage Logic Output. Asserts low
when the VH input voltage is below threshold. Held low
for a programmed delay time after the VH input is valid.
triggered. Tie pin to V if unused.
CC
VL (Pin 3/Pin 6): Voltage Low Input. When the voltage
on this pin is above 0.5V, an overvoltage condition is
triggered. Tie pin to GND if unused.
Pin has a weak pull‑up to V and may be pulled above
CC
V
CC
using an external pull‑up. Leave pin open if unused.
BLOCK DIAGRAM
1
4
V
CC
TMR
V
CC
400k
OSCILLATOR
UV
VH
–
+
7
2
UV PULSE
GENERATOR
DISABLE
UVLO
+
–
2V
V
V
CC
CC
UVLO
400k
OV PULSE
–
+
LTC2912-1
LTC2912-2
GENERATOR
OV/OV
VL
6
3
5
DISABLE
0.5V
GND
LTC2912-3
OV LATCH
CLEAR/BYPASS
8
8
LATCH
+
–
1V
LTC2912-1, LTC2912-3
–
+
1V
DIS
2µA
LTC2912-2
2912 BD
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LTC2912
APPLICATIONS INFORMATION
Voltage Monitoring
21 Choose R to obtain the desired UV trip point
B
The LTC2912 is a low power voltage monitoring circuit
with an undervoltage and an overvoltage input. A timeout
period that holds OV and UV asserted after a fault has
cleared is adjustable using an external capacitor and may
beexternallydisabled.Whenconfiguredtomonitoraposi‑
Once R is known, R is chosen to set the desired trip
A
B
point for the undervoltage monitor.
Vn
VUV
0.5V
In
RB =
•
–RA
(2)
tive voltage V using the 3‑resistor circuit configuration
n
31 Choose R to complete the design
C
shown in Figure 1, VH will be connected to the high side
tap of the resistive divider and VL will be connected to the
low side tap of the resistive divider.
Once R and R are known, R is determined by:
A
B
C
Vn
In
RC =
–RA –RB
(3)
3-Step Design Procedure
The following 3‑step design procedure allows selecting
appropriate resistances to obtain the desired UV and OV
trip points for the voltage monitor circuit in Figure 1.
If any of the variables V , I , V or V change, then each
n
n
UV
OV
step must be recalculated.
For supply monitoring, V is the desired nominal operat‑
Voltage Monitor Example
n
ing voltage, I is the desired nominal current through the
n
A typical voltage monitor application is shown in Figure 2.
The monitored voltage is a 5V 10ꢀ supply. Nominal
current in the resistive divider is 10µA.
resistive divider, V is the desired overvoltage trip point
OV
and V is the desired undervoltage trip point.
UV
±1 Choose R to obtain the desired OV trip point
A
1. Find R to set the OV trip point of the monitor.
A
R is chosen to set the desired trip point for the over‑
A
0.5V 5V
10µA 5.5V
voltage monitor.
RA =
•
≈ 45.3k
Vn
VOV
0.5V
In
RA =
•
(1)
2. Find R to set the UV trip point of the monitor.
B
0.5V 5V
10µA 4.5V
RB =
•
– 45.3k ≅ 10.2k
V
n
LTC2912
VH
R
C
3. Determine R to complete the design.
C
–
+
UV
OV
5V
10µA
RC =
– 45.3k − 10.2k ≈ 442k
+
–
R
0.5V
B
V1
5V 10ꢀ
V
CC
5V
–
+
R
C
VL
V
CC
442k
VH1
LTC2912-1
VL1 UV
OV
R
R
B
10.2k
A
2912 F01
R
A
GND
45.3k
Figure ±1 3-Resistor Positive UV/OV Monitoring Configuration
2912 F02
Figure 21 Typical Supply Monitor
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LTC2912
APPLICATIONS INFORMATION
Power-Up/Power-Down
The two extreme conditions, with a relative accuracy of
1.5ꢀ and resistance accuracy of 1ꢀ, result in:
AssoonasV reaches1Vduringpowerup, theUVoutput
CC
asserts low and the OV output weakly pulls to V .
CC
⎛
⎞
⎟
RC • 0.99
V
UV(MIN) = 0.5V • 0.985 • 1+
⎜
The LTC2912 is guaranteed to assert UV low, OV high
R + R • 1.01
(
)
⎝
⎠
A
B
(LTC2912‑1, LTC2912‑2) and OV low (LTC2912‑3) under
conditions of low V , down to V = 1V. Above V =
and
CC
CC
CC
2V (2.1V maximum), the VH and VL inputs take control.
⎛
⎜
⎝
⎞
RC • 1.01
Once the VH input and V become valid an internal timer
V
UV(MAX) = 0.5V • 1.015 • 1+
CC
⎟
R + R • 0.99
(
)
⎠
A
B
is started. After an adjustable delay time, UV weakly pulls
high.
RC
RA + RB
For a desired trip point of 4.5V,
= 8
Threshold Accuracy
Resetthresholdaccuracyisimportantinasupply‑sensitive
system.Ideally,suchasystemresetsonlyifsupplyvoltages
fall outside the exact thresholds for a specified margin.
Both LTC2912 inputs have a relative threshold accuracy
of 1.5ꢀ over the full operating temperature range.
Therefore,
⎛
⎝
⎞
⎠
0.99
1.01
VUV(MIN) = 0.5V • 0.985 • 1+ 8
= 4.354V
= 4.650V
and
For example, when the LTC2912 is programmed to moni‑
tor a 5V input with a 10ꢀ tolerance, the desired UV trip
point is 4.5V. Because of the 1.5ꢀ relative accuracy of
the LTC2912, the UV trip point can be anywhere between
4.433V and 4.567V which is 4.5V 1.5ꢀ.
⎛
⎝
⎞
⎠
1.01
0.99
VUV(MAX) = 0.5V • 1.015 • 1+ 8
Glitch Immunity
In any supervisory application, noise riding on the moni‑
tored DC voltage causes spurious resets. To solve this
problem without adding hysteresis, which causes a new
error term in the trip voltage, the LTC2912 lowpass filters
the output of the first stage comparator at each input. This
filter integrates the output of the comparator before as‑
serting the UV or OV logic. A transient at the input of the
comparator of sufficient magnitude and duration triggers
the output logic. The Typical Performance Characteristics
show a graph of the Transient Duration vs Comparator
Overdrive.
Likewise, the accuracy of the resistances chosen for R ,
A
R and R can affect the UV and OV trip points as well.
B
C
Using the example just given, if the resistances used to
set the UV trip point have 1ꢀ accuracy, the UV trip range
is between 4.354V and 4.650V. This is illustrated in the
following calculations.
The UV trip point is given as:
⎛
⎞
RC
RA + RB
V
UV = 0.5V 1+
⎜
⎟
⎝
⎠
UV/OV Timing
TheLTC2912hasanadjustabletimeoutperiod(t
)that
UOTO
holds OV, OV or UV asserted after each fault has cleared.
This delay assures a minimum reset pulse width allowing
settling time for the monitored voltage after it has entered
the “valid” region of operation.
2912fb
9
For more information www.linear.com/LTC2912
LTC2912
APPLICATIONS INFORMATION
and should have a resistance R between the supply and
When the VH input drops below its designed threshold,
the UV pin asserts low. When the input recovers above
its designed threshold, the UV output timer starts. If the
input remains above the designed threshold when the
timer finishes, the UV pin weakly pulls high. However, if
the input falls below its designed threshold during this
timeout period, the timer resets and restarts when the
input is above the designed threshold. The OV and OV
outputs behave as the UV output when LATCH is high
(LTC2912‑1, LTC2912‑3).
Z
the V pin to limit the current to no greater than 10mA.
CC
Whenchoosingthisresistancevalue,selectanappropriate
locationontheI‑VcurveshownintheTypicalPerformance
Characteristics to accommodate any variations in V due
CC
to changes in current through R .
Z
UV, OV and OV Output Characteristics
The DC characteristics of the UV, OV and 0V pull‑up and
pull‑down strength are shown in the Typical Performance
Characteristics. Each pin has a weak internal pull‑up to
Selecting the UV/OV Timing Capacitor
V
and a strong pull‑down to ground. This arrangement
CC
The UV and OV timeout period (t
) for the LTC2912
UOTO
allows these pins to have open‑drain behavior while pos‑
sessing several other beneficial characteristics. The weak
pull‑up eliminates the need for an external pull‑up resistor
when the rise time on the pin is not critical. On the other
hand, the open‑drain configuration allows for wired‑OR
connections, and is useful when more than one signal
is adjustable to accommodate a variety of applications.
Connecting a capacitor, C , between the TMR pin and
TMR
ground sets the timeout period. The value of capacitor
needed for a particular timeout period is:
–9
C
TMR
= t
• 115 • 10 [F/s]
UOTO
needs to pull down on the output. V of 1V guarantees
CC
The Reset Timeout Period vs Capacitance graph found in
theTypicalPerformanceCharacteristicsshowsthedesired
delay time as a function of the value of the timer capacitor
that must be used. The TMR pin must have a minimum
a maximum V = 0.15V at UV.
OL
AtV =1V,theweakpull‑upcurrentonOVisbarelyturned
CC
on. Therefore, an external pull‑up resistor of no more
than 100k is recommended on the OV pin if the state and
10pF load or be tied to V . For long timeout periods, the
CC
pull‑up strength of the OV pin is crucial at very low V .
only limitation is the availability of a large value capacitor
with low leakage. Capacitor leakage current must not ex‑
ceed the minimum TMR charging current of 1.3µA.Tying
CC
Note however, by adding an external pull‑up resistor, the
pull‑up strength on the OV pin is increased. Therefore, if
it is connected in a wired‑OR connection, the pull‑down
strength of any single device must accommodate this
additional pull‑up strength.
the TMR pin to V bypasses the timeout period.
CC
Undervoltage Lockout
When V falls below 2V, the LTC2912 asserts an under‑
CC
Output Rise and Fall Time Estimation
voltage lockout (UVLO) condition. During UVLO, UV is
asserted and pulled low while OV and OV are cleared and
The UV, OV and OV outputs have strong pull‑down capa‑
bility. The following formula estimates the output fall time
(90ꢀ to 10ꢀ) for a particular external load capacitance
blocked from asserting. When V rises above 2V, UV
CC
follows the same timing procedure as an undervoltage
condition on the VH input.
(C ):
LOAD
t
≈ 2.2 • R • C
PD LOAD
Shunt Regulator
FALL
where R is the on‑resistance of the internal pull‑down
The LTC2912 has an internal shunt regulator. The V pin
PD
CC
transistor, typically 50Ω at V > 1V and at room tem‑
operates as a direct supply input for voltages up to 6V.
CC
perature (25°C). C
is the external load capacitance
on the pin. Assuming a 150pF load capacitance, the fall
Under this condition, the quiescent current of the device
LOAD
remains below a maximum of 70µA. For V voltages
CC
time is 16.5ns.
higher than 6V, the device operates as a shunt regulator
2912fb
10
For more information www.linear.com/LTC2912
LTC2912
APPLICATIONS INFORMATION
TherisetimeontheUV,OVand0Vpinsislimitedbya400k
low while the timeout period is active, the OV and OV pins
pull‑up resistance to V . A similar formula estimates the
latch as before.
CC
output rise time (10ꢀ to 90ꢀ) at the UV, OV and OV pins:
Disable (LTC29±2-2)
t
≈ 2.2 • R • C
PU LOAD
RISE
TheLTC2912‑2allowsdisablingtheUVandOVoutputsvia
theDISpin. PullingDIShighforcesbothoutputstoremain
weakly pulled high, regardless of any faults that occur on
the inputs. However, if a UVLO condition occurs, UV as‑
serts and pulls low, but the timeout function is bypassed.
UV pulls high as soon as the UVLO condition is cleared.
where R is the pull‑up resistance.
PU
OV/OV Latch (LTC29±2-±, LTC29±2-3)
With the LATCH pin held low, the OV pin latches low
(LTC2912‑1) and the OV pin latches high (LTC2912‑3)
when an OV condition is detected. The latch is cleared
by raising the LATCH pin high. If an OV condition clears
while LATCH is held high, the latch is bypassed and the
OV and OV pins behave the same as the UV pin with a
similar timeout period at the output. If LATCH is pulled
DIS has a weak 2µA (typical) internal pull‑down current
guaranteeing normal operation with the pin left open.
TYPICAL APPLICATIONS
Dual UV/OV Supply Monitor, 313V ±±ꢀ5 Tolerance
48V Supply Monitor (<±±ꢀ5 = Powergood)
3.3V
48V
POWER
SUPPLY
POWER
SUPPLY
C
BYP
0.1µF
R
Z
C
BYP
0.1µF
200k
1
R
PG
30k
R
C
V
27.4k
1
CC
2
6
7
SYSTEM
R
C
VH
VL
OV
UV
V
37.4M
CC
2
3
6
7
R
B
LTC2912-1
VH
VL
OV
UV
1k
3
R
B
LTC2912-2
80.6k
R
A
4.53k
8
POWERGOOD
LED
R
A
357k
LATCH
TMR
4
8
GND
2912 TA02
DIS
TMR
5
GND
C
TMR
22nF
TIMEOUT = 200ms
5
4
C
TMR
10nF
TIMEOUT = 85ms
2912 TA03
Dual UV Supply Monitor, 313V, 21.V, ±ꢀ5 Tolerance
3.3V
POWER
SUPPLIES
2.5V
C
BYP
0.1µF
R
UV
10k
R
OV
10k
1
4
R
B1
54.9k
SYSTEM
V
H
TMR
OV
CC
2
6
7
V
R
A1
11k
LTC2912-2
UV
R
B2
39.2k
3
8
V
L
DIS
R
A2
11k
GND
5
2912 TA04
2912fb
11
For more information www.linear.com/LTC2912
LTC2912
PACKAGE DESCRIPTION
Please refer to http://www1linear1com/designtools/packaging/ for the most recent package drawings1
DDB Package
8-Lead Plastic DFN (3mm × 2mm)
(Reference LTC DWG # 05-08-ꢀ702 Rev B)
0.6ꢀ 0.05
(2 SIDES)
R = 0.ꢀꢀ5
0.40 0.ꢀ0
3.00 0.ꢀ0
(2 SIDES)
TYP
5
R = 0.05
TYP
8
0.70 0.05
2.55 0.05
ꢀ.ꢀ5 0.05
2.00 0.ꢀ0
(2 SIDES)
PIN ꢀ BAR
TOP MARK
PIN ꢀ
R = 0.20 OR
(SEE NOTE 6)
0.25 × 45°
PACKAGE
OUTLINE
0.56 0.05
(2 SIDES)
CHAMFER
4
ꢀ
(DDB8) DFN 0905 REV B
0.25 0.05
0.25 0.05
0.75 0.05
0.200 REF
0.50 BSC
2.20 0.05
(2 SIDES)
0.50 BSC
2.ꢀ5 0.05
(2 SIDES)
0 – 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
BOTTOM VIEW—EXPOSED PAD
ꢀ. DRAWING CONFORMS TO VERSION (WECD-ꢀ) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.ꢀ5mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION ON THE TOP AND BOTTOM OF PACKAGE
TS8 Package
8-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1637 Rev A)
2.90 BSC
(NOTE 4)
0.40
MAX
0.65
REF
1.22 REF
1.4 MIN
1.50 – 1.75
(NOTE 4)
2.80 BSC
3.85 MAX 2.62 REF
PIN ONE ID
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.22 – 0.36
8 PLCS (NOTE 3)
0.65 BSC
0.80 – 0.90
0.20 BSC
DATUM ‘A’
0.01 – 0.10
1.00 MAX
0.30 – 0.50 REF
1.95 BSC
TS8 TSOT-23 0710 REV A
0.09 – 0.20
(NOTE 3)
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
2912fb
12
For more information www.linear.com/LTC2912
LTC2912
REVISION HISTORY (Revision history begins at Rev B)
REV
DATE
06/14 Updated Package/Order Information
Added OV/OV Output Voltage vs V graph
DESCRIPTION
PAGE NUMBER
B
2, 3
6
CC
2912fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa‑
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
13
LTC2912
TYPICAL APPLICATION
Single UV/OV Supply Monitor with 313V ±±ꢀ5
12V
POWER
SUPPLY
Q1
3.3V
0.1µF
10k
27.4k
1k
SYSTEM
V
CC
VH
VL
OV
LTC2912-3
UV
4.53k
LATCH
TMR
GND
2912 TA05
22nF
TIMEOUT = 200ms
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LTC690
5V Supply Monitor, Watchdog Timer and Battery Backup
3.3V Supply Monitor, Watchdog Timer and Battery Backup
5V Supply Monitor and Watchdog Timer
4.65 Threshold
2.9V Threshold
4.65 Threshold
LTC694‑3.3
LTC699
LTC1232
5V Supply Monitor, Watchdog Timer and Push‑Button Reset
4.37V/4.62V Threshold
LTC1326/
LTC1326‑2.5
Micropower Precision Triple Supply Monitor for 5V/2.5V, 3.3V
and ADJ
4.725V, 3.118V, 1V Threshold ( 0.75ꢀ)
LTC1536
Precision Triple Supply Monitor for PCI Applications
Meets PCI t
Timing Specifications
FAIL
LTC1726‑2.5/
LTC1726‑5
Micropower Triple Supply Monitor for 2.5V/5V, 3.3V and ADJ
Adjustable RESET and Watchdog Time‑Outs
LTC1728‑1.8/
LTC1728‑3.3
Micropower Triple Supply Monitor with Open‑Drain Reset
5‑Lead SOT‑23 Package
LTC1985‑1.8
LTC2900
Micropower Triple Supply Monitor with Open‑Drain Reset
Programmable Quad Supply Monitor
5‑Lead SOT‑23 Package
Adjustable RESET, 10‑Lead MSOP and 3mm × 3mm
10‑Lead DFN Package
LTC2901
LTC2902
Programmable Quad Supply Monitor
Programmable Quad Supply Monitor
Adjustable RESET and Watchdog Timer, 16‑Lead SSOP Package
Adjustable RESET and Tolerance, 16‑Lead SSOP Package,
Margining Functions
LTC2903‑1
LTC2904
LTC2905
LTC2906
LTC2907
LTC2908
LTC2909
Precision Quad Supply Monitor
6‑Lead TSOT‑23 Package, Ultralow Voltage Reset
Adjustable Tolerance, 8‑Lead TSOT‑23 Package
Adjustable RESET and Tolerance, 8‑Lead TSOT‑23 Package
3‑State Programmable Precision Dual Supply Monitor
3‑State Programmable Precision Dual Supply Monitor
Precision Dual Supply Monitor 1‑Selectable and 1 Adjustable
Precision Dual Supply Monitor 1‑Selectable and 1 Adjustable
Precision Six Supply Monitor (Four Fixed and 2 Adjustable)
Prevision Dual Input UV, OV and Negative Voltage Monitor
Separate V Pin, RST/RST Outputs
CC
Separate V , Adjustable Reset Timer
CC
8‑Lead TSOT‑23 and DFN Packages
Separate V Pin, Adjustable Reset Timer, 8‑Lead TSOT‑23 and DFN
CC
Packages
LTC2913
LTC2914
Dual UV/OV Voltage Monitor
Separate V Pin, Two Inputs, Adjustable Reset Timer, 10‑Lead
CC
MSOP and DFN Packages
Quad UV/OV Positive/Negative Voltage Monitor
Separate V Pin, Four inputs, Up To Two Negative Monitors,
CC
Adjustable Reset Timer, 16‑Lead TSSOP and DFN Packages
2912fb
LT 0614 REV B • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035‑7417
14
(408)432‑1900 FAX: (408) 434‑0507 www.linear.com/LTC2912
●
●
LINEAR TECHNOLOGY CORPORATION 2006
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