LTC2378IMS-20PBF_技术文档

LTC2378-20

20-Bit, 1Msps, Low Power

SAR ADC with 0.5ppm INL

FeaTures

DescripTion

The LTC^®2378-20 is a low noise, low power, high speed

20-bit successive approximation register (SAR) ADC.

Operating from a 2.5V supply, the LTC2378-20 has a

n

1Msps Throughput Rate

n

±±0.ppꢀ INꢁ ꢂTyp)

n

Guaranteed 2±-Bit No Missing Codes

ꢁow Power: 21ꢀW at 1Msps, 21µW at 1ksps

1±4dB SNR ꢂTyp) at f = 2kHz

–12.dB THD ꢂTyp) at f = 2kHz

n

V

fully differential input range with V ranging from

REF REF

n

2.5V to 5.1V. The LTC2378-20 consumes only 21mW and

achieves 2ppm INL maximum, no missing codes at 20

bits with 104dB SNR.

IN

n

Digital Gain Coꢀpression ꢂDGC)

Guaranteed Operation to 85°C

2.5V Supply

The LTC2378-20 has a high speed SPI-compatible serial

interface that supports 1.8V, 2.5V, 3.3V and 5V logic

while also featuring a daisy-chain mode. The fast 1Msps

throughput with no cycle latency makes the LTC2378-20

ideally suited for a wide variety of high speed applications.

Aninternaloscillatorsetstheconversiontime,easingexter-

nal timing considerations. The LTC2378-20 automatically

powers down between conversions, leading to reduced

power dissipation that scales with the sampling rate.

Fully Differential Input Range V

REF

V

Input Range from 2.5V to 5.1V

REF

No Pipeline Delay, No Cycle Latency

1.8V to 5V I/O Voltages

SPI-Compatible Serial I/O with Daisy-Chain Mode

Internal Conversion Clock

16-Lead MSOP and 4mm × 3mm DFN Packages

The LTC2378-20 features a unique digital gain compres-

sion(DGC)function,whicheliminatesthedriveramplifier’s

negative supply while preserving the full resolution of the

ADC. When enabled, the ADC performs a digital scaling

applicaTions

n

Medical Imaging

n

High Speed Data Acquisition

n

Portable or Compact Instrumentation

Industrial Process Control

Low Power Battery-Operated Instrumentation

ATE

function that maps zero-scale code from 0V to 0.1 • V

REF

n

and full-scale code from V

to 0.9 • V . For a typical

REF

n

reference voltage of 5V, the full-scale input range is now

0.5V to 4.5V, which provides adequate headroom for

powering the driving amplifier from a single 5.5V supply.

n

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners. Patents Pending. Protected by U.S. Patents, including

7705765, 7961132, 8319673.

Typical applicaTion

Integral Nonlinearity vs Output Code

2.0

2.5V 1.8V TO 5V

10µF

1.5

0.1µF

1.0

0.5

V

OV

DD

CHAIN

RDL/SDI

SDO

SCK

BUSY

CNV

REF/DGC

DD

6800pF

3300pF

6800pF

V

REF

10Ω

+

–

IN

+

–

0

0V

LTC2378-20

REF

–0.5

–1.0

–1.5

–2.0

IN

SAMPLE CLOCK

0V

V

REF

GND

REF

237820 TA01

2.5V TO 5.1V

47µF

(X7R, 1210 SIZE)

0

262144

524288

786432 1048576

OUTPUT CODE

237820 TA02

237820f

1

For more information www.linear.com/LTC2378-20

LTC2378-20

absoluTe MaxiMuM raTings

ꢂNotes 1, 2)

Supply Voltage (V )...............................................2.8V

Digital Output Voltage

DD

Supply Voltage (OV )................................................6V

(Note 3)........................... (GND –0.3V) to (OV + 0.3V)

DD

Reference Input (REF).................................................6V

Power Dissipation.............................................. 500mW

Operating Temperature Range

LTC2378C................................................ 0°C to 70°C

LTC2378I .............................................–40°C to 85°C

Storage Temperature Range .................. –65°C to 150°C

Analog Input Voltage (Note 3)

+

–

IN , IN ......................... (GND –0.3V) to (REF + 0.3V)

REF/DGC Input (Note 3) .... (GND –0.3V) to (REF + 0.3V)

Digital Input Voltage

(Note 3)........................... (GND –0.3V) to (OV + 0.3V)

DD

pin conFiguraTion

TOP VIEW

CHAIN

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

GND

OV

TOP VIEW

V

DD

CHAIN 1

16 GND

GND

SDO

V

2

15 OV

DD

+

GND 3

14 SDO

13 SCK

17

GND

IN

SCK

+

–

IN

4

5

–

IN

RDL/SDI

BUSY

GND

12 RDL/SDI

11 BUSY

10 GND

GND

REF

GND 6

REF 7

REF/DGC 8

9

CNV

REF/DGC

CNV

MS PACKAGE

16-LEAD PLASTIC MSOP

DE PACKAGE

T

= 150°C, θ = 110°C/W

16-LEAD (4mm × 3mm) PLASTIC DFN

JMAX

JA

T

= 150°C, θ = 40°C/W

JA

JMAX

EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB

orDer inForMaTion

ꢁEAD FREE FINISH

TAPE AND REEꢁ

PART MARKING*

PACKAGE DESCRIPTION

16-Lead Plastic MSOP

TEMPERATURE RANGE

0°C to 70°C

LTC2378CMS-20#PBF

LTC2378IMS-20#PBF

LTC2378CDE-20#PBF

LTC2378IDE-20#PBF

LTC2378CMS-20#TRPBF 237820

LTC2378IMS-20#TRPBF 237820

LTC2378CDE-20#TRPBF 23780

–40°C to 85°C

0°C to 70°C

16-Lead (4mm × 3mm) Plastic DFN

LTC2378IDE-20#TRPBF

23780

–40°C to 85°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping

container.

Consult LTC Marketing for information on non-standard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

237820f

2

For more information www.linear.com/LTC2378-20

LTC2378-20

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full operating

teꢀperature range, otherwise specifications are at T_A= 2.°C0 ꢂNote 4)

SYMBOꢁ

V +

PARAMETER

CONDITIONS

(Note 5)

MIN

–0.1

TYP

MAX

UNITS

+

l

Absolute Input Range (IN )

V

+ 0.1

V

IN

REF

–

V –

IN

Absolute Input Range (IN )

(Note 5)

+ 0.1

REF

V + – V – Input Differential Voltage Range

V

IN

= V + – V –

–V

REF

+V

IN

REF

V

CM

Common-Mode Input Range

V

/2–

V /2

REF

V

/2+

REF

0.1

I

Analog Input Leakage Current

Analog Input Capacitance

0.01

µA

IN

C

Sample Mode

Hold Mode

45

5

pF

IN

CMRR

Input Common Mode Rejection Ratio

f

IN

= 500kHz

86

dB

converTer characTerisTics ^Thel denotes the specifications which apply over the full operating

teꢀperature range, otherwise specifications are at T_A= 2.°C0 ꢂNote 4)

SYMBOꢁ PARAMETER

CONDITIONS

MIN

20

TYP

MAX

UNITS

Bits

l

Resolution

No Missing Codes

20

Bits

Transition Noise

2.3

ppm

RMS

l

INL

Integral Linearity Error

(Note 6)

REF/DGC = GND, (Note 6)

–2

0.5

2

ppm

l

DNL

BZE

Differential Linearity Error

Bipolar Zero-Scale Error

Bipolar Zero-Scale Error Drift

Bipolar Full-Scale Error

(Note 10)

(Note 7)

–0.5

–13

0.2

0

0.5

13

ppm

7

ppb/°C

ppm

l

FSE

(Note 7)

–100

10

0.05

100

Bipolar Full-Scale Error Drift

ppm/°C

DynaMic accuracy ^Thel denotes the specifications which apply over the full operating teꢀperature range,

otherwise specifications are at T_A= 2.°C and A_IN= –1dBFS0 ꢂNotes 4, 8)

SYMBOꢁ PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

SINAD

SNR

Signal-to-(Noise + Distortion) Ratio

f

= 2kHz, V = 5V

101

104

dB

IN

REF

l

Signal-to-Noise Ratio

f

= 2kHz, V = 5V

101

99

95.4

104

102

98

dB

IN

REF

= 2kHz, V = 5V, REF/DGC = GND

REF

= 2kHz, V = 2.5V

REF

l

THD

Total Harmonic Distortion

f

IN

f

IN

f

IN

= 2kHz, V = 5V

–125

–123

–114

–113

dB

REF

= 2kHz, V = 5V, REF/DGC = GND

REF

= 2kHz, V = 2.5V

REF

l

SFDR

Spurious Free Dynamic Range

–3dB Input Bandwidth

Aperture Delay

f

= 2kHz, V = 5V

115

128

34

dB

MHz

ps

IN

REF

500

4

Aperture Jitter

ps

Transient Response

Full-Scale Step

312

ns

237820f

3

For more information www.linear.com/LTC2378-20

LTC2378-20

reFerence inpuT ^Thel denotes the specifications which apply over the full operating teꢀperature range, otherwise

specifications are at T_A= 2.°C0 ꢂNote 4)

SYMBOꢁ

PARAMETER

CONDITIONS

(Note 5)

MIN

TYP

MAX

5.1

UNITS

l

V

Reference Voltage

2.5

V

mA

V

REF

I

Reference Input Current

High Level Input Voltage REF/DGC Pin

Low Level Input Voltage REF/DGC Pin

(Note 9)

0.94

1.1

V

IHDGC

V

ILDGC

0.8V

REF

0.2V

V

REF

DigiTal inpuTs anD DigiTal ouTpuTs ^Thel denotes the specifications which apply over the

full operating teꢀperature range, otherwise specifications are at T_A= 2.°C0 ꢂNote 4)

SYMBOꢁ PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

l

V

High Level Input Voltage

Low Level Input Voltage

Digital Input Current

0.8 • OV

IH

IL

DD

0.2 • OV

V

DD

I

V

= 0V to OV

DD

–10

10

µA

pF

IN

C

V

Digital Input Capacitance

High Level Output Voltage

Low Level Output Voltage

Hi-Z Output Leakage Current

Output Source Current

Output Sink Current

5

IN

l

I = –500µA

O

OV – 0.2

DD

V

OH

OL

I = 500µA

O

0.2

10

V

I

V

= 0V to OV

DD

–10

µA

mA

OZ

OUT

= 0V

= OV

–10

10

SOURCE

SINK

DD

power requireMenTs ^Thel denotes the specifications which apply over the full operating teꢀperature

range, otherwise specifications are at T_A= 2.°C0 ꢂNote 4)

SYMBOꢁ

PARAMETER

Supply Voltage

CONDITIONS

MIN

2.375

1.71

TYP

MAX

2.625

5.25

10

UNITS

l

V

DD

2.5

V

OV

DD

I

Supply Current

Power Down Mode

1Msps Sample Rate

8.4

0.2

1

mA

µA

VDD

OVDD

PD

1Msps Sample Rate (C = 20pF)

L

VDD

l

Conversion Done (I

+ I

)

90

OVDD

REF

P

Power Dissipation

Power Down Mode

1Msps Sample Rate

Conversion Done (I

21

2.5

25

225

mW

µW

D

+ I

REF

VDD

OVDD

aDc TiMing characTerisTics ^Thel denotes the specifications which apply over the full operating

teꢀperature range, otherwise specifications are at T_A= 2.°C0 ꢂNote 4)

SYMBOꢁ

PARAMETER

CONDITIONS

MIN

TYP

MAX

1

UNITS

Msps

ns

l

f

t

Maximum Sampling Frequency

Conversion Time

SMPL

CONV

ACQ

615

312

1

675

Acquisition Time

t

= t

CYC

– t

– t (Note 10)

BUSYLH

ns

ACQ

CONV

Time Between Conversions

CNV High Time

µs

CYC

20

ns

CNVH

BUSYLH

CNVL

QUIET

SCK

C = 20pF

L

13

ns

CNV↑ to BUSY Delay

Minimum Low Time for CNV

SCK Quiet Time from CNV↑

SCK Period

(Note 11)

(Note 10)

20

10

ns

(Notes 11, 12)

ns

237820f

4

For more information www.linear.com/LTC2378-20

LTC2378-20

aDc TiMing characTerisTics ^Thel denotes the specifications which apply over the full operating

teꢀperature range, otherwise specifications are at T_A= 2.°C0 ꢂNote 4)

SYMBOꢁ

PARAMETER

CONDITIONS

MIN

4

TYP

MAX

UNITS

ns

l

t

SCK High Time

SCKH

SCK Low Time

4

ns

SCKL

(Note 11)

4

ns

SDI Setup Time From SCK↑

SDI Hold Time From SCK↑

SCK Period in Chain Mode

SDO Data Valid Delay from SCK↑

SSDISCK

HSDISCK

SCKCH

DSDO

1

ns

t

= t

+ t (Note 11)

DSDO

13.5

ns

SCKCH

SSDISCK

l

C = 20pF, OV = 5.25V

7.5

8

9.5

ns

L

DD

C = 20pF, OV = 2.5V

L

C = 20pF, OV = 1.71V

L

l

t

C = 20pF (Note 10)

1

ns

SDO Data Remains Valid Delay from SCK↑

SDO Data Valid Delay from BUSY↓

Bus Enable Time After RDL↓

HSDO

DSDOBUSYL

EN

L

C = 20pF (Note 10)

L

5

(Note 11)

16

13

Bus Relinquish Time After RDL↑

DIS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may effect device

reliability and lifetime.

Note 7: Bipolar zero-scale error is the offset voltage measured from

–0.5LSB when the output code flickers between 0000 0000 0000 0000 0000

and 1111 1111 1111 1111 1111. Full-scale bipolar error is the worst-case

of –FS or +FS untrimmed deviation from ideal first and last code transitions

and includes the effect of offset error.

Note 2: All voltage values are with respect to ground.

Note 8: All specifications in dB are referred to a full-scale 5V input with a

5V reference voltage.

Note 3: When these pin voltages are taken below ground or above REFor

OV , they will be clamped by internal diodes. This product can handle

DD

input currents up to 100mA below ground or above REFor OV without

latch-up.

Note 9: f

= 1MHz, I varies proportionately with sample rate.

SMPL REF

DD

Note 1±: Guaranteed by design, not subject to test.

Note 11: Parameter tested and guaranteed at OV = 1.71V, OV = 2.5V

Note 4: V = 2.5V, OV = 2.5V, REF = 5V, V = 2.5V, f

= 1MHz,

DD

CM

SMPL

DD

REF/DGC = V

.

REF

and OV = 5.25V.

DD

Note .: Recommended operating conditions.

Note 12: t

of 10ns maximum allows a shift clock frequency up to

SCK

Note 6: Integral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

100MHz for rising capture.

0.8*OV

DD

t

WIDTH

0.2*OV

DD

50%

t

DELAY

237820 F01

0.8*OV

0.2*OV

DD

0.2*OV

DD

Figure 10 Voltage ꢁevels for Tiꢀing Specifications

237820f

5

For more information www.linear.com/LTC2378-20

LTC2378-20

Typical perForMance characTerisTics ^T_A^{= 2.°C, V}_DD= 20.V, OV_DD= 20.V, V_CM= 20.V,

REF = .V, f_SMPꢁ= 1Msps, unless otherwise noted0

Integral Nonlinearity

vs Output Code

Differential Nonlinearity

vs Output Code

DC Histograꢀ

2.0

1.5

0.5

0.4

50000

45000

40000

35000

30000

25000

20000

15000

10000

5000

σ = 2.3

0.3

1.0

0.2

0.5

0.1

0

0.0

–0.1

–0.2

–0.3

–0.4

–0.5

–1.0

–1.5

–2.0

0

262144

524288

786432 1048576

0

262144

524288

786432 1048576

524279 524283 524287 524291 524295

OUTPUT CODE

237820 G01

237820 G02

237820 G03

THD, Harꢀonics

128k Point FFT f_S= 1Msps,

f_IN= 2kHz

vs Input Frequency

SNR, SINAD vs Input Frequency

0

–20

108

106

104

102

100

98

–90

SNR = 104dB

THD

2ND

3RD

–95

–100

–105

–110

–115

–120

–125

–130

–135

–140

THD = –128dB

SINAD = 104dB

SFDR = 132dB

SNR

–40

–60

–80

SINAD

–100

–120

–140

–160

–180

96

94

92

0

100

200

300

400

500

0

25 50 75 100 125 150 175 200

0

25 50 75 100 125 150 175 200

FREQUENCY (kHz)

237820 G05

237820 G06

237820 G04

SNR, SINAD vs Input level,

f_IN= 2kHz

SNR, SINAD vs Reference

Voltage, f_IN= 2kHz

THD, Harꢀonics vs Reference

Voltage, f_IN= 2kHz

105.0

104.5

104.0

103.5

103.0

105

104

103

102

101

100

99

–110

–115

–120

–125

–130

–135

–140

THD

3RD

SNR

SINAD

98

97

96

2ND

95

–40

–30

–20

–10

0

2.5

3.0

3.5

4.0

4.5

5.0

2.5

3.0

3.5

4.0

4.5

5.0

INPUT LEVEL (dB)

REFERENCE VOLTAGE (V)

237820 G07

237820 G08

237820 G09

237820f

6

For more information www.linear.com/LTC2378-20

LTC2378-20

Typical perForMance characTerisTics ^T_A^{= 2.°C, V}_DD= 20.V, OV_DD= 20.V, V_CM= 20.V,

REF = .V, f_SMPꢁ= 1Msps, unless otherwise noted0

SNR, SINAD vs Teꢀperature,

f_IN= 2kHz

THD, Harꢀonics vs Teꢀperature,

f_IN= 2kHz

INꢁ vs Teꢀperature

–120

–125

–130

–135

–140

2.0

1.5

106

105

104

103

102

101

100

SNR

1.0

MAX INL

MIN INL

0.5

SINAD

THD

0

3RD

2ND

–0.5

–1.0

–1.5

–2.0

–55 –35 –15

5

25 45 65 85 105 125

–55 –35 –15

5

25 45 65 85 105 125

–55 –35 –15

5

25 45 65 85 105 125

TEMPERATURE (°C)

237820 G11

237820 G12

237820 G10

Supply Current vs Teꢀperature

Full-Scale Error vs Teꢀperature

Offset Error vs Teꢀperature

4

3

10

9

8

7

6

5

4

3

2

1

0

20

15

I

VDD

2

10

1

5

–FS

+FS

0

–1

–2

–3

–4

–5

–10

–15

–20

I

REF

I

OVDD

–55 –35 –15

5

25 45 65 85 105 125

–55 –35 –15

5

25 45 65 85 105 125

–55 –35 –15

5

25 45 65 85 105 125

TEMPERATURE (°C)

237820 G14

237820 G15

237820 G13

Reference Current

vs Reference Voltage

Shutdown Current vs Teꢀperature

CMRR vs Input Frequency

45

40

35

30

25

20

15

10

5

100

95

90

85

80

75

70

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

I

+ I

VDD OVDD REF

0

2.5

3.0

3.5

4.0

4.5

5.0

0

100

200

300

400

500

–50 –25

0

25

50

75 100 125

REFERENCE VOLTAGE (V)

FREQUENCY (kHz)

TEMPERATURE (°C)

237820 G16

237820 G17

237820 G18

237820f

7

For more information www.linear.com/LTC2378-20

LTC2378-20

pin FuncTions

CHAIN ꢂPin 1): Chain Mode Selector Pin. When low, the

LTC2378-20 operates in normal mode and the RDL/SDI

input pin functions to enable or disable SDO. When high,

the LTC2378-20 operates in chain mode and the RDL/SDI

pin functions as SDI, the daisy-chain serial data input.

BUSY ꢂPin 11): BUSY Indicator. Goes high at the start of

a new conversion and returns low when the conversion

has finished. Logic levels are determined by OV .

DD

RDꢁ/SDI ꢂPin 12): When CHAIN is low, the part is in Nor-

mal Mode and the pin is treated as a bus enabling input.

When CHAIN is high, the part is in chain mode and the

pin is treated as a serial data input pin where data from

another ADC in the daisy chain is input. Logic levels are

Logic levels are determined by OV .

DD

V

ꢂPin 2): 2.5V Power Supply. The range of V is

DD

2.375Vto2.625V. BypassV toGNDwitha10µFceramic

DD

capacitor.

determined by OV .

DD

GND ꢂPins 3, 6, 1± and 16): Ground.

SCKꢂPin13):SerialDataClockInput.WhenSDOisenabled,

the conversion result or daisy-chain data from another

ADC is shifted out on the rising edges of this clock MSB

+

–

IN , IN ꢂPins 4, .): Positive and Negative Differential

Analog Inputs.

first. Logic levels are determined by OV .

DD

REF ꢂPin 7): Reference Input. The range of REF is 2.5V

to 5.1V. This pin is referred to the GND pin and should be

decoupledcloselytothepinwitha47µFceramiccapacitor

(X7R, 1210 size, 10V rating).

SDOꢂPin14):SerialDataOutput. Theconversionresultor

daisy-chain data is output on this pin on each rising edge

of SCK MSB first. The output data is in 2’s complement

format. Logic levels are determined by OV .

DD

REF/DGC ꢂPin 8): When tied to REF, digital gain compres-

OV ꢂPin 1.): I/O Interface Digital Power. The range of

DD

sion is disabled and the LTC2378-20 defines full-scale ac-

OV is 1.71V to 5.25V. This supply is nominally set to

DD

cordingtothe V analoginputrange.WhentiedtoGND,

REF

the same supply as the host interface (1.8V, 2.5V, 3.3V,

digital gain compression is enabled and the LTC2378-20

or 5V). Bypass OV to GND with a 0.1µF capacitor.

DD

defines full-scale with inputs that swing between 10% and

90% of the V analog input range.

GND ꢂExposed Pad Pin 17 – DFNPackage Only): Ground.

Exposedpadmustbesoldereddirectlytothegroundplane.

REF

CNV ꢂPin 9): Convert Input. A rising edge on this input

powers up the part and initiates a new conversion. Logic

levels are determined by OV .

DD

FuncTional block DiagraM

V

= 2.5V

DD

OV = 1.8V to 5V

DD

REF = 5V

CHAIN

SDO

RDL/SDI

SCK

+

IN

SPI

PORT

20-BIT SAMPLING ADC

–

IN

CNV

BUSY

REF/DGC

CONTROL LOGIC

GND

237820 BD01

237820f

8

For more information www.linear.com/LTC2378-20

LTC2378-20

TiMing DiagraM

Conversion Tiꢀing Using the Serial Interface

CHAIN, RDL/SDI = 0

CNV

POWER-DOWN AND ACQUIRE

CONVERT

BUSY

SCK

D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

SDO

237820 TD01

applicaTions inForMaTion

OVERVIEW

CONVERTER OPERATION

The LTC2378-20 is a low noise, low power, high speed

20-bit successive approximation register (SAR) ADC.

Operating from a single 2.5V supply, the LTC2378-20

The LTC2378-20 operates in two phases. During the ac-

quisition phase, the charge redistribution capacitor D/A

+

–

converter (CDAC) is connected to the IN and IN pins

to sample the differential analog input voltage. A rising

edge on the CNV pin initiates a conversion. During the

conversionphase,the20-bitCDACissequencedthrougha

successiveapproximationalgorithm,effectivelycomparing

the sampled input with binary-weighted fractions of the

supports a large and flexible V fully differential input

REF

range with V ranging from 2.5V to 5.1V, making it ideal

REF

for high performance applications which require a wide

dynamic range. The LTC2378-20 achieves 2ppm INL

maximum, no missing codes at 20 bits and 104dB SNR.

reference voltage (e.g. V /2, V /4 … V /1048576)

REF

Fast 1Msps throughput with no cycle latency makes the

LTC2378-20 ideally suited for a wide variety of high speed

applications.Aninternaloscillatorsetstheconversiontime,

easing external timing considerations. The LTC2378-20

dissipatesonly21mWat1Msps,whileanautopower-down

feature is provided to further reduce power dissipation

during inactive periods.

usingthedifferentialcomparator.Attheendofconversion,

the CDAC output approximates the sampled analog input.

The ADC control logic then prepares the 20-bit digital

output code for serial transfer.

TRANSFER FUNCTION

The LTC2378-20 digitizes the full-scale voltage of 2 × REF

The LTC2378-20 features a unique digital gain compres-

sion(DGC)function,whicheliminatesthedriveramplifier’s

negative supply while preserving the full resolution of the

ADC. When enabled, the ADC performs a digital scaling

20

into 2 levels, resulting in an LSB size of 9.5µV with

REF = 5V. Note that 1 LSB at 20 bits is approximately

1ppm. The ideal transfer function is shown in Figure 2.

The output data is in 2’s complement format.

function that maps zero-scale code from 0V to 0.1 • V

REF

and full-scale code from V

to 0.9 • V . For a typical

REF

reference voltage of 5V, the full-scale input range is now

0.5V to 4.5V, which provides adequate headroom for

powering the driving amplifier from a single 5.5V supply.

ANAꢁOG INPUT

The analog inputs of the LTC2378-20 are fully differential

in order to maximize the signal swing that can be digitized.

Theanaloginputscanbemodeledbytheequivalentcircuit

237820f

9

For more information www.linear.com/LTC2378-20

LTC2378-20

applicaTions inForMaTion

tling of the analog signal during the acquisition phase. It

also provides isolation between the signal source and the

ADC input currents.

011...111

BIPOLAR

ZERO

011...110

000...001

000...000

111...111

111...110

Noise and Distortion

The noise and distortion of the buffer amplifier and signal

sourcemustbeconsideredsincetheyaddtotheADCnoise

and distortion. Noisy input signals should be filtered prior

to the buffer amplifier input with an appropriate filter to

minimizenoise.Thesimple1-poleRClowpassfilter(LPF1)

shown in Figure 4 is sufficient for many applications.

100...001

100...000

FSR = +FS – –FS

1LSB = FSR/1048576 ≈ 1ppm

–1 0V

LSB

1

LSB

–FSR/2

FSR/2 – 1LSB

INPUT VOLTAGE (V)

237820 F02

LPF2

Figure 20 ꢁTC2378-2± Transfer Function

6800pF

SINGLE-ENDED-

10Ω

shown in Figure 3. The diodes at the input provide ESD

protection. In the acquisition phase, each input sees ap-

LPF1

INPUT SIGNAL

+

–

IN

500Ω

3300pF

LTC2378-20

proximately 45pF (C ) from the sampling CDAC in series

IN

6600pF

IN

10Ω

with 40Ω (R ) from the on-resistance of the sampling

ON

237820 F04

SINGLE-ENDED- 6800pF

TO-DIFFERENTIAL

DRIVER

switch. Any unwanted signal that is common to both

inputs will be reduced by the common mode rejection of

the ADC. The inputs draw a current spike while charging

BW = 48kHz

BW = 1.2MHz

Figure 40 Input Signal Chain

the C capacitors during acquisition. During conversion,

IN

the analog inputs draw only a small leakage current.

A coupling filter network (LPF2) should be used between

thebufferandADCinputtominimizedisturbancesreflected

into the buffer from sampling transients. Long RC time

constants at the analog inputs will slow down the settling

of the analog inputs. Therefore, LPF2 typically requires a

widerbandwidththanLPF1. Thisfilteralsohelpsminimize

the noise contribution from the buffer. A buffer amplifier

with a low noise density must be selected to minimize

degradation of the SNR.

INPUT DRIVE CIRCUITS

Alowimpedancesourcecandirectlydrivethehighimped-

ance inputs of the LTC2378-20 without gain error. A high

impedance source should be buffered to minimize settling

time during acquisition and to optimize ADC linearity. For

best performance, a buffer amplifier should be used to

drive the analog inputs of the LTC2378-20. The amplifier

provides low output impedance, which produces fast set-

Highqualitycapacitorsandresistorsshouldbeusedinthe

RCfilterssincethesecomponentscanadddistortion.NPO

and silver mica type dielectric capacitors have excellent

linearity. Carbon surface mount resistors can generate

distortion from self heating and from damage that may

occurduringsoldering.Metalfilmsurfacemountresistors

are much less susceptible to both problems.

REF

C

45pF

IN

R

ON

40Ω

+

IN

BIAS

VOLTAGE

REF

C

45pF

IN

R

40Ω

ON

Input Currents

–

One of the biggest challenges in coupling an amplifier to

the LTC2378-20 is in dealing with current spikes drawn

by the ADC inputs at the start of each acquisition phase.

237820 F03

Figure 30 The Equivalent Circuit for the

Differential Analog Input of the ꢁTC2378-2±

237820f

10

For more information www.linear.com/LTC2378-20

LTC2378-20

applicaTions inForMaTion

The input leakage currents of the LTC2378-20 should

also be considered when designing the input drive circuit,

because source impedances will convert input leakage

currentstoanaddedinputvoltageerror. Theinputleakage

currents,bothcommonmodeanddifferential,aretypically

extremely small over the entire operating temperature

range. Figure 6 shows input leakage currents over tem-

perature for a typical part.

The ADC inputs may be modeled as a switched capacitor

load of the drive circuit. A drive circuit may rely partially

on attenuating switched-capacitor current spikes with

small filter capacitors C

placed directly at the ADC

FILT

inputs, and partially on the driver amplifier having suffi-

cient bandwidth to recover from the residual disturbance.

Amplifiers optimized for DC performance may not have

sufficientbandwidthtofullyrecoverattheADC’smaximum

conversionrate, whichcanproducenonlinearityandother

errors. Coupling filter circuits may be classified in three

broad categories:

+

LTC2378-20

IN

R

EQ

C

FILT >> 45pF

BIAS

VOLTAGE

–

IN

Fully Settled – This case is characterized by filter time

constants and an overall settling time that is consider-

ably shorter than the sample period. When acquisition

begins, the coupling filter is disturbed. For a typical first

order RC filter, the disturbance will look like an initial step

with an exponential decay. The amplifier will have its own

response to the disturbance, which may include ringing. If

the input settles completely (to within the accuracy of the

LTC2378-20),thedisturbancewillnotcontributeanyerror.

R

EQ

FILT >> 45pF

237820 F05

1

R_EQ

=

f

_SMPL•45pF

Figure .0 Equivalent Circuit for the Differential Analog

Input of the ꢁTC2378-2± at 1Msps

30

PartiallySettled–Inthiscase, thebeginningofacquisition

causes a disturbance of the coupling filter, which then

begins to settle out towards the nominal input voltage.

However, acquisition ends (and the conversion begins)

before the input settles to its final value. This generally

produces a gain error, but as long as the settling is linear,

no distortion is produced. The coupling filter’s response

is affected by the amplifier’s output impedance and other

parameters. A linear settling response to fast switched-

capacitor current spikes can NOT always be assumed for

precision, low bandwidth amplifiers. The coupling filter

serves to attenuate the current spikes’ high-frequency

energy before it reaches the amplifier.

20

10

DIFFERENTIAL

0

COMMON

–10

–55 –35 –15

5

25

45

65

85

TEMPERATURE (°C)

237820 F06

Figure 60 Coꢀꢀon Mode and Differential Input ꢁeakage Current

over Teꢀperature

Let R and R be the source impedances of the dif-

FullyAveraged–Ifthecouplingfiltercapacitors(C )atthe

S1

S2

FILT

ferential input drive circuit shown in Figure 7, and let I

ADCinputsaremuchlargerthantheADC’ssamplecapacitors

(45pF), then the sampling glitch is greatly attenuated. The

driving amplifier effectively only sees the average sampling

current, whichisquitesmall. At1Msps, theequivalentinput

resistance is approximately 22k (as shown in Figure 5), a

benignresistiveloadformostprecisionamplifiers.However,

resistive voltage division will occur between the coupling

filter’s DC resistance and the ADC’s equivalent (switched-

capacitor) input resistance, thus producing a gain error.

L1

and I be the leakage currents flowing out of the ADC’s

analog inputs. The voltage error, V , due to the leakage

L2

E

currents can be expressed as:

R_S1+R_S2

I_L1+I_L2

V_E=

• I –I + R –R

•

S2

(

)

(

)

L1 L2

S1

2

The common mode input leakage current, (I + I )/2, is

L1

L2

typically extremely small (Figure 6) over the entire operat-

237820f

11

For more information www.linear.com/LTC2378-20

LTC2378-20

applicaTions inForMaTion

Single-Ended-to-Differential Conversion

I

L1

R

S1

+

IN

+

For single-ended input signals, a single-ended-to-

differential conversion circuit must be used to produce

a differential signal at the inputs of the LTC2378-20. The

LT6203ADCdriverisrecommendedforperformingsingle-

ended-to-differential conversions. The LT6203 is flexible

and may be configured to convert single-ended signals

of various amplitudes to the 5V differential input range

of the LTC2378-20.

LTC2378-20

V

–

E

–

IN

R

S2

I

L2

237820 F07

Figure 70 Source Iꢀpedances of a Driver and Input ꢁeakage

Currents of the ꢁTC2378-2±

ing temperature range and common mode input voltage

range. Thus, any reasonable mismatch (below 5%) of the

Figure 9a shows the LT6203 being used to convert a 0V to

5Vsingle-endedinputsignal.Inthiscase,thefirstamplifier

is configured as a unity gain buffer and the single-ended

inputsignaldirectlydrivesthehigh-impedanceinputofthe

amplifier. As shown in the FFT of Figure 9b, the LT6203

drivestheLTC2378-20tonearfulldatasheetperformance.

sourceimpedancesR andR willcauseonlyanegligible

S1

S2

error. The differential input leakage current, (I – I ),

L1

IN

L2

REF

dependsontemperatureandismaximumwhenV =V

,

as shown in Figure 6. The differential leakage current is

also typically very small, and its nonlinear component is

even smaller. Only the nonlinear component will impact

the ADC’s linearity.

499Ω

For optimal performance, it is recommended that the

LT6203

5V

0V

6

5

–

+

source impedances, R and R , be between 10Ω and

S1

S2

OUT2

OUT1

7

1

5V

0V

50Ω and with 1% tolerance. For source impedances in

3

2

+

–

this range, the voltage and temperature coefficients of

5V

0V

R

and R are usually not critical. The guaranteed AC

S2

S1

and DC specifications are tested with 10Ω source imped-

ances, and the specifications will gradually degrade with

increased source impedances due to incomplete settling

of the inputs.

249Ω

+

–

V

= REF/2

10µF

CM

237820 F09a

Fully Differential Inputs

Figure 9a0 ꢁT62±3 Converting a ±V to .V Single-Ended

Signal to a ±.V Differential Input Signal

A low distortion fully differential signal source driven

through the LT6203 configured as two unity gain buffers

as shown in Figure 8 can be used to get the full data sheet

distortion performance of –125dB.

0

SNR = 104dB

–20

–40

THD = –112.7dB

SINAD = 103.6dB

SFDR = 115dB

5V

LT6203

–60

5V

3

2

+

–

1

7

–80

0V

5V

–100

–120

–140

–160

–180

5V

0V

5

6

+

–

0V

237820 F08

0

100

200

300

400

500

Figure 80 ꢁT62±3 Buffering a Fully Differential Signal Source

FREQUENCY (kHz)

237820 F09b

Figure 9b0 128k Point FFT Plot with f_IN= 2kHz

for Circuit Shown in Figure 9a

237820f

12

For more information www.linear.com/LTC2378-20

LTC2378-20

applicaTions inForMaTion

Digital Gain Coꢀpression

tion and reducing complexity. As shown in the FFT of

Figure 11b, the single 5V supply solution can achieve up

to 100dB of SNR.

The LTC2378-20 offers a digital gain compression (DGC)

feature which defines the full-scale input swing to be be-

tween 10% and 90% of the V analog input range. To

REF

DC Accuracy

enable digital gain compression, bring the REF/DGC pin

low. This feature allows the SAR ADC driver to be powered

off of a single positive supply since each input swings

between 0.5V and 4.5V as shown in Figure 10. Needing

only one positive supply to power the SAR ADC driver

results in additional power savings for the entire system.

Manydrivercircuitspresentedinthisdatasheetemphasize

ACperformance(DistortionandSignaltoNoiseRatio),and

the amplifiers are chosen accordingly. The very low level

ofdistortionisadirectconsequenceoftheexcellentINLof

the LTC2378-20, and this property can be exploited in DC

applicationsaswell.NotethatwhiletheLT6362andLT6203

are characterized by excellent AC specifications, their DC

specifications do not match those of the LTC2378-20. The

offsetoftheseamplifiers,forexample,ismorethan500μV

under certain conditions. In contrast, the LTC2378-20 has

a guaranteed maximum offset error of 130µV (typical drift

0.007ppm/°C), and a guaranteed maximum full-scale

error of 100ppm (typical drift 0.05ppm/°C). Low drift

is important to maintain accuracy over wide temperature

ranges in a calibrated system.

With DGC enabled, the LTC2378-20 can be driven by the

low power LTC6362 differential driver which is powered

fromasingle5Vsupply.Figure11ashowshowtoconfigure

the LTC6362 to accept a 3.28V true bipolar single-ended

input signal and level shift the signal to the reduced input

range of the LTC2378-20 when digital gain compression

is enabled. When paired with the LTC6655-4.096 for the

reference, the entire signal chain solution can be powered

from a single 5V supply, minimizing power consump-

5V

Amplifiers have to be selected very carefully to provide a

20-bit accurate DC signal chain. A large-signal open-loop

gain of at least 126dB may be required to ensure 1ppm

linearity for amplifiers configured for a gain of negative

1. However, less gain is sufficient if the amplifier’s gain

characteristic is known to be (mostly) linear. An ampli-

fier’s offset versus signal level must be considered for

amplifiers configured as unity gain buffers. For example,

4.5V

0.5V

0V

237820 F10

Figure 1±0 Input Swing of the ꢁTC2378 with Gain

Coꢀpression Enabled

5V

V

LTC6655-4.096

0

–20

IN

SNR = 100dB

THD = –110dB

SINAD = 99.7dB

SFDR = 113dB

OUT_F

OUT_S

4.096V

–40

1k

47µF

–60

1k

V

CM

3.69V

0.41V

2.5V

1k

10µF

–80

3

4

+

–

V

6800pF

–100

–120

–140

–160

–180

REF

V

1k

DD

LTC2378-20

REF/DGC

+

–

8

1

35.7Ω

3300pF

35.7Ω

IN

+

LTC6362

3.28V

0V

–3.28V

1k

–

5

6

3.69V

2

V

CM

237820 F11a

V

6800pF

0

100

200

300

400

500

0.41V

FREQUENCY (kHz)

1k

237820 F11b

Figure 11a0 ꢁTC6362 Configured to Accept a ±3028V Input Signal While Running froꢀ

a Single .V Supply When Digital Gain Coꢀpression Is Enabled in the ꢁTC2378-2±

Figure 11b0 64k Point FFT Plot

with f_IN= 2kHz for Circuit Shown

in Figure 11a

237820f

13

For more information www.linear.com/LTC2378-20

LTC2378-20

applicaTions inForMaTion

1ppm linearity may require that the offset is known to

vary less than 5μV for a 5V swing. However, greater offset

variations may be acceptable if the relationship is known

to be (mostly) linear. Unity-gain buffer amplifiers typically

require substantial headroom to the power supply rails for

best performance. Inverting amplifier circuits configured

to minimize swing at the amplifier input terminals may

perform better with only little headroom than unity-gain

buffer amplifiers. The linearity and thermal properties

of an inverting amplifier’s feedback network should be

considered carefully to ensure DC accuracy.

I

= Q

/t . The DC current draw of the REF pin,

CONV CYC

REF

, depends on the sampling rate and output code. If

the LTC2378-20 is used to continuously sample a signal

at a constant rate, the LTC6655-5 will keep the deviation

of the reference voltage over the entire code span to less

than 0.5LSBs.

When idling, the REF pin on the LTC2378-20 draws only

a small leakage current (< 1µA). In applications where a

burst of samples is taken after idling for long periods as

shown in Figure 12, I quickly goes from approximately

REF

0µA to a maximum of 1.1mA at 1Msps. This step in DC

currentdrawtriggersatransient responseinthereference

that must be considered since any deviation in the refer-

ence output voltage will affect the accuracy of the output

code. In applications where the transient response of the

reference is important, the fast settling LTC6655-5 refer-

ence is also recommended.

ADC REFERENCE

The LTC2378-20 requires an external reference to define

its input range. A low noise, low temperature drift refer-

enceiscriticaltoachievingthefulldatasheetperformance

of the ADC. Linear Technology offers a portfolio of high

performance references designed to meet the needs of

manyapplications. Withitssmallsize, lowpowerandhigh

accuracy, the LTC6655-5 is particularly well suited for

use with the LTC2378-20. The LTC6655-5 offers 0.025%

(max) initial accuracy and 2ppm/°C (max) temperature

coefficient for high precision applications.

DYNAMIC PERFORMANCE

Fast Fourier Transform (FFT) techniques are used to test

the ADC’s frequency response, distortion and noise at the

ratedthroughput.Byapplyingalowdistortionsinewaveand

analyzingthedigitaloutputusinganFFT algorithm,theADC’s

spectralcontentcanbeexaminedforfrequenciesoutsidethe

fundamental. The LTC2378-20 provides guaranteed tested

limits for both AC distortion and noise measurements.

WhenchoosingabypasscapacitorfortheLTC6655-5, the

capacitor’s voltage rating, temperature rating, and pack-

age size should be carefully considered. Physically larger

capacitorswithhighervoltageandtemperatureratingstend

to provide a larger effective capacitance, better filtering

the noise of the LTC6655-5, and consequently producing

a higher SNR. Therefore, we recommend bypassing the

LTC6655-5 with a 47μF ceramic capacitor (X7R, 1210

size, 10V rating) close to the REF pin.

Signal-to-Noise and Distortion Ratio ꢂSINAD)

The signal-to-noise and distortion ratio (SINAD) is the

ratio between the RMS amplitude of the fundamental input

frequency and the RMS amplitude of all other frequency

components at the A/D output. The output is band-limited

to frequencies from above DC and below half the sampling

frequency. Figure 13 shows that the LTC2378-20 achieves

a typical SINAD of 104dB at a 1MHz sampling rate with a

2kHz input.

TheREFpinoftheLTC2378-20drawscharge(Q

)from

CONV

the 47µF bypass capacitor during each conversion cycle.

The reference replenishes this charge with a DC current,

CNV

IDLE

PERIOD

IDLE

PERIOD

237820 F12

Figure 120 CNV Waveforꢀ Showing Burst Saꢀpling

237820f

14

For more information www.linear.com/LTC2378-20

LTC2378-20

applicaTions inForMaTion

Signal-to-Noise Ratio ꢂSNR)

Power Supply Sequencing

The signal-to-noise ratio (SNR) is the ratio between the

RMS amplitude of the fundamental input frequency and

the RMS amplitude of all other frequency components

except the first five harmonics and DC. Figure 13 shows

that the LTC2378-20 achieves a typical SNR of 104dB at

a 1MHz sampling rate with a 2kHz input.

The LTC2378-20 does not have any specific power supply

sequencing requirements. Care should be taken to adhere

to the maximum voltage relationships described in the

Absolute Maximum Ratings section. The LTC2378-20

has a power-on-reset (POR) circuit that will reset the

LTC2378-20 at initial power-up or whenever the power

supply voltage drops below 1V. Once the supply voltage

re-enters the nominal supply voltage range, the POR will

reinitialize the ADC. No conversions should be initiated

until 200µs after a POR event to ensure the reinitialization

period has ended. Any conversions initiated before this

time will produce invalid results.

0

SNR = 104dB

–20

–40

THD = –128dB

SINAD = 104dB

SFDR = 132dB

–60

–80

–100

–120

–140

–160

–180

TIMING AND CONTROꢁ

CNV Tiꢀing

0

100

200

300

400

500

The LTC2378-20 conversion is controlled by CNV. A ris-

ing edge on CNV will start a conversion and power up

the LTC2378-20. Once a conversion has been initiated,

it cannot be restarted until the conversion is complete.

For optimum performance, CNV should be driven by a

clean low jitter signal. Converter status is indicated by the

BUSY output which remains high while the conversion is

in progress. To ensure that no errors occur in the digitized

results, any additional transitions on CNV should occur

within 40ns from the start of the conversion or after the

conversion has been completed. Once the conversion has

completed, the LTC2378-20 powers down and begins

acquiring the input signal.

FREQUENCY (kHz)

237820 F13

Figure 130 128k Point FFT Plot with f_IN= 2kHz of the ꢁTC2378-2±

Total Harꢀonic Distortion ꢂTHD)

TotalHarmonicDistortion(THD)istheratiooftheRMSsum

ofallharmonicsoftheinputsignaltothefundamentalitself.

The out-of-band harmonics alias into the frequency band

between DC and half the sampling frequency (f

THD is expressed as:

/2).

SMPL

V2²+ V3²+ V4²+…+ V_N²

THD=20log

V1

Internal Conversion Clock

where V1 is the RMS amplitude of the fundamental fre-

The LTC2378-20 has an internal clock that is trimmed to

achieveamaximumconversiontimeof675ns.Withamin-

imum acquisition time of 312ns, throughput performance

of 1Msps is guaranteed without any external adjustments.

quencyandV2throughV aretheamplitudesofthesecond

N

through Nth harmonics.

POWER CONSIDERATIONS

Auto Power-Down

The LTC2378-20 provides two power supply pins: the

The LTC2378-20 automatically powers down after a

conversion has been completed and powers up once a

new conversion is initiated on the rising edge of CNV.

During power down, data from the last conversion can

be clocked out. To minimize power dissipation during

2.5V power supply (V ), and the digital input/output

DD

interface power supply (OV ). The flexible OV supply

DD

allows the LTC2378-20 to communicate with any digital

logic operating between 1.8V and 5V, including 2.5V and

3.3V systems.

237820f

15

For more information www.linear.com/LTC2378-20

LTC2378-20

applicaTions inForMaTion

power down, disable SDO and turn off SCK. The auto

power-down feature will reduce the power dissipation of

the LTC2378-20 as the sampling frequency is reduced.

Since power is consumed only during a conversion, the

LTC2378-20remainspowered-downforalargerfractionof

DIGITAꢁ INTERFACE

The LTC2378-20 has a serial digital interface. The flexible

OV supplyallowstheLTC2378-20tocommunicatewith

DD

any digital logic operating between 1.8V and 5V, including

2.5V and 3.3V systems.

the conversion cycle (t ) at lower sample rates, thereby

CYC

The serial output data is clocked out on the SDO pin when

anexternalclockisappliedtotheSCKpinifSDOisenabled.

Clocking out the data after the conversion will yield the

best performance. With a shift clock frequency of at least

64MHz, a 1Msps throughput is still achieved. The serial

output data changes state on the rising edge of SCK and

can be captured on the falling edge or next rising edge of

SCK. D19 remains valid until the first rising edge of SCK.

reducing the average power dissipation which scales with

the sampling rate as shown in Figure 14.

10

9

8

7

6

I

VDD

5

4

3

The serial interface on the LTC2378-20 is simple and

straightforwardtouse.Thefollowingsectionsdescribethe

operationoftheLTC2378-20. Severalmodesareprovided

depending on whether a single or multiple ADCs share the

SPI bus or are daisy chained.

I

OVDD

2

1

0

I

REF

0

100 200 300 400 500 600 700 800 9001000

SAMPLING RATE (kHz)

237820 F14

Figure 140 Power Supply Current of the ꢁTC2378-2±

Versus Saꢀpling Rate

237820f

16

For more information www.linear.com/LTC2378-20

LTC2378-20

TiMing DiagraMs

Norꢀal Mode, Single Device

Figure 15 shows a single LTC2378-20 operated in normal

mode with CHAIN and RDL/SDI tied to ground. With RDL/

SDI grounded, SDO is enabled and the MSB(D19) of the

new conversion data is available at the falling edge of

BUSY.ThisisthesimplestwaytooperatetheLTC2378-20.

When CHAIN = 0, the LTC2378-20 operates in normal

mode. In normal mode, RDL/SDI enables or disables the

serial data output pin SDO. If RDL/SDI is high, SDO is in

high impedance. If RDL/SDI is low, SDO is driven.

CONVERT

DIGITAL HOST

IRQ

CNV

CHAIN

BUSY

LTC2378-20

SCK

RDL/SDI

SDO

DATA IN

CLK

237820 F15a

POWER-DOWN

AND ACQUIRE

CONVERT

POWER-DOWN AND ACQUIRE

CONVERT

CHAIN = 0

RDL/SDI = 0

t

CYC

t

CNVH

t

CNVL

CNV

t

= t

– t

ACQ CYC CONV BUSYLH

t

CONV

ACQ

BUSY

t

SCK

t

BUSYLH

t

QUIET

SCKH

1

2

3

18

19

20

SCK

SDO

t

SCKL

HSDO

t

DSDO

DSDOBUSYL

D19

D18

D17

D1

D0

237820 F15

Figure 1.0 Using a Single ꢁTC2378-2± in Norꢀal Mode

237820f

17

For more information www.linear.com/LTC2378-20

LTC2378-20

TiMing DiagraMs

Norꢀal Mode, Multiple Devices

Since SDO is shared, the RDL/SDI input of each ADC must

be used to allow only one LTC2378-20 to drive SDO at a

timeinordertoavoidbusconflicts. AsshowninFigure16,

the RDL/SDI inputs idle high and are individually brought

low to read data out of each device between conversions.

When RDL/SDI is brought low, the MSB of the selected

device is output onto SDO.

Figure 16 shows multiple LTC2378-20 devices operating

in normal mode (CHAIN = 0) sharing CNV, SCK and SDO.

By sharing CNV, SCK and SDO, the number of required

signals to operate multiple ADCs in parallel is reduced.

RDL

B

A

CONVERT

CNV

CHAIN

BUSY

SDO

IRQ

CHAIN

LTC2378-20

B

LTC2378-20

A

DIGITAL HOST

SDO

RDL/SDI

SCK

DATA IN

CLK

237820 F16a

POWER-DOWN

AND ACQUIRE

CONVERT

POWER-DOWN AND ACQUIRE

CHAIN = 0

t

CNVL

CNV

t

CONV

BUSY

t

BUSYLH

RDL/SDI

A

B

RDL/SDI

t

SCK

t

QUIET

SCKH

21

SCK

SDO

1

2

3

18

19

20

22

23

38

39

40

t

SCKL

HSDO

t

DSDO

DIS

t

EN

Hi-Z

D19

A

D18

D17

D1

A

D0

D19

D18

D17

D1

B

D0

B

A

B

237820 F16

Figure 160 Norꢀal Mode With Multiple Devices Sharing CNV, SCK and SDO

237820f

18

For more information www.linear.com/LTC2378-20

LTC2378-20

TiMing DiagraMs

Chain Mode, Multiple Devices

This is useful for applications where hardware constraints

may limitthe numberoflinesneeded to interface to a large

number of converters. Figure 17 shows an example with

two daisy-chained devices. The MSB of converter A will

appear at SDO of converter B after 20 SCK cycles. The

MSB of converter A is clocked in at the SDI/RDL pin of

converter B on the rising edge of the first SCK.

When CHAIN = OV , the LTC2378-20 operates in chain

DD

mode.Inchainmode,SDOisalwaysenabledandRDL/SDI

serves as the serial data input pin (SDI) where daisy-chain

data output from another ADC can be input.

CONVERT

OV

DD

CNV

CHAIN

DIGITAL HOST

LTC2378-20

RDL/SDI

SDO

RDL/SDI

BUSY

SDO

IRQ

A

B

DATA IN

SCK

CLK

237820 F17a

POWER-DOWN

AND ACQUIRE

CONVERT

POWER-DOWN AND ACQUIRE

CONVERT

CHAIN = OV

DD

RDL/SDI = 0

A

t

CYC

t

CNVL

CNV

BUSY

t

CONV

t

BUSYLH

SCK

t

SCKCH

t

QUIET

SCKH

1

2

3

18

19

20

21

22

38

39

40

t

SCKL

t

HSDO

SSDISCK

t

DSDO

HSDISCK

SDO = RDL/SDI

A

B

D19

D18

D17

D1

D0

A

t

DSDOBUSYL

D19

D17

D1

B

D19

D18

D1

A

D0

A

SDO

B

A

B

237820 F17

Figure 170 Chain Mode Tiꢀing Diagraꢀ

237820f

19

For more information www.linear.com/LTC2378-20

LTC2378-20

boarD layouT

To obtain the best performance from the LTC2378-20

a printed circuit board is recommended. Layout for the

printed circuit board (PCB) should ensure the digital and

analog signal lines are separated as much as possible.

In particular, care should be taken not to run any digital

clocks or signals alongside analog signals or underneath

the ADC.

Recoꢀꢀended ꢁayout

ThefollowingisanexampleofarecommendedPCBlayout.

A single solid ground plane is used. Bypass capacitors to

the supplies are placed as close as possible to the supply

pins. Low impedance common returns for these bypass

capacitors are essential to the low noise operation of the

ADC. The analog input traces are screened by ground.

For more details and information refer to DC1925A, the

evaluation kit for the LTC2378-20.

Top Silkscreen

237820f

20

For more information www.linear.com/LTC2378-20

LTC2378-20

boarD layouT

ꢁayer 1 Coꢀponent Side

237820f

21

For more information www.linear.com/LTC2378-20

LTC2378-20

boarD layouT

ꢁayer 2 Ground Plane

237820f

22

For more information www.linear.com/LTC2378-20

LTC2378-20

boarD layouT

ꢁayer 3 PWR Plane

237820f

23

For more information www.linear.com/LTC2378-20

LTC2378-20

boarD layouT

ꢁayer 4 Bottoꢀ ꢁayer

237820f

24

For more information www.linear.com/LTC2378-20

LTC2378-20

boarD layouT

Partial Scheꢀatic of Deꢀoboard

D G C R E F /

R E F

8

7

1 5

2

1

G N D

D D

V

G N D 1 6

O V

G N D

1 0

G N D

6

3

2

1

3

2

1

237820f

25

For more information www.linear.com/LTC2378-20

LTC2378-20

package DescripTion

Please refer to http://www0linear0coꢀ/designtools/packaging/ for the ꢀost recent package drawings0

DE Package

16-Lead Plastic DFN (4mm × 3mm)

(Reference LTC DWG # 05-08-ꢀ732 Rev Ø)

R = 0.ꢀꢀ5

TYP

0.40 0.ꢀ0

4.00 0.ꢀ0

(2 SIDES)

9

ꢀ6

R = 0.05

0.70 0.05

TYP

3.30 0.05

ꢀ.70 0.05

3.30 0.ꢀ0

3.60 0.05

2.20 0.05

3.00 0.ꢀ0

(2 SIDES)

PACKAGE

OUTLINE

ꢀ.70 0.ꢀ0

PIN ꢀ NOTCH

R = 0.20 OR

PIN ꢀ

0.35 × 45°

TOP MARK

CHAMFER

(SEE NOTE 6)

(DEꢀ6) DFN 0806 REV Ø

8

ꢀ

0.23 0.05

0.45 BSC

0.75 0.05

0.200 REF

0.25 0.05

0.45 BSC

3.ꢀ5 REF

0.00 – 0.05

BOTTOM VIEW—EXPOSED PAD

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

NOTE:

ꢀ. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC

PACKAGE OUTLINE MO-229

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.ꢀ5mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

237820f

26

For more information www.linear.com/LTC2378-20

LTC2378-20

package DescripTion

Please refer to http://www0linear0coꢀ/designtools/packaging/ for the ꢀost recent package drawings0

MS Package

16-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1669 Rev Ø)

4.039 0.102

(.159 .004)

0.889 0.127

(.035 .005)

(NOTE 3)

0.280 0.076

(.011 .003)

REF

16151413121110

9

5.23

(.206)

MIN

3.00 0.102

(.118 .004)

(NOTE 4)

DETAIL “A”

0° – 6° TYP

3.20 – 3.45

(.126 – .136)

4.90 0.152

(.193 .006)

0.254

(.010)

GAUGE PLANE

0.53 0.152

(.021 .006)

1 2 3 4 5 6 7 8

0.50

(.0197)

BSC

0.305 0.038

(.0120 .0015)

TYP

0.86

(.034)

REF

1.10

(.043)

MAX

DETAIL “A”

0.18

(.007)

RECOMMENDED SOLDER PAD LAYOUT

SEATING

PLANE

0.17 – 0.27

(.007 – .011)

TYP

0.1016 0.0508

(.004 .002)

0.50

(.0197)

BSC

MSOP (MS16) 1107 REV Ø

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

237820f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

For more information www.linear.com/LTC2378-20

27

LTC2378-20

Typical applicaTion

ꢁTC6362 Configured to Accept a ±3028V Input Signal While Running froꢀ a Single

.V Supply with Digital Gain Coꢀpression Enabled in the ꢁTC2378-2±

5V

V

LTC6655-4.096

IN

OUT_F

OUT_S

4.096V

1k

47µF

1k

V

CM

3.69V

2.5V

10µF

3

4

+

V

6800pF

0.41V

REF

V

DD

1k

+

–

8

1

35.7Ω

3300pF

35.7Ω

IN

+

LTC6362

LTC2378-20

REF/DGC

3.28V

0V

–3.28V

1k

–

5

6

3.69V

2

V

CM

–

237820 TA03

V

6800pF

0.41V

1k

relaTeD parTs

PART NUMBER

DESCRIPTION

COMMENTS

ADCs

LTC2379-18/LTC2378-18 18-Bit, 1.6Msps/1Msps/500ksps/250ksps Serial,

LTC2377-18/LTC2376-18 Low Power ADC

2.5V Supply, Differential Input, 101.2dB SNR, 5V Input Range, DGC,

Pin Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages

LTC2380-16/LTC2378-16 16-Bit, 2Msps/1Msps/500ksps/250ksps Serial, Low 2.5V Supply, Differential Input, 96.2dB SNR, 5V Input Range, DGC,

LTC2377-16/LTC2376-16 Power ADC

Pin Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages

LTC2369-18/LTC2368-18/ 18-Bit, 1.6Msps/1Msps/500ksps/250ksps Serial,

LTC2367-18/LTC2364-18 Low Power ADC

2.5V Supply, Pseudo-Differential Unipolar Input, 96.5dB SNR, 0V to 5V

Input Range, Pin Compatible Family in MSOP-16 and 4mm × 3mm

DFN-16 Packages

LTC2370-16/LTC2368-16 16-Bit, 2Msps/1Msps/500ksps/250ksps Serial, Low 2.5V Supply, Pseudo-Differential Unipolar Input, 94dB SNR, 0V to 5V

LTC2367-16/LTC2364-16 Power ADC

Input Range, Pin Compatible Family in MSOP-16 and 4mm × 3mm

DFN-16 Packages

LTC2389-18/LTC2389-16 18-/16-Bit, 2.5Msps Parallel/Serial, ADC

5V Supply, Pin Configurable Input Range, 99.8dB SNR, Pin Compatible

Parts in 7mm × 7mm LQFP-48 and QFN-48 Packages

DACS

LTC2756/LTC2757

LTC2641

18-Bit, Single Serial/Parallel I

SoftSpan™ DAC

DAC

1LSB INL/DNL, SSOP-28 and 7mm × 7mm LQFP-48 Packages

1LSB INL/DNL, MSOP-8 Package, 0V to 5V Output

OUT

16-/14-/12-Bit Single Serial V

OUT

LTC2630

12-/10-/8-Bit Single V

DACs

SC70 6-Pin Package, Internal Reference, 1LSB INL (12 Bits)

OUT

REFERENCES

LTC6655

Precision Low Drift Low Noise Buffered Reference

5V/2.5V, 5ppm/°C, 0.25ppm Peak-to-Peak Noise, MSOP-8 Package

5V/2.5V, 5ppm/°C, 2.1ppm Peak-to-Peak Noise, MSOP-8 Package

LTC6652

AMPꢁIFIERS

LTC6362

Low Power Rail-to-Rail Input/Output Differential

Output Amplifier/ADC Driver

Single 2.8V to 5.25V Supply, 1mA Supply Current, MSOP-8 and

3mm × 3mm DFN-8 Packages

LT6200/LT6200-5/

LT6200-10

165MHz/800MHz/1.6GHz Op Amp with

Unity Gain/AV = 5/AV = 10

Low Noise Voltage: 0.95nV/√Hz (100kHz), Low Distortion: –80dB at

1MHz, TSOT23-6 Package

LT6202/LT6203

Single/Dual 100MHz Rail-to-Rail Input/Output Noise 1.9nV√Hz, 3mA Maximum, 100MHz Gain Bandwidth, TSOT23-5, SO-8 ,

Low Power Amplifiers MSOP-8 and 3mm × 3mm DFN-8 Packages

237820f

LT 0413 • PRINTED IN USA

28 ^{LinearTechnology Corporation}

1630 McCarthy Blvd., Milpitas, CA 95035-7417

For more information www.linear.com/LTC2378-20

●

 LINEAR TECHNOLOGY CORPORATION 2013

(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC2378-20


型号：	LTC2378IMS-20PBF
厂家：	Linear
描述：	20-Bit, 1Msps, Low Power SAR ADC with 0.5ppm INL 20位， 1Msps的，低功耗SAR型ADC为0.5ppm INL
文件：	总28页 (文件大小：1062K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC2378IMS-20PBF [Linear]

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