LTC2360CTS8#PBF [Linear]
LTC2360 - 100ksps, 12-Bit Serial ADCs in TSOT-23; Package: SOT; Pins: 8; Temperature Range: 0°C to 70°C;型号: | LTC2360CTS8#PBF |
厂家: | Linear |
描述: | LTC2360 - 100ksps, 12-Bit Serial ADCs in TSOT-23; Package: SOT; Pins: 8; Temperature Range: 0°C to 70°C 转换器 模数转换器 |
文件: | 总20页 (文件大小:321K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC2360/LTC2361/LTC2362
100ksps/250ksps/500ksps,
12-Bit Serial ADCs in TSOT-23
FEATURES
DESCRIPTION
The LTC®2360/LTC2361/LTC2362 are 100ksps/250ksps/
500ksps, 12-bit, sampling A/D converters that draw only
0.5mA, 0.75mA and 1.1mA, respectively, from a single
3V supply. The supply current drops at lower sampling
rates because these devices automatically power down
after conversions. The full-scale input of the LTC2360/
n
12-Bit Resolution
n
Low Noise: 73dB SNR
n
Low Power Dissipation: 1.5mW @ 100ksps
n
100ksps/250ksps/500ksps Sampling Rates
n
Single Supply 2.35V to 3.6V Operation
n
No Data Latency
n
Sleep Mode with 0.1μA Typical Supply Current
LTC2361/LTC2362 is 0V to V or V . These ADCs are
available in tiny 6- and 8-lead TSOT-23 packages.
DD
REF
n
Dedicated External Reference (TSOT23-8)
n
1V to 3.6V Digital Output Supply (TSOT23-8)
The serial interface, tiny TSOT-23 package and extremely
high sample rate-to-power ratio make the LTC2360/
LTC2361/LTC2362 ideal for compact, low power, high
speed systems.
n
SPI/MICROWIRE™ Compatible Serial I/O
n
Guaranteed Operation from –40°C to 125°C
n
Tiny 6- and 8-Lead TSOT-23 Packages
APPLICATIONS
The high impedance single-ended analog input and the
ability to operate with reduced spans (down to 1.4V full
scale)allowdirectconnectiontosensorsandtransducersin
many applications, eliminating the need for gain stages.
n
Communication Systems
n
Data Acquisition Systems
n
Handheld Portable Devices
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
n
Uninterrupted Power Supplies
n
Battery-Operated Systems
n
Automotive
TYPICAL APPLICATION
12-Bit TSOT23-6/-8 ADC Family
DATA OUTPUT RATE
3Msps
1Msps
500ksps
250ksps
100ksps
Part Number
LTC2366 LTC2365 LTC2362 LTC2361 LTC2360
Single 3V Supply, 500ksps, 12-Bit Sampling ADC
Supply Current vs Sample Rate
1200
1000
800
V
A
= 3.6V
DD
T
= 25°C
3V
2.2μF
LTC2362
LTC2361
V
V
CONV
SCK
DD
600
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
OR SHIFT REGISTORS
LTC2362
REF
400
GND SDO
OV
LTC2360
DIGITAL OUTPUT SUPPLY
1V TO 3.6V
ANALOG INPUT
0V TO 3V
A
200
0
IN
DD
2.2μF
1
10
100
1000
236012 TA01a
SAMPLE RATE (ksps)
236012 TA01b
236012f
1
LTC2360/LTC2361/LTC2362
(Notes 1, 2)
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (V , OV )........................................4V
REF
Operating Temperature Range
DD
DD
V
and Analog Input Voltage
LTC2360C/LTC2361C/LTC2362C .............. 0°C to 70°C
LTC2360I/LTC2361I/LTC2362I.............. –40°C to 85°C
LTC2360H/LTC2361H/LTC2362H (Note 12).. –40°C to 125°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
(Note 3).........................................–0.3V to (V + 0.3V)
DD
Digital Input Voltage......................–0.3V to (V + 0.3V)
DD
Digital Output Voltage ...................–0.3V to (V + 0.3V)
DD
Power Dissipation...............................................100mW
PIN CONFIGURATION
TOP VIEW
TOP VIEW
V
1
2
8 CONV
7 SCK
6 SDO
DD
V
1
6 CONV
5 SDO
4 SCK
DD
V
REF
GND 2
GND 3
A
A
3
IN
4
5 OV
DD
IN
TS8 PACKAGE
8-LEAD PLASTIC TSOT-23
S6 PACKAGE
6-LEAD PLASTIC TSOT-23
T = 150°C, θ = 250°C/W
JMAX
T
= 150°C, θ = 250°C/W
JMAX
JA
JA
ORDER INFORMATION
Lead Free Finish
TAPE AND REEL (MINI)
LTC2362CTS8#TRMPBF
LTC2362ITS8#TRMPBF
LTC2362HTS8#TRMPBF
LTC2362CS6#TRMPBF
LTC2362IS6#TRMPBF
LTC2362HS6#TRMPBF
LTC2361CTS8#TRMPBF
LTC2361ITS8#TRMPBF
LTC2361HTS8#TRMPBF
LTC2361CS6#TRMPBF
LTC2361IS6#TRMPBF
LTC2361HS6#TRMPBF
LTC2360CTS8#TRMPBF
LTC2360ITS8#TRMPBF
LTC2360HTS8#TRMPBF
LTC2360CS6#TRMPBF
LTC2360IS6#TRMPBF
LTC2360HS6#TRMPBF
TAPE AND REEL
PART MARKING*
LTDBV
PACKAGE DESCRIPTION
8-Lead Plastic TSOT23
8-Lead Plastic TSOT23
8-Lead Plastic TSOT23
6-Lead Plastic TSOT23
6-Lead Plastic TSOT23
6-Lead Plastic TSOT23
8-Lead Plastic TSOT23
8-Lead Plastic TSOT23
8-Lead Plastic TSOT23
6-Lead Plastic TSOT23
6-Lead Plastic TSOT23
6-Lead Plastic TSOT23
8-Lead Plastic TSOT23
8-Lead Plastic TSOT23
8-Lead Plastic TSOT23
6-Lead Plastic TSOT23
6-Lead Plastic TSOT23
6-Lead Plastic TSOT23
TEMPERATURE RANGE
LTC2362CTS8#TRPBF
LTC2362ITS8#TRPBF
0°C to 70°C
LTDBV
-40°C to 85°C
-40°C to 125°C
0°C to 70°C
LTC2362HTS8#TRPBF
LTC2362CS6#TRPBF
LTC2362IS6#TRPBF
LTC2362HS6#TRPBF
LTC2361CTS8#TRPBF
LTC2361ITS8#TRPBF
LTC2361HTS8#TRPBF
LTC2361CS6#TRPBF
LTC2361IS6#TRPBF
LTC2361HS6#TRPBF
LTC2360CTS8#TRPBF
LTC2360ITS8#TRPBF
LTC2360HTS8#TRPBF
LTC2360CS6#TRPBF
LTC2360IS6#TRPBF
LTC2360HS6#TRPBF
LTDBV
LTDGP
LTDGP
LTDGP
LTDGM
LTDGM
LTDGM
LTDGN
LTDGN
LTDGN
LTDGJ
-40°C to 85°C
-40°C to 125°C
0°C to 70°C
-40°C to 85°C
-40°C to 125°C
0°C to 70°C
-40°C to 85°C
-40°C to 125°C
0°C to 70°C
LTDGJ
-40°C to 85°C
-40°C to 125°C
0°C to 70°C
LTDGJ
LTDGK
LTDGK
LTDGK
-40°C to 85°C
-40°C to 125°C
TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container.
Consult LTC Marketing for information on lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
236012f
2
LTC2360/LTC2361/LTC2362
CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Bits
l
l
l
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Transition Noise
12
(Notes 5, 6)
(Note 6)
(Note 7)
(Note 6)
(Note 6)
(Note 6)
0.25
0.25
0.25
1
1
1
LSB
LSB
LSB
RMS
l
l
l
Offset Error
3.5
2
LSB
Gain Error
0.1
LSB
LSB
Total Unadjusted Error
1.1
3.5
ANALOG INPUT The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
V
IN
Analog Input Voltage
S6 Package
TS8 Package
–0.05
–0.05
V
REF
+ 0.05
+ 0.05
V
DD
V
l
I
Analog Input Leakage Current
Analog Input Capacitance
CONV = High
1
μA
IN
C
Between Conversions
During Conversions
20
4
pF
pF
IN
l
l
V
Reference Input Voltage
TS8 Package
TS8 Package
TS8 Package
1.4
V
+ 0.05
1
V
μA
pF
ns
ns
REF
REF
DD
I
Reference Input Leakage Current
Reference Input Capacitance
C
20
1
REF
t
t
Sample-and-Hold Aperture Delay Time
Sample-and-Hold Aperture Delay Time Jitter
AP
JITTER
0.3
DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SINAD
Signal-to-(Noise + Distortion) Ratio
f
IN
f
IN
= 49kHz for LTC2360/LTC2361,
= 100kHz for LTC2362
72
dB
SNR
Signal-to-Noise Ratio
f
f
= 49kHz for LTC2360/LTC2361,
= 100kHz for LTC2362
73
–85
86
dB
dB
dB
dB
IN
IN
THD
Total Harmonic Distortion
Spurious Free Dynamic Range
Intermodulation Distortion
Full-Power Bandwidth
f
IN
f
IN
= 49kHz for LTC2360/LTC2361,
= 100kHz for LTC2362
SFDR
IMD
f
IN
f
IN
= 49kHz for LTC2360/LTC2361,
= 100kHz for LTC2362
f
IN1
f
IN1
= 97kHz, f = 100kHz for LTC2362
–75
IN2
= 47kHz, f = 49kHz for LTC2360/LTC2361
IN2
at 3dB
at 0.1dB
10
2
MHz
MHz
Full-Linear Bandwidth
SINAD ≥ 68dB
1
MHz
236012f
3
LTC2360/LTC2361/LTC2362
DIGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
CONDITIONS
2.7V < V ≤ 3.6V
MIN
TYP
MAX
UNITS
l
l
V
High Level Input Voltage
2
1.7
V
V
IH
DD
2.35V ≤ V ≤ 2.7V
DD
l
l
V
IL
Low Level Input Voltage
2.7V < V ≤ 3.6V
0.8
0.7
V
V
DD
2.35V ≤ V ≤ 2.7V
DD
l
l
I
I
High Level Input Current
Low Level Input Current
Digital Input Capacitance
High Level Output Voltage
Low Level Output Voltage
Hi-Z Output Leakage
V
= V
DD
2.5
μA
μA
pF
V
IH
IN
IN
V
= 0V
–2.5
IL
C
V
V
2
IN
l
l
l
V
V
= 2.35V to 3.6V, I
= 2.35V to 3.6V, I
= 200μA
V
DD
– 0.2
OH
OL
DD
SOURCE
= 200μA
0.2
3
V
DD
SINK
I
OZ
CONV = V
CONV = V
μA
pF
mA
mA
DD
DD
C
Hi-Z Output Capacitance
Output Source Current
Output Sink Current
4
OZ
I
I
V
= 0V
–10
10
SOURCE
SINK
OUT
OUT
V
= V
DD
POWER REQUIREMENT The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN
2.35
1.0V
TYP
MAX
3.6
UNITS
l
l
V
DD
Supply Voltage
3.0
V
V
OV
Digital Output Supply Voltage
3.6
DD
I
DD
Supply Current
l
l
l
l
l
l
Operational Mode, LTC2362
Operational Mode, LTC2361
Operational Mode, LTC2360
Sleep Mode
f
f
f
= 500ksps
= 250ksps
= 100ksps
1.1
0.75
0.5
0.1
0.1
0.1
2
1.5
1
mA
mA
mA
μA
SMPL
SMPL
SMPL
0°C to 70°C
2
Sleep Mode
Sleep Mode
–40°C to 85°C
–40°C to 125°C
2
5
μA
μA
P
Power Dissipation
Operational Mode, LTC2362
Operational Mode, LTC2361
Operational Mode, LTC2360
Sleep Mode
D
l
l
l
l
l
l
f
f
f
= 500ksps
= 250ksps
= 100ksps
3.3
2.25
1.5
0.3
0.3
0.3
7.2
5.4
3.6
7.2
7.2
18
mW
mW
mW
μW
SMPL
SMPL
SMPL
0°C to 70°C
Sleep Mode
–40°C to 85°C
–40°C to 125°C
μW
Sleep Mode
μW
236012f
4
LTC2360/LTC2361/LTC2362
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
LTC2360
LTC2361
LTC2362
SYMBOL
PARAMETER
CONDITIONS
(Notes 8, 9)
(Notes 8, 9)
MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
l
l
l
l
l
l
l
l
l
l
l
l
l
f
f
t
t
t
t
t
t
t
t
t
t
t
t
Maximum Sampling Frequency
Shift Clock Frequency
Shift Clock Period
100
100
250
40
500
20
kHz
MHz
ns
SMPL(MAX)
10
10
25
4
50
2
SCK
SCK
Minimum Throughput Time, t
Acquisition Time
+ t
CONV
μs
THROUGHPUT
ACQ
2
8
1
3
0.5
1.5
1.5
16
μs
ACQ
Conversion Time
μs
CONV
Minimum Positive CONV Pulse Width
SCK↑ Setup Time After CONV↓
SDO Enabled Time After CONV↓
(Note 8)
8
3
μs
1
2
3
4
5
6
7
8
(Note 8)
16
16
ns
(Notes 8, 9)
16
8
16
8
16
8
ns
SDO Data Valid Access Time After SCK↓ (Notes 8, 9, 10)
ns
SCK Low Time
(Note 11)
40%
40%
4
40%
40%
4
40%
40%
4
t
t
SCK
SCK High Time
(Note 11)
SCK
SDO Data Valid Hold Time After SCK↓
(Notes 8, 9, 10)
ns
SDO Into Hi-Z State Time After CONV↑ (Notes 8, 9)
6
6
6
ns
Note 6: Linearity, offset and gain specifications apply for a single-ended
input with respect to GND.
Note 7: Typical RMS noise at code transitions.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
A
IN
Note 8: Guaranteed by characterization. All input signals are specified with
Note 2: All voltage values are with respect to GND.
t = t = 2ns (10% to 90% of V ) and timed from a voltage level of 1.6V.
r
f
DD
Note 3: When pins A and V are taken below GND or above V ,
IN
REF
DD
Note 9: All timing specifications given are with a 10pF capacitance load.
With a capacitance load greater than this value, a digital buffer or latch
must be used.
they will be clamped by internal diodes. These products can handle input
currents greater than 100mA below GND or above V without latch-up.
DD
Note 4: V = OV = V = 2.35V to 3.6V, f
= f
and
SMPL(MAX)
DD
DD
REF
SMPL
Note 10: The time required for the output to cross the V or V voltage.
Note 11: Guaranteed by design, not subject to test.
Note 12: High temperatures degrade operating lifetimes. Operating lifetime
is derated at temperatures greater than 105°C.
IH
IL
f
= f
unless otherwise specified.
SCK
SCK(MAX)
Note 5: Integral linearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
236012f
5
LTC2360/LTC2361/LTC2362
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VDD = OVDD = VREF (LTC2360, Note 4)
Differential Nonlinearity
vs Output Code
Integral and Differential Nonlinearity
vs Reference Voltage (TS8 Package)
Integral Nonlinearity
vs Output Code
1
0.8
1
0.8
1
0.8
V
= 3V
V
= 3V
DD
DD
V
= 3.6V
DD
0.6
0.6
0.6
MAX DNL
MAX INL
0.4
0.4
0.4
0.2
0.2
0.2
0
0
0
MIN INL
–0.2
–0.4
–0.6
–0.8
–1
–0.2
–0.4
–0.6
–0.8
–1
–0.2
–0.4
–0.6
–0.8
–1
MIN DNL
0
512 1024 1536 2048 2560 3072 3584 4096
0
512 1024 1536 2048 2560 3072 3584 4096
0.8 1.2 1.6
2
2.4 2.8 3.2 3.6
OUTPUT CODE
OUTPUT CODE
REFERENCE VOLTAGE (V)
236012 G01
236012 G02
236012 G03
Reference Current vs Sample
Rate (TS8 Package)
Histogram for 16384 Conversions
Supply Current vs Sample Rate
500
400
300
200
100
0
10000
8000
6000
4000
2000
0
20.0
16.0
12.0
8.0
V
= 3V
V
= 3.6V
V
DD
= 3.6V
DD
DD
4.0
0.0
0
10 20 30 40 50 60 70 80 90 100
2045 2046 2047 2048 2049 2050
CODE
0
10 20 30 40 50 60 70 80 90 100
SAMPLING FREQUENCY (ksps)
SAMPLE RATE (ksps)
236012 G05
236012 G04
236012 G06
THD vs Input Frequency
48kHz Sine Wave 8192 FFT Plot
SINAD vs Input Frequency
–78
–80
–82
–84
–86
–88
–90
–92
0
–20
74
73
72
71
70
69
V
= 3.6V
V
f
= 3V
SMPL
DD
DD
= 100ksps
V
= 2.35V
–40
V
= 3.0V
DD
DD
V
= 2.35V
DD
–60
V
= 3.6V
–80
DD
–100
–120
–140
V
= 3.0V
DD
1
10
100
0
10
20
30
40
50
1
10
INPUT FREQUENCY (kHz)
100
INPUT FREQUENCY (kHz)
INPUT FREQUENCY (kHz)
236012 G08
2306012 G09
236012 G07
236012f
6
LTC2360/LTC2361/LTC2362
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VDD = OVDD = VREF (LTC2361, Note 4)
Integral Nonlinearity
vs Output Code
Differential Nonlinearity
vs Output Code
Integral and Differential Nonlinearity
vs Reference Voltage (TS8 Package)
1
0.8
1
0.8
1
0.8
V
= 3V
V
= 3V
DD
DD
V
= 3.6V
DD
0.6
0.6
0.6
MAX DNL
MAX INL
0.4
0.4
0.4
0.2
0.2
0.2
0
0
0
MIN INL
–0.2
–0.4
–0.6
–0.8
–1
–0.2
–0.4
–0.6
–0.8
–1
–0.2
–0.4
–0.6
–0.8
–1
MIN DNL
0.8 1.2 1.6
2
2.4 2.8 3.2 3.6
0
512 1024 1536 2048 2560 3072 3584 4096
0
512 1024 1536 2048 2560 3072 3584 4096
REFERENCE VOLTAGE (V)
OUTPUT CODE
OUTPUT CODE
236012 G12
236012 G10
236012 G11
Reference Current vs Sample
Rate (TS8 Package)
Histogram for 16384 Conversions
Supply Current vs Sample Rate
800
600
400
200
0
10000
8000
6000
4000
2000
0
50.0
40.0
30.0
20.0
10.0
0.0
V
= 3V
DD
V
DD
= 3.6V
V
DD
= 3.6V
0
50
100
150
200
250
2045 2046 2047 2048 2049 2050
CODE
0
50
100
150
200
250
SAMPLE RATE (ksps)
SAMPLE RATE (ksps)
236012 G14
236012 G13
236012 G15
THD vs Input Frequency
124kHz Sine Wave 8192 FFT Plot
SINAD vs Input Frequency
74
73
72
71
70
69
0
–20
–71
–73
–75
–77
–79
–81
–83
–85
–87
–89
–91
V
SMPL
= 3V
DD
V
= 3.6V
DD
f
= 250ksps
–40
V
= 2.35V
DD
V
= 3.0V
DD
–60
V
= 2.35V
DD
–80
–100
–120
–140
V
= 3.6V
DD
V
= 3.0V
DD
1
10
100
1000
0
25
50
75
100
125
1
10
100
1000
INPUT FREQUENCY (kHz)
INPUT FREQUENCY (kHz)
INPUT FREQUENCY (kHz)
2306012 G16
2306012 G18
236012 G17
236012f
7
LTC2360/LTC2361/LTC2362
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VDD = OVDD = VREF (LTC2362, Note 4)
Integral Nonlinearity
vs Output Code
Integral and Differential Nonlinearity
vs Reference Voltage (TS8 Package)
Differential Nonlinearity
vs Output Code
1
0.8
1
0.8
1
0.8
V
= 3V
V
= 3V
DD
DD
V
= 3.6V
DD
0.6
0.6
0.6
MAX DNL
MAX INL
0.4
0.4
0.4
0.2
0.2
0.2
0
0
0
MIN INL
–0.2
–0.4
–0.6
–0.8
–1
–0.2
–0.4
–0.6
–0.8
–1
–0.2
–0.4
–0.6
–0.8
–1
MIN DNL
0
512 1024 1536 2048 2560 3072 3584 4096
0
512 1024 1536 2048 2560 3072 3584 4096
0.8 1.2 1.6
2
2.4 2.8 3.2 3.6
OUTPUT CODE
OUTPUT CODE
REFERENCE VOLTAGE (V)
236012 G20
236012 G19
236012 G21
Reference Current vs Sample
Rate (TS8 Package)
Supply Current vs Sample Rate
Histogram for 16384 Conversions
1200
1000
800
600
400
200
0
10000
8000
6000
4000
2000
0
80.0
60.0
40.0
20.0
0.0
V
= 3V
DD
V
DD
= 3.6V
V
DD
= 3.6V
0
100
200
300
400
500
2045 2046 2047 2048 2049 2050
CODE
0
50 100 150 200 250 300 350 400 450 500
SAMPLE RATE (ksps)
SAMPLE RATE (ksps)
236012 G23
236012 G22
236012 G24
THD vs Input Frequency
248kHz Sine Wave 8192 FFT Plot
SINAD vs Input Frequency
–67
–71
–75
–79
–83
–87
–91
0
–20
74
73
72
71
70
69
V
SMPL
= 3V
DD
V
V
= 3.6V
= 3.0V
DD
f
= 500ksps
DD
–40
V
= 2.35V
DD
–60
V
= 2.35V
= 3.0V
DD
–80
V
DD
–100
–120
–140
V
= 3.6V
DD
1
10
100
1000
0
50
100
150
200
250
1
10
100
1000
INPUT FREQUENCY (kHz)
INPUT FREQUENCY (kHz)
INPUT FREQUENCY (kHz)
2306012 G26
2306012 G27
2306012 G25
236012f
8
LTC2360/LTC2361/LTC2362
PIN FUNCTIONS
S6 Package
TS8 Package
V
(Pin 1): Positive Supply. The V range is 2.35V to
V
(Pin 1): Positive Supply. The V range is 2.35V to
DD
DD
DD DD
3.6V. V also defines the input span of the ADC, 0V to
DD
3.6V. Bypass to GND and to a solid ground plane with a
2.2ꢀF ceramic capacitor (or 2.2ꢀF tantalum in parallel
with 0.1ꢀF ceramic).
DD
V . Bypass to GND and to a solid ground plane with a
2.2ꢀF ceramic capacitor (or 2.2ꢀF tantalum in parallel
with 0.1ꢀF ceramic).
V
REF
(Pin 2): Reference Input. V
defines the input
REF
REF
GND (Pin 2): Ground. The GND pin must be tied directly
to a solid ground plane.
span of the ADC, 0V to V . The V
range is 1.4V to
REF
V . Bypass to GND and to a solid ground plane with a
DD
2.2ꢀF ceramic capacitor (or 2.2ꢀF tantalum in parallel
A (Pin 3): Analog Input. A is a single-ended input with
respect to GND with a range from 0V to V .
IN
IN
with 0.1ꢀF ceramic).
DD
GND (Pin 3): Ground. The GND pin must be tied directly
to a solid ground plane.
SCK (Pin 4): Shift Clock Input. The SCK serial clock syn-
chronizes the serial data transfer. SDO data transitions on
the falling edge of SCK.
A (Pin 4): Analog Input. A is a single-ended input with
IN
IN
respect to GND with a range from 0V to V
.
REF
SDO (Pin 5): Three-State Serial Data Output. The A/D
conversion result is shifted out on SDO as a serial data
stream with MSB first. The data stream consists of 12 bits
of conversion data followed by trailing zeros.
OV (Pin 5): Output Driver Supply for SDO. The OV
DD
DD
range is 1V to 3.6V. Bypass to GND and to a solid ground
plane with a 2.2ꢀF ceramic capacitor (or 2.2ꢀF tantalum in
parallelwith0.1ꢀFceramic).OV canbedrivenseparately
DD
CONV (Pin 6): Convert Input. This active high signal starts
a conversion on the rising edge. The device automatically
powers down after conversion. A logic low on this input
enables the SDO pin, allowing the data to be shifted out.
from V and OV can be higher than V .
DD
DD
DD
SDO (Pin 6): Three-State Serial Data Output. The A/D
conversion result is shifted out on SDO as a serial data
stream with MSB first. The data stream consists of 12 bits
of conversion data followed by trailing zeros.
SCK (Pin 7): Shift Clock Input. The SCK serial clock syn-
chronizes the serial data transfer. SDO data transitions on
the falling edge of SCK.
CONV (Pin 8): Convert Input. This active high signal starts
a conversion on the rising edge. The device automatically
powers down after conversion. A logic low on this input
enables the SDO pin, allowing the data to be shifted out.
236012f
9
LTC2360/LTC2361/LTC2362
BLOCK DIAGRAM
2.2μF
2.2μF
+
+
1
5
V
OV
DD
DD
ANALOG
INPUT
A
IN
4
THREE-STATE
SERIAL
OUTPUT
PORT
RANGE
SDO
0V TO V
REF
S AND H
12-BIT ADC
6
V
REF
2
3
SCK
7
8
2.2μF
TIMING
LOGIC
GND
CONV
TS8 PACKAGE
236012 BD
TIMING DIAGRAMS
t
8
t
7
CONV
SDO
1.6V
SCK
1.6V
Hi-Z
236012 F01
V
IH
SDO
V
IL
236012 F02
Figure 1. SDO Into Hi-Z State After CONV Rising Edge
Figure 2. SDO Data Valid Hold Time After SCK Falling Edge
t
4
SCK
SDO
1.6V
V
V
IH
IL
236012 F03
Figure 3. SDO Data Valid Acess Time After SCK Falling Edge
236012f
10
LTC2360/LTC2361/LTC2362
APPLICATIONS INFORMATION
DC PERFORMANCE
DYNAMIC PERFORMANCE
The noise of an ADC can be evaluated in two ways: sig-
nal-to-noise ratio (SNR) in the frequency domain and
histogram in the time domain. The LTC2360/LTC2361/
LTC2362 excel in both. Figure 5 demonstrates that the
LTC2360/LTC2361/LTC2362 have an SNR of over 73dB.
The noise in the time domain histogram is the transition
noise associated with a 12-bit resolution ADC which can
be measured with a fixed DC signal applied to the input of
the ADC. The resulting output codes are collected over a
large number of conversions. The shape of the distribu-
tion of codes will give an indication of the magnitude of
the transition noise. In Figure 4, the distribution of output
codes is shown for a DC input that has been digitized
16384 times. The distribution is Gaussian and the RMS
code transition is about 0.32LSB. This corresponds to a
noise level of 73dB relative to a full scale of 3V.
TheLTC2360/LTC2361/LTC2362haveexcellenthighspeed
sampling capability. Fast fourier transform (FFT) test
techniquesareusedtotesttheADCs’frequencyresponse,
distortion and noise at the rated throughput. By applying
a low distortion sine wave and analyzing the digital output
using an FFT algorithm, the ADCs’ spectral content can
be examined for frequencies outside the fundamental.
Figures 5 and 6 show typical LTC2361 and LTC2362 FFT
plots respectively.
10000
V
= 3V
DD
8000
6000
4000
2000
0
2045 2046 2047 2048 2049 2050
CODE
236012 F04
Figure 4. Histogram for 16384 Conversions
0
–20
0
V
= 3V
V
= 3V
DD
DD
f
f
= 250ksps
f
f
= 500ksps
SMPL
IN
SINAD = 73dB
THD = –84dB
SMPL
–20
–40
= 124kHz
= 248kHz
IN
SINAD = 73dB
THD = –81dB
–40
–60
–60
–80
–80
–100
–120
–140
–100
–120
–140
0
25
50
75
100
125
0
50
100
150
200
250
INPUT FREQUENCY (kHz)
INPUT FREQUENCY (kHz)
236012 F05
236012 F06
Figure 5. LTC2361 FFT Plot
Figure 6. LTC2362 FFT Plot
236012f
11
LTC2360/LTC2361/LTC2362
APPLICATIONS INFORMATION
Signal-to-Noise plus Distortion Ratio
rate of 500kHz, the LTC2362 maintains ENOB above 11
bits up to the Nyquist input frequency of 250kHz (refer
to Figure 7).
The signal-to-noise plus distortion ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental
input frequency to the RMS amplitude of all other fre-
quency components at the A/D output. The output is band
limited to frequencies from above DC and below half the
sampling frequency. Figure 6 shows a typical FFT with a
500kHz sampling rate and a 248kHz input. The dynamic
performance is excellent for input frequencies up to and
beyond the Nyquist frequency of 250kHz.
Total Harmonic Distortion
Thetotalharmonicdistortion(THD)istheratiooftheRMS
sumofallharmonicsoftheinputsignaltothefundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD
is expressed as:
2
2
2
2
V2 + V3 + V4 +...Vn
Effective Number of Bits
THD= 20log
V1
The effective number of bits (ENOB) is a measurement of
the resolution of an ADC and is directly related to SINAD
by the equation:
where V is the RMS amplitude of the fundamental
frequency and V through V are the amplitudes of the
second through nth harmonics. THD vs. Input Frequency
is shown in Figure 8. The LTC2362 has excellent distortion
performance up to the Nyquist frequency and beyond.
1
2
n
SINAD–1.76
ENOB =
6.02
where ENOB is the effective number of bits of resolution
and SINAD is expressed in dB. At the maximum sampling
74
73
72
71
70
69
68
67
12
–67
–71
–75
V
= 3.6V
= 3.0V
DD
V
DD
11.67
11.34
11
V
= 2.35V
DD
V
= 2.35V
= 3.0V
DD
–79
–83
–87
–91
V
DD
V
= 3.6V
DD
1
10
100
1000
1
10
100
1000
INPUT FREQUENCY (kHz)
INPUT FREQUENCY (kHz)
2306012 F07
2306012 F08
Figure 7. LTC2362 ENOB and SINAD vs Input Frequency
Figure 8. LTC2362 THD vs Input Frequency
236012f
12
LTC2360/LTC2361/LTC2362
APPLICATIONS INFORMATION
Intermodulation Distortion
Peak Harmonic or Spurious Noise
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermoduation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused
by the presence of another sinusoidal input at a different
frequency.
Thepeakharmonicorspuriousnoiseisthelargestspectral
component excluding the input signal and DC. This value
is expressed in decibels relative to the RMS value of a
full-scale input signal.
Full-Power and Full-Linear Bandwidth
The full-power bandwidth is that input frequency at which
the amplitude of reconstructed fundamental is reduced by
3dB for full-scale input signal.
If two pure sine waves of frequencies f and f are applied
a
b
totheADCinput,nonlinearitiesintheADCtransferfunction
can create distortion products at the sum and difference
frequencies of mf nf , where m and n = 0, 1, 2, 3, etc.
a
b
Thefull-linearbandwidthistheinputfrequencyatwhichthe
SINADhasdroppedto68dB(11effectivebits).TheLTC2362
hasbeendesignedtooptimizeinputbandwidth,allowingthe
ADC to undersample input signals with frequencies above
the converter’s Nyquist frequency. The noise floor stays
very low at high frequencies; SINAD becomes dominated
by distortion at frequencies far beyond Nyquist.
For example, the 2nd order IMD terms include (f f ).
a
b
If the two input sine waves are equal in magnitude, the
value (in decibels) of the 2nd order IMD products can be
expressed by the following formula:
Amplitude at f ± f
(
)
a
b
IMD f ± f = 20log
(
)
a
b
Amplitude at fa
0
V
= 3.6V
DD
f
f
f
= 500ksps
SMPL
a
b
–20
–40
= 99kHz
= 101kHz
IMD = –76.5dB
–60
–80
–100
–120
0
50
100
150
200
250
INPUT FREQUENCY (kHz)
236012 F09
Figure 9. LTC2362 Intermodulation Distortion Plot
236012f
13
LTC2360/LTC2361/LTC2362
APPLICATIONS INFORMATION
OVERVIEW
Data Transfer
The LTC2360/LTC2361/LTC2362 use a successive ap-
proximationalgorithmandinternalsample-and-holdcircuit
to convert an analog signal to a 12-bit serial output. All
devices operate from a single 2.35V to 3.6V supply. The
conversion time of the devices is controlled by an internal
oscillator, which allows the LTC2360/LTC2361/LTC2362
to sample at a rate of 100ksps, 250ksps and 500ksps
respectively.
A rising CONV edge starts a conversion and disables SDO.
Aftertheconversion,theADCautomaticallygoesintosleep
mode, drawing only leakage current.
CONV going low enables SDO and clocks out the MSB bit,
B11. SCK then synchronizes the data transfer with each
bit being transmitted on the falling SCK edge and can be
captured on the rising SCK edge. After completing the
data transfer, if further SCK clocks are applied with CONV
low, SDO will output zeros indefinitely (see Figure 10). For
example, 16-clocks at SCK will produce the 12-bit data
and four trailing zeros on SDO.
TheLTC2360/LTC2361/LTC2362containa12-bit,switched-
capacitor ADC, a sample-and-hold, a serial interface(see
Block Diagram) and are available in tiny 6- or 8-lead
TSOT-23 packages.
SLEEP MODE
The S6 package of the LTC2360/LTC2361/LTC2362 uses
DD
V
as the reference and has an analog input range of 0V
The LTC2360/LTC2361/LTC2362 enter sleep mode to save
poweraftereachconversionifCONVremainshigh.Insleep
mode, all bias currents are shut down and only leakage
currents remain (about 0.1μA). The sample-and-hold is
in hold mode while the ADC is in sleep mode. The ADC
returns to sample mode after the falling edge of CONV
during power-up (see Figure 10).
to V . The ADC samples the analog input with respect to
DD
GND and outputs the result through the serial interface.
TheTS8packageprovidestwoadditionalpins:areference
pin, V , and an output supply pin, OV . The ADC can
REF
DD
operate with reduced spans down to 1.4V and achieve
342ꢀV resolution. OV controls the output swing of the
DD
digital output pin, SDO, and allows the device to com-
Exiting Sleep Mode and Power-Up Time
municate with 1.8V, 2.5V or 3V digital systems.
By taking CONV low, the ADC powers up and acquires an
input signal completely after the aquisition time (t ).
SERIAL INTERFACE
ACQ
Aftert , theADCcanperformaconversionasdescribed
ACQ
TheLTC2360/LTC2361/LTC2362communicatewithmicro-
controllers, DSPs and other external circuitry via a 3-wire
interface. Figure 10 shows the operating sequence of the
serial interface.
in the Serial Interface section (see Figure 10).
BY TAKING CONV LOW, THE DEVICE POWERS UP
AND ACQUIRES AN INPUT ACCURATELY AFTER t
ACQ
CONV
t
SLEEP MODE
RECOMMENDED HIGH OR LOW
CONV
t
t
2
6
1
2
3
4
9
10
11
12
SCK
SDO
t
5
t
t
t
t
8
3
4
7
Hi-Z STATE
B11
B10
B9
B3
B2
B1
B0*
236012 F10
(MSB)
t
1
t
ACQ
t
THROUGHPUT
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE
APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY
Figure 10. LTC2360/LTC2361/LTC2362 Serial Interface Timing Diagram
236012f
14
LTC2360/LTC2361/LTC2362
APPLICATIONS INFORMATION
current.Toobtainthelowestsupplycurrent,bringtheCONV
ACHIEVING MICROPOWER PERFORMANCE
pin to GND when it is low and to V when it is high.
DD
With typical operating currents of 0.5mA, 0.75mA and
1.1mA for the LTC2360/LTC2361/LTC2362 and automati-
cally entering sleep mode right after a conversion, these
devices achieve extremely low power consumption over
a wide range of sample rates (see Figure 11). The sleep
mode allows the supply current to drop with reduced
sample rate. Several things must be taken into account
to achieve such low power consumption.
AftertheconversionwithCONVstayinghigh,theconverter
isinsleepmodeanddrawsonlyleakagecurrent.Thestatus
of the SCK input has no effect on supply current during
this time. For the best performance, hold SCK either high
or low while the ADC is converting.
Minimize the Device Active Time
Insystemsthathavesignificanttimebetweenconversions,
the ADC draws a minimal amount of power. Figures 12
and 13 show two ways to minimize the amount of time
the ADC draws power. In Figure 12, the ADC draws power
Minimize Power Consumption in Sleep Mode
The LTC2360/LTC2361/LTC2362 enter sleep mode after
each conversion if CONV remains high and draw only
leakage current (see Figure 10). If the CONV input is not
runningrail-to-rail, theinputlogicbufferwilldrawcurrent.
This current may be large compared to the typical supply
during t
and t
and is in sleep mode for the rest of
ACQ
CONV
the time. The conversion results are available at the next
CONV falling edge. In Figure 13, the ADC draws twice the
power than that in Figure 12, but the conversion results
are available during t
. The user can use the fastest
DATA
SCK available in the system to shorten data transfer time,
as long as t and t are not violated.
1200
V
A
= OV = V
= 3.6V
REF
DD
DD
t
DATA
4
7
T
= 25°C
1000
800
600
400
SDO Loading
Capacitiveloadingonthedigitaloutputcanincreasepower
consumption. A 100pF capacitor on the SDO pin can add
more than 50μA to the supply current at a 200kHz clock
frequency. An extra 50μA or so of current goes into charg-
ing and discharging the load capacitor. The same goes for
digital lines driven at a high frequency by any logic. The
C • V • f currents must be evaluated with the troublesome
ones minimized.
LTC2361
LTC2362
LTC2360
200
0
1
10
100
1000
SAMPLE RATE (ksps)
236012 TA01b
Figure 11. Supply Current vs Sample Rate
EXECUTING A CONVERSION AND PUTTING
THE DEVICE INTO SLEEP MODE
SAMPLING INPUT AND
TRANSFERRING DATA
CONV
t
t
CONV
SLEEP MODE
RECOMMENDED HIGH OR LOW
ACQ
SCK
SDO
1
2
3
4
9
10
B2
11
12
Hi-Z STATE
B11 B10 B9
B3
B1 B0
236012 F12
t
= t
+ t
+ t
THROUGHPUT ACQ CONV SLEEPMODE
Figure 12. Minimize the Time When the Device Draws Power, While the Conversion Results are Available After the Device Wakes Up
236012f
15
LTC2360/LTC2361/LTC2362
APPLICATIONS INFORMATION
EXECUTE CONVERSION
EXECUTING A DUMMY CONVERSION AND
PUT THE DEVICE INTO SLEEP MODE
ACQUIRE
INPUT
DATA TRANSFER
CONV
SCK
t
t
t
t
CONV
SLEEP MODE
ACQ
CONV
DATA
RECOMMENDED HIGH OR LOW
RECOMMENDED HIGH OR LOW
1
2
3
4
9
10
11
12
Hi-Z STATE
SDO
B11 B10 B9
B3
= t
B2
B1 B0
+ t
236012 F13
t
+ 2 • t
+ t
CONV DATA SLEEPMODE
THROUGHPUT ACQ
Figure 13. Minimize the Time When the Device Draws Power, While the Conversion Results are Available Right After Conversion
SINGLE-ENDED ANALOG INPUT
Driving the Analog Input
used, more time for settling can be provided by increasing
the time between conversions. The best choice for an op
amp to drive the LTC2360/LTC2361/LTC2362 will depend
on the application. Generally, applications fall into two
categories: AC applications where dynamic specifications
are most critical and time domain applications where DC
accuracy and settling time are most critical. The follow-
ing list is a summary of the op amps that are suitable for
driving the LTC2360/LTC2361/LTC2362. (More detailed
informationisavailableontheLinearTechnologywebsiteat
www.linear.com.)
The analog input of the LTC2360/LTC2361/LTC2362 is
easy to drive. The input draws only one small current
spike while charging the sample-and-hold capacitor with
the ADC going into track mode. During the conversion,
the analog input draws only a small leakage current. If
the source impedance of the driving circuit is low, then
the input of the LTC2360/LTC2361/LTC2362 can be driven
directly. As source impedance increases, so will acquisi-
tion time. For minimum acquisition time with high source
impedance, a buffer amplifier should be used. The main
requirement is that the amplifier driving the analog input
must settle after the small current spike before the next
LTC1566-1: Low Noise 2.3MHz Continuous Time Low-
pass Filter.
LT®1630: Dual 30MHz Rail-to-Rail Voltage FB Amplifier.
2.7Vto 15Vsupplies. VeryhighAVOL, 500μVoffsetand
520ns settling to 0.5LSB for a 4V swing. THD and noise
conversion starts (settling time must be less than t
ACQ
for full throughput rate). While choosing an input ampli-
fier, also keep in mind the amount of noise and harmonic
distortion the amplifier contributes.
are –93dB to 40kHz and below 1LSB to 320kHz (A =
V
1, 2V into 1k, V = 5V), making the part excellent for
P-P
S
AC applications (to 1/3 Nyquist) where rail-to-rail perfor-
mance is desired. Quad version is available as LT1631.
Choosing an Input Amplifier
LTC6241: Dual 18MHz, Low Noise, Rail-to-Rail, CMOS
VoltageFBAmplifier.2.8Vto6Vsupplies.VeryhighAVOL
and125μVoffset.Itissuitableforapplicationswithasingle
5V supply. Quad version is available as LTC6242.
Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, to limit the magnitude
of the voltage spike seen by the amplifier from charging
the sampling capacitor, choose an amplifier that has a low
output impedance (<100Ω) at the closed-loop bandwidth
frequency. For example, if an amplifier is used in a gain
of 1 and has a unity-gain bandwidth of 10MHz, then the
output impedance at 10MHz must be less than 100Ω. The
secondrequirementisthattheclosed-loopbandwidthmust
be greater than 8MHz to ensure adequate small-signal
settling for full throughput rate. If slower op amps are
LT1797: Unity-Gain Stable 10MHz, Rail-to-Rail Voltage
Feedback Amplifier.
LT1801: 180MHz GBWP, –75dBc at 500kHz, 2mA/Ampli-
fier, 8.5nV/√Hz.
LT6203:100MHzGBWP,–80dBcDistortionat1MHz,Unity-
Gain Stable, R-R In and Out, 3mA/Amplifier, 1.9nV/√Hz.
236012f
16
LTC2360/LTC2361/LTC2362
APPLICATIONS INFORMATION
Input Filtering and Source Impedance
Reference Input
The noise and the distortion of the input amplifier and
other circuitry must be considered since they will add to
the LTC2360/LTC2361/LTC2362 noise and distortion. The
small-signal bandwidth of the sample-and-hold circuit is
10MHz. Any noise or distortion products that are pres-
ent at the analog inputs will be summed over this entire
bandwidth. Noisy input circuitry should be filtered prior
to the analog inputs to minimize noise. A simple 1-pole
RC filter is sufficient for many applications. For example,
On the TS8 package of the LTC2360/LTC2361/LTC2362,
the voltage on the V
pin defines the full-scale range
REF
of the ADC. The reference voltage can range from V
down to 1.4V.
DD
Input Range
The analog input of the LTC2360/LTC2361/LTC2362 is
driven single-ended with respect to GND from a single
supply. The input may swing up to V for the S6 package
DD
Figure 14 shows a 220pF capacitor from A to ground
IN
and to V for the TS8 package. The 0V to 2.5V range is
REF
and a 51Ω source resistor to limit the input bandwidth
to 10MHz. The 220pF capacitor also acts as a charge
reservoir for the input sample-and-hold and isolates the
ADC input from sampling-glitch sensitive circuitry. High
qualitycapacitorsandresistorsshouldbeusedsincethese
components can add distortion. NPO and silvermica type
dielectriccapacitorshaveexcellentlinearity.Carbonsurface
mount resistors can generate distortion from self heating
and from damage that may occur during soldering. Metal
film surface mount resistors are much less susceptible to
both problems. When high amplitude unwanted signals
are close in frequency to the desired signal frequency,
a multiple pole filter is required. High external source
resistance, combined with the 20pF of input capacitance,
will reduce the rated 10MHz bandwidth and increase
acquisition time beyond 500ns.
also ideally suited for single-ended input use with V or
DD
V
=2.5Vforsinglesupplyapplications. Ifthedifference
REF
between the A input and GND exceeds V for the S6
IN
REF
DD
package or V for the TS8 package, the output code will
stay fixed at all ones, and if this difference goes below 0V,
the output code will stay fixed at all zeros.
Figure 15 shows the ideal input/output characteristics for
the LTC2360/LTC2361/LTC2362. The code transitions oc-
cur midway between successive integer LSB values (i.e.,
0.5LSB, 1.5LSB, 2.5LSB, …, FS – 1.5LSB). The output
code is straight binary with 1LSB = V /4096 for the S6
DD
package and 1LSB = V /4096 for the TS8 package.
REF
111...111
111...110
LTC2362
1
2
3
6
5
4
V
CONV
GND SDO
SCK
DD
2.2μF
220pF
A
IN
51Ω
000...001
236012 F14
000...000
0
1LSB
FS – 1LSB
INPUT VOLTAGE (V)
Figure 14. RC Input Filter
236012 F15
Figure 15. Transfer Characteristics
236012f
17
LTC2360/LTC2361/LTC2362
APPLICATIONS INFORMATION
BOARD LAYOUT AND BYPASSING
connecting the pins and the bypass capacitors must be
kept short and should be made as wide as possible.
Wirewrapboardsarenotrecommendedforhighresolution
and/or high speed A/D converters. To obtain the best per-
formance from the LTC2360/LTC2361/LTC2362, a printed
circuit board with ground plane is required. Layout for the
printed circuit board should ensure that digital and analog
signallinesareseparatedasmuchaspossible.Inparticular,
care should be taken not to run any digital track alongside
an analog signal track or underneath the ADC. The analog
input should be screened by the ground plane.
Figure 16 shows the recommended system ground con-
nections.Allanalogcircuitrygroundsshouldbeterminated
at the LTC2360/LTC2361/LTC2362. The ground return
from the LTC2360/LTC2361/LTC2362 to the power supply
should be low impedance for noise free operation. Digital
circuitry grounds must be connected to the digital supply
common.
InapplicationswheretheADCdataoutputsandcontrolsig-
nalsareconnectedtoacontinuouslyactivemicroprocessor
bus, it is possible to get errors in the conversion results.
These errors are due to feedthrough from the micropro-
cessor to the successive approximation comparator. The
problem can be eliminated by forcing the microprocessor
into a wait state during conversion or by using three-state
buffers to isolate the ADC data bus.
High quality tantalum and ceramic bypass capacitors
should be used at the V pin as shown in the Block
DD
Diagram on the first page of this data sheet. For optimum
performance, a 2.2μF surface mount AVX capacitor with
a 0.1μF ceramic is recommended for the V and V
DD
REF
pins. Alternatively, 2.2μF ceramic chip capacitors such as
MurataGRM235Y5V106Z016maybeused.Thecapacitors
mustbelocatedasclosetothepinsaspossible.Thetraces
CV
DD
+
2.2μF
PIN 1
V
CONV
SDO
SCK
DD
GND
CA
IN
A
IN
VIAS TO GROUND PLANE
236012 F16
Figure 16. Power Supply Ground Practice
236012f
18
LTC2360/LTC2361/LTC2362
PACKAGE DESCRIPTION
S6 Package
6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636)
2.90 BSC
(NOTE 4)
0.62
MAX
0.95
REF
1.22 REF
1.50 – 1.75
(NOTE 4)
2.80 BSC
1.4 MIN
3.85 MAX 2.62 REF
PIN ONE ID
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.30 – 0.45
6 PLCS (NOTE 3)
0.95 BSC
0.80 – 0.90
0.20 BSC
DATUM ‘A’
0.01 – 0.10
1.00 MAX
0.30 – 0.50 REF
1.90 BSC
0.09 – 0.20
(NOTE 3)
S6 TSOT-23 0302 REV B
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
3. DIMENSIONS ARE INCLUSIVE OF PLATING 6. JEDEC PACKAGE REFERENCE IS MO-193
TS8 Package
8-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1637)
2.90 BSC
(NOTE 4)
0.52
MAX
0.65
REF
1.22 REF
1.4 MIN
1.50 – 1.75
(NOTE 4)
2.80 BSC
3.85 MAX 2.62 REF
PIN ONE ID
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.22 – 0.36
8 PLCS (NOTE 3)
0.65 BSC
0.80 – 0.90
0.20 BSC
DATUM ‘A’
0.01 – 0.10
1.00 MAX
0.30 – 0.50 REF
1.95 BSC
0.09 – 0.20
(NOTE 3)
TS8 TSOT-23 0802
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
236012f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC2360/LTC2361/LTC2362
TYPICAL APPLICATION
Recommended AC Test Circuitry for the LTC2362
3V
+
+
4.7μF
2.2μF
1k
1%
V
DD
50Ω
5%
4.7μF
CONV
SCK
1.5V AC INPUT
TO
A
IN
LTC2362
MCU
220pF
SDO
GND
1k
1%
2200pF
236012 TA02
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
ADCs
LTC1403/LTC1403A
LTC1407/LTC1407A
LTC1860
12-/14-Bit, 2.8Msps Serial Sampling ADC
3V, Differential Input, 12mW, MSOP Package
12-/14-Bit, 3Msps Simultaneous Sampling ADC 3V, 2-Channel Differential, 14mW, MSOP Package
12-Bit, 250ksps Serial ADC
5V Supply, 1-Channel, 4.3mW, MSOP-8 Package
3V Supply, 1-Channel, 1.3mW, MSOP-8 Package
5V Supply, 2-Channel, 4.3mW, MSOP-8 Package
3V Supply, 2-Channel, 1.3mW, MSOP-8 Package
LTC1860L
12-Bit, 150ksps Serial ADC
LTC1861
12-Bit, 250ksps Serial ADC
LTC1861L
12-Bit, 150ksps Serial ADC
LTC1863
12-Bit, 200ksps Serial ADC 8-Channel ADC
5V Supply, 6.5mW, SSOP-16 Package, Pin Compatible to LTC1863L,
LTC1867
LTC1863L
12-Bit, 250ksps Serial ADC 8-Channel ADC
5V Supply, 2.2mW, SSOP-16 Package, Pin Compatible to LTC1863,
LTC1867L
LTC1864/LTC1865
LTC1867
16-Bit, 250ksps Serial ADC
5V Supply, 1 and 2 Channel, 4.3mW, MSOP Package
16-Bit, 200ksps Serial ADC 8-Channel ADC
5V Supply, 6.5mW, SSOP-16 Package, Pin Compatible to LTC1863,
LTC1867L
LTC1867L
16-Bit, 175ksps Serial ADC 8-Channel ADC
3V Supply, 2.2mW, SSOP-16 Package, Pin Compatible to LTC1863L,
LTC1867
LTC2355/LTC2356
LTC2365/LTC2366
12-/14-Bit, 3.5Msps Serial ADCs
3.3V Supply, Differential Input, 18mW, MSOP Package
12-Bit, 1/3 Msps Serial ADCs in TSOT23
2.35V to 3.6V Supply, Pin and Software Compatible to
LTC2360/LTC2361/LTC2362
DACs
LTC1592
16-Bit, Serial SoftSpan™ I
DAC
1LSB INL/DNL, Software Selectable Spans
87dB SFDR, 20ns Settling Time
OUT
LTC1666/LTC1667/LTC1668 12-/14-/16-Bit, 50Msps DACs
LTC2630
12-/10-/8-Bit Single V
DACs
SC70 6-Pin Package, Internal Reference, 1LSB INL (12 Bits)
OUT
References
LT1460-2.5
LT1461-2.5
LT1790-2.5
LT6660
Micropower Series Voltage Reference
Precision Voltage Reference
0.1% Initial Accuracy, 10ppm Drift
0.05% Initial Accuracy, 3ppm Drift
Micropower Series Reference in SOT-23
Ultra-Tiny Micropower Series Reference
0.05% Initial Accuracy, 10ppm Drift
2mm × 2mm DFN Package, 0.2% Initial Accuracy, 10ppm Drift
SoftSpan is a trademark of Linear Technology Corporation.
236012f
LT 0408 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
●
© LINEAR TECHNOLOGY CORPORATION 2008
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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