LTC1854IG#PBF_技术文档

LTC1854/LTC1855/LTC1856

8-Channel, ±10V Input

12-/14-/16-Bit, 100ksps ADC

Converters with Shutdown

DescripTion

The LTC^®1854/LTC1855/LTC1856 are 8-channel, low

power, 12-/14-/16-bit, 100ksps, analog-to-digital con-

verters (ADCs). These ADCs operate from a single 5V

supplyandthe8-channelmultiplexercanbeprogrammed

for single-ended inputs, pairs of differential inputs, or

combinations of both. In addition, all channels are fault

protectedto±±0V.Afaultconditiononanychannelwillnot

affect the conversion result of the selected channel.

FeaTures

n

Single 5V Supply

Sample Rate: 100ksps

8-Channel Multiplexer with 30V Protection

10V Bipolar ꢀnput Range

n

Single Ended or Differential

3ꢁSB ꢀIꢁ for the ꢁTC1856, 1ꢂ5ꢁSB ꢀIꢁ for the

n

ꢁTC1855, 1ꢁSB ꢀIꢁ for the ꢁTC1854

Power Dissipation: 40mW (Typ)

SPꢀ/MꢀCROWꢀRE™ Compatible Serial ꢀ/O

Power Shutdown: Nap and Sleep

SINAD: 87dꢀ (LTC1856)

Operates with Internal or External Reference

Internal Synchronized Clock

28-Pin SSOP Package

n

An onboard precision reference minimizes external com-

ponents.Powerdissipationis40mWat100kspsandlower

intwopowershutdownmodes(27.5mWinNapmodeand

40µW in Sleep mode.) DC speciﬁcations include ±±LSꢀ

INL for the LTC1856, ±1.5LSꢀ INL for the LTC1855 and

±1LSꢀ for the LTC1854.

n

Theinternalclockistrimmedfor5µsmaximumconversion

time and the sampling rate is guaranteed at 100ksps. A

separate convert start input and data ready signal (BUSY)

ease connections to FIFOs, DSPs and microprocessors.

applicaTions

n

Industrial Process Control

Multiplexed Data Acquisition Systems

High Speed Data Acquisition for PCs

n

L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

n

Digital Signal Processing

Typical applicaTion

100kHz, 12-Bit/14-/16-Bit Sampling ADC

ꢁTC1856 Typical ꢀIꢁ Curve

2.0

COM

CH0

CONVST

RD

1.5

1.0

0.5

0

LTC1854/

CH1 LTC1855/ SCK

LTC1856

µP

CONTROL

LINES

CH2

SDI

DGND

SDO

SOFTWARE-PROGRAMMABLE

SINGLE-ENDED OR

CH3

CH4

DIFFERENTIAL INPUTS

10V BIPOLAR INPUT RANGE

CH5

BUSY

3V TO 5V

–0.5

CH6

CH7

MUXOUT

ADC

OV

DV

AV

AGND3

AGND2

DD

5V

+

–

5V

–1.0

0.1µF

10µF

0.1µF

10µF

0.1µF

+

–1.5

–

ADC

AGND1

REFCOMP

–2.0

V

2.5V

–32768

–16384

0

16384

32767

REF

1µF

10µF

0.1µF

CODE

185456 G01

1854565af

1

LTC1854/LTC1855/LTC1856

absoluTe maximum raTings

package/orDer inFormaTion

(Iotes 1, 2)

TOP VIEW

Supply Voltage (OV = DV = AV = V )............ 6V

DD

1

2

28 CONVST

27 RD

COM

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

Ground Voltage Difference

3

26 SCK

DGND, AGND1, AGND2, AGND± ....................... ±0.±V

Analog Input Voltage

4

25 SDI

5

24 DGND

23 SDO

22 BUSY

+

–

ADC , ADC

6

7

(Note ±)...................(AGND1 – 0.±V) to (AV + 0.±V)

DD

8

21 OV

DD

CH0-CH7, COM ................................................... ±±0V

9

20 DV

DD

+

Digital Input Voltage (Note 4) ......(DGND – 0.±V) to 10V

10

11

12

13

14

19 AV

DD

MUXOUT

–

18 AGND3

17 AGND2

16 REFCOMP

MUXOUT

Digital Output Voltage ....(DGND – 0.±V) to (DV + 0.±V)

DD

+

ADC

Power Dissipation................................................ 500mW

–

ADC

Operating Temperature Range

15

V

REF

AGND1

LTC1854C/LTC1855C/LTC1856C.............. 0°C to 70°C

LTC1854I/LTC1855I/LTC1856I............. –40°C to 85°C

Storage Temperature Range ................... –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. ±00°C

G PACKAGE

28-LEAD PLASTIC SSOP

T

= 125°C, θ = 160°C/W

JA

JMAX

EXPOSED PAD (PIN #) IS GND, MUST ꢀE SOLDERED TO PCꢀ

ORDER PART NUMꢀER

LTC1854CG

LTC1854IG

LTC1855CG

LTC1855IG

LTC1856CG

LTC1856IG

Order Options Tape and Reel: Add #TR

Lead Free: Add #PꢀF Lead Free Tape and Reel: Add #TRPꢀF

Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges.

converTer anD mulTiplexer characTerisTics

The l denotes the speciﬁcations which apply over the full operating temperature range, otherwise speciﬁcations are at T_A= 25°Cꢂ

MUXOUT connected to ADC inputsꢂ (Iotes 5, 6)

ꢁTC1854

TYP

ꢁTC1855

TYP

ꢁTC1856

TYP

PARAMETER

COIDꢀTꢀOIS

MꢀI

12

MAX MꢀI

MAX

UIꢀTS

ꢀits

l

Resolution

14

15

No Missing Codes

Transition Noise

12

ꢀits

0.06

±0.1

0.25

±0.1

1

LSꢀ

RMS

l

Integral Linearity Error

Differential Linearity Error

ꢀipolar Zero Error

ꢀipolar Zero Error Drift

ꢀipolar Zero Error Match

ꢀipolar Full-Scale Error

(Note 7)

(Note 8)

±1

±1.5

±±

4

LSꢀ

–1

1

–1

1.5

±8

–2

LSꢀ

±5

±2±

±0.1

ppm/°C

LSꢀ

±

4

10

l

External Reference (Note 11)

Internal Reference (Note 11)

±0.±4

±0.45

±0.14

±0.40

±0.1

±0.4

%

ꢀipolar Full-Scale Error Drift

External Reference

Internal Reference

±2.5

±7

±2.5

±7

±2.5

±7

ppm/°C

ꢀipolar Full-Scale Error Match

Input Common Mode Range

5

10

15

LSꢀ

V

l

±10

96

±+10

96

±10

96

Input Common Mode Rejection Ratio

dꢀ

185456fa

2

LTC1854/LTC1855/LTC1856

analog inpuT ^Thel denotes the speciﬁcations which apply over the full operating temperature range, otherwise

speciﬁcations are at T_A= 25°Cꢂ (Iote 5)

PARAMETER

COIDꢀTꢀOIS

MꢀI

TYP

MAX

UIꢀTS

V

Analog Input Range

CH0 to CH7, COM

±10

+

–

ADC , ADC (Note ±)

ADC ±2.048

V

Impedance

Capacitance

CH0 to CH7, COM

±1

5

kΩ

pF

+

–

MUXOUT , MUXOUT

CH0 to CH7, COM

5

+

–

Sample Mode ADC , ADC

12

4

pF

+

–

Hold Mode ADC , ADC

pF

+

–

l

Input Leakage Current

ADC , ADC , CONVST = Low

±1

µA

Dynamic accuracy ^Thel denotes the speciﬁcations which apply over the full operating temperature range,

otherwise speciﬁcations are at T_A= 25°Cꢂ MUXOUT connected to ADC inputsꢂ (Iote 5)

ꢁTC1854

MꢀI TYP

ꢁTC1855

MAX MꢀI TYP

ꢁTC1856

SYMBOꢁ PARAMETER

COIDꢀTꢀOIS

MAX MꢀI TYP MAX

UIꢀTS

dꢀ

S/(N + D) Signal-to-(Noise + Distortion) Ratio 1kHz Input Signal

74

8±

87

THD

Total Harmonic Distortion

1kHz Input Signal

First Five Harmonics

–102

–95

–101

dꢀ

Peak Harmonic or Spurious Noise 1kHz Input Signal

–99

–120

1

–99

–120

1

–10±

–120

1

dꢀ

Channel-to-Channel Isolation

–±dꢀ Input ꢀandwidth

Aperture Delay

1kHz Input Signal

MHz

ns

–70

60

–70

60

–70

60

Aperture Jitter

ps

Transient Response

Full-Scale Step

(Note 9)

4

µs

Overvoltage Recovery

(Note 12)

150

ns

1854565af

3

LTC1854/LTC1855/LTC1856

inTernal reFerence characTerisTics

The l denotes the speciﬁcations which apply over the full

operating temperature range, otherwise speciﬁcations are at T_A= 25°Cꢂ (Iote 5)

PARAMETER

COIDꢀTꢀOIS

MꢀI

TYP

2.50

±10

8

MAX

UIꢀTS

l

V

Output Voltage

I

= 0

2.475

2.525

V

ppm/°C

kΩ

REF

OUT

Output Temperature Coefﬁcient

Output Impedance

REF

–0.1mA ≤ I

≤ 0.1mA

REF

OUT

Output Voltage

I

= 0

4.096

V

REFCOMP

OUT

DigiTal inpuTs anD DigiTal ouTpuTs

The l denotes the speciﬁcations which apply over the full

operating temperature range, otherwise speciﬁcations are at T_A= 25°Cꢂ (Iote 5)

SYMBOꢁ

PARAMETER

COIDꢀTꢀOIS

MꢀI

TYP

MAX

UIꢀTS

l

V

High Level Input Voltage

Low Level Input Voltage

Digital Input Current

Digital Input Capacitance

High Level Output Voltage

V

= 5.25V

= 4.75V

= 0V to V

2.4

V

IH

IL

DD

IN

0.8

I

IN

±10

µA

pF

DD

C

IN

5

V

DD

V

DD

= 4.75V, I = –10µA, OV = V

DD

= 4.75V, I = –200µA, OV = V

DD

4.74

V

OH

O

DD

l

4

V

Low Level Output Voltage

V

= 4.75V, I = 160µA, OV = V

DD

0.05

0.10

V

OL

DD

O

DD

l

= 4.75V, I = 1.6mA, OV = V

DD

0.4

O

DD

I

Hi-Z Output Leakage

Hi-Z Output Capacitance

Output Source Current

Output Sink Current

V

OUT

= 0V to V , RD = High

±10

µA

pF

OZ

DD

C

RD = High

15

–10

10

OZ

I

V

OUT

V

OUT

= 0V

mA

SOURCE

SINK

= V

DD

power requiremenTs

The l denotes the speciﬁcations which apply over the full operating temperature

range, otherwise speciﬁcations are at T_A= 25°Cꢂ (Iote 5)

PARAMETER

COIDꢀTꢀOIS

MꢀI

TYP

MAX

UIꢀTS

Positive Supply Voltage

(Notes 9 and 10)

4.75

5.00

5.25

V

l

Positive Supply Current

Nap Mode

Sleep Mode

8.0

5.5

8.0

12

7

1±

mA

µA

CONVST = 0V or 5V

Power Dissipation

Nap Mode

Sleep Mode

40.0

27.5

40.0

mW

µW

185456fa

4

LTC1854/LTC1855/LTC1856

Timing characTerisTics ^Thel denotes the speciﬁcations which apply over the full operating temperature

range, otherwise speciﬁcations are at T_A= 25°Cꢂ (Iote 5)

SYMBOꢁ

PARAMETER

COIDꢀTꢀOIS

MꢀI

TYP

MAX

UIꢀTS

l

f

Maximum Sampling Frequency

Through CH0 to CH7 Inputs

100

kHz

SAMPLE(MAX)

+

–

Through ADC , ADC Only

166

4

l

t

Conversion Time

Acquisition Time

5

4

µs

CONV

Through CH0 to CH7 Inputs

µs

ACQ

+

–

Through ADC , ADC Only

(Note 1±)

1

l

f

t

SCK Frequency

SDO Rise Time

SDO Fall Time

0

20

MHz

ns

SCK

See Test Circuits

6

r

f

l

CONVST High Time

CONVST to BUSY Delay

SCK Period

40

1

C = 25pF, See Test Circuits

L

15

±0

2

50

10

±

SCK High

4

SCK Low

5

Delay Time, SCK↓ to SDO Valid

C = 25pF, See Test Circuits

L

25

20

45

±0

6

Time from Previous SDO Data Remains C = 25pF, See Test Circuits

Valid After SCK↓

5

7

L

l

t

SDO Valid After RD↓

C = 25pF, See Test Circuits

L

11

ns

8

RD↓ to SCK Setup Time

SDI Setup Time ꢀefore SCK↑

SDI Hold Time After SCK↑

SDO Valid ꢀefore BUSY↑

ꢀus Relinquish Time

20

0

9

10

11

12

1±

7

RD = Low, C = 25pF, See Test Circuits

5

20

10

L

See Test Circuits

±0

Iote 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Iote 2: All voltage values are with respect to ground with DGND, AGND1,

AGND2 and AGND± wired together unless otherwise noted.

Iote 7: Integral nonlinearity is deﬁned as the deviation of a code from a

straight line passing through the actual end points of the transfer curve.

The deviation is measured from the center of the quantization band.

Iote 8: ꢀipolar zero error is the offset voltage measured from –0.5LSꢀ

when the output code ﬂickers between 0000 0000 0000 0000 and 1111

1111 1111 1111 for the LTC1856, between 00 0000 0000 0000 and 11

1111 1111 1111 for the LTC1855 and between 0000 0000 0000 and 1111

1111 1111 for the LTC1854.

Iote 3: When these pin voltages are taken below ground or above AV

=

DD

DV = OV = V , they will be clamped by internal diodes. This product

DD

can handle currents of greater than 100mA below ground or above V

without latchup.

Iote 9: Guaranteed by design, not subject to test.

Iote 10: Recommended operating conditions.

DD

Iote 4: When these pin voltages are taken below ground they will be

clamped by internal diodes. This product can handle currents of greater

than 100mA below ground without latchup. These pins are not clamped to

Iote 11: Full-scale bipolar error is the worst case of –FS or +FS

untrimmed deviation from ideal ﬁrst and last code transitions, divided by

the full-scale range, and includes the effect of offset error.

Iote 12: Recovers to speciﬁed performance after (2 • FS) input

overvoltage.

V

DD

.

Iote 5: V = 5V, f

= 100kHz, t = t = 5ns unless otherwise

r f

DD

SAMPLE

speciﬁed.

Iote 13: t of 45ns maximum allows f

up to 10MHz for rising capture

6

SCK

Iote 6: Linearity, offset and full-scale speciﬁcations apply for a single-

with 50% duty cycle and f

up to 20MHz for falling capture (with 5ns

SCK

+

ended analog MUX input with respect to ground or ADC with respect to

setup time for the receiving logic).

–

ADC tied to ground.

1854565af

5

LTC1854/LTC1855/LTC1856

Typical perFormance characTerisTics

ꢁTC1856 Ionaveraged

4096-Point FFT Plot

ꢁTC1856 Typical ꢀIꢁ Curve

ꢁTC1856 Typical DIꢁ Curve

2.0

1.5

2.0

1.5

0

–10

–20

f

= 100kHz

SAMPLE

IN

SINAD = 87dB

THD = –101dB

= 1kHz

–30

1.0

–40

–50

0.5

–60

–70

0

–80

–90

–100

–110

–120

–130

–0.5

–1.0

–1.5

–2.0

–0.5

–1.0

–1.5

–2.0

0

–32768

–16384

16384

32767

–32768

–16384

16384

32767

20

0

5

10 15

25 30 35 40 45 50

CODE

FREQUENCY (kHz)

185456 G02

185456 G01

185456 G03

ꢁTC1855 Ionaveraged

4096-Point FFT Plot

ꢁTC1855 Typical ꢀIꢁ Curve

ꢁTC1855 Typical DIꢁ Curve

1

0

–10

–20

–30

–40

1

0.8

0.6

0.4

0.2

f

= 100kHz

SAMPLE

IN

SINAD = 83dB

THD = –95dB

0.8

0.6

0.4

0.2

= 1kHz

–50

–60

–70

–80

–90

–100

–110

–120

–130

0

–0.2

–0.4

–0.6

–0.8

–1

0

–0.2

–0.4

–0.6

–0.8

–1

–8192

0

8191

20

10 15

25 30 35 40 45 50

–8192

–4096

4096

8191

–4096

4096

0

5

CODE

FREQUENCY (kHz)

185455 G04

185456 G05

185456 G06

ꢁTC1854 Ionaveraged

4096-Point FFT Plot

ꢁTC1854 Typical ꢀIꢁ Curve

ꢁTC1854 Typical DIꢁ Curve

1.0

0.8

1.0

0.8

0

–10

–20

f

= 100kHz

SAMPLE

IN

SINAD = 73.6dB

THD = –102dB

= 1kHz

0.6

–30

0.4

–40

–50

0.2

–60

–70

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–0.8

–1.0

–80

–90

–100

–110

–120

–130

–2048

–1024

0

1024

2047

0

10

30

40

50

–2048

–1024

0

1024

2047

20

CODE

FREQUENCY (kHz)

185456 G08

185456 G09

185456 G07

185456fa

6

LTC1854/LTC1855/LTC1856

Typical perFormance characTerisTics

ꢁTC1856 Channel-to-Channel

Offset Error Matching vs

Temperature

ꢁTC1856 SꢀIAD

vs ꢀnput Frequency

ꢁTC1856 Total Harmonic

Distortion vs ꢀnput Frequency

–70

–80

90

88

86

84

82

80

78

76

74

1.0

0.5

0

–90

–0.5

–100

–110

–1.0

–50

–25

0

25

50

75

100

1

10

100

1

10

100

TEMPERATURE (°C)

INPUT FREQUENCY (kHz)

185456 G12

185456 G11

185456 G10

ꢁTC1855 Channel-to-Channel

Offset Error Matching vs

Temperature

ꢁTC1855 SꢀIAD

vs ꢀnput Frequency

ꢁTC1855 Total Harmonic

Distortion vs ꢀnput Frequency

85

80

75

–60

–70

0.5

0.25

0

–80

–90

70

–0.25

65

60

–100

–110

–0.5

1

10

100

–50

–25

0

25

50

75

100

1

10

100

INPUT FREQUENCY (kHz)

TEMPERATURE (°C)

INPUT FREQUENCY (kHz)

185456 G13

185456 G15

185456 G14

ꢁTC1854 Channel-to-Channel

Offset Error Matching vs

Temperature

ꢁTC1854 SꢀIAD

ꢁTC1854 Total Harmonic

vs ꢀnput Frequency

Distortion vs ꢀnput Frequency

80

75

70

65

60

–60

–70

0.25

0.20

0.15

0.10

0.05

0

–80

–0.05

–0.10

–0.15

–0.20

–0.25

–90

–100

–110

1

10

100

–50

–25

25

50

75

100

1

10

0

INPUT FREQUENCY (kHz)

TEMPERATURE (°C)

INPUT FREQUENCY (kHz)

185456 G17

185456 G16

185456 G18

1854565af

7

LTC1854/LTC1855/LTC1856

Typical perFormance characTerisTics

ꢁTC1856 Channel-to-Channel Gain

Error Matching vs Temperature

ꢁTC1854 Channel-to-Channel Gain

Error Matching vs Temperature

ꢁTC1855 Channel-to-Channel Gain

Error Matching vs Temperature

0.5

0.25

0

0.25

0.20

0.15

0.10

0.05

0

1.0

0.5

0

–0.05

–0.10

–0.15

–0.20

–0.25

–0.5

–1.0

–50

–25

0

25

50

75

100

–50

–25

25

50

75

100

0

–50

–25

0

25

50

75

100

TEMPERATURE (°C)

185456 G20

185456 G21

185456 G19

ꢀnternal Reference Voltage

vs Temperature

Change in REFCOMP Voltage

vs ꢁoad Current

ꢁTC1856 Power Supply

Feedthrough vs Ripple Frequency

2.520

2.515

2.510

2.505

2.500

2.495

2.490

2.485

2.480

0.04

0.02

0

–10

–20

–30

–40

–50

–60

–70

–80

f

= 100kHz

= 60mV

SAMPLE

RIPPLE

V

–0.02

–0.04

–50 –40

–30

–20

–10

0

10

–25

0

50

100

1k

10k

100k

1M

–50

75

25

LOAD CURRENT (mA)

RIPPLE FREQUENCY (Hz)

TEMPERATURE (°C)

185456 G24

185456 G23

185456 G22

Supply Current vs Supply Voltage

Supply Current vs Temperature

9.0

8.5

8.0

7.5

7.0

9.0

8.5

8.0

7.5

f

= 100kHz

f

= 100kHz

SAMPLE

7.0

5

5.25

–50

–25

0

25

50

75

100

4.5

5.5

4.75

TEMPERATURE (°C)

SUPPLY VOLTAGE (V)

185456 G26

185454 G25

185456fa

8

LTC1854/LTC1855/LTC1856

pin FuncTions

COM(Pin1):CommonInput.Thisisthenegativereference

point for all single-ended inputs. It must be free of noise

and is usually connected to the analog ground plane.

AGID1 (Pin 14): Analog Ground.

V

(Pin 15): 2.5V Reference Output. ꢀypass to analog

REF

ground with a 1µF tantalum capacitor.

CH0 (Pin 2): Analog MUX Input.

CH1 (Pin 3): Analog MUX Input.

CH2 (Pin 4): Analog MUX Input.

CH3 (Pin 5): Analog MUX Input.

CH4 (Pin 6): Analog MUX Input.

CH5 (Pin 7): Analog MUX Input.

CH6 (Pin 8): Analog MUX Input.

CH7 (Pin 9): Analog MUX Input.

REFCOMP (Pin 16): Reference ꢀuffer Output. ꢀypass to

analog ground with a 10µF tantalum and a 0.1µF ceramic

capacitor. Nominal output voltage is 4.096V.

AGID2 (Pin 17): Analog Ground.

AGID3 (Pin 18): Analog Ground. This is the substrate

connection.

AV (Pin19):5VAnalogSupply.ꢀypasstoanalogground

DD

with a 0.1µF ceramic and a 10µF tantalum capacitor.

DV (Pin 20): 5V Digital Supply. ꢀypass to digital ground

DD

+

with a 0.1µF ceramic and a 10µF tantalum capacitor.

MUXOUT (Pin 10): Positive MUX Output. Output of the

+

analog multiplexer. Connect to ADC for normal opera-

OV (Pin 21): Positive Supply for the Digital Output

DD

tion.

ꢀuffers (±V to 5V). ꢀypass to digital ground with a 0.1µF

–

ceramic and a 10µF tantalum capacitor.

MUXOUT (Pin 11): Negative MUX Output. Output of the

–

analog multiplexer. Connect to ADC for normal opera-

BUSY (Pin 22): Output shows converter status. It is low

when a conversion is in progress.

tion.

+

ADC (Pin 12): Positive Analog Input to the Analog-to-

SDO (Pin 23): Serial Data Output.

Digital Converter.

–

ADC (Pin 13): Negative Analog Input to the Analog-to-

Digital Converter.

1854565af

9

LTC1854/LTC1855/LTC1856

pin FuncTions

DGID (Pin 24): Digital Ground.

SDꢀ (Pin 25): Serial Data Input.

SCK (Pin 26): Serial Data Clock.

RD (Pin 27): Read Input. This active low signal enables

the digital output pin SDO and enables the serial interface,

SDI and SCK are ignored when RD is high.

COIVST (Pin 28): Conversion Start. The ADC starts a

conversion on CONVST’s rising edge.

FuncTional block Diagram

DV

AV

DD

19

20

MUX ADDRESS

2

3

28

25

22

CONVST

CH0

CH1

CONTROL

LOGIC

SDI

INTERNAL

CLOCK

BUSY

•

INPUT MUX

26

SCK

+

–

27

21

9

1

RD

12-/14-/16-BIT

SAMPLING ADC

CH7

DATA OUT

SERIAL I/O

OV

DD

COM

23

SDO

4.096V

2.5V

REFERENCE

1.6384X

8k

–

+

–

MUXOUT

ADC

14

11 10

12 13

15

16

REFCOMP

17

18

24

AGND1

V

REF

AGND2 AGND3 DGND

18545 BD

185456fa

10

LTC1854/LTC1855/LTC1856

TesT circuiTs

ꢁoad Circuits for Access Timing

ꢁoad Circuits for Output Float Delay

5V

1k

DN

1k

25pF

1k

25pF

(A) V TO Hi-Z

OH

(B) V TO Hi-Z

OL

(A) Hi-Z TO V AND V TO V

OH OL

(B) Hi-Z TO V AND V TO V

OL OH

OH

OL

18545 TC02

18545 TC01

Timing Diagrams

t (CONVST to BUSY Delay)

2

t

2

2.4V

t (For Short Pulse Mode)

1

CONVST

t

1

50%

BUSY

CONVST

0.4V

18545 TD02

18545 TD01

t (Delay Time, SCK↓ to SDO Valid)

6

t (Time from Previous Data Remains Valid After SCK↓)

7

t

6

7

t , t , t (SCK Timing)

3

4 5

SCK

SDO

0.4V

t

4

t

5

SCK

2.4V

0.4V

18545 TD03

t

3

18545 TD04

t (RD↓ to SCK Setup Time)

9

t (SDO Valid After RD↓)

8

t

8

t

9

RD

0.4V

RD

0.4V

Hi-Z

2.4V

0.4V

2.4V

SCK

SDO

18545 TD05

18545 TD06

1854565af

11

LTC1854/LTC1855/LTC1856

Timing Diagrams

t

11

(SDI Hold Time After SCK↑)

t

10

(SDI Setup Time Before SCK↑)

t

11

10

2.4V

SCK

SDI

SCK

SDI

2.4V

0.4V

2.4V

0.4V

18545 TD08

18545 TD07

t

(SDO Valid Before BUSY↑, RD = 0)

t

13

(BUS Relinquish Time)

13

12

t

12

2.4V

BUSY

RD

90%

10%

Hi-Z

2.4V

SDO

B15

18545 TD10

18545 TD09

185456fa

12

LTC1854/LTC1855/LTC1856

applicaTions inFormaTion

OVERVꢀEW

ꢀefore starting a conversion, an 8-bit data word is clocked

into the SDI input on the ﬁrst eight rising SCK edges to

select the MUX address and power down mode. The ADC

enters acquisition mode on the falling edge of the sixth

clock in the 8-bit data word and ends on the rising edge

of the CONVST signal which also starts a conversion (see

Figure7).Aminimumtimeof4µswillprovideenoughtime

for the sample-and-hold capacitors to acquire the analog

signal. Once a conversion cycle has begun, it cannot be

restarted.

The LTC1854/LTC1855/LTC1856 are innovative, multi-

channel ADCs. The on-chip resistors provide attenuation

andoffsetforeachchannel.Thepreciselytrimmedattenua-

torsensureanaccurateinputrange.ꢀecausetheyprecede

the multiplexer, errors due to multiplexer on-resistance

are eliminated.

The input word selects the single ended or differential

inputs for each channel or pair of channels. Overrange

protection is provided for unselected channels. An over-

range condition on an unused channel will not affect the

conversion result on the selected channel.

During the conversion, the internal differential 12-/14-/16-

bit capacitive DAC output is sequenced by the SAR from

the most signiﬁcant bit (MSꢀ) to the least signiﬁcant bit

(LSꢀ). The input is successively compared with the binary

weighted charges supplied by the differential capacitive

DAC.ꢀitdecisionsaremadebyahighspeedcomparator.At

theendofaconversion,theDACoutputbalancestheanalog

COIVERSꢀOI DETAꢀꢁS

The LTC1854/LTC1855/LTC1856 use a successive ap-

proximation algorithm and an internal sample-and-hold

circuittoconvertananalogsignaltoa12-/14-/16-bitserial

outputrespectively.TheADCsarecompletewithaprecision

reference and an internal clock. The control logic provides

easyinterfacetomicroprocessorsandDSPs.(Pleaserefer

to the Digital Interface section for the data format.)

+

–

input (ADC – ADC ). The SAR contents (a 12-/14-/16-bit

+

data word) which represents the difference of ADC and

ADC are loaded into the 12-/14-/16-bit shift register.

–

DRꢀVꢀIG THE AIAꢁOG ꢀIPUTS

The analog signals applied at the MUX input channels are

rescaled by the resistor divider network formed by R1, R2

and R± as shown below. The rescaled signals appear on

the MUXOUT (Pins 10, 11) which are also connected to

the ADC inputs (Pins 12, 1±) under normal operation.

The input range for the LTC1854/LTC1855/LTC1856 is

±10V and the MUX inputs are overvoltage protected to

±±0V. The input impedance is typically ±1kΩ; therefore, it

should be driven with a low impedance source. Wideband

noise coupling into the input can be minimized by placing

a ±000pF capacitor at the input as shown in Figure 2. An

NPO-type capacitor gives the lowest distortion. Place the

capacitor as close to the device input pin as possible. If

an ampliﬁer is to be used to drive the input, care should

be taken to select an ampliﬁer with adequate accuracy,

linearity and noise for the application. The following list is

a summary of the op amps that are suitable for driving the

LTC1854/LTC1855/LTC1856. More detailed information is

available in the Linear Technology data books and online

at www.linear.com.

REFCOMP

R3

R1

CH SEL

10k

25k

MUX

INPUT

MUXOUT

R2

17k

185456 AI01

LT^®1007: Low noise precision ampliﬁer. 2.7mA supply

current ±5V to ±15V supplies. Gain bandwidth product

8MHz. DC applications.

1854565af

13

LTC1854/LTC1855/LTC1856

applicaTions inFormaTion

DV

DD

AV

DD

MUX ADDRESS

CONVST

CH0

CH1

CONTROL

LOGIC

SDI

INTERNAL

CLOCK

BUSY

•

INPUT MUX

SCK

+

–

RD

12-/14-/16-BIT

SAMPLING ADC

CH7

DATA OUT

SERIAL I/O

OV

DD

COM

SDO

4.096V

2.5V

REFERENCE

1.6384X

8k

–

+

–

18545 F01

MUXOUT

AGND1

MUXOUT

ADC

V

REF

REFCOMP

AGND2 AGND3 DGND

Figure 1ꢂ ꢁTC1854/ꢁTC1855/ꢁTC1856 Simpliﬁed Equivalent Circuit

LT1792: Single, low noise JFET input op amp, ±5V sup-

plies.

+

–

A

CH0

CH1

•

IN

3000pF

LT179±: Single, low noise JFET input op amp, 10pA bias

current, ±5V supplies.

+

–

MUXOUT

LT1881/LT1882: Dual and quad, 200pA bias current, rail-

to-rail output op amps. Up to ±15V supplies.

MUXOUT

+

ADC

LT1844/LT1885: Dual and quad, 400pA bias current,

rail-to-rail output op amps. Up to ±15V supplies. Faster

response and settling time.

–

ADC

18545 F02

Figure 2ꢂ Analog ꢀnput Filtering

ꢀITERIAꢁ VOꢁTAGE REFEREICE

LT1227: 140MHz video current feedback ampliﬁer. 10mA

supply current. ±5V to ±15V supplies. Low noise and low

distortion.

The LTC1854/LTC1855/LTC1856 have an on-chip, tem-

perature compensated, curvature corrected, bandgap

reference,whichisfactorytrimmedto2.50V.Thefull-scale

range of the LTC1854/LTC1855/LTC1856 is equal to ±10V.

The output of the reference is connected to the input of a

gain of 1.6±84x buffer through an 8k resistor (see Figure

±). The input to the buffer or the output of the reference

LT1468/LT1469: Single and dual 90MHz, 16-bit accurate

op amp. Good AC/DC specs. ±5V to ±15V supplies.

LT1677: Single, low noise op amp. Rail-to-rail input and

output. Up to ±15V supplies.

185456fa

14

LTC1854/LTC1855/LTC1856

applicaTions inFormaTion

is available at V (Pin 15). The internal reference can be

tween successive integer LSꢀ values (i.e., –FS+0.5LSꢀ,

–FS+1.5LSꢀ, –FS+2.5LSꢀ, … FS–1.5LSꢀ, FS–0.5LSꢀ).

The output is two’s complement binary with:

REF

overdriven with an external reference if more accuracy is

needed. The buffer output drives the internal DAC and is

available at REFCOMP (Pin 16). The REFCOMP pin can be

used to drive a steady DC load of less than 2mA. Driving

an AC load is not recommended because it can cause the

performance of the converter to degrade.

FS− (− FS) 20V

1LSB =

=

= 305.2µV

65566

65536

In applications where absolute accuracy is important,

offsetandfull-scaleerrorscanbeadjustedtozeroduringa

calibrationsequence. Offseterrormustbeadjustedbefore

full-scale error. Zero offset is achieved by adjusting the

offsetappliedtothe“–”input.Forsingle-endedinputs,this

offset should be applied to the COM pin. For differential

inputs, the “–” input is dictated by the MUX address.

8k

15

1µF

V

REF

2.5V

REFERENCE

12-/14-/16-BIT

CAPACITIVE DAC

1.6384X BUFFER

16 REFCOMP

4.096V

0.1µF

For zero offset error, apply –0.5LSꢀ to the “+” input and

adjusttheoffsetatthe“–”inputuntiltheoutputcodeﬂick-

ers between 0000 0000 0000 0000 and 1111 1111 1111

1111 for the LTC1856, between 00 0000 0000 0000 and

11 1111 1111 1111 for the LTC1855 and between 0000

0000 0000 and 1111 1111 1111 for the LTC1854.

18545 F03

10µF

Figure 3ꢂ ꢀnternal or External Reference Source

For minimum code transition noise the V pin and the

REF

REFCOMPpinshouldeachbedecoupledwithacapacitorto

ﬁlter wideband noise from the reference and the buffer.

Forfull-scaleadjustment, aninputvoltageofFS–1.5LSꢀs

should be applied to the “+” input and the appropriate

reference adjusted until the output code ﬂickers between

0111 1111 1111 1110 and 0111 1111 1111 1111 for the

LTC1856, between 01 1111 1111 1110 and 01 1111 1111

1111 for the LTC1855 and between 0111 1111 1110 and

0111 1111 1111 for the LTC1854.

FUꢁꢁ SCAꢁE AID OFFSET

Figure 4 shows the ideal input/output characteristics for

the LTC1856. The code transitions occur midway be-

These adjustments as well as the factory trims affect all

channels. The channel-to-channel offset and gain error

matching are guaranteed by design to meet the speciﬁca-

tions in the Converter Characteristics table.

011...111

011...110

000...001

000...000

111...111

111...110

100...001

100...000

–(FS – 1LSB)

FS – 1LSB

INPUT VOLTAGE (V)

185456 F04

Figure 4ꢂ Bipolar Transfer Characteristics

1854565af

15

LTC1854/LTC1855/LTC1856

applicaTions inFormaTion

DC PERFORMAICE

output supply pin (OV ) that controls the output swings

DD

of the digital output pins (SDO, BUSY) and allows the part

to interface to either ±V or 5V digital systems. The SDO

output is two’s complement.

One way of measuring the transition noise associated

with a high resolution ADC is to use a technique where

a DC signal is applied to the input of the MUX and the

resulting output codes are collected over a large number

of conversions. For example in Figure 5 the distribution

of output code is shown for a DC input that has been

digitized 4096 times. The distribution is Gaussian and the

RMS code transition is about 1LSꢀ for the LTC1856.

Timing and Control

Conversionstartanddatareadarecontrolledbytwodigital

inputs: CONVST and RD. To start a conversion and put the

sample-and-hold into the hold mode bring CONVST high

for at least 40ns. Once initiated it cannot be restarted until

the conversion is complete. Converter status is indicated

by the BUSY output, which goes low while the conversion

is in progress.

DꢀGꢀTAꢁ ꢀITERFACE

ꢀnternal Clock

Figures 6a and 6b show two different modes of opera-

tion for the LTC1856. For the 12-bit LTC1854 and 14-bit

LTC1855, the last four and two bits of the SDO will output

zeros, respectively. In mode 1 (Figure 6a), RD is tied low.

TherisingedgeofCONVSTstartstheconversion. Thedata

outputs are always enabled. The MSꢀ of the data output

is available after the conversion. In mode 2 (Figure 6b),

CONVST and RD are tied together. The rising edge of the

CONVST signal starts the conversion. Data outputs are in

three-state at this time. When the conversion is complete

(BUSY goes high), CONVST and RD go low to enable the

data output for the previous conversion.

The ADC has an internal clock that is trimmed to achieve

a typical conversion time of 4µs. No external adjustments

are required and, with the maximum acquisition time of

4µs, throughput performance of 100ksps is assured.

3V ꢀnput/Output Compatible

The LTC1854/LTC1855/LTC1856 operate on a 5V supply,

which makes the devices easy to interface to 5V digital

systems. These devices can also interface to ±V digital

systems: the digital input pins (SCK, SDI, CONVST and

RD)oftheLTC1854/LTC1855/LTC1856recognize±Vor5V

inputs. The LTC1854/LTC1855/LTC1856 have a dedicated

1800

1600

1400

1200

1000

800

600

400

200

0

–4 –3 –2 –1

0

1

4

2

3

CODE

185456 F05

Figure 5ꢂ ꢁTC1856 Histogram for 4096 Conversions

185456fa

16

LTC1854/LTC1855/LTC1856

applicaTions inFormaTion

1854565af

17

LTC1854/LTC1855/LTC1856

applicaTions inFormaTion

SERIAL DATA INPUT (SDI) INTERFACE

conversion is delayed by one conversion from the input

word requesting it.

TheLTC1854/LTC1855/LTC1856communicatewithmicro-

processorsandotherexternalcircuitryviaasynchronous,

full duplex, 3-wire serial interface (see Figure 7). The shift

clock (SCK) synchronizes the data transfer with each bit

being transmitted on the falling SCK edge and captured

on the rising SCK edge in both transmitting and receiving

systems. The data is transmitted and received simultane-

ously (full duplex).

SDI

SDI WORD 1

SDI WORD 2

SDI WORD 3

SDO SDO WORD 0

SDO WORD 1

SDO WORD 2

185456 AI02

t

CONV

A/D

CONV

A/D

DATA

TRANSFER

DATA

TRANSFER

CONVERSION

INPUT DATA WORD

An 8-bit input word is shifted into the SDI input which

conﬁgures the LTC1854/LTC1855/LTC1856 for the next

conversion. Simultaneously, the result of the previous

conversion is output on the SDO line. At the end of the

data exchange the requested conversion begins by ap-

plying a rising edge on CONVST. After t_CONV, the conver-

sion is complete and the results will be available on the

next data transfer cycle. As shown below, the result of a

TheLTC1854/LTC1855/LTC18568-bitdatawordisclocked

into the SDI input on the ﬁrst eight rising SCK edges. Fur-

ther inputs on the SDI pin are then ignored until the next

conversion. The eight bits of the input word are deﬁned

as follows:

SGL/

ODD

SIGN

SELECT SELECT

DON'T

CARE

DON'T

CARE

NAP

SLEEP

DIFF

1

0

POWER DOWN

SELECTION

MUX ADDRESS

185456 AI03

Table 1. Multiplexer Channel Selection

MUX ADDRESS

DIFFERENTIAL CHANNEL SELECTION

MUX ADDRESS

SINGLE-ENDED CHANNEL SELECTION

SGL/ ODD SELECT

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

COM

DIFF SIGN

1

0

1

0

1

0

1

0

1

0

1

0

1

DIFF SIGN

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

+

–

1

0

1

+

–

+

–

+

–

+

–

+

–

+

–

+

–

+

Combinations of

Differential and Single-Ended

Changing the

MUX Assignment “On the Fly”

4 Differential

8 Single-Ended

CHANNEL

+ (

)

0

1

2

3

4

5

6

7

+

–

+

–

+

0,1

{

(

–

+ ⁽

)

+

–

+

–

2,3

4,5

6,7

4,5

{

6

7

{

(

+

–

4

5

6

7

+

–

+

+ (

)

–

+

4,5

{

+

{

(

–

+

COM (UNUSED)

COM ( )

+ (

)

+

–

+

–

6,7

{

(

COM (

)

COM (

)

–

1ST CONVERSION

2ND CONVERSION

18545 F08

Figure 8. Examples of Multiplexer Options on the LTC1854/LTC1855/LTC1856

185456fa

18

LTC1854/LTC1855/LTC1856

applicaTions inFormaTion

MUX ADDRESS

Sleep mode will occur when Sleep = 1 is selected,

regardless of the selection of the Nap input. The previ-

ous conversion result can be clocked out and the Sleep

mode will start on the falling edge of the last (16th) SCK.

Notice that the CONVST should stay either high or low in

sleep mode (see Figure 10). To wake up from the sleep

mode, apply a rising edge on the CONVST signal and

then apply Sleep = 0 on the next SDI word and the part

will wake up on the falling edge of the last (16th) SCK

(see Figure 11).

The ﬁrst four bits of the input word assign the MUX

conﬁguration for the requested conversion. For a given

channel selection, the converter will measure the voltage

between the two channels indicated by the + and – signs in

the selected row of Table 1. Note that in differential mode

(SGL/DIFF = 0) measurements are limited to four adjacent

input pairs with either polarity. In single-ended mode, all

input channels are measured with respect to COM. Both

the “+” and “–” inputs are sampled simultaneously so

common mode noise is rejected. Bits 5 and 6 of the input

words are Don’t Care bits.

InSleepmode,allbiascurrentsareshutdownandonlythe

power on reset circuit and leakage currents (about 10µA)

remain.Sleepmodewake-uptimeisdependentonthevalue

of the capacitor connected to the REFCOMP (Pin 16). The

wake-up time is typically 40ms with the recommended

10µF capacitor connected on the REFCOMP pin.

P

OWER DOWN SELECTION (NAP, SLEEP)

The last two bits of the input word (Nap and Sleep) deter-

minethepowershutdownmodeoftheLTC1854/LTC1855/

LTC1856. See Table 2. Nap mode is selected when Nap =

1 and Sleep = 0. The previous conversion result will be

clocked out and a conversion will occur before entering

the Nap mode. The Nap mode starts at the end of the

conversion which is indicated by the rising edge of the

BUSY signal. Nap mode lasts until the falling edge of the

2nd SCK (see Figure 9). Automatic nap will be achieved

if Nap = 1 is selected each time an input word is written

to the ADC.

DYNAMIC PERFORMANCE

FFT (Fast Fourier Transform) test techniques are used to

test the ADC’s frequency response, distortion and noise

at the rated throughput. By applying a low distortion

sine wave and analyzing the digital output using an FFT

algorithm, the ADC’s spectral content can be examined

forfrequenciesoutsidethefundamental. Figure12shows

a typical LTC1856 FFT plot which yields a SINAD of 87dB

and THD of –101dB.

Table 2. Power Down Selection

NAP

0

SLEEP

POWER DOWN MODE

0

1

Power On

Nap

1

X

Sleep

1854565af

19

LTC1854/LTC1855/LTC1856

applicaTions inFormaTion

185456fa

20

LTC1854/LTC1855/LTC1856

applicaTions inFormaTion

SIGNAL-TO-NOISE AND DISTORTION RATIO

BOARD LAYOUT, POWER SUPPLIES

AND DECOUPLING

The Signal-to-Noise and Distortion Ratio (SINAD) is the

ratiobetweentheRMSamplitudeofthefundamentalinput

frequency to the RMS amplitude of all other frequency

components at the A/D output. The output is band limited

tofrequenciesfromaboveDCandbelowhalfthesampling

frequency. Figure 12 shows a typical SINAD of 87dB with

a 100kHz sampling rate and a 1kHz input.

Wire wrap boards are not recommended for high reso-

lution or high speed A/D converters. To obtain the best

performance from the LTC1854/LTC1855/LTC1856, a

printed circuit board is required. Layout for the printed

circuit board should ensure the digital and analog signal

lines are separated as much as possible. In particular, care

should be taken not to run any digital track alongside an

analog signal track or underneath the ADC. The analog

input should be screened by AGND.

TOTAL HARMONIC DISTORTION

Total Harmonic Distortion (THD) is the ratio of the RMS

sumofallharmonicsoftheinputsignaltothefundamental

itself. The out-of-band harmonics alias into the frequency

band between DC and half the sampling frequency. THD

is expressed as:

InapplicationswheretheMUXisconnectedtotheADC,itis

possible to get noise coupling into the ADC from the trace

connecting the MUXOUT to the ADC. Therefore, reducing

thelengthofthetracesconnectingtheMUXOUTpins(Pins

10, 11) to the ADC pins (Pins 12, 13) can minimize the

problem. The unused MUX inputs should be grounded to

prevent noise coupling into the inputs.

2

V₂+ V₃+ V₄...+ V_N

THD = 20log

V₁

Figure13showsthepowersupplygroundingthatwillhelp

obtain the best performance from the 12-bit/14-bit/16-bit

ADCs. Pay particular attention to the design of the analog

and digital ground planes. The DGND pin of the LTC1854/

where V is the RMS amplitude of the fundamental fre-

1

quencyandV throughV aretheamplitudesofthesecond

2

N

through Nth harmonics.

0

–10

–20

f

= 100kHz

SAMPLE

IN

= 1kHz

SINAD = 87dB

THD = –101dB

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

20

0

5

10 15

25 30 35 40 45 50

FREQUENCY (kHz)

185456 F12

Figure 12. LTC1856 Nonaveraged 4096 Point FFT Plot

1854565af

21

LTC1854/LTC1855/LTC1856

applicaTions inFormaTion

LTC1855/LTC1856 can be tied to the analog ground plane.

Placing the bypass capacitor as close as possible to the

power supply pins, thereferenceand reference bufferout-

putisveryimportant.Lowimpedancecommonreturnsfor

thesebypasscapacitorsareessentialtolownoiseoperation

of the ADC, and the foil width for these tracks should be

as wide as possible. Also, since any potential difference in

grounds between the signal source and ADC appears as

an error voltage in series with the input signal, attention

should be paid to reducing the ground circuit impedance

as much as possible. The digital output latches and the

onboard sampling clock have been placed on the digital

ground plane. The two ground planes are tied together at

the ADC through a wide, low inductance path.

LTC1854/

LTC1855/

LTC1856

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

COM

10 12

+

–

+

–

MUXOUT

ADC

DIGITAL

SYSTEM

LTC1854/LTC1855/LTC1856

ADC

MUXOUT

+

V

REFCOMP AGND

AV

DV

DD

DGND

24

OV

13

REF

DD

11

–

15

16 14, 17, 18 19

20

21

1µF

10µF

DIGITAL

GROUND PLANE

ANALOG GROUND PLANE

18545 F13

Figure 13. Power Supply Grounding Practice

185456fa

22

LTC1854/LTC1855/LTC1856

package DescripTion

G Package

28-Lead Plastic SSOP (5.3mm)

(Reference LTC DWG # 05-08-1640)

9.90 – 10.50*

(.390 – .413)

28 27 26 25 24 23 22 21 20 19 18

16 15

17

1.25 0.12

5.3 – 5.7

7.8 – 8.2

7.40 – 8.20

(.291 – .323)

0.42 0.03

0.65 BSC

5

7

8

1

2

3

4

6

9 10 11 12 13 14

RECOMMENDED SOLDER PAD LAYOUT

2.0

(.079)

MAX

5.00 – 5.60**

(.197 – .221)

0° – 8°

0.65

(.0256)

BSC

0.09 – 0.25

0.55 – 0.95

(.0035 – .010)

(.022 – .037)

0.05

0.22 – 0.38

(.009 – .015)

TYP

(.002)

NOTE:

MIN

1. CONTROLLING DIMENSION: MILLIMETERS

MILLIMETERS

2. DIMENSIONS ARE IN

(INCHES)

G28 SSOP 0204

3. DRAWING NOT TO SCALE

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED .152mm (.006") PER SIDE

**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE

1854565af

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

23

LTC1854/LTC1855/LTC1856

Typical applicaTion

5V

10µF

0.1µF

10µF

0.1µF

19

20

AV

DV

DD

CONVST 28

1

2

3

COM

CH0

CH1

MUX ADDRESS

SDI 25

CONTROL

LOGIC

SINGLE-ENDED

OR DIFFERENTIAL

CHANNEL

8-BIT SERIAL

DATA INPUT

BUSY 22

INTERNAL

CLOCK

SELECTION

•

INPUT MUX

(SEE TABLE 1)

26

SCK

INPUT RANGE:

10V

16 SHIFT CLOCK CYCLES

+

–

RD 27

CH7

9

12-/14-/16-BIT

SAMPLING ADC

DATA OUT

OV

DD

21

3V TO 5V

SERIAL I/O

10µF

0.1µF

4.096V

SDO 23

2.5V

REFERENCE

16-BIT SERIAL DATA OUT

1.6384X

8k

–

+

–

V

AGND1 MUXOUT

MUXOUT

10

ADC

12

ADC

13

REFCOMP

AGND2 AGND3 DGND

17 18 24

REF

18545 TA03

14

11

15

16

1µF

10µF

0.1µF

relaTeD parTs

PART NUMBER

Sampling ADCs

LTC1418

DESCRIPTION

COMMENTS

14-Bit, 200ksps, Single 5V or ±5V ADC

16-Bit, 333ksps, ±5V ADC

15mW, Serial/Parallel I/O

LTC1604

90dB SINAD, 220mW Power Dissipation, Pin Compatible with LTC1608

±10V Inputs, 55mW, Byte or Parallel I/O, Pin Compatible with LTC1606

±10V Inputs, 75mW, Byte or Parallel I/O, Pin Compatible with LTC1605

90dB SINAD, 270mW Power Dissipation, Pin Compatible with LTC1604

Conﬁgurable Unipolar/Bipolar Input, Up to 10V Single 5V Supply

Programmable MUX and Sequencer, Parallel I/O

LTC1605

16-Bit, 100ksps, Single 5V ADC

16-Bit, 250ksps, Single 5V ADC

16-Bit, 500ksps, ±5V ADC

LTC1606

LTC1608

LTC1609

16-Bit, 200ksps Serial ADC

LTC1850/LTC1851

10-Bit/12-Bit, 8-Channel, 1.25Msps ADC

LTC1859/LTC1858/ 16-Bit, 14-Bit, 12-Bit, 100ksps, SoftSpan ADCs

LTC1857

Software-Selectable Spans, Pin Compatible with

LTC1864/LTC1865

16-Bit, 1-/2-Channel, 250ksps ADC in MSOP

Single 5V Supply, 850µA with Autoshutdown

LTC1864L/LTC1865L 3V, 16-Bit, 1-/2-Channel, 150ksps ADC in MSOP

Single 3V Supply, 450µA with Autoshutdown

LTC1856/LTC1855/LTC1854

DACs

LTC1588/LTC1589

LTC1592

12-/14-/16-Bit, Serial, SoftSpan I

DACs

Software-Selectable Spans, ±1LSB INL/DNL

OUT

LTC1595

LTC1596

LTC1597

LTC1650

16-Bit Serial Multiplying I

DAC in SO-8

DAC

±1LSB Max INL/DNL, Low Glitch, DAC8043 16-Bit Upgrade

±1LSB Max INL/DNL, Low Glitch, AD7543/DAC8143 16-Bit Upgrade

±1LSB Max INL/DNL, Low Glitch, 4 ꢀuadrant Resistors

Low Power, Low Glitch, 4-ꢀuadrant Multiplication

OUT

16-Bit Parallel, Multiplying DAC

16-Bit Serial V ±5V DAC

OUT

LTC2704-16/

LTC2704-14/

LTC2704-12

16-Bit, 14-Bit, 12-Bit, Serial, ꢀuad SoftSpan

DACs

Software-Selectable Spans, ±2LSB INL, ±1LSB INL,

Force/Sense Output

V

OUT

185456fa

LT 0407 REV A • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

24

●

 LINEAR TECHNOLOGY CORPORATION 2006

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC1854IG#PBF
厂家：	Linear
描述：	LTC1854 - 8-Channel, ±10V Input 12-Bit, 100ksps ADC Converter with Shutdown; Package: SSOP; Pins: 28; Temperature Range: -40°C to 85°C 光电二极管转换器
文件：	总24页 (文件大小：630K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC1854IG#PBF [Linear]

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