LTC1855CG_技术文档

LTC1854/LTC1855/LTC1856

8-Channel, ±10V Input

12-/14-/16-Bit, 100ksps ADC

Converters with Shutdown

U

FEATURES

DESCRIPTIO

The LTC^®1854/LTC1855/LTC1856 are 8-channel, low

power, 12-/14-/16-bit, 100ksps, analog-to-digital con-

verters (ADCs). These ADCs operate from a single 5V

supplyandthe8-channelmultiplexercanbeprogrammed

for single-ended inputs, pairs of differential inputs, or

combinations of both. In addition, all channels are fault

protected to ±30V. A fault condition on any channel will

not affect the conversion result of the selected channel.

■

Single 5V Supply

■

Sample Rate: 100ksps

■

8-Channel Multiplexer with ±30V Protection

■

±10V Bipolar Input Range

Single Ended or Differential

■

±3LSB INL for the LTC1856, ±1.5LSB INL for the

LTC1855, ±1LSB INL for the LTC1854

■

Power Dissipation: 40mW (Typ)

SPI/MICROWIRE^TMCompatible Serial I/O

■

An onboard precision reference minimizes external com-

ponents. Powerdissipationis40mWat100kspsandlower

in two power shutdown modes (27.5mW in Nap mode and

40mW in Sleep mode.) DC specifications include ±3LSB

INL for the LTC1856, ±1.5LSB INL for the LTC1855 and

±1LSB for the LTC1854.

■

Power Shutdown: Nap and Sleep

SINAD: 87dB (LTC1856)

Operates with Internal or External Reference

Internal Synchronized Clock

28-Pin SSOP Package

■

U

APPLICATIO S

The internal clock is trimmed for 5ms maximum conver-

sion time and the sampling rate is guaranteed at 100ksps.

Aseparateconvertstartinputanddatareadysignal(BUSY)

ease connections to FIFOs, DSPs and microprocessors.

■

Industrial Process Control

■

Multiplexed Data Acquisition Systems

■

High Speed Data Acquisition for PCs

Digital Signal Processing

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

■

U

TYPICAL APPLICATIO

100kHz, 12-Bit/14-/16-Bit Sampling ADC

LTC1856 Typical INL Curve

2.0

COM

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

CONVST

1.5

1.0

0.5

0

RD

SCK

SDI

LTC1854/

LTC1855/

LTC1856

μP

CONTROL

LINES

SOFTWARE-PROGRAMMABLE

SINGLE-ENDED OR

DGND

SDO

BUSY

DIFFERENTIAL INPUTS

±10V BIPOLAR INPUT RANGE

–0.5

–1.0

–1.5

–2.0

3V TO 5V

5V

OV

DV

AV

DD

+

MUXOUT

–

AGND3

AGND2

REFCOMP

0.1μF

10μF

0.1μF

10μF

0.1μF

+

ADC

–

ADC

–32768

–16384

0

16384

32767

AGND1

V

2.5V

REF

CODE

1μF

10μF

0.1μF

185456 G01

185456fa

1

LTC1854/LTC1855/LTC1856

W W W

U

U W

U

ABSOLUTE AXI U RATI GS

PACKAGE/ORDER I FOR ATIO

(Notes 1, 2)

TOP VIEW

Supply Voltage (OV_DD= DV_DD= AV_DD= V_DD) ........... 6V

Ground Voltage Difference

1

2

CONVST

RD

28

27

26

25

24

23

22

21

20

19

18

17

16

15

COM

CH0

CH1

CH2

CH3

CH4

CH5

CH6

DGND, AGND1, AGND2, AGND3 ...................... ±0.3V

Analog Input Voltage

3

SCK

4

SDI

ADC⁺, ADC^–

5

DGND

SDO

(Note 3) ...................(AGND1 – 0.3V) to (AV_DD+ 0.3V)

CH0-CH7, COM.................................................. ±30V

Digital Input Voltage (Note 4) ...... (DGND – 0.3V) to 10V

Digital Output Voltage .... (DGND – 0.3V) to (DV_DD+ 0.3V)

Power Dissipation .............................................. 500mW

Operating Temperature Range

LTC1854C/LTC1855C/LTC1856C ............ 0∞C to 70∞C

LTC1854I/LTC1855I/LTC1856I .......... –40∞C to 85∞C

Storage Temperature Range ................. –65∞C to 150∞C

Lead Temperature (Soldering, 10 sec) ................. 300∞C

6

7

BUSY

8

OV

DD

9

DV

DD

CH7

+

10

11

12

13

14

AV

DD

MUXOUT

–

+

–

AGND3

MUXOUT

ADC

AGND2

REFCOMP

ADC

V

REF

AGND1

G PACKAGE

28-LEAD PLASTIC SSOP

T_JMAX= 110∞C, q_JA= 95∞C/W

ORDER PART NUMBER

LTC1854CG

LTC1854IG

LTC1855CG

LTC1855IG

LTC1856CG

LTC1856IG

Order Options Tape and Reel: Add #TR

Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF

Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts specified with wider operating temperature ranges.

U

U W

CO VERTER A D ULTIPLEXER CHARACTERISTICS

The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T_A= 25∞C.

MUXOUT connected to ADC inputs. (Notes 5, 6)

LTC1854

MIN TYP MAX MIN

LTC1855

TYP MAX MIN

LTC1856

TYP MAX UNITS

PARAMETER

CONDITIONS

Resolution

●

12

14

16

15

Bits

No Missing Codes

Transition Noise

0.06

0.25

1

LSB

RMS

Integral Linearity Error

Differential Linearity Error

Bipolar Zero Error

Bipolar Zero Error Drift

Bipolar Zero Error Match

Bipolar Full-Scale Error

(Note 7)

(Note 8)

●

±1

1

±1.5

1.5

±3

4

LSB

–1

–2

LSB

±5

±8

±23

±0.1

ppm/∞C

3

4

10

LSB

External Reference (Note 11)

Internal Reference (Note 11)

●

±0.34

±0.45

±0.14

±0.40

±0.1

±0.4

%

Bipolar Full-Scale Error Drift

External Reference

Internal Reference

±2.5

±7

±2.5

±7

±2.5

±7

ppm/∞C

Bipolar Full-Scale Error Match

Input Common Mode Range

5

10

15

LSB

V

±10

Input Common Mode Rejection Ratio

96

dB

185456fa

2

LTC1854/LTC1855/LTC1856

A ALOG I PUT _{The ● denotes the specifications which apply over the full operating temperature range, otherwise}

U

specifications are at T_A= 25∞C. (Note 5)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

Analog Input Range

CH0 to CH7, COM

±10

+

–

ADC , ADC (Note 3)

ADC ±2.048

V

Impedance

Capacitance

CH0 to CH7, COM

31

5

kW

pF

+

–

MUXOUT , MUXOUT

CH0 to CH7, COM

5

+

–

Sample Mode ADC , ADC

12

4

pF

+

–

Hold Mode ADC , ADC

pF

+

–

Input Leakage Current

ADC , ADC , CONVST = Low

●

±1

mA

U W

DY A IC ACCURACY ^The● denotes the specifications which apply over the full operating temperature range,

otherwise specifications are at T_A= 25∞C. MUXOUT connected to ADC inputs. (Note 5)

LTC1854

MIN TYP MAX MIN

LTC1855

TYP MAX MIN

LTC1856

TYP MAX

SYMBOL PARAMETER

CONDITIONS

UNITS

dB

S/(N + D) Signal-to-(Noise + Distortion) Ratio 1kHz Input Signal

74

83

87

THD

Total Harmonic Distortion

1kHz Input Signal,

First Five Harmonics

–102

–95

–101

dB

Peak Harmonic or Spurious Noise

Channel-to-Channel Isolation

–3dB Input Bandwidth

Aperture Delay

1kHz Input Signal

–99

–120

1

–99

–120

1

–103

–120

1

dB

MHz

ns

–70

60

–70

60

–70

60

Aperture Jitter

ps

Transient Response

Full-Scale Step

(Note 9)

4

ms

Overvoltage Recovery

(Note 12)

150

ns

185456fa

3

LTC1854/LTC1855/LTC1856

U U

U

I TER AL REFERE CE CHARACTERISTICS

The ● denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at T_A= 25∞C. (Note 5)

PARAMETER CONDITIONS

MIN

TYP

2.50

±10

8

MAX

UNITS

V

Output Voltage

I

= 0

●

2.475

2.525

V

ppm/∞C

kW

REF

OUT

Output Temperature Coefficient

Output Impedance

REF

–0.1mA £ I

£ 0.1mA

REF

OUT

Output Voltage

I

= 0

OUT

4.096

V

REFCOMP

U

DIGITAL I PUTS A D DIGITAL OUTPUTS ^The● denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at T_A= 25∞C. (Note 5)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

High Level Input Voltage

Low Level Input Voltage

Digital Input Current

Digital Input Capacitance

High Level Output Voltage

V

= 5.25V

= 4.75V

= 0V to V

●

2.4

V

IH

IL

DD

IN

0.8

I

±10

mA

pF

IN

DD

C

V

5

IN

V

= 4.75V, I = –10mA, OV = V

DD

4.74

V

OH

DD

O

DD

= 4.75V, I = –200mA, OV = V

●

4

O

DD

V

Low Level Output Voltage

V

= 4.75V, I = 160mA, OV = V

DD

0.05

0.10

V

OL

DD

O

DD

= 4.75V, I = 1.6mA, OV = V

●

0.4

O

DD

I

Hi-Z Output Leakage

Hi-Z Output Capacitance

Output Source Current

Output Sink Current

V

= 0V to V , RD = High

±10

mA

pF

OZ

OUT

DD

C

RD = High

15

–10

10

OZ

I

V

= 0V

mA

SOURCE

SINK

OUT

= V

DD

W U

POWER REQUIRE E TS

The ● denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25∞C. (Note 5)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Positive Supply Voltage

(Notes 9 and 10)

4.75

5.00

5.25

V

Positive Supply Current

Nap Mode

Sleep Mode

●

8.0

5.5

8.0

12

7

13

mA

CONVST = 0V or 5V

Power Dissipation

Nap Mode

Sleep Mode

40.0

27.5

40.0

mW

185456fa

4

LTC1854/LTC1855/LTC1856

W U

TI I G CHARACTERISTICS

The ● denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25∞C. (Note 5)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

f

Maximum Sampling Frequency

Through CH0 to CH7 Inputs

Through ADC , ADC Only

●

100

kHz

SAMPLE(MAX)

+

–

166

4

t

Conversion Time

Acquisition Time

●

5

4

ms

CONV

ACQ

Through CH0 to CH7 Inputs

ms

+

–

Through ADC , ADC Only

(Note 13)

1

f

t

SCK Frequency

SDO Rise Time

SDO Fall Time

●

0

20

MHz

ns

SCK

r

See Test Circuits

6

f

CONVST High Time

CONVST to BUSY Delay

SCK Period

●

40

1

C = 25pF, See Test Circuits

L

15

30

2

50

10

3

SCK High

4

SCK Low

5

Delay Time, SCKØ to SDO Valid

C = 25pF, See Test Circuits

L

25

20

45

30

6

Time from Previous SDO Data Remains C = 25pF, See Test Circuits

Valid After SCKØ

5

7

L

t

SDO Valid After RDØ

C = 25pF, See Test Circuits

L

●

11

ns

8

RDØ to SCK Setup Time

SDI Setup Time Before SCK≠

SDI Hold Time After SCK≠

SDO Valid Before BUSY≠

Bus Relinquish Time

20

0

9

10

11

12

13

7

RD = Low, C = 25pF, See Test Circuits

5

20

10

L

See Test Circuits

30

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All voltage values are with respect to ground with DGND, AGND1,

AGND2 and AGND3 wired together unless otherwise noted.

Note 7: Integral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual end points of the transfer curve.

The deviation is measured from the center of the quantization band.

Note 8: Bipolar zero error is the offset voltage measured from –0.5LSB

when the output code flickers between 0000 0000 0000 0000 and 1111

1111 1111 1111 for the LTC1856, between 00 0000 0000 0000 and 11

1111 1111 1111 for the LTC1855 and between 0000 0000 0000 and 1111

1111 1111 for the LTC1854.

Note 3: When these pin voltages are taken below ground or above AV

=

DD

DV = OV = V , they will be clamped by internal diodes. This product

DD

can handle currents of greater than 100mA below ground or above V

without latchup.

Note 4: When these pin voltages are taken below ground they will be

clamped by internal diodes. This product can handle currents of greater

than 100mA below ground without latchup. These pins are not clamped

Note 9: Guaranteed by design, not subject to test.

Note 10: Recommended operating conditions.

Note 11: Full-scale bipolar error is the worst case of –FS or +FS

untrimmed deviation from ideal first and last code transitions, divided by

the full-scale range, and includes the effect of offset error.

DD

to V

.

DD

Note 12: Recovers to specified performance after (2 • FS) input

overvoltage.

Note 5: V = 5V, f

= 100kHz, t = t = 5ns unless otherwise

r f

DD

SAMPLE

specified.

Note 13: t of 45ns maximum allows f

up to 10MHz for rising capture

6

SCK

Note 6: Linearity, offset and full-scale specifications apply for a single-

with 50% duty cycle and f

up to 20MHz for falling capture (with 5ns

SCK

+

ended analog MUX input with respect to ground or ADC with respect to

setup time for the receiving logic).

–

ADC tied to ground.

185456fa

5

LTC1854/LTC1855/LTC1856

U W

TYPICAL PERFOR A CE CHARACTERISTICS

LTC1856 Nonaveraged

4096-Point FFT Plot

LTC1856 Typical INL Curve

LTC1856 Typical DNL Curve

2.0

1.5

2.0

1.5

0

–10

–20

f

= 100kHz

SAMPLE

= 1kHz

SINAD = 87dB

THD = –101dB

IN

–30

1.0

–40

–50

–60

–70

0.5

0

–0.5

–1.0

–1.5

–2.0

–0.5

–1.0

–1.5

–2.0

–80

–90

–100

–110

–120

–130

0

–32768

–16384

16384

32767

–32768

–16384

16384

32767

20

0

5

10 15

25 30 35 40 45 50

CODE

FREQUENCY (kHz)

185456 G01

185456 G02

185456 G03

LTC1855 Nonaveraged

4096-Point FFT Plot

LTC1855 Typical INL Curve

LTC1855 Typical DNL Curve

0

–10

–20

1

0.8

0.6

0.4

0.2

f

= 100kHz

SAMPLE

IN

= 1kHz

0.8

0.6

0.4

0.2

SINAD = 83dB

THD = –95dB

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

0

–0.2

–0.4

–0.6

–0.8

–1

0

–0.2

–0.4

–0.6

–0.8

–1

–8192

20

0

5

10 15

25 30 35 40 45 50

0

–8192

–4096

4096

8191

0

–4096

4096

8191

FREQUENCY (kHz)

CODE

185456 G06

185455 G04

185456 G05

LTC1854 Nonaveraged

4096-Point FFT Plot

LTC1854 Typical INL Curve

LTC1854 Typical DNL Curve

0

–10

–20

1.0

0.8

1.0

0.8

f

= 100kHz

SAMPLE

IN

= 1kHz

SINAD = 73.6dB

THD = –102dB

0.6

–30

0.4

–40

0.4

–50

–60

–70

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–0.8

–1.0

–80

–90

–100

–110

–120

–130

0

10

20

30

40

50

–2048

–1024

0

1024

2047

–2048

–1024

0

1024

2047

FREQUENCY (kHz)

CODE

185456 G09

185456 G08

185456 G07

185456fa

6

LTC1854/LTC1855/LTC1856

TYPICAL PERFOR A CE CHARACTERISTICS

U W

LTC1856 Channel-to-Channel

Offset Error Matching vs

Temperature

LTC1856 SINAD

LTC1856 Total Harmonic

vs Input Frequency

Distortion vs Input Frequency

90

88

86

84

82

80

78

76

74

1.0

0.5

0

–70

–80

–90

–0.5

–100

–110

–1.0

1

10

100

–50

–25

0

25

50

75

100

1

10

100

INPUT FREQUENCY (kHz)

TEMPERATURE (°C)

INPUT FREQUENCY (kHz)

185456 G10

185456 G12

185456 G11

LTC1855 Channel-to-Channel

Offset Error Matching vs

Temperature

LTC1855 SINAD

vs Input Frequency

LTC1855 Total Harmonic

Distortion vs Input Frequency

–60

–70

85

80

75

0.5

0.25

0

–80

–90

70

–0.25

–100

–110

65

60

–0.5

1

10

100

–50

–25

0

25

50

75

100

1

10

100

INPUT FREQUENCY (kHz)

TEMPERATURE (°C)

INPUT FREQUENCY (kHz)

185456 G14

185456 G15

185456 G13

LTC1854 Channel-to-Channel

Offset Error Matching vs

Temperature

LTC1854 SINAD

LTC1854 Total Harmonic

Distortion vs Input Frequency

vs Input Frequency

–60

–70

80

75

70

65

60

0.25

0.20

0.15

0.10

0.05

0

–80

–90

–0.05

–0.10

–0.15

–0.20

–0.25

–100

–110

100

1

10

1

10

100

–50 –25

25

50

75

100

0

INPUT FREQUENCY (kHz)

TEMPERATURE (°C)

185456 G17

185456 G16

185456 G18

185456fa

7

LTC1854/LTC1855/LTC1856

U W

TYPICAL PERFOR A CE CHARACTERISTICS

LTC1856 Channel-to-Channel Gain

Error Matching vs Temperature

LTC1855 Channel-to-Channel Gain

Error Matching vs Temperature

LTC1854 Channel-to-Channel Gain

Error Matching vs Temperature

1.0

0.5

0

0.25

0.20

0.15

0.10

0.05

0

0.5

0.25

0

–0.05

–0.10

–0.15

–0.20

–0.25

–0.5

–0.25

–1.0

–0.5

–50

–25

0

25

50

75

100

–50 –25

25

50

75

100

0

–50 –25

0

25

50

75

100

TEMPERATURE (°C)

185456 G19

185456 G21

185456 G20

Internal Reference Voltage

vs Temperature

Change in REFCOMP Voltage

vs Load Current

LTC1856 Power Supply

Feedthrough vs Ripple Frequency

0.04

0.02

0

2.520

2.515

2.510

2.505

2.500

2.495

2.490

2.485

2.480

–10

–20

–30

–40

–50

–60

–70

–80

f

= 100kHz

= 60mV

SAMPLE

RIPPLE

V

–0.02

–0.04

–50 –40

–30

–20

–10

0

10

–25

0

50

100

1k

10k

100k

1M

–50

75

100

25

LOAD CURRENT (mA)

RIPPLE FREQUENCY (Hz)

TEMPERATURE (°C)

185456 G24

185456 G23

185456 G22

Supply Current vs Supply Voltage

Supply Current vs Temperature

9.0

8.5

8.0

7.5

9.0

8.5

8.0

7.5

7.0

f = 100kHz

SAMPLE

f

= 100kHz

SAMPLE

7.0

–50 –25

0

25

50

75

100

5

5.25

4.5

5.5

4.75

TEMPERATURE (°C)

SUPPLY VOLTAGE (V)

185456 G26

185454 G25

185456fa

8

LTC1854/LTC1855/LTC1856

U

PI FU CTIO S

AGND1 (Pin 14): Analog Ground.

COM (Pin 1): Common Input. This is the negative refer-

ence point for all single-ended inputs. It must be free of

noiseandisusuallyconnectedtotheanaloggroundplane.

V_REF(Pin 15): 2.5V Reference Output. Bypass to analog

ground with a 1mF tantalum capacitor.

CH0 (Pin 2): Analog MUX Input.

CH1 (Pin 3): Analog MUX Input.

CH2 (Pin 4): Analog MUX Input.

CH3 (Pin 5): Analog MUX Input.

CH4 (Pin 6): Analog MUX Input.

CH5 (Pin 7): Analog MUX Input.

CH6 (Pin 8): Analog MUX Input.

CH7 (Pin 9): Analog MUX Input.

REFCOMP (Pin 16): Reference Buffer Output. Bypass to

analog ground with a 10mF tantalum and a 0.1mF ceramic

capacitor. Nominal output voltage is 4.096V.

AGND2 (Pin 17): Analog Ground.

AGND3 (Pin 18): Analog Ground. This is the substrate

connection.

AV_DD(Pin19):5VAnalogSupply.Bypasstoanalogground

with a 0.1mF ceramic and a 10mF tantalum capacitor.

DV_DD(Pin20):5VDigitalSupply. Bypasstodigitalground

with a 0.1mF ceramic and a 10mF tantalum capacitor.

MUXOUT⁺(Pin 10): Positive MUX Output. Output of the

analogmultiplexer.ConnecttoADC⁺fornormaloperation.

OV_DD(Pin 21): Positive Supply for the Digital Output

Buffers (3V to 5V). Bypass to digital ground with a 0.1mF

ceramic and a 10mF tantalum capacitor.

MUXOUT^–(Pin 11): Negative MUX Output. Output of the

analogmultiplexer.ConnecttoADC^–fornormaloperation.

ADC⁺(Pin 12): Positive Analog Input to the Analog-to-

Digital Converter.

BUSY (Pin 22): Output shows converter status. It is low

when a conversion is in progress.

ADC^–(Pin 13): Negative Analog Input to the Analog-to-

Digital Converter.

SDO (Pin 23): Serial Data Output.

185456fa

9

LTC1854/LTC1855/LTC1856

U

PI FU CTIO S

DGND (Pin 24): Digital Ground.

SDI (Pin 25): Serial Data Input.

SCK (Pin 26): Serial Data Clock.

RD(Pin27):ReadInput. Thisactivelowsignalenablesthe

digitaloutputpinSDOandenablestheserialinterface, SDI

and SCK are ignored when RD is high.

CONVST (Pin 28): Conversion Start. The ADC starts a

conversion on CONVST’s rising edge.

U

W

FU CTIO AL BLOCK DIAGRA

DV

AV

DD

20

DD

19

MUX ADDRESS

2

28

25

22

CONVST

CH0

3

CONTROL

LOGIC

CH1

SDI

INTERNAL

CLOCK

BUSY

•

INPUT MUX

26

SCK

RD

•

+

27

21

9

12-/14-/16-BIT

SAMPLING ADC

CH7

DATA OUT

1

SERIAL I/O

OV

DD

COM

–

23

SDO

4.096V

2.5V

REFERENCE

1.6384X

8k

–

+

–

MUXOUT

ADC

14

AGND1

11 10

12 13

15

16

REFCOMP

17

18

24

V

AGND2 AGND3 DGND

REF

18545 BD

185456fa

10

LTC1854/LTC1855/LTC1856

TEST CIRCUITS

Load Circuits for Access Timing

Load Circuits for Output Float Delay

5V

1k

5V

1k

DN

1k

25pF

(A) Hi-Z TO V AND V TO V

OH OL OH

(B) Hi-Z TO V AND V TO V

(A) V TO Hi-Z

OH

(B) V TO Hi-Z

OL

OH

OL

18545 TC01

18545 TC02

W U

W

TI I G DIAGRA S

t (CONVST to BUSY Delay)

2

t

2

2.4V

t

(For Short Pulse Mode)

1

CONVST

BUSY

t

1

50%

CONVST

0.4V

18545 TD01

18545 TD02

t (Delay Time, SCK to SDO Valid)

6

t (Time from Previous Data Remains Valid After SCK )

7

t

6

7

t , t , t (SCK Timing)

3

4 5

SCK

SDO

0.4V

t

5

4

SCK

2.4V

0.4V

18545 TD03

t

3

18545 TD04

t (RD to SCK Setup Time)

9

t (SDO Valid After RD )

8

t

8

t

9

RD

0.4V

RD

0.4V

Hi-Z

2.4V

0.4V

SCK

SDO

18545 TD06

18545 TD05

185456fa

11

LTC1854/LTC1855/LTC1856

WU

W

TI I G DIAGRA S

t

(SDI Setup Time Before SCK )

t

11

(SDI Hold Time After SCK )

10

t

11

10

2.4V

SCK

SDI

SCK

SDI

2.4V

0.4V

2.4V

0.4V

18545 TD07

18545 TD08

t

(SDO Valid Before BUSY , RD = 0)

t

(BUS Relinquish Time)

13

12

t

12

13

2.4V

BUSY

SDO

RD

90%

10%

Hi-Z

2.4V

B15

SDO

18545 TD10

18545 TD09

185456fa

12

LTC1854/LTC1855/LTC1856

W U U

U

APPLICATIO S I FOR ATIO

Before starting a conversion, an 8-bit data word is clocked

into the SDI input on the first eight rising SCK edges to

select the MUX address and power down mode. The ADC

enters acquisition mode on the falling edge of the sixth

clock in the 8-bit data word and ends on the rising edge of

the CONVST signal which also starts a conversion (see

Figure7).Aminimumtimeof4mswillprovideenoughtime

for the sample-and-hold capacitors to acquire the analog

signal. Once a conversion cycle has begun, it cannot be

restarted.

OVERVIEW

The LTC1854/LTC1855/LTC1856 are innovative, multi-

channel ADCs. The on-chip resistors provide attenuation

andoffsetforeachchannel. Thepreciselytrimmedattenu-

ators ensure an accurate input range. Because they pre-

cede the multiplexer, errors due to multiplexer

on-resistance are eliminated.

The input word selects the single ended or differential

inputs for each channel or pair of channels. Overrange

protection is provided for unselected channels. An

overrange condition on an unused channel will not affect

the conversion result on the selected channel.

Duringtheconversion,theinternaldifferential12-/14-/16-

bitcapacitiveDACoutputissequencedbytheSARfromthe

mostsignificantbit(MSB)totheleastsignificantbit(LSB).

The input is successively compared with the binary

weighted charges supplied by the differential capacitive

DAC. Bit decisions are made by a high speed comparator.

At the end of a conversion, the DAC output balances the

analog input (ADC⁺– ADC^–). The SAR contents (a 12-/14-

/16-bitdataword)whichrepresentsthedifferenceofADC⁺

and ADC^–are loaded into the 12-/14-/16-bit shift register.

CONVERSION DETAILS

TheLTC1854/LTC1855/LTC1856useasuccessiveapproxi-

mation algorithm and an internal sample-and-hold circuit

to convert an analog signal to a 12-/14-/16-bit serial out-

put respectively. The ADCs are complete with a precision

reference and an internal clock. The control logic provides

easyinterfacetomicroprocessorsandDSPs.(Pleaserefer

to the Digital Interface section for the data format.)

DRIVING THE ANALOG INPUTS

The analog signals applied at the MUX input channels are

rescaled by the resistor divider network formed by R1, R2

and R3 as shown below. The rescaled signals appear on

theMUXOUT(Pins10,11)whicharealsoconnectedtothe

ADC inputs (Pins 12, 13) under normal operation.

The input range for the LTC1854/LTC1855/LTC1856 is

±10V and the MUX inputs are overvoltage protected to

±30V. The input impedance is typically 31kW; therefore, it

should be driven with a low impedance source. Wideband

noise coupling into the input can be minimized by placing

a 3000pF capacitor at the input as shown in Figure 2. An

NPO-type capacitor gives the lowest distortion. Place the

capacitor as close to the device input pin as possible. If an

amplifier is to be used to drive the input, care should be

takentoselectanamplifierwithadequateaccuracy,linear-

ity and noise for the application. The following list is a

summary of the op amps that are suitable for driving the

LTC1854/LTC1855/LTC1856. More detailed information

isavailableintheLinearTechnologydatabooksandonline

at www.linear.com.

REFCOMP

R3

R1

CH SEL

10k

25k

MUX

INPUT

MUXOUT

R2

17k

18545 AI01

LT^®1007: Low noise precision amplifier. 2.7mA supply

current ±5V to ±15V supplies. Gain bandwidth product

8MHz. DC applications.

185456fa

13

LTC1854/LTC1855/LTC1856

W U U

U

APPLICATIO S I FOR ATIO

DV

AV

DD

MUX ADDRESS

CONVST

CH0

CH1

CONTROL

LOGIC

SDI

INTERNAL

CLOCK

BUSY

•

INPUT MUX

SCK

RD

+

12-/14-/16-BIT

SAMPLING ADC

CH7

DATA OUT

SERIAL I/O

OV

DD

COM

–

SDO

4.096V

2.5V

REFERENCE

1.6384X

8k

–

+

–

18545 F01

MUXOUT

ADC

AGND1

V

REFCOMP

AGND2 AGND3 DGND

REF

Figure 1. LTC1854/LTC1855/LTC1856 Simplified Equivalent Circuit

LT1792: Single, low noise JFET input op amp, ±5V

supplies.

+

–

A

CH0

CH1

IN

3000pF

IN

LT1793: Single, low noise JFET input op amp, 10pA bias

•

current, ±5V supplies.

+

–

MUXOUT

LT1881/LT1882: Dual and quad, 200pA bias current, rail-

to-rail output op amps. Up to ±15V supplies.

+

ADC

–

ADC

LT1844/LT1885: Dual and quad, 400pA bias current, rail-

to-rail output op amps. Up to ±15V supplies. Faster

response and settling time.

18545 F02

Figure 2. Analog Input Filtering

INTERNAL VOLTAGE REFERENCE

LT1227: 140MHz video current feedback amplifier. 10mA

supply current. ±5V to ± 15V supplies. Low noise and low

distortion.

The LTC1854/LTC1855/LTC1856 have an on-chip, tem-

perature compensated, curvature corrected, bandgap ref-

erence, which is factory trimmed to 2.50V. The full-scale

rangeoftheLTC1854/LTC1855/LTC1856isequalto ±10V.

The output of the reference is connected to the input of a

gain of 1.6384x buffer through an 8k resistor (see Figure

3). The input to the buffer or the output of the reference is

LT1468/LT1469: Single and dual 90MHz, 16-bit accurate

op amp. Good AC/DC specs. ±5V to ±15V supplies.

LT1677: Single, low noise op amp. Rail-to-rail input and

output. Up to ±15V supplies.

185456fa

14

LTC1854/LTC1855/LTC1856

W U U

APPLICATIO S I FOR ATIO

U

available at V_REF(Pin 15). The internal reference can be

overdriven with an external reference if more accuracy is

needed. The buffer output drives the internal DAC and is

available at REFCOMP (Pin 16). The REFCOMP pin can be

used to drive a steady DC load of less than 2mA. Driving

an AC load is not recommended because it can cause the

performance of the converter to degrade.

successive integer LSB values (i.e., –FS+0.5LSB,

–FS+1.5LSB, –FS+2.5LSB, … FS–1.5LSB, FS–0.5LSB).

The output is two’s complement binary with:

FS –(–FS) 20V

1LSB =

=

= 305.2mV

65566

65536

In applications where absolute accuracy is important,

offset and full-scale errors can be adjusted to zero during

a calibration sequence. Offset error must be adjusted

before full-scale error. Zero offset is achieved by adjusting

theoffsetappliedtothe“–”input. Forsingle-endedinputs,

this offset should be applied to the COM pin. For differen-

tial inputs, the “–” input is dictated by the MUX address.

8k

15

1μF

V

REF

2.5V

REFERENCE

12-/14-/16-BIT

CAPACITIVE DAC

1.6384X BUFFER

16 REFCOMP

4.096V

0.1μF

For zero offset error, apply –0.5LSB to the “+” input and

adjust the offset at the “–” input until the output code

flickers between 0000 0000 0000 0000 and 1111 1111

11111111fortheLTC1856,between00000000000000

and 11 1111 1111 1111 for the LTC1855 and between

0000 0000 0000 and 1111 1111 1111 for the LTC1854.

18545 F03

10μF

Figure 3. Internal or External Reference Source

For minimum code transition noise the V_REFpin and the

REFCOMPpinshouldeachbedecoupledwithacapacitor

tofilterwidebandnoisefromthereferenceandthebuffer.

Forfull-scaleadjustment, aninputvoltageofFS–1.5LSBs

should be applied to the “+” input and the appropriate

reference adjusted until the output code flickers between

0111 1111 1111 1110 and 0111 1111 1111 1111 for the

LTC1856, between 01 1111 1111 1110 and 01 1111 1111

1111 for the LTC1855 and between 0111 1111 1110 and

0111 1111 1111 for the LTC1854.

FULL SCALE AND OFFSET

Figure 4 shows the ideal input/output characteristics for

theLTC1856. Thecodetransitionsoccurmidwaybetween

These adjustments as well as the factory trims affect all

channels. The channel-to-channel offset and gain error

matching are guaranteed by design to meet the specifica-

tions in the Converter Characteristics table.

011...111

011...110

000...001

000...000

111...111

111...110

100...001

100...000

–(FS – 1LSB)

FS – 1LSB

INPUT VOLTAGE (V)

18545 F04

Figure 4. Bipolar Transfer Characteristics

185456fa

15

LTC1854/LTC1855/LTC1856

W U U

U

APPLICATIO S I FOR ATIO

DC PERFORMANCE

cated output supply pin (OV_DD) that controls the output

swings of the digital output pins (SDO, BUSY) and allows

the part to interface to either 3V or 5V digital systems. The

SDO output is two’s complement.

One way of measuring the transition noise associated

with a high resolution ADC is to use a technique where a

DC signal is applied to the input of the MUX and the

resulting output codes are collected over a large number

of conversions. For example in Figure 5 the distribution of

outputcodeisshownforaDCinputthathasbeendigitized

4096 times. The distribution is Gaussian and the RMS

code transition is about 1LSB for the LTC1856.

Timing and Control

Conversion start and data read are controlled by two

digital inputs: CONVST and RD. To start a conversion and

putthesample-and-holdintotheholdmodebringCONVST

high for at least 40ns. Once initiated it cannot be restarted

until the conversion is complete. Converter status is

indicated by the BUSY output, which goes low while the

conversion is in progress.

DIGITAL INTERFACE

Internal Clock

Figures 6a and 6b show two different modes of operation

for the LTC1856. For the 12-bit LTC1854 and 14-bit

LTC1855, the last four and two bits of the SDO will output

zeros, respectively. In mode 1 (Figure 6a), RD is tied low.

TherisingedgeofCONVSTstartstheconversion. Thedata

outputs are always enabled. The MSB of the data output is

available after the conversion. In mode 2 (Figure 6b),

CONVST and RD are tied together. The rising edge of the

CONVST signal starts the conversion. Data outputs are in

three-state at this time. When the conversion is complete

(BUSY goes high), CONVST and RD go low to enable the

data output for the previous conversion.

The ADC has an internal clock that is trimmed to achieve

a typical conversion time of 4ms. No external adjustments

arerequiredand,withthemaximumacquisitiontimeof4ms,

throughput performance of 100ksps is assured.

3V Input/Output Compatible

The LTC1854/LTC1855/LTC1856 operate on a 5V supply,

which makes the devices easy to interface to 5V digital

systems. These devices can also interface to 3V digital

systems: the digital input pins (SCK, SDI, CONVST and

RD) of the LTC1854/LTC1855/LTC1856 recognize 3V or

5V inputs. The LTC1854/LTC1855/LTC1856 have a dedi-

1800

1600

1400

1200

1000

800

600

400

200

0

–4 –3 –2 –1

0

1

4

2

3

CODE

185456 F05

Figure 5. LTC1856 Histogram for 4096 Conversions

185456fa

16

LTC1854/LTC1855/LTC1856

W U U

APPLICATIO S I FOR ATIO

U

185456fa

17

LTC1854/LTC1855/LTC1856

W U U

U

APPLICATIO S I FOR ATIO

SERIAL DATA INPUT (SDI) INTERFACE

is delayed by one conversion from the input word re-

questing it.

The LTC1854/LTC1855/LTC1856 communicate with mi-

croprocessors and other external circuitry via a synchro-

nous, full duplex, 3-wire serial interface (see Figure 7).

The shift clock (SCK) synchronizes the data transfer with

each bit being transmitted on the falling SCK edge and

captured on the rising SCK edge in both transmitting and

receiving systems. The data is transmitted and received

simultaneously (full duplex).

SDI

SDI WORD 1

SDI WORD 2

SDI WORD 3

SDO SDO WORD 0

SDO WORD 1

SDO WORD 2

18545 AI02

t

CONV

A/D

CONV

A/D

DATA

TRANSFER

DATA

TRANSFER

CONVERSION

INPUT DATA WORD

TheLTC1854/LTC1855/LTC18568-bitdatawordisclocked

into the SDI input on the first eight rising SCK edges.

FurtherinputsontheSDIpinarethenignoreduntilthenext

conversion. The eight bits of the input word are defined as

follows:

An 8-bit input word is shifted into the SDI input which

configures the LTC1854/LTC1855/LTC1856 for the next

conversion. Simultaneously, the result of the previous

conversionisoutputontheSDOline.Attheendofthedata

exchange the requested conversion begins by applying a

rising edge on CONVST. After t_CONV, the conversion is

complete and the results will be available on the next data

transfer cycle. As shown below, the result of a conversion

SGL/

DIFF

ODD

SIGN

SELECT SELECT

DON'T

CARE

DON'T

CARE

NAP

SLEEP

1

0

POWER DOWN

SELECTION

MUX ADDRESS

18545 AI03

Table 1. Multiplexer Channel Selection

DIFFERENTIAL CHANNEL SELECTION

SINGLE-ENDED CHANNEL SELECTION

MUX ADDRESS

ODD SELECT

MUX ADDRESS

SGL/ ODD SELECT

SGL/

DIFF SIGN

0

1

2

3

4

5

6

7

COM

0

1

2

3

4

5

6

7

1

0

1

0

1

0

1

0

1

0

1

0

1

DIFF SIGN

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

+

–

1

0

1

+

–

+

–

+

–

+

–

+

–

+

–

+

–

+

Combinations of

Differential and Single-Ended

Changing the

MUX Assignment “On the Fly”

4 Differential

8 Single-Ended

CHANNEL

+

–

+

–

(

)

0

1

2

3

4

5

6

7

+

–

0,1

{

+

–

(

)

+

–

+

–

2,3

{

4,5

6,7

4,5

{

6

7

{

+

4

5

6

7

+

–

+

–

(

)

–

4,5

{

+

COM (UNUSED)

COM ( )

(

)

+

–

6,7

{

+

COM (

)

–

COM (

)

–

1ST CONVERSION

2ND CONVERSION

18545 F08

Figure 8. Examples of Multiplexer Options on the LTC1854/LTC1855/LTC1856

185456fa

18

LTC1854/LTC1855/LTC1856

W U U

APPLICATIO S I FOR ATIO

U

MUX ADDRESS

Sleep mode will occur when Sleep = 1 is selected,

regardless of the selection of the Nap input. The previous

conversion result can be clocked out and the Sleep mode

will start on the falling edge of the last (16th) SCK. Notice

that the CONVST should stay either high or low in sleep

mode (see Figure 10). To wake up from the sleep mode,

apply a rising edge on the CONVST signal and then apply

Sleep = 0 on the next SDI word and the part will wake up

on the falling edge of the last (16th) SCK (see Figure 11).

The first four bits of the input word assign the MUX

configuration for the requested conversion. For a given

channel selection, the converter will measure the voltage

between the two channels indicated by the + and – signs

in the selected row of Table 1. Note that in differential

mode (SGL/DIFF = 0) measurements are limited to four

adjacent input pairs with either polarity. In single-ended

mode, all input channels are measured with respect to

COM. Both the “+” and “–” inputs are sampled simulta-

neously so common mode noise is rejected. Bits 5 and 6

of the input words are Don’t Care bits.

InSleepmode,allbiascurrentsareshutdownandonlythe

power on reset circuit and leakage currents (about 10mA)

remain. Sleep mode wake-up time is dependent on the

valueofthecapacitorconnectedtotheREFCOMP(Pin16).

The wake-up time is typically 40ms with the recom-

mended 10mF capacitor connected on the REFCOMP pin.

P

OWER DOWN SELECTION (NAP, SLEEP)

The last two bits of the input word (Nap and Sleep) deter-

minethepowershutdownmodeoftheLTC1854/LTC1855/

LTC1856. See Table 2. Nap mode is selected when Nap =

1 and Sleep = 0. The previous conversion result will be

clocked out and a conversion will occur before entering

the Nap mode. The Nap mode starts at the end of the con-

version which is indicated by the rising edge of the BUSY

signal. Napmodelastsuntilthefallingedgeofthe2ndSCK

(see Figure 9). Automatic nap will be achieved if Nap = 1

is selected each time an input word is written to the ADC.

DYNAMIC PERFORMANCE

FFT (Fast Fourier Transform) test techniques are used to

test the ADC’s frequency response, distortion and noise

at the rated throughput. By applying a low distortion sine

wave and analyzing the digital output using an FFT

algorithm, the ADC’s spectral content can be examined

forfrequenciesoutsidethefundamental. Figure12shows

a typical LTC1856 FFT plot which yields a SINAD of 87dB

and THD of –101dB.

Table 2. Power Down Selection

NAP

0

SLEEP

POWER DOWN MODE

0

1

Power On

Nap

1

X

Sleep

185456fa

19

LTC1854/LTC1855/LTC1856

W U U

U

APPLICATIO S I FOR ATIO

185456fa

20

LTC1854/LTC1855/LTC1856

W U U

APPLICATIO S I FOR ATIO

U

SIGNAL-TO-NOISE AND DISTORTION RATIO

BOARD LAYOUT, POWER SUPPLIES

AND DECOUPLING

The Signal-to-Noise and Distortion Ratio (SINAD) is the

ratiobetweentheRMSamplitudeofthefundamentalinput

frequency to the RMS amplitude of all other frequency

components at the A/D output. The output is band limited

tofrequenciesfromaboveDCandbelowhalfthesampling

frequency. Figure 12 shows a typical SINAD of 87dB with

a 100kHz sampling rate and a 1kHz input.

Wire wrap boards are not recommended for high resolu-

tion or high speed A/D converters. To obtain the best

performance from the LTC1854/LTC1855/LTC1856, a

printed circuit board is required. Layout for the printed

circuit board should ensure the digital and analog signal

linesareseparatedasmuchaspossible. Inparticular, care

should be taken not to run any digital track alongside an

analog signal track or underneath the ADC. The analog

input should be screened by AGND.

TOTAL HARMONIC DISTORTION

Total Harmonic Distortion (THD) is the ratio of the RMS

sumofallharmonicsoftheinputsignaltothefundamental

itself. The out-of-band harmonics alias into the frequency

band between DC and half the sampling frequency. THD is

expressed as:

In applications where the MUX is connected to the ADC, it

is possible to get noise coupling into the ADC from the

trace connecting the MUXOUT to the ADC. Therefore,

reducing the length of the traces connecting the MUXOUT

pins (Pins 10, 11) to the ADC pins (Pins 12, 13) can

minimize the problem. The unused MUX inputs should be

grounded to prevent noise coupling into the inputs.

2

V₂²+ V₃²+ V₄... + V_N

THD = 20log

V₁

Figure13showsthepowersupplygroundingthatwillhelp

obtain the best performance from the 12-bit/14-bit/16-bit

ADCs. Pay particular attention to the design of the analog

and digital ground planes. The DGND pin of the LTC1854/

where V₁is the RMS amplitude of the fundamental fre-

quency and V₂through V_Nare the amplitudes of the

second through Nth harmonics.

0

–10

–20

f

= 100kHz

SAMPLE

IN

= 1kHz

SINAD = 87dB

THD = –101dB

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

20

0

5

10 15

25 30 35 40 45 50

FREQUENCY (kHz)

185456 F12

Figure 12. LTC1856 Nonaveraged 4096 Point FFT Plot

185456fa

21

LTC1854/LTC1855/LTC1856

W U U

U

APPLICATIO S I FOR ATIO

LTC1855/LTC1856canbetiedtotheanaloggroundplane.

Placing the bypass capacitor as close as possible to the

power supply pins, the reference and reference buffer

outputisveryimportant.Lowimpedancecommonreturns

for these bypass capacitors are essential to low noise op-

erationoftheADC,andthefoilwidthforthesetracksshould

beaswideaspossible. Also, sinceanypotentialdifference

in grounds between the signal source and ADC appears as

an error voltage in series with the input signal, attention

should be paid to reducing the ground circuit impedance

as much as possible. The digital output latches and the

onboard sampling clock have been placed on the digital

ground plane. The two ground planes are tied together at

the ADC through a wide, low inductance path.

LTC1854/

LTC1855/

LTC1856

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

COM

10 12

+

–

+

–

MUXOUT

ADC

DIGITAL

SYSTEM

LTC1854/LTC1855/LTC1856

MUXOUT

+

V

REFCOMP AGND

AV

DV

DGND

24

OV

13

REF

15

DD

20

DD

21

11

–

16 14, 17, 18 19

1μF

10μF

DIGITAL

GROUND PLANE

ANALOG GROUND PLANE

18545 F13

Figure 13. Power Supply Grounding Practice

185456fa

22

LTC1854/LTC1855/LTC1856

U

PACKAGE DESCRIPTIO

G Package

28-Lead Plastic SSOP (5.3mm)

(Reference LTC DWG # 05-08-1640)

9.90 – 10.50*

(.390 – .413)

28 27 26 25 24 23 22 21 20 19 18

16 15

17

1.25 ±0.12

7.8 – 8.2

5.3 – 5.7

7.40 – 8.20

(.291 – .323)

0.42 ±0.03

0.65 BSC

5

7

8

1

2

3

4

6

9 10 11 12 13 14

RECOMMENDED SOLDER PAD LAYOUT

2.0

(.079)

MAX

5.00 – 5.60**

(.197 – .221)

0° – 8°

0.65

(.0256)

BSC

0.09 – 0.25

0.55 – 0.95

(.0035 – .010)

(.022 – .037)

0.05

0.22 – 0.38

(.009 – .015)

TYP

(.002)

NOTE:

MIN

1. CONTROLLING DIMENSION: MILLIMETERS

MILLIMETERS

2. DIMENSIONS ARE IN

(INCHES)

G28 SSOP 0204

3. DRAWING NOT TO SCALE

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED .152mm (.006") PER SIDE

**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE

185456fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

23

LTC1854/LTC1855/LTC1856

U

TYPICAL APPLICATIO

5V

10μF

0.1μF

10μF

0.1μF

19

20

AV

DD

DV

DD

CONVST 28

1

2

3

COM

CH0

CH1

MUX ADDRESS

SDI 25

CONTROL

LOGIC

SINGLE-ENDED

OR DIFFERENTIAL

CHANNEL

8-BIT SERIAL

DATA INPUT

BUSY 22

INTERNAL

CLOCK

SELECTION

•

INPUT MUX

(SEE TABLE 1)

26

SCK

INPUT RANGE:

±10V

16 SHIFT CLOCK CYCLES

+

–

RD 27

CH7

9

12-/14-/16-BIT

SAMPLING ADC

DATA OUT

OV

DD

21

3V TO 5V

10μF

0.1μF

SERIAL I/O

4.096V

SDO 23

2.5V

REFERENCE

16-BIT SERIAL DATA OUT

1.6384X

8k

–

+

–

V

AGND1 MUXOUT

MUXOUT

10

ADC

12

ADC

13

REFCOMP

AGND2 AGND3 DGND

17 18 24

REF

18545 TA03

14

11

15

16

1μF

0.1μF

10μF

RELATED PARTS

PART NUMBER

Sampling ADCs

LTC1418

DESCRIPTION

COMMENTS

15mW, Serial/Parallel I/O

90dB SINAD, 220mW Power Dissipation, Pin Compatible with LTC1608

±10V Inputs, 55mW, Byte or Parallel I/O, Pin Compatible with LTC1606

±10V Inputs, 75mW, Byte or Parallel I/O, Pin Compatible with LTC1605

90dB SINAD, 270mW Power Dissipation, Pin Compatible with LTC1604

Configurable Unipolar/Bipolar Input, Up to 10V Single 5V Supply

Programmable MUX and Sequencer, Parallel I/O

14-Bit, 200ksps, Single 5V or ±5V ADC

16-Bit, 333ksps, ±5V ADC

LTC1604

LTC1605

LTC1606

LTC1608

16-Bit, 100ksps, Single 5V ADC

16-Bit, 250ksps, Single 5V ADC

16-Bit, 500ksps, ±5V ADC

LTC1609

16-Bit, 200ksps Serial ADC

LTC1850/LTC1851

10-Bit/12-Bit, 8-Channel, 1.25Msps ADC

LTC1859/LTC1858/

LTC1857

16-Bit, 14-Bit, 12-Bit, 100ksps, SoftSpan ADCs

Software-Selectable Spans, Pin Compatible with

LTC1864/LTC1865

16-Bit, 1-/2-Channel, 250ksps ADC in MSOP

Single 5V Supply, 850mA with Autoshutdown

LTC1864L/LTC1865L 3V, 16-Bit, 1-/2-Channel, 150ksps ADC in MSOP

Single 3V Supply, 450mA with Autoshutdown

LTC1856/LTC1855/LTC1854

DACs

LTC1588/LTC1589

LTC1592

12-/14-/16-Bit, Serial, SoftSpan I

DACs

Software-Selectable Spans, ±1LSB INL/DNL

OUT

LTC1595

LTC1596

LTC1597

LTC1650

16-Bit Serial Multiplying I

DAC in SO-8

DAC

±1LSB Max INL/DNL, Low Glitch, DAC8043 16-Bit Upgrade

±1LSB Max INL/DNL, Low Glitch, AD7543/DAC8143 16-Bit Upgrade

±1LSB Max INL/DNL, Low Glitch, 4 Quadrant Resistors

Low Power, Low Glitch, 4-Quadrant Multiplication

OUT

16-Bit Parallel, Multiplying DAC

16-Bit Serial V ±5V DAC

OUT

LTC2704-16/

LTC2704-14/

LTC2704-12

16-Bit, 14-Bit, 12-Bit, Serial, Quad SoftSpan

DACs

Software-Selectable Spans, ±2LSB INL, ±1LSB INL,

V

Force/Sense Output

OUT

185456fa

LT 0407 REV A • PRINTED IN THE USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

24

●

„ LINEAR TECHNOLOGY CORPORATION 2006

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC1855CG
厂家：	Linear
描述：	8-Channel, ±10V Input 12-/14-/16-Bit, 100ksps ADC Converters with Shutdown 8通道，± 10V输入12位/ 14位/ 16位， 100ksps的ADC转换器，带有关断转换器
文件：	总24页 (文件大小：299K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC1855CG [Linear]

相关型号：

LTC1855CG#PBF

LTC1855CG#TR

LTC1855CG#TRPBF

LTC1855CG-PBF

LTC1855CG-TR

LTC1855CG-TRPBF

LTC1855IG

LTC1855IG#TRPBF

LTC1855IG-PBF

LTC1855IG-TR

LTC1855IG-TRPBF

LTC1855_15