LTC1851CFW#TRPBF_技术文档

LTC1850/LTC1851

8-Channel, 10-Bit/12-Bit,

1.25Msps Sampling ADCs

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FEATURES

DESCRIPTIO

The 10-bit LTC^®1850 and 12-bit LTC1851 are complete

8-channel data acquisition systems. They include a flex-

ible8-channelmultiplexer,a1.25Mspssuccessiveapproxi-

mation analog-to-digital converter with sample-and-hold,

an internal 2.5V reference and reference buffer amplifier,

andaparalleloutputinterface. Themultiplexercanbecon-

figured for single-ended or differential inputs, two gain

ranges and unipolar or bipolar operation.

■

Flexible 8-Channel Multiplexer

■

Single-Ended or Differential Inputs

■

Two Gain Ranges Plus Unipolar and Bipolar

Operation

1.25Msps Sampling Rate

■

Single 5V Supply and 40mW Power Dissipation

■

Scan Mode and Programmable Sequencer

■

Pin Compatible 10-Bit LTC1850 and 12-Bit LTC1851

■

True Differential Inputs Reject Common Mode Noise

The ADCs have a scan mode that will repeatedly cycle

through all 8 multiplexer channels and can also be

programmed with a sequence of up to 16 addresses and

configurations that can be scanned in succession. The

sequence memory can also be read back. The reference

and buffer amplifier provide pin strappable ranges of

4.096V, 2.5V and 2.048V. The parallel output includes

the 10-bit or 12-bit conversion result plus the 4-bit

multiplexer address. The digital outputs are powered

from a separate supply allowing for easy interface to 3V

digital logic. Typical power consumption is 40mW at

1.25Msps from a single 5V supply.

■

Internal 2.5V Reference

Parallel Output Includes MUX Address

Easy Interface to 3V Logic

Nap and Sleep Shutdown Modes

■

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APPLICATIO S

■

High Speed Data Acquisition

■

Test and Measurement

■

Imaging Systems

■

Telecommunications

■

Industrial Process Control

■

, LTC and LT are registered trademarks of Linear Technology Corporation.

Spectrum Analysis

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BLOCK DIAGRA

M1

SHDN

CS

LTC1851

CH0

CH1

CONVST

RD

CONTROL LOGIC

WR

CH2

CH3

CH4

CH5

CH6

CH7

COM

AND

DIFF

Integral Linearity, LTC1851

PROGRAMMABLE

SEQUENCER

A2

A1

1.00

0.50

A0

8-CHANNEL

INTERNAL

CLOCK

UNI/BIP

PGA

M0

MULTIPLEXER

OV

DD

BUSY

DIFF /S6

0.00

OUT

A2 /S5

OUT

A1 /S4

OUT

A0 /S3

OUT

D11/S2

D10/S1

D9/S0

D8

–0.50

2.5V

REFERENCE

12-BIT

1.25Msps ADC

DATA

LATCHES

OUTPUT

DRIVERS

REFOUT

D7

–1.00

D6

0

512 1024 1536 2048 2560 3072 3584 4096

CODE

D5

D4

LTC1850/51 G01

D3

REFIN

REF AMP

D2

D1

D0

OGND

1851 BD

REFCOMP

18501f

1

LTC1850/LTC1851

W W W

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OV_DD= V_DD(Notes 1, 2)

ABSOLUTE AXI U RATI GS

Supply Voltage (V_DD)................................................. 6V

Analog Input Voltage (Note 3) ..... –0.3V to (V_DD+ 0.3V)

Digital Input Voltage (Note 4) ....................–0.3V to 10V

Digital Output Voltage.................. –0.3V to (V_DD+ 0.3V)

Power Dissipation.............................................. 500mW

Ambient Operating Temperature Range

LTC1850C/LTC1851C ............................ 0°C to 70°C

LTC1850I/LTC1851I .......................... –40°C to 85°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec)................ 300°C

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PACKAGE RDER I FOR ATIO

TOP VIEW

ORDER PART

NUMBER

1

2

M1

1

2

M1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

CH0

CH1

CH0

CH1

SHDN

CS

SHDN

CS

LTC1850CFW

LTC1850IFW

LTC1851CFW

LTC1851IFW

3

CH2

4

CONVST

RD

4

CONVST

RD

CH3

5

CH4

6

WR

6

WR

CH5

7

DIFF

A2

7

DIFF

A2

CH6

8

CH7

9

A1

9

A1

COM

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

A0

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

A0

REFOUT

REFIN

REFCOMP

GND

REFOUT

REFIN

REFCOMP

GND

UNI/BIP

PGA

M0

UNI/BIP

PGA

M0

OV

DD

OV

DD

V

DD

V

DD

OGND

BUSY

NC

OGND

BUSY

D0

V

DD

GND

DIFF /S6

GND

DIFF /S6

OUT

NC

D1

A2 /S5

OUT

A2 /S5

OUT

D0

D2

A1 /S4

OUT

A1 /S4

OUT

D1

D3

A0 /S3

OUT

A0 /S3

OUT

D2

D4

D9/S2

D8/S1

D7/S0

D6

D11/S2

D10/S1

D9/S0

D8

D3

D5

D4

D6

D5

D7

FW PACKAGE

48-LEAD PLASTIC TSSOP

FW PACKAGE

48-LEAD PLASTIC TSSOP

T_JMAX= 150°C, θ_JA= 110°C/W

Consult LTC Marketing for parts specified with wider operating temperature ranges.

18501f

2

LTC1850/LTC1851

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CO VERTER CHARACTERISTICS

The ● denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. (Notes 5, 6)

LTC1850

TYP

LTC1851

TYP

PARAMETER

CONDITIONS

MIN

MAX MIN

MAX UNITS

Resolution (No Missing Codes)

Integral Linearity Error

Differential Linearity Error

●

10

12

Bits

(Note 7)

±0.25 ±0.5

±0.35

±0.25

±1

LSB

Offset Error (Bipolar and Unipolar)

Gain = 1 (PGA = 1)

(Note 8)

REFCOMP ≥ 2V

±2

±4

±5

±7

±10

LSB

●

±0.5

±1

±2

Gain = 2 (PGA = 0)

Offset Error Match

±0.5

±1

LSB

Unipolar Gain Error

Gain = 1 (PGA = 1)

Gain = 2 (PGA = 0)

With External 4.096V Reference

Applied to REFCOMP (Note 12)

±2

±4

±6

±10

LSB

Unipolar Gain Error Match

±0.5

±1

LSB

Bipolar Gain Error

Gain = 1 (PGA = 1)

Gain = 2 (PGA = 0)

With External 4.096V Reference

Applied to REFCOMP (Note 12)

±2

±4

±6

±10

LSB

Bipolar Gain Error Match

±0.5

±1

LSB

Full-Scale Error Temperature Coefficient

15

ppm/°C

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A ALOG I PUT _{The ● denotes the specifications which apply over the full operating temperature range, otherwise}

specifications are at T_A= 25°C. (Note 5)

SYMBOL

PARAMETER

CONDITIONS

4.75V ≤ V ≤ 5.25V

MIN

TYP

MAX

UNITS

V

IN

Analog Input Range (Note 9)

Unipolar, Gain = 1 (PGA = 1)

Unipolar, Gain = 2 (PGA = 0)

Bipolar, Gain = 1 (PGA = 1)

Bipolar, Gain = 2 (PGA = 0)

DD

0 – REFCOMP

0 – REFCOMP/2

±REFCOMP/2

±REFCOMP/4

V

I

Analog Input Leakage Current

Analog Input Capacitance

V

> 0V < V , All Channels

●

±1

µA

IN

DD

C

Between Conversions (Gain = 1)

Between Conversions (Gain = 2)

During Conversions

15

25

5

pF

IN

t

Sample-and-Hold Acquisition Time

Multiplexer Settling Time (Includes t

●

50

150

ns

ACQ

)

ACQ

S(MUX)

AP

Sample-and-Hold Aperture Delay Time

–0.5

2

Sample-and-Hold Aperture Delay Time Jitter

Analog Input Common Mode Rejection Ratio

ps

RMS

jitter

–

+

CMRR

0V < (A = A ) < 5V

60

dB

IN

18501f

3

LTC1850/LTC1851

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(Note 5)

DY A IC ACCURACY

LTC1850

TYP

LTC1851

TYP

SYMBOL

PARAMETER

CONDITIONS

MIN

MAX

MIN

MAX

UNITS

SNR

Signal-to-Noise Ratio

Unipolar, PGA = 0

Unipolar, PGA = 1

Bipolar, PGA = 0

Bipolar, PGA = 1

47kHz Input Signal

61.6

61.7

61.6

61.7

71

72

71

72

dB

S/(N+D)

THD

Signal-to-(Noise + Distortion) Ratio

Unipolar, PGA = 0

47kHz Input Signal

61.0

61.2

70

71

72

dB

Unipolar, PGA = 1

Bipolar, PGA = 0

Bipolar, PGA = 1

Total Harmonic Distortion

Unipolar, PGA = 0

Unipolar, PGA = 1

Bipolar, PGA = 0

47kHz Input Signal,

First 5 Harmonics

–76

–78

–81

–80

–82

–87

–86

dB

Bipolar, PGA = 1

SFDR

Spurious-Free Dynamic Range

Unipolar, PGA = 0

47kHz Input Signal

74

80

84

82

86

90

88

dB

Unipolar, PGA = 1

Bipolar, PGA = 0

Bipolar, PGA = 1

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I TER AL REFERE CE

T_A= 25°C. (Notes 5, 6)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

REFOUT Output Voltage

REFOUT Output Temperature Coefficient

REFOUT Line Regulation

Reference Buffer Gain

I

= 0

2.48

2.50

±15

2.52

OUT

ppm/°C

LSB/V

V/V

0.01

1.638

V

/V

1.636

1.640

REFCOMP REFIN

REFCOMP Output Voltage

External 2.5V Reference

Internal 2.5V Reference

4.090

4.060

4.096

4.100

4.132

V

REFCOMP Impedance

REFIN = V

6.4

kΩ

DD

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DIGITAL I PUTS A D DIGITAL OUTPUTS ^The● denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at T_A= 25°C. (Note 5)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

High Level Input Voltage

Low Level Input Voltage

Digital Input Current

Digital Input Capacitance

High Level Output Voltage

V

= 5.25V

= 4.75V

= 0V to V

●

2.4

V

IH

IL

DD

IN

0.8

I

±5

µA

pF

IN

DD

C

V

2

IN

V

DD

V

DD

= 4.75V, I = –10µA

= 4.75V, I = –200µA

4.5

V

OH

O

●

4.0

O

V

Low Level Output Voltage

V

= 4.75V, I = 160µA

0.05

0.10

V

OL

DD

O

= 4.75V, I = 1.6mA

●

0.4

±10

15

O

I

Hi-Z Output Leakage D11 to D0, AD , A1 , A2 , DIFF

V

OUT

= 0V to V , CS High

µA

pF

OZ

OUT

DD

C

Hi-Z Capacitance D11 to D0, AD , A1 , A2 , DIFF

OUT

CS High (Note 9)

OZ

OUT

I

Output Source Current

Output Sink Current

V

OUT

V

OUT

= 0V

–20

30

mA

SOURCE

SINK

= V

mA

18501f

DD

4

LTC1850/LTC1851

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POWER REQUIRE E TS

The ● denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. (Note 5)

SYMBOL

PARAMETER

CONDITIONS

(Note 10)

MIN

4.75

2.7

TYP

MAX

5.25

10

UNITS

V

Positive Supply Voltage

Output Positive Supply Voltage

Positive Supply Current

●

V

DD

OV

DD

(Note 10)

I

V

= V = OV = 5V,

8

mA

DD

f

= 1.25MHz

SAMPLE

P

Power Dissipation

●

40

50

mW

DISS

Power Down Positive Supply Current

Nap Mode

Sleep Mode

SHDN = 0V, CS = 0V

SHDN = 0V, CS = 5V

1

50

mA

µA

Power Down Power Dissipation

Nap Mode

Sleep Mode

SHDN = 0V, CS = 0V

SHDN = 0V, CS = 5V

5

0.25

mW

W U

TI I G CHARACTERISTICS

The ● denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. (Note 5)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

f

Maximum Sampling Frequency

Acquisition + Conversion

●

1.25

MHz

ns

SAMPLE(MAX)

800

650

150

t

Conversion Time

●

ns

CONV

Acquisition Time

ACQ

CS to RD Setup Time

CS to CONVST Setup Time

CS to SHDN Setup Time

SHDN to CONVST Wake-Up Time

(Notes 9, 10)

0

1

2

3

4

10

200

Nap Mode (Note 10)

Sleep Mode, 10µF REFCOMP

200

10

ns

ms

Bypass Capacitor (Note 10)

t

CONVST Low Time

(Notes 10, 11)

●

50

ns

5

6

CONVST to BUSY Delay

C = 25pF

L

10

35

ns

60

t

Data Ready Before BUSY

20

15

ns

7

●

t

Delay Between Conversions

Wait Time RD After BUSY

Data Access Time After RD

(Note 10)

50

ns

8

–5

9

C = 25pF

L

20

25

10

35

45

ns

10

●

C = 100pF

L

45

60

ns

t

BUS Relinquish Time

30

35

40

ns

11

0°C to 70°C

–40°C to 85°C

●

t

RD Low Time

●

t

ns

12

13

14

15

16

10

CONVST High Time

Latch Setup Time

Latch Hold Time

WR Low Time

(Note 10)

50

10

50

(Notes 9, 10)

(Note 10)

18501f

5

LTC1850/LTC1851

W U

TI I G CHARACTERISTICS

The ● denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. (Note 5)

SYMBOL

PARAMETER

CONDITIONS

(Note 10)

MIN

50

TYP

MAX

UNITS

ns

t

WR High Time

●

17

18

19

20

21

22

23

24

25

26

27

M1 to M0 Setup Time

M0 to BUSY Delay

(Notes 9, 10)

M1 High

10

ns

20

ns

M0 to WR (or RD) Setup Time

M0 High Pulse Width

RD High Time Between Readback Reads

Last WR (or RD) to M0

M0 to RD Setup Time

M0 to CONVST

(Notes 9, 10)

(Note 10)

●

t

ns

19

50

10

ns

(Note 10)

ns

(Note 10)

ns

(Notes 9, 10)

(Note 10)

t

ns

19

ns

Aperture Delay

–0.5

2

ns

Aperture Jitter

ps

RMS

Note 1: Absolute maximum ratings are those values beyond which the life

of a device may be impaired.

Note 2: All voltage values are with respect to ground with GND, OGND and

Note 7: Integral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual end points of the transfer curve.

The deviation is measured from the center of the quantization band.

GND wired together unless otherwise noted.

Note 3: When these pin voltages are taken below ground or above V

they will be clamped by internal diodes. This product can handle input

Note 8: Bipolar offset is the offset voltage measured from –0.5LSB when

the output code flickers between 0111 1111 1111 and 1000 0000 0000 for

LTC1851 and between 01 1111 1111 and 10 0000 0000 for LTC1850.

,

DD

currents of 100mA below ground or above V without latchup.

Note 4: When these pin voltages are taken below ground, they will be

Note 9: Guaranteed by design, not subject to test.

Note 10: Recommended operating conditions.

DD

clamped by internal diodes. This product can handle input currents of

100mA below ground without latchup. These pins are not clamped to V

Note 11: The falling CONVST edge starts a conversion. If CONVST returns

high at a critical point during the conversion it can create small errors. For

the best results, ensure that CONVST returns high either within 400ns

after the start of the conversion or after BUSY rises.

.

DD

Note 5: V = 4.75V to 5.25V, f

= 1.25MHz, t = t = 2ns unless

r f

DD

SAMPLE

otherwise specified.

Note 6: Linearity, offset and full-scale specifications apply for a single-

ended input on any channel with COM grounded.

Note 12: The analog input range is determined by the voltage on

REFCOMP. The gain error specification is tested with an external 4.096V

but is valid for any value of REFCOMP.

18501f

6

LTC1850/LTC1851

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TYPICAL PERFOR A CE CHARACTERISTICS

Typical DNL, PGA =1, LTC1851

Typical INL, PGA =1, LTC1851

Typical DNL, PGA = 0, LTC1851

1.00

0.50

1.00

0.50

1.00

0.50

0.00

–0.50

–1.00

0

512 1024 1536 2048 2560 3072 3584 4096

CODE

0

512 1024 1536 2048 2560 3072 3584 4096

CODE

0

512 1024 1536 2048 2560 3072 3584 4096

CODE

LTC1850/51 G04

LTC1850/51 G01

LTC1850/51 G02

Nonaveraged 4096 Point FFT,

f_IN= 47kHz, Bipolar Mode,

PGA = 0, LTC1851

Nonaveraged 4096 Point FFT,

f_IN= 47kHz, Unipolar Mode,

PGA = 0, LTC1851

Typical INL, PGA = 0, LTC1851

1.00

0.50

0

–20

SNR = 71.2dB

SFDR = 82.0dB

SINAD = 70.6dB

SNR = 71.35dB

SFDR = 90.4dB

SINAD = 71.2dB

–20

–40

–60

–80

–40

0.00

–60

–80

–0.50

–100

–120

–100

–110

–1.00

0

512 1024 1536 2048 2560 3072 3584 4096

CODE

0

200

300

400

500

600

100

0

200

300

400

500

600

100

FREQUENCY (kHz)

LTC1850/51 G07

LTC1850/51 G03

LTC1850/51 G05

Nonaveraged 4096 Point FFT,

_IN= 47kHz, Unipolar Mode,

PGA = 1, LTC1851

Nonaveraged 4096 Point FFT,

_IN= 47kHz, Bipolar Mode,

PGA = 1, LTC1851

f

0

–20

–40

–60

–80

0

–20

SNR = 72.3dB

SFDR = 87.3dB

SINAD = 71.4dB

SNR = 72.3dB

SFDR = 89.3dB

SINAD = 72.1dB

–40

–60

–80

–100

–120

–100

–110

0

200

300

400

500

600

100

0

200

300

400

500

600

100

FREQUENCY (kHz)

LTC1850/51 G06

LTC1850/51 G08

18501f

7

LTC1850/LTC1851

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TYPICAL PERFOR A CE CHARACTERISTICS

Distortion vs Input Frequency,

Unipolar Mode, PGA = 0

Distortion vs Input Frequency,

Bipolar Mode, PGA = 0

Distortion vs Input Frequency,

Bipolar Mode, PGA = 1

–50

–55

–50

–55

–50

–55

–60

–65

–70

–60

–65

–70

–60

–65

–70

THD

–75

–80

–75

–80

–75

–80

2ND HARMONIC

3RD HARMONIC

–85

–90

–85

–90

–85

–90

3RD HARMONIC

2ND HARMONIC

–95

–100

10

1000

100

FREQUENCY (kHz)

10000

10

1000

100

FREQUENCY (kHz)

10000

10

1000

100

FREQUENCY (kHz)

10000

185051 G10

185051 G19

185051 G09

Input Common Mode Rejection

Ratio vs Frequency, Unipolar Mode,

PGA = 0

Input Common Mode Rejection

Ratio vs Frequency, Bipolar Mode,

PGA = 0

Distortion vs Input Frequency,

Unipolar Mode, PGA = 1

–50

–55

80

70

60

50

40

30

20

10

0

80

70

60

50

40

30

20

10

0

–60

–65

–70

THD

2ND HARMONIC

–75

–80

–85

–90

3RD HARMONIC

–95

–100

100k

1k

10k

1M

10M

10

1000

FREQUENCY (kHz)

10000

100

100k

1k

10k

1M

10M

FREQUENCY (Hz)

LTC1850/51 G11

185051 G20

LTC1850/51 G13

Input Common Mode Rejection

Ratio vs Frequency, Bipolar Mode,

PGA = 1

Input Common Mode Rejection Ratio

vs Frequency, Unipolar Mode,

PGA = 1

80

70

60

50

40

30

20

10

0

80

70

60

50

40

30

20

10

0

100k

1k

10k

1M

10M

100k

1k

10k

1M

10M

FREQUENCY (Hz)

LTC1850/51 G14

LTC1850/51 G16

18501f

8

LTC1850/LTC1851

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TYPICAL PERFOR A CE CHARACTERISTICS

Channel-to-Channel Isolation

(Worst Pair), Unipolar Mode,

PGA = 0

(Worst Pair) Bipolar Mode,

PGA = 0

110

100

90

80

90

80

LIMIT OF MEASUREMENT

70

60

50

70

60

50

0

2M

4M

6M

8M

10M

0

2M

4M

6M

8M

10M

INPUT FREQUENCY (Hz)

LTC1850/51 G12

LTC1850/51 G15

Channel-to-Channel Isolation

(Worst Pair), Bipolar Mode,

PGA =1

Channel-to-Channel Isolation

(Worst Pair), Unipolar Mode,

PGA = 1

110

100

110

100

90

80

90

80

LIMIT OF MEASUREMENT

70

60

50

70

60

50

0

2M

4M

6M

8M

10M

0

2M

4M

6M

8M

10M

INPUT FREQUENCY (Hz)

FREQUENCY (Hz)

LTC1850/51 G17

LTC1850/51 G18

18501f

9

LTC1850/LTC1851

U

PI FU CTIO S

current sequencer location (S6) is available on this pin.

The output swings between OV_DDand OGND.

CH0toCH7(Pins1to8):AnalogInputPins.Inputpinscan

be used single ended relative to the analog input common

pin(COM)ordifferentiallyinpairs(CH0andCH1, CH2and

CH3, CH4 and CH5, CH6 and CH7).

A2_OUT/S5, A1_OUT/S4, A0_OUT/S3 (Pins 18 to 20): Three-

State Digital MUX Address Outputs. Active when RD is

low. Following a conversion, the MUX address of the

present conversion is available on these pins concurrent

with the conversion result. In Readback mode, the MUX

address of the current sequencer location (S5-S3) is

available on these pins. The outputs swing between OV_DD

and OGND.

COM(Pin9):AnalogInputCommonPin. Forsingle-ended

operation (DIFF = 0), COM is the “–” analog input. COM is

disabled when DIFF is high.

REFOUT (Pin 10): Internal 2.5V Reference Output. Re-

quires bypass to analog ground plane with 1µF.

REFIN (Pin 11): Reference Mode Select/Reference Buffer

Input. REFIN selects the Reference mode and acts as the

reference buffer Input. REFIN tied to ground will produce

2.048V on the REFCOMP pin. REFIN tied to the positive

supply disables the reference buffer to allow REFCOMP to

be driven externally. For voltages between 1V and 2.6V,

the reference buffer produces an output voltage on the

REFCOMP pin equal to 1.6384 times the voltage on REFIN

(4.096V on REFCOMP for a 2.5V input on REFIN).

D9/S2 (Pin 21, LTC1850): Three-State Digital Data Out-

put. Active when RD is low. Following a conversion, bit 9

of the present conversion is available on this pin. In

Readback mode, the unipolar/bipolar bit of the current

sequencerlocation(S2)isavailableonthispin. Theoutput

swings between OV_DDand OGND.

D11/S2 (Pin 21, LTC1851): Three-State Digital Data Out-

put. Active when RD is low. Following a conversion, bit 11

of the present conversion is available on this pin. In

Readback mode, the unipolar/bipolar bit of the current

sequencerlocation(S2)isavailableonthispin. Theoutput

swings between OV_DDand OGND.

REFCOMP (Pin 12): Reference Buffer Output. REFCOMP

sets the full-scale input span. The reference buffer pro-

duces an output voltage on the REFCOMP pin equal to

1.6384 times the voltage on the REFIN pin (4.096V on

REFCOMP for a 2.5V input on REFIN). REFIN tied to

ground will produce 2.048V on the REFCOMP pin.

REFCOMP can be driven externally if REFIN is tied to the

positive supply. Requires bypass to analog ground plane

with 10µF tantalum in parallel with 0.1µF ceramic or 10µF

ceramic.

D8/S1 (Pin 22, LTC1850): Three-State Digital Data Out-

puts. Active when RD is low. Following a conversion, bit 8

of the present conversion is available on this pin. In

Readback mode, the gain bit of the current sequencer

location (S1) is available on this pin. The output swings

between OV_DDand OGND.

D10/S1 (Pin 22, LTC1851): Three-State Digital Data Out-

puts.ActivewhenRDislow.Followingaconversion,bit10

of the present conversion is available on this pin. In

Readback mode, the gain bit of the current sequencer

location (S1) is available on this pin. The output swings

between OV_DDand OGND.

GND (Pin 13): Ground. Tie to analog ground plane.

V_DD(Pin 14): 5V Supply. Short to Pin 15.

V_DD(Pin 15): 5V Supply. Bypass to GND with 10µF

tantalum in parallel with 0.1µF ceramic or 10µF ceramic.

GND (Pin 16): Ground for Internal Logic. Tie to analog

ground plane.

D7/S0 (Pin 23, LTC1850): Three-State Digital Data Out-

puts. Active when RD is low. Following a conversion, bit 7

of the present conversion is available on this pin. In

Readback mode, the end of sequence bit of the current

sequencerlocation(S0)isavailableonthispin. Theoutput

swings between OV_DDand OGND.

DIFF_OUT/S6 (Pin 17): Three-State Digital Data Output.

Active when RD is low. Following a conversion, the single-

ended/differentialbitofthepresentconversionisavailable

on this pin concurrent with the conversion result. In

Readback mode, the single-ended/differential bit of the

18501f

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LTC1850/LTC1851

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PI FU CTIO S

D9/S0 (Pin 23, LTC1851): Three-State Digital Data Out-

puts. Active when RD is low. Following a conversion, bit 9

of the present conversion is available on this pin. In

Readback mode, the end of sequence bit of the current

sequencerlocation(S0)isavailableonthispin. Theoutput

swings between OV_DDand OGND.

UNI/BIP(Pin38):Unipolar/BipolarSelectInput. Logiclow

selects a unipolar input span, a high logic level selects a

bipolar input span.

A0 to A2 (Pins 39 to 41): MUX Address Input Pins.

DIFF (Pin 42): Single-Ended/Differential Select Input. A

low logic level selects single-ended mode, a high logic

level selects differential mode.

D6 to D0 (Pins 24 to 30, LTC1850): Three-State Digital

Data Outputs. Active when RD is low. The outputs swing

between OV_DDand OGND.

WR(Pin43):WriteInput.InDirectAddressmode,WRlow

enables the MUX address and configuration input pins

(Pins 37 to 42). WR can be tied low or the rising edge of

WR can be used to latch the data. In Program mode, WR

is used to program the sequencer. WR low enables the

MUXaddressandconfigurationinputpins(Pins37to42).

The rising edge of WR latches the data and increments the

counter to the next sequencer location.

D8 to D0 (Pins 24 to 32, LTC1851): Three-State Digital

Data Outputs. Active when RD is low. The outputs swing

between OV_DDand OGND.

NC (Pins 31, 32, LTC1850): No Connect. There is no

internal connection to these pins.

BUSY (Pin 33): Converter Busy Output. The BUSY output

has two functions. At the start of a conversion, BUSY will

go low and remain low until the conversion is completed.

Therisingedgemaybeusedtolatchtheoutputdata.BUSY

will also go low while the part is in Program/Readback

mode (M1 high, M0 low) and remain low until M0 is

brought back high. The output swings between OV_DDand

OGND.

RD (Pin 44): Read Input. During normal operation, RD

enables the output drivers when CS is low. In Readback

mode (M1 high, M0 low), RD going low reads the current

sequencerlocation,RDhighadvancestothenextsequencer

location.

CONVST (Pin 45): Conversion Start Input. This active low

signal starts a conversion on its falling edge.

OGND (Pin 34): Digital Data Output Ground. Tie to analog

ground plane. May be tied to logic ground if desired.

CS (Pin 46): Chip Select Input. The chip select input must

be low for the ADC to recognize the CONVST and RD

inputs. If SHDN is low, a low logic level on CS selects Nap

mode; a high logic level on CS selects Sleep mode.

OV_DD(Pin 35): Digital Data Output Supply. Normally tied

to5V, canbeusedtointerfacewith3Vdigitallogic. Bypass

toOGNDwith10µFtantaluminparallelwith0.1µFceramic

or 10µF ceramic. See Table 5.

SHDN (Pin 47): Power Shutdown Input. A low logic level

will invoke the Shutdown mode selected by the CS pin. CS

low selects Nap mode, CS high selects Sleep mode. Tie

high if unused.

M0 (Pin 36): Mode Select Pin 0. Used in conjunction with

M1 to select operating mode. See Table 5

PGA (Pin 37): Gain Select Input. A high logic level selects

gain = 1, a low logic level selects gain = 2.

M1 (Pin 48): Mode Select Pin 1. Used in conjunction with

M0 to select operating mode.

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NOMINAL (V)

TYP

ABSOLUTE MAXIMUM (V)

MAX

1 to 8

9

NAME

DESCRIPTION

MIN

0

MAX

MIN

–0.3

– 0.3

–0.3

CH0 to CH7

COM

Analog Inputs

V

+ 0.3

DD

Analog Input Common Pin

2.5V Reference Output

Reference Buffer Input

Reference Buffer Output

Ground, Substrate Ground

Supply

0

+ 0.3

10

REFOUT

REFIN

2.5

11

0

2.5

V

DD

12

REFCOMP

GND

4.096

13

0

5

0

14

V

4.75

5.25

6

DD

15

Supply

6

16

GND

DIFF /S6

Ground

V

+ 0.3

DD

17

Single-Ended/Differential Output

MUX Address Output

Data Output

OGND

OV

+ 0.3

OUT

DD

18

A2 /S5

OUT

19

A1 /S4

OUT

20

A0 /S3

OUT

21

D9/S2 (LTC1850)

D11/S2 (LTC1851)

D8/S1 (LTC1850)

D10/S1 (LTC1851)

D7/S0 (LTC1850)

D9/S0 (LTC1851)

D6 to D0 (LTC1850)

D8 to D0 (LTC1851)

NC (LTC1850)

21

Data Output

22

Data Output

22

Data Output

23

Data Output

23

Data Output

24 to 30

24 to 32

31 to 32

33

Data Outputs

BUSY

Converter Busy Output

Output Ground

OGND

OV

–0.3

V

+ 0.3

DD

34

OGND

0

5

35

OV

Output Supply

2.7

0

5.25

6

DD

36

M0

Mode Select Pin 0

V

10

DD

37

PGA

Gain Select Input

0

38

UNI/BIP

A0 to A2

DIFF

Unipolar/Bipolar Input

MUX Address Inputs

Single-Ended/Differential Input

Write Input, Active Low

Read Input, Active Low

Conversion Start Input, Active Low

Chip Select Input, Active Low

Shutdown Input, Active Low

Mode Select Pin 1

0

39 to 41

42

0

43

WR

0

44

RD

0

45

CONVST

CS

0

46

0

47

SHDN

M1

0

48

0

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DYNAMIC PERFORMANCE

TheLTC1850/LTC1851arecompleteandveryflexibledata

acquisition systems. They consist of a 10-bit/12-bit,

1.25Msps capacitive successive approximation A/D con-

verter with a wideband sample-and-hold, a configurable

8-channel analog input multiplexer, an internal reference

and reference buffer amplifier, a 16-bit parallel digital

output and digital control logic including a programmable

sequencer.

Signal-to-Noise Ratio

The signal-to-noise plus distortion ratio [S/(N + D)] is the

ratiobetweentheRMSamplitudeofthefundamentalinput

frequency and the RMS amplitude of all other frequency

components at the ADC output. The output is band limited

to frequencies above DC to below half the sampling

frequency. The effective number of bits (ENOBs) is a

measurement of the resolution of an ADC and is directly

related to the S/(N + D) by the equation:

CONVERSION DETAILS

T

he core analog-to-digital converter in the LTC1850/

ENOB = [S/(N + D) – 1.76]/6.02

LTC1851usesasuccessiveapproximationalgorithmand

an internal sample-and-hold circuit to convert an analog

signal to a 10-bit/12-bit parallel output. Conversion start

is controlled by the CS and CONVST inputs. At the start of

the conversion, the successive approximation register

(SAR)isreset.Onceaconversioncycleisbegun,itcannot

be restarted. During the conversion, the internal differen-

tial 10-bit/12-bit capacitive DAC output is sequenced by

the SAR from the most significant bit (MSB) to the least

significant bit (LSB). The outputs of the analog input

multiplexer are connected to the sample-and-hold ca-

pacitors (C_SAMPLE) during the acquire phase and the

comparator offset is nulled by the zeroing switches. In

thisacquirephase,aminimumdelayof150nswillprovide

enough time for the sample-and-hold capacitors to ac-

quire the analog signal. During the convert phase, the

comparator zeroing switches are open, putting the com-

parator into compare mode. The input switches connect

C_SAMPLEto ground, transferring the differential analog

input charge onto the summing junction. This input

chargeissuccessivelycomparedwiththebinaryweighted

charges supplied by the differential capacitive DAC. Bit

decisions are made by the high speed comparator. At the

end of the conversion, the differential DAC output bal-

ances the input charges. The SAR contents (a 10-bit/

12-bit data word), which represents the difference of the

analog input multiplexer outputs, and the 4-bit address

word are loaded into the 14-bit/16-bit output latches.

where ENOB is the effective number of bits and S/(N + D)

is expressed in dB. At the maximum sampling rate of

1.25MHz, the LTC1850/LTC1851 maintain near ideal

ENOBs up to and beyond the Nyquist input frequency of

625kHz.

Total Harmonic Distortion

Total harmonic distortion is the ratio of the RMS sum of all

harmonicsoftheinputsignaltothefundamentalitself.The

out-of-band harmonics alias into the frequency band

between DC and half the sampling frequency. THD is

expressed as:

V2²+ V3²+ V4²+...Vn²

THD = 20Log

V1

where V1 is the RMS amplitude of the fundamental fre-

quency and V2 through Vn are the amplitudes of the

second through nth harmonics. The LTC1850/LTC1851

have good distortion performance up to the Nyquist fre-

quency and beyond.

Intermodulation Distortion

If the ADC input signal consists of more than one spectral

component, the ADC transfer function nonlinearity can

produce intermodulation distortion (IMD) in addition to

THD. IMD is the change in one sinusoidal input caused by

the presence of another sinusoidal input at a different

frequency.

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APPLICATIO S I FOR ATIO

If two pure sine waves of frequencies fa and fb are applied

to the ADC input, nonlinearities in the ADC transfer func-

tion can create distortion products at the sum and differ-

ence frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3,

etc.Forexample,the2ndorderIMDtermsinclude(fa±fb).

If the two input sine waves are equal in magnitude, the

value (in decibels) of the 2nd order IMD products can be

expressed by the following formula:

(COM) when DIFF is low or as four differential pairs (CH0

andCH1,CH2andCH3,CH4andCH5,CH6andCH7)when

DIFF is high. The channels (and polarity in the differential

case)areselectedusingtheMUXaddressinputsasshown

in Table 1. Unused inputs (including the COM in the

differential case) should be grounded to prevent noise

coupling.

Table 1. Multiplexer Address Table

MUX ADDRESS

SINGLE-ENDED CHANNEL SELECTION

Amplitude at fa ± fb

(

)

DIFF A2 A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM

IMD fa ± fb = 20Log

(

)

Amplitude at fa

0

1

0

1

0

1

0

1

0

1

0

1

0

1

+

–

+

Peak Harmonic or Spurious Noise

+

The peak harmonic or spurious noise is the largest spec-

tral component excluding the input signal and DC. This

value is expressed in decibels relative to the RMS value of

a full-scale input signal.

+

Full-Power and Full-Linear Bandwidth

The full-power bandwidth is that input frequency at which

the amplitude of the reconstructed fundamental is

reduced by 3dB for a full-scale input signal.

MUX ADDRESS

DIFFERENTIAL CHANNEL SELECTION

DIFF A2 A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

+

–

+

*

The full-linear bandwidth is the input frequency at which

the S/(N + D) has dropped to 68dB for the LTC1851 (11

effective bits) or 56dB for the LTC1850 (9 effective bits).

The LTC1850/LTC1851 have been designed to optimize

input bandwidth, allowing the ADC to undersample input

signals with frequencies above the converter’s Nyquist

frequency. The noise floor stays very low at high frequen-

cies; S/(N + D) becomes dominated by distortion at

frequencies far beyond Nyquist.

+

–

+

–

+

–

+

*Not used in differential mode. Connect to GND.

In addition to selecting the MUX channel, the LTC1850/

LTC1851 also allows the user to select between two gains

and unipolar or bipolar inputs for a total of four input

spans. PGAhighselectsagainof1(theinputspanisequal

to the voltage on REFCOMP). PGA low selects a gain of 2

where the input span is equal to half of the voltage on

REFCOMP. UNI/BIP low selects a unipolar input span,

UNI/BIPhighselectsabipolarinputspan. Table2summa-

rizes the possible input spans.

ANALOG INPUT MULTIPLEXER

Theanaloginputmultiplexeriscontrolledusingthesingle-

ended/differentialpin(DIFF), threeMUXaddresspins(A2,

A1, A0), the unipolar/bipolar pin (UNI/BIP) and the gain

select pin (PGA). The single-ended/differential pin (DIFF)

allows the user to configure the MUX as eight single-

ended channels relative to the analog input common pin

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APPLICATIO S I FOR ATIO

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Table 2. Input Span Table

sampled at the same instant. Any unwanted signal that is

common mode to both inputs will be reduced by the

common mode rejection of the sample-and-hold circuit.

The inputs draw only one small current spike while charg-

ing the sample-and-hold capacitors at the end of conver-

sion. During conversion, the analog inputs draw only a

small leakage current. If the source impedance of the

driving circuit is low, then the LTC1850/LTC1851 inputs

can be driven directly. As source impedance increases, so

will acquisition time. For minimum acquisition time with

high source impedance, a buffer amplifier should be used.

The only requirement is that the amplifier driving the

analog input(s) must settle after the small current spike

before the next conversion starts (settling time must be

150ns for full throughput rate).

INPUT SPAN

REFCOMP = 4.096V

UNI/BIP

PGA

0

1

0

1

0

1

0 – REFCOMP/2

0 – REFCOMP

±REFCOMP/4

±REFCOMP/2

0 – 2.048V

0 – 4.096V

±1.024V

±2.048V

It should be noted that the bipolar input span of the

LTC1850/LTC1851 does not allow negative inputs with

respect to ground. The LTC1850/LTC1851 have a unique

differential sample-and-hold circuit that allows rail-to-rail

inputs. The ADC will always convert the difference of the

“+” and “–” inputs independent of the common mode

voltage. The common mode rejection holds up to high

frequencies. The only requirement is that both inputs can

notexceedtheV_DDpowersupplyvoltageorground. When

a bipolar input span is selected the “+” input can swing

±full scale relative to the “–” input but neither input can

exceed V_DDor go below ground.

Choosing an Input Amplifier

Choosing an input amplifier is easy if a few requirements

are taken into consideration. First, to limit the magnitude

of the voltage spike seen by the amplifier from charging

the sampling capacitor, choose an amplifier that has a low

output impedance (<100Ω) at the closed-loop bandwidth

frequency. For example, if an amplifier is used in a gain of

+1 and has a unity-gain bandwidth of 50MHz, then the

output impedance at 50MHz should be less than 100Ω.

Thesecondrequirementisthattheclosed-loopbandwidth

must be greater than 20MHz to ensure adequate small-

signal settling for full throughput rate. The following list is

a summary of the op amps that are suitable for driving the

LTC1850/LTC1851, moredetailedinformationisavailable

in the Linear Technology Databooks, the LinearView^TM

CD-ROM and on our web site at www.linear-tech.com.

Integral nonlinearity errors (INL) and differential nonlin-

earity errors (DNL) areindependent of the common mode

voltage, however, the bipolar zero error (BZE) will vary.

The change in BZE is typically less than 0.1% of the

common mode voltage.

Some AC applications may have their performance lim-

itedbydistortion.TheADCandmanyothercircuitsexhibit

higher distortion when signals approach the supply or

ground. THD will degrade as the inputs approach either

power supply rail. Distortion can be reduced by reducing

the signal amplitude and keeping the common mode

voltage at approximately midsupply.

LT^®1360: 50MHz Voltage Feedback Amplifier. ±2.5V to

±15V supplies. 5mA supply current. Low distortion.

Driving the Analog Inputs

LT1363: 70MHz Voltage Feedback Amplifier. ±2.5V to

±15V supplies. 7.5mA supply current. Low distortion.

The inputs of the LTC1850/LTC1851 are easy to drive.

Each of the analog inputs can be used as a single-ended

input relative to the input common pin (CH0-COM, CH1-

COM, etc.) or in pairs (CH0 and CH1, CH2 and CH3, CH4

and CH5, CH6 and CH7) for differential inputs. Regardless

of the MUX configuration, the “+” and “–” inputs are

LT1364/LT1365: DualandQuad70MHzVoltageFeedback

Amplifiers. ±2.5Vto±15Vsupplies. 7.5mAsupplycurrent

per amplifier. Low distortion.

LinearView is a trademark of Linear Technology Corporation.

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APPLICATIO S I FOR ATIO

LT1468/LT1469: Single and Dual 90MHz Voltage Feed-

backAmplifier. ±5Vto±15Vsupplies. 7mAsupplycurrent

per amplifier. Lowest noise and low distortion.

REFERENCE

The LTC1850/LTC1851 include an on-chip, temperature

compensated, curvature corrected, bandgap reference

that is factory trimmed to 2.500V and has a very flexible

3-pin interface. REFOUT is the 2.5V bandgap output,

REFIN is the input to the reference buffer and REFCOMP

is the reference buffer output. REFOUT must be bypassed

with a 1µF or greater capacitor to ground for stability. The

input span is determined by the voltage appearing on the

REFCOMP pin as shown in Table 2. The reference buffer

has a gain of 1.6384 and is factory trimmed by forcing an

external2.500VontheREFINpinandtrimmingREFCOMP

to 4.096V. The 3-pin interface allows for three pin-

strappable Reference modes as well as two additional

external Reference modes. For voltages on the REFIN pin

ranging from 1V to 2.6V, the output voltage on REFCOMP

will equal 1.6384 times the voltage on the REFIN pin. In

this mode, the REFIN pin can be tied to REFOUT to utilize

the internal 2.5V reference to get 4.096V on REFCOMP or

driven with an external reference or DAC. If REFIN is tied

low, the internal 2.5V reference divided by 2 (1.25V) is

connected internally to the input of the reference buffer

resultingin2.048VonREFCOMP.IfREFINistiedhigh,the

reference buffer is disabled and REFCOMP can be tied to

REFOUT to achieve a 2.5V span or driven with an external

reference or DAC. Table 3 summarizes the Reference

modes.

LT1630/LT1631: Dual and Quad 30MHz Rail-to-Rail Volt-

age Feedback Amplifiers. Single 3V to ±15V supplies.

3.5mA supply current per amplifier. Low noise and low

distortion.

LT1632/LT1633: Dual and Quad 45MHz Rail-to-Rail Volt-

age Feedback Amplifiers. Single 3V to ±15V supplies.

4.3mA supply current per amplifier. Low distortion.

LT1806/LT1807: Single and Dual 325MHz Rail-to-Rail

Voltage Feedback Amplifier. Single 3V to ±5V supplies.

13mA supply current. Lowest distortion.

LT1809/LT1810: Single and Dual 180MHz Rail-to-Rail

Voltage Feedback Amplifier. Single 3V to ±15V supplies.

20mA supply current. Lowest distortion.

LT1812/LT1813: 100MHz Voltage Feedback Amplifier.

Single 5V to ±5V supplies. 3.6mA supply current. Low

noise and low distortion.

Input Filtering

The noise and the distortion of the input amplifier and

other circuitry must be considered since they will add to

the LTC1850/LTC1851 noise and distortion. Noisy input

circuitry should be filtered prior to the analog inputs to

minimize noise. A simple 1-pole RC filter is sufficient for

many applications. For instance, a 100Ω source resistor

anda1000pFcapacitortogroundontheinputwilllimitthe

input bandwidth to 1.6MHz. The capacitor also acts as a

charge reservoir for the input sample-and-hold and iso-

lates the ADC input from sampling glitch sensitive cir-

cuitry. High quality capacitors and resistors should be

usedsincethesecomponentscanadddistortion.NPOand

silver mica type dielectric capacitors have excellent linear-

ity. Carbon surface mount resistors can also generate

distortion from self heating and from damage that may

occurduringsoldering.Metalfilmsurfacemountresistors

are much less susceptible to both problems.

Table 3. Reference Mode Table

MODE

REFIN

= GND

REFCOMP

REFIN Tied Low

REFIN is Buffer Input

2.048V Output

1V to 2.6V Input

1.6384V to 4.26V Output

(1.6384 • REFIN)

REFIN Tied High

= V

Input, 6.4kΩ to Ground

DD

Full Scale and Offset

In applications where absolute accuracy is important,

offset and full-scale errors can be adjusted to zero during

a calibration sequence. Offset error must be adjusted

before full-scale error. Zero offset is achieved by adjusting

18501f

16

LTC1850/LTC1851

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APPLICATIO S I FOR ATIO

U

theoffsetappliedtothe“–”input. Forsingle-endedinputs,

this offset should be applied to the COM pin. For differen-

tial inputs, the “–” input is dictated by the MUX address.

Forzerooffseterror, apply0.5LSB(actualvoltagewillvary

with input span selected) to the “+” input and adjust the

offset at the “–” input until the output code flickers

between 0000 0000 0000 and 0000 0000 0001 for the

LTC1851andbetween0000000000and0000000001for

the LTC1850.

OUTPUT DATA FORMAT

The LTC1850/LTC1851 have a 14-bit/16-bit parallel out-

put. The output word normally consists of a 10-bit/12-bit

conversion result data word and a 4-bit address (three

address bits A2_OUT, A1_OUT, A0_OUTand the DIFF_OUTbit).

The output drivers are enabled when RD is low provided

the chip is selected (CS is low). All 14/16 data output pins

and BUSY are supplied by OV_DDand OGND to allow easy

interface to 3V or 5V digital logic.

As mentioned earlier, the internal reference is factory

trimmed to 2.500V. To make sure that the reference buffer

gain is not compensating for trim errors in the reference,

REFCOMP is trimmed to 4.096V with an accurate external

2.5V reference applied to REFIN. Likewise, to make sure

that the full-scale gain trim is not compensating for errors

in the reference buffer gain, the input full-scale gain is

trimmed with an accurate 4.096V reference applied to

REFCOMP (REFIN = 5V to disable the reference buffer).

This allows the use of either a 2.5V reference applied to

REFIN or a 4.096V reference applied to REFCOMP to

achieve accurate results. Full-scale errors can be trimmed

to zero by adjusting the appropriate reference voltage. For

unipolar inputs, an input voltage of FS – 1.5LSBs should

be applied to the “+” input and the appropriate reference

adjusted until the output code flickers between 1111 1111

1110 and 1111 1111 1111 for the LTC1851 and between

11 1111 1110 and 11 1111 1111 for the LTC1850.

The data format of the conversion result is automatically

selected and determined by the UNI/BIP input pin. If the

UNI/BIP pin is low indicating a unipolar input span

(0 – REFCOMP assuming PGA = 1), the format for the

data is straight binary with 1 LSB = FS/4096 (1mV for

REFCOMP = 4.096V) for the LTC1851 and 1LSB = FS/

1024 (4mV for REFCOMP = 4.096V) for the LTC1850.

If the UNI/BIP pin is high indicating a bipolar input span

(±REFCOMP/2 for PGA = 1), the format for the data is

two’s complement binary with 1 LSB = [(+FS) – (–FS)]/

4096 (1mV for REFCOMP = 4.096V) for the LTC1851 and

1LSB = [(+FS) – (–FS)]/1024 (4mV for REFCOMP =

4.096V) for the LTC1850.

In both cases, the code transitions occur midway between

successive integer LSB values (i.e., –FS + 0.5LSB,

–FS + 1.5LSB, ... –1.5LSB, –0.5LSB, 0.5LSB, 1.5LSB, ...

FS – 1.5LSB, FS – 0.5LSB).

Forbipolarinputs, aninputvoltageofFS–1.5LSBsshould

be applied to the “+” input and the appropriate reference

adjusted until the output code flickers between 0111 1111

1110 and 0111 1111 1111 for the LTC1851 and between

01 1111 1110 and 01 1111 1111 for the LTC1850.

The three most significant bits of the data word (D11,

D10, and D9 for the LTC1851; D9, D8 and D7 for the

LTC1850) also function as output bits when reading the

contents of the programmable sequencer. During

readback, a 7-bit status word (S6-S0) containing the

contents of the current sequencer location is available

when RD is low. The individual bits of the status word are

outlined in Figure 1. During readback, the D8 to D0 pins

(LTC1851) or D6 to D0 pins (LTC1850) remain high

impedance irrespective of the state of RD.

These adjustments as well as the factory trims affect all

channels. The channel-to-channel offset and gain error

matching are guaranteed by design to meet the specifica-

tions in the Converter Characteristics table.

18501f

17

LTC1850/LTC1851

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APPLICATIO S I FOR ATIO

Unipolar Transfer Characteristic

(UNI/BIP = 0)

as free of breaks and holes as possible, such that a low

impedance path between all ADC grounds and all ADC

decoupling capacitors is provided. It is critical to prevent

digital noise from being coupled to the analog inputs,

reference or analog power supply lines. Layout for the

printed circuit board should ensure that digital and analog

signal lines are separated as much as possible. In particu-

lar, care should be taken not to run any digital track

alongside an analog signal track or underneath the ADC.

1111...1111

1111...1110

1111...1101

1000...0001

1000...0000

0111...1111

0111...1110

0000...0010

0000...0001

0000...0000

An analog ground plane separate from the logic system

ground should be established under and around the ADC.

Pin 34 (OGND), Pin 13 (GND), Pin 16 (ADC’s GND) and all

other analog grounds should be connected to this single

analog ground point. The bypass capacitors should also

be connected to this analog ground plane. No other digital

groundsshouldbeconnectedtothisanaloggroundplane.

In some applications, it may be desirable to connect the

OV_DDto the logic system supply and OGND to the logic

system ground. In these cases, OV_DDshould be bypassed

to OGND instead of the analog ground plane.

FS = V

REFCOMP

0

FS – 1LSB

INPUT VOLTAGE (V)

1851 F01A

Bipolar Transfer Characteristic

(UNI/BIP = 1)

0111...1111

0111...1110

0111...1101

0000...0001

0000...0000

1111...1111

1111...1110

1000...0010

1000...0001

1000...0000

BIPOLAR

ZERO

Low impedance analog and digital power supply common

returns are essential to the low noise operation of the ADC

and the foil width for these tracks should be as wide as

possible. In applications where the ADC data outputs and

control signals are connected to a continuously active

microprocessor bus, it is possible to get errors in the

conversion results. These errors are due to feedthrough

fromthemicroprocessortothesuccessiveapproximation

comparator. The problem can be eliminated by forcing the

microprocessor into a WAIT state during conversions or

by using three-state buffers to isolate the ADC bus. The

traces connecting the pins and bypass capacitors must be

kept short and should be made as wide as possible.

V

REFCOMP

2

FS =

–FS

–1LSB 0 1LSB

FS – 1LSB

INPUT VOLTAGE (V)

1851 F01B

S6

S5

A2

S4

A1

S3

A0

S2

S1

S0

PGA BIT

MUX ADDRESS

END OF

SEQUENCE BIT

SINGLE-ENDED/

DIFFERENTIAL BIT

UNIPOLAR/

BIPOLAR BIT

1851 F01

Figure 1. Readback Status Word

The LTC1850/LTC1851 have differential inputs to mini-

mize noise coupling. Common mode noise on the “+” and

“–”inputswillberejectedbytheinputCMRR.TheLTC1850/

LTC1851 will hold and convert the difference between

whichever input is selected as the “+” input and whichever

input is selected as the “–” input. Leads to the inputs

should be kept as short as possible.

BOARD LAYOUT AND BYPASSING

To obtain the best performance from the LTC1850/

LTC1851, a printed circuit board with ground plane is

required. The ground plane under the ADC area should be

18501f

18

LTC1850/LTC1851

W U U

APPLICATIO S I FOR ATIO

U

SUPPLY BYPASSING

CS

CONVST

RD

High quality, low series resistance ceramic 10µF bypass

capacitors should be used. Surface mount ceramic ca-

pacitors provide excellent bypassing in a small board

space. Alternatively, 10µF tantalum capacitors in parallel

with 0.1µF ceramic capacitors can be used. Bypass ca-

pacitors must be located as close to the pins as possible.

The traces connecting the pins and the bypass capacitors

must be kept short and should be made as wide as

possible.

t

2

t

1

1851 F04

Figure 4. CS to CONVST Setup Timing

Power Shutdown

The LTC1850/LTC1851 provide two power shutdown

modes, Nap and Sleep, to save power during inactive

periods. The Nap mode reduces the power to 5mW and

leavesonlythedigitallogicandreferencepoweredup.The

wake-up time from Nap to active is 200ns. In Sleep mode,

all bias currents are shut down and only leakage current

remains—about 50µA. Wake-up time from sleep mode is

much slower since the reference circuit must power-up

andsettleto0.005%forfull12-bitaccuracy(0.02%forfull

10-bit accuracy). Sleep mode wake-up time is dependent

on the value of the capacitor connected to the REFCOMP

(Pin 12). The wake-up time is 10ms with the recom-

mended 10µF capacitor.

DIGITAL INTERFACE

Internal Clock

The A/D converter has an internal clock that eliminates the

need of synchronization between the external clock and

the CS and RD signals found in other ADCs. The internal

clock is factory trimmed to achieve a typical conversion

time of 550ns, and a maximum conversion time over the

full operating temperature range of 650ns. No external

adjustments are required. The guaranteed maximum ac-

quisition time is 150ns. In addition, a throughput time of

800ns and a minimum sampling rate of 1.25Msps is

guaranteed.

Shutdown is controlled by Pin 47 (SHDN); the ADC is in

shutdown when it is low. The shutdown mode is selected

with Pin 46 (CS); low selects Nap.

CS

t

3

Timing and Control

SHDN

1851 F02

Conversion start and data read operations are controlled

by three digital inputs: CONVST, CS and RD. A transition

from 1 to 0 applied to the CONVST pin will start a

conversion after the ADC has been selected (i.e., CS is

low).Onceinitiated, itcannotberestarteduntiltheconver-

sion is complete. Converter status is indicated by the

BUSYoutput.BUSYislowduringaconversion.IfCONVST

returns high at a critical point during the conversion it can

create small errors. For the best results, ensure that

CONVST returns high either within 400ns after the start of

the conversion or after BUSY rises.

Figure 2. CS to SHDN Timing

SHDN

t

4

CONVST

1851 F03

Figure 3. SHDN to CONVST Wake-Up Timing

18501f

19

LTC1850/LTC1851

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APPLICATIO S I FOR ATIO

Figures 5 through 9 show several different modes of

operation. In modes 1a and 1b (Figures 5 and 6),

CS and RD are both tied low. The falling edge of

CONVST starts the conversion. The data outputs are

always enabled and data can be latched with the

BUSYrisingedge.Mode1ashowsoperationwithanarrow

logic low CONVST pulse. Mode 1b shows a narrow logic

high CONVST pulse.

In mode 2 (Figure 7), CS is tied low. The falling edge of

CONVST signal again starts the conversion. Data outputs

are in three-state until read by the MPU with the

RD signal.Mode 2 can be used for operation with a shared

MPU databus.

In slow memory and ROM modes (Figures 8 and 9), CS is

tied low and CONVST and RD are tied together. The MPU

starts the conversion and reads the output with the RD

signal. Conversions are started by the MPU or DSP (no

external sample clock).

CS = RD = LOW

t

CONV

t

5

CONVST

t

6

t

8

BUSY

DATA

t

7

DATA (N – 1)

DATA N

1851 F05

Figure 5. Mode 1a CONVST Starts a Conversion. Data Outputs Always Enabled

t

8

CS = RD = LOW

CONV

t

13

t

5

CONVST

t

6

t

6

BUSY

DATA

t

7

DATA (N – 1)

DATA N

1851 F06

Figure 6. Mode 1b CONVST Starts a Conversion. Data is Read by RD

18501f

20

LTC1850/LTC1851

W U U

U

APPLICATIO S I FOR ATIO

t

CS = LOW

CONV

t

8

5

CONVST

t

13

t

6

BUSY

RD

t

9

t

12

t

11

10

DATA

DATA N

1851 F07

Figure 7. Mode 2 CONVST Starts a Conversion. Data is Read by RD

CS = LOW

t

CONV

t

8

RD = CONVST

t

11

6

BUSY

t

7

10

DATA

DATA (N – 1)

DATA N

DATA (N + 1)

1851 F08

Figure 8. Slow Memory Mode Timing

t

8

CS = LOW

CONV

RD = CONVST

t

11

6

BUSY

t

10

DATA

DATA (N–1)

DATA N

1851 F09

Figure 9. ROM Mode Timing

18501f

21

LTC1850/LTC1851

W U U

U

APPLICATIO S I FOR ATIO

In slow memory mode, the processor applies a logic low

to RD ( = CONVST), starting the conversion. BUSY goes

low, forcing the processor into a Wait state. The previous

conversion result appears on the data outputs. When the

conversion is complete, the new conversion results ap-

pear on the data outputs; BUSY goes high releasing the

processor, and the processor takes RD ( = CONVST) back

high and reads the new conversion data.

CH4-COM, CH5-COM, CH6-COM, CH7-COM, repeat). At

themaximumconversionratethethroughputrateforeach

channel would be 1.25Msps/8 or 156.25ksps. If DIFF is

held high, the scan pattern will consist of four differential

pairs (CH0-CH1, CH2-CH3, CH4-CH5, CH6-CH7, repeat).

At the maximum conversion rate, the throughput rate for

each pair would be 1.25Msps/4 or 312.5ksps. It is pos-

sible to drive the DIFF input pin while the part is in Scan

mode to achieve combinations of single-ended and differ-

ential inputs. For instance, if the A0_OUTpin is tied to the

DIFF input pin, the scan pattern will consist of four single-

ended inputs and two differential pairs (CH0-COM single-

ended, CH1-COM single-ended, CH2-CH3 differential,

CH4-COM single-ended, CH5-COM single-ended, CH6-

CH7 differential, repeat).

In ROM mode, the processor takes RD ( = CONVST) low,

startingaconversionandreadingthepreviousconversion

result.Aftertheconversioniscomplete, theprocessorcan

read the new result and initiate another conversion.

MODES OF OPERATION

Direct Address Mode

The scan counter is reset to zero whenever the M0 pin

changes state so that the first conversion after M0 rises

willbeMUXAddress000(CH0-COMsingle-endedorCH0-

CH1 differential depending on the state of the DIFF pin). A

conversionisinitiatedbythefallingedgeofCONVST. After

each conversion, the address counter is advanced (by one

if DIFF is low, by two if DIFF is high) and the MUX address

for the present conversion is available on the address

output pins (DIFF_OUT, A2_OUTto A0_OUT) along with the

conversion result.

The simplest mode of operation is the Direct Address

mode. This mode is selected when both the M1 and M0

pins are low. In this mode, the address input pins directly

control the MUX and the configuration input pins directly

control the input span. The address and configuration

inputpinsareenabledwhenWRislow. WRcanbetiedlow

ifthepinswillbeconstantlydrivenortherisingedgeofWR

can be used to latch and hold the inputs for as long as WR

is held high.

Program/Readback Mode

Scan Mode

The LTC1850/LTC1851 include a sequencer that can be

programmed to run a sequence of up to 16 locations

containing a MUX address and input configuration. The

MUXaddressandinputconfigurationforeachlocationare

programmed using the DIFF, A2 to A0, UNI/BIP and PGA

pins and are stored in memory along with an end-of-

sequence (EOS) bit that is generated automatically. The

six input address and configuration bits plus the EOS bit

can be read back by accessing the 7-bit readback status

word(S6-S0)throughthedataoutputpins.Thesequencer

memory is a 16 × 7 block of memory represented by the

block diagram in Figure 10.

ScanmodeisselectedwhenM1islowandM0ishigh.This

mode allows the converter to scan through all of the input

channels sequentially and repeatedly without the user

having to provide an address. The address input pins (A2

to A0) are ignored but the DIFF, PGA and UNI/BIP pins are

still enabled when WR is low. As in the direct address

mode, WR can be held low or the rising edge of WR can be

used to latch and hold the information on these pins for as

long as WR is held high. The DIFF pin selects the scan

pattern. If DIFF is held low, the scan pattern will consist of

all eight channels in succession, single-ended relative to

COM (CH0-COM, CH1-COM, CH2-COM, CH3-COM,

18501f

22

LTC1850/LTC1851

W U U

U

APPLICATIO S I FOR ATIO

S6

DIFF

S5

A2

S4

A1

S3

A0

S2

UNI/BIP

S1

PGA

S0

EOS

LOCATION 0000

LOCATION 0001

LOCATION 0010

•

LOCATION 1110

LOCATION 1111

1851 F10

Figure 10. Sequencer Memory Block Diagram

The sequencer is accessed by taking the M1 mode pin The sequencer memory can be read by holding WR high

high. WithM1high, thesequencermemoryisaccessedby and driving RD. Taking RD low accesses the sequencer

taking the M0 mode pin low. This will cause BUSY to go memory and enables the data output pins. The sequencer

low, disabling conversions during the programming and should be reset to location 0000 (by pulsing M0 high)

readback of the sequencer. The sequencer is reset to before beginning a read operation. The seven output bits

location 0000 whenever M1 or M0 changes state. One of will be available on the DIFF_OUT/S6, A2_OUT/S5, A1_OUT/S4,

these signals should be cycled prior to any read or write A0_OUT/S3, D11/S2, D10/S1 and D9/S0 pins (LTC1851) or

operation to guarantee that the sequencer will be pro- DIFF_OUT/S6, A2_OUT/S5, A1_OUT/S4, A0_OUT/S3, D9/S2, D8/

grammed or read starting at location 0000.

S1 and D7/S0 pins (LTC1850). The D8 to D0 (LTC1851) or

D6 to D0 (LTC1850) data output pins will remain high

impedance during readback. RD going high will return the

dataoutputpinstoahighimpedancestateandadvancethe

pointer to the next location. A logic 1 on the D9/S0 (or D7/

S0) pin indicates the last location in the current sequence

but all 16 locations can be read by continuing to clock RD.

After 16 reads, the pointer is reset to location 0000. When

all programming and/or reading of the sequencer memory

is complete, M0 is taken high. BUSY will come back high

enabling CONVST and indicating that the part is ready to

start a conversion.

The sequencer is programmed sequentially starting from

location 0000. RD and WR should be held high, the

appropriate signals applied to the DIFF pin, the A2 to A0

MUX address pins, the UNI/BIP pin and the PGA pin and

WR taken low to write to the memory. The rising edge of

WR will latch the data into memory and advance the

pointer to the next sequencer location. Up to 16 locations

can be programmed and the last location written before

M0 is taken back high will be the last location in the

sequence. After 16 writes, the pointer is reset to location

0000 and any subsequent writes will overwrite the previ-

ous contents and start a new sequence.

18501f

23

LTC1850/LTC1851

W U U

U

APPLICATIO S I FOR ATIO

Sequence Run Mode

sequencer will also reset to location 0000 anytime the M1

or M0 pin changes state.

Once the sequencer is programmed, M0 is taken high.

BUSY will also come back high enabling CONVST and the

next falling CONVST will begin a conversion using the

MUX address and input configuration stored in location

0000ofthesequencermemory.Aftereachconversion,the

sequencer pointer is advanced by one and the MUX

address (the actual channel or channels being converted,

not the sequencer pointer) for the present conversion is

available on the address output pins along with the con-

version result. When the sequencer finishes converting

the last programmed location, the sequencer pointer will

return to location 0000 for the next conversion. The

The contents of the sequencer memory will be retained as

long as power is continuously applied to the part. This

allows the user to switch from Sequence Run mode to

either Direct Address or Scan Mode and back without

losing the programmed sequence. The part can also be

disabled using CS or shutdown in Nap or Sleep mode

without losing the programmed sequence. Table 5 out-

lines the operational modes of the LTC1850/LTC1851.

Figures11and12showthetimingdiagramsforwritingto,

reading from and running a sequence with the LTC1850/

LTC1851.

Table 5

OPERATION MODE

M1

M0

WR

RD

COMMENTS

Direct Address

0

OE

Address and Configuration are Driven from External Pins

Address and Configuration are Latched on Rising Edge of WR or Falling Edge of CONVST

Scan

0

1

0

OE

Address is Provided by Internal Scan Counter, Configuration is Driven from External Pins

Configuration is Latched on Rising Edge of WR or Falling Edge of CONVST

Program

1

0

1

Write Sequencer Location, WR Low Enables Inputs, Rising Edge of WR Latches Data and

Advances to Next Location

Readback

1

0

1

Read Sequencer Location, Falling Edge of RD Enables Output, Rising Edge of RD

Advances to Next Location

Sequence Run

1

X

OE

Run Programmed Sequence, Falling Edge of CONVST Starts Conversion and Advances to

Next Location

18501f

24

LTC1850/LTC1851

W U U

APPLICATIO S I FOR ATIO

U

18501f

25

LTC1850/LTC1851

W U U

U

APPLICATIO S I FOR ATIO

18501f

26

LTC1850/LTC1851

U

PACKAGE DESCRIPTIO

FW Package

48-Lead Plastic TSSOP (6.1mm)

(Reference LTC DWG # 05-08-1651)

12.4 – 12.6*

(.488 – .496)

44

42

41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

48 47 46 45

43

0.95 ±0.10

8.1 ±0.10

6.2 ±0.10

7.9 – 8.3

(.311 – .327)

0.32 ±0.05

0.50 TYP

5

7

8

1

2

3

4

6

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

RECOMMENDED SOLDER PAD LAYOUT

1.20

(.0473)

MAX

6.0 – 6.2**

(.236 – .244)

0° – 8°

-T-

-C-

.10 C

FW48 TSSOP 0502

0.45 – 0.75

(.018 – .029)

0.50

(.0197)

BSC

0.17 – 0.27

(.0067 – .0106)

0.09 – 0.20

(.0035 – .008)

0.05 – 0.15

(.002 – .006)

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS

MILLIMETERS

2. DIMENSIONS ARE IN

(INCHES)

3. DRAWING NOT TO SCALE

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE

**

DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE

18501f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

27

LTC1850/LTC1851

U

TYPICAL APPLICATIO

Data buffering using two IDT7202LA15 1k x 9-bit FIFOs

allows rapid collection of 1024 samples and simple inter-

face to low power, low speed, 8-bit microcontrollers. Data

and channel information are clocked in simultaneously

and read out as two bytes using READ HIGH FIFO and

READ LOW FIFO lines. In the event of bus contention,

resistors limit peak output current. If both FIFOs are read

completely or reset before a burst of conversions, the

empty, half full, and full flags from only one FIFO need to

be monitored. The retransmit inputs may also be tied

together. Retransmit may be used to read data repeatedly,

allowing a memory limited processor to perform trans-

form and filtering functions that would otherwise be

difficult.

0.1µF

INPUT

5V

CONFIGURATION:

ALL 8 CHANNELS

SINGLE ENDED TO COM

CH0–CH7: 0V TO 4.096V

28

5V

IDT7202LA15

13

18

17

16

12

11

10

9

10µF

0.1µF

8-BIT

10µF

2

24

25

26

27

3

D8

Q8

Q7

Q6

Q5

Q4

Q3

Q2

Q1

Q0

R

8 × 1k

DATA BUS

OV

14

15

DD

35

D7

D6

D5

D4

D3

D2

D1

D0

WR

FF

D7

D6

D5

D4

D3

D2

D1

D0

V

DD

48

36

47

46

45

44

43

42

41

40

39

38

37

M1

M0

LTC1851

5V

SHDN

CS

1

2

3

4

5

6

7

8

9

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

COM

CONVST

RD

4

CONTROL LOGIC

AND

PROGRAMMABLE

SEQUENCER

5

WR

6

DIFF

A2

15

21

20

23

1

READ_HIGH_FIFO

8

A1

EF

HIGH_FIFO_EMPTY

22

A0

RS

HF

HIGH_FIFO_HALF_FULL

HIGH BYTE_FIFO_RETRANSMIT

8-CHANNEL

MULTIPLEXER

INTERNAL

CLOCK

UNI/BIP

PGA

RT

XI

7

GND

5V

14

BUSY 33

DIFF /S6 17

OUT

HIGH_FIFO_FULL_FLAG

LOW_FIFO_FULL_FLAG

FIFO_RESET

A2 /S5 18

OUT

A1 /S4 19

OUT

A0 /S3 20

OUT

0.1µF

D11/S2 21

D10/S1 22

D9/S0 23

D8 24

10 REFOUT

2.5V

REFERENCE

12-BIT

SAMPLING

ADC

5V

+

–

DATA

LATCHES

2.5V

OUTPUT

DRIVERS

28

IDT7202LA15

2

24

25

26

27

3

13

19

18

17

16

12

11

10

9

D8

D7

D6

D5

D4

D3

D2

D1

D0

WR

FF

Q8

Q7

Q6

Q5

Q4

Q3

Q2

Q1

Q0

R

8 × 1k

D7 25

11 REFIN

D6 26

REF AMP

D5 27

1µF

D4 28

1.6384X

D3 29

4

D2 30

5

D1 31

6

D0 32

1

15

21

20

23

OGND 34

READ_LOW_FIFO

GND

13

GND

16

REFCOMP

8

EF

LOW_FIFO_EMPTY

LOW_FIFO_HALF_FULL

12

22

4.096V

0.1µF

RS

HF

*CONVERT

CLOCK

UP TO 1024

RT

GND

14

LOW BYTE_FIFO_RETRANSMIT

10µF

XI

7

18501 TA01

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18501f

LT/TP 0303 2K • PRINTED IN THE USA

28 ^{LinearTechnology Corporation}

1630 McCarthy Blvd., Milpitas, CA 95035-7417

●

LINEAR TECHNOLOGY CORPORATION 2001

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC1851CFW#TRPBF
厂家：	Linear
描述：	LTC1851 - 8-Channel, 12-Bit, 1.25Msps Sampling ADCs; Package: TSSOP; Pins: 48; Temperature Range: 0°C to 70°C 光电二极管转换器
文件：	总28页 (文件大小：287K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC1851CFW#TRPBF [Linear]

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