LTC1852CFW_技术文档

LTC1852/LTC1853

8-Channel, 10-Bit/12-Bit,

400ksps, Low Power, Sampling ADCs

FEATURES

DESCRIPTION

The 10-bit LTC^®1852 and 12-bit LTC1853 are complete

8-channeldataacquisitionsystems.Theyincludeaﬂexible

8-channel multiplexer, a 400ksps successive approxima-

tionanalog-to-digitalconverter,aninternalreferenceanda

paralleloutputinterface.Themultiplexercanbeconﬁgured

forsingle-endedordifferentialinputs,twogainrangesand

unipolar or bipolar operation. The ADCs have a scan mode

thatwillrepeatedlycyclethroughall8multiplexerchannels

and can also be programmed to sequence through up to

16 addresses and conﬁgurations. The sequence can also

be read back from internal memory.

n

Flexible 8-Channel Multiplexer

Single-Ended or Differential Inputs

Two Gain Ranges

Unipolar or Bipolar Operation

n

Scan Mode and Programmable Sequencer

Eliminate Conﬁguration Software Overhead

n

Low Power: 3mW at 250ksps

2.7V to 5.5V Supply Range

n

Internal or External Reference Operation

n

Parallel Output Includes MUX Address

n

Nap and Sleep Shutdown Modes

n

Pin Compatible up-grade 1.25Msps 10-Bit LTC1850

and 12-Bit LTC1851

The reference and buffer ampliﬁer provide pin strappable

ranges of 4.096V, 2.5V and 2.048V. The parallel output

includes the 10-bit or 12-bit conversion result plus the

4-bit multiplexer address. The digital outputs are pow-

ered from a separate supply allowing for easy interface

to 3V digital logic. Typical power consumption is 10mW

at 400ksps from a single 5V supply and 3mW at 250ksps

from a single 3V supply.

APPLICATIONS

n

High Speed Data Acquisition

n

Test and Measurement

n

Imaging Systems

Telecommunications

Industrial Process Control

Spectrum Analysis

n

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

n

BLOCK DIAGRAM

LTC1853

M1

SHDN

CS

CONVST

RD

WR

DIFF

A2

A1

A0

UNI/BIP

PGA

M0

CH0

CH1

Integral Linearity

CONTROL LOGIC

CH2

AND

1.0

0.5

PROGRAMMABLE

SEQUENCER

CH3

CH4

CH5

CH6

CH7

COM

8-CHANNEL

INTERNAL

CLOCK

MULTIPLEXER

OV

DD

BUSY

DIFF /S6

0

OUT

A2 /S5

OUT

A1 /S4

OUT

A0 /S3

OUT

D11/S2

D10/S1

D9/S0

D8

–0.5

–1.0

2.5V

REFERENCE

12-BIT

SAMPLING

ADC

+

–

DATA

LATCHES

REFOUT

OUTPUT

DRIVERS

D7

D6

D5

D4

0

512 1024 1536 2048 2560 3072 3584 4096

D3

REFIN

REF AMP

CODE

D2

1852 F01

D1

D0

REFCOMP

OGND

18523 BD

18523fa

1

LTC1852/LTC1853

ABSOLUTE MAXIMUM RATINGS ^OV_DD= V_DD(Note 1, 2)

Supply Voltage (V ) ..................................................6V

Ambient Operating Temperature Range

DD

Analog Input Voltage (Note 3) ..... –0.3V to (V + 0.3V)

LTC1852C/LTC1853C .............................. 0°C to 70°C

LTC1852I/LTC1853I............................. –40°C to 85°C

Storage Temperature Range...................–65°C to 150°C

Lead Temperature (Soldering, 10 sec) ................. 300°C

DD

Digital Input Voltage (Note 4) .................... –0.3V to 10V

Digital Output Voltage ..................–0.3V to (V + 0.3V)

DD

Power Dissipation...............................................500mW

PIN CONFIGURATION

LTC1852

LTC1853

TOP VIEW

1

2

48 M1

1

2

48 M1

CH0

CH1

CH0

CH1

47 SHDN

46 CS

47 SHDN

46 CS

3

CH2

4

45 CONVST

44 RD

4

45 CONVST

44 RD

CH3

5

CH4

6

43 WR

42 DIFF

41 A2

6

43 WR

42 DIFF

41 A2

CH5

7

CH6

8

CH7

9

40 A1

9

40 A1

COM

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

39 A0

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

39 A0

REFOUT

REFIN

REFCOMP

GND

REFOUT

REFIN

REFCOMP

GND

38 UNI/BIP

37 PGA

36 M0

38 UNI/BIP

37 PGA

36 M0

35 OV

DD

35 OV

DD

V

DD

V

DD

34 OGND

33 BUSY

32 NC

31 NC

30 D0

29 D1

28 D2

27 D3

26 D4

25 D5

34 OGND

33 BUSY

32 D0

31 D1

30 D2

29 D3

28 D4

27 D5

26 D6

25 D7

V

DD

GND

DIFF /S6

DD

GND

DIFF /S6

OUT

A2 /S5

OUT

A2 /S5

OUT

A1 /S4

OUT

A1 /S4

OUT

A0 /S3

OUT

A0 /S3

OUT

D9/S2

D8/S1

D7/S0

D6

D11/S2

D10/S1

D9/S0

D8

FW PACKAGE

48-LEAD PLASTIC TSSOP

FW PACKAGE

48-LEAD PLASTIC TSSOP

T

= 150°C, θ = 110°C/W

T = 150°C, θ = 110°C/W

JMAX JA

JMAX

JA

ORDER INFORMATION

LEAD FREE FINISH

LTC1852CFW#PBF

LTC1852IFW#PBF

LTC1853CFW#PBF

LTC1853IFW#PBF

TAPE AND REEL

PART MARKING

LTC1852CFW

LTC1852IFW

LTC1853CFW

LTC1853IFW

PACKAGE DESCRIPTION

TEMPERATURE RANGE

0°C to 70°C

LTC1852CFW#TRPBF

LTC1852IFW#TRPBF

LTC1853CFW#TRPBF

LTC1853IFW#TRPBF

48-Lead Plastic TSSOP (6.1mm)

–40°C to 85°C

0°C to 70°C

–40°C to 85°C

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges.

Consult LTC Marketing for information on non-standard lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

18523fa

2

LTC1852/LTC1853

CONVERTER CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. V_DD= 2.7V to 5.5V, REFCOMP < V_DD(Notes 5,6)

LTC1852

TYP

LTC1853

TYP

PARAMETER

CONDITIONS

MIN

MAX

MIN

MAX

UNITS

Bits

l

Resolution (No Missing Codes)

Integral Linearity Error

Differential Linearity Error

10

12

(Note 7)

0.25

1

0.35

0.25

1

LSB

Offset Error (Bipolar and Unipolar)

Gain = 1 (PGA = 1)

(Note 8)

REFCOMP ≥ 2V

l

0.5

1

2

4

1

2

6

12

LSB

Gain = 2 (PGA = 0)

Offset Error Match (Bipolar and Unipolar)

0.5

1

LSB

Unipolar Gain Error

Gain = 1 (PGA = 1)

Gain = 2 (PGA = 0)

With External 4.096V Reference

Applied to REFCOMP (Note 12)

DD

2

4

8

LSB

V

= 4.75V to 5.25V, f ≤ 400kHz

S

Unipolar Gain Error Match

0.5

1

LSB

Bipolar Gain Error

Gain = 1 (PGA = 1)

Gain = 2 (PGA = 0)

With External 4.096V Reference

Applied to REFCOMP (Note 12)

DD

2

4

8

LSB

V

= 4.75V to 5.25V, f ≤ 400kHz

S

Bipolar Gain Error Match

0.5

1

LSB

Unipolar Gain Error

Gain = 1 (PGA = 1)

Gain = 2 (PGA = 0)

With External 2.5V Reference

Applied to REFCOMP

l

1

2

3

6

1.5

3

8

16

LSB

V

= 2.7V to 5.5V, f ≤ 250kHz

DD

S

Bipolar Gain Error

Gain = 1 (PGA = 1)

Gain = 2 (PGA = 0)

With External 2.5V Reference

Applied to REFCOMP

l

1

2

3

6

1.5

3

8

16

LSB

V

= 2.7V to 5.5V, f ≤ 250kHz

DD

S

Full-Scale Error Temperature Coefﬁcient

15

ppm/°C

ANALOG INPUT ^Thel denotes the speciﬁcations which apply over the full operating temperature range, otherwise

speciﬁcations are at T_A= 25°C. (Notes 5)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

Analog Input Range (Note 9)

Unipolar, Gain = 1 (PGA = 1)

Unipolar, Gain = 2 (PGA = 0)

Bipolar, Gain = 1 (PGA = 1)

Bipolar, Gain = 2 (PGA = 0)

2.7V ≤ V ≤ 5.5V, REFCOMP ≤ V

IN

DD

0 – REFCOMP

0 – REFCOMP/2

REFCOMP/2

REFCOMP/4

V

l

I

Analog Input Leakage Current

Analog Input Capacitance

1

μA

IN

C

Between Conversions (Gain = 1)

Between Conversions (Gain = 2)

During Conversions

15

25

5

pF

IN

t

Sample-and-Hold Acquisition Time

Multiplexer Settling Time (Includes t

50

150

ns

ACQ

)

ACQ

S(MUX)

AP

Sample-and-Hold Aperture Delay Time

V

= 5V

–0.5

2

DD

Sample-and-Hold Aperture Delay Time Jitter

Analog Input Common Mode Rejection Ratio

ps

RMS

jitter

DD

CMRR

60

dB

DYNAMIC ACCURACY ^T_A^{= 25°C. (Notes 5)}

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

72.5

–80

–85

MAX

UNITS

dB

S/(N + D) Signal-to-Noise Plus Distortion Ratio

40kHz Input Signal

THD

Total Harmonic Distortion

40kHz Input Signal, First 5 Harmonics

40kHz Input Signal

dB

SFDR

Spurious Free Dynamic Range

dB

18523fa

3

LTC1852/LTC1853

INTERNAL REFERENCE

PARAMETER

T_A= 25°C. (Notes 5, 6)

CONDITIONS

MIN

TYP

2.50

15

MAX

UNITS

V

REFOUT Output Voltage

I

= 0

2.48

2.52

OUT

REFOUT Output Temperature Coefﬁcient

REFOUT Line Regulation

I

ppm/°C

LSB/V

V/V

2.7 ≤ V ≤ 5.5, I

= 0

0.01

1.6384

DD

OUT

Reference Buffer Gain

1.6368

1.6400

REFCOMP Output Voltage

External 2.5V Reference (V = 5V)

4.092

4.060

4.096

4.100

4.132

V

DD

Internal 2.5V Reference (V = 5V)

DD

REFCOMP Impedance

Impedance to GND, REFIN = V

19.2

kΩ

DD

The ● denotes the speciﬁcations which apply over the full

DIGITAL INPUTS AND DIGITAL OUTPUTS

operating temperature range, otherwise speciﬁcations are at T_A= 25°C. V_DD= 5V (Note 5)

SYMBOL

PARAMETER

CONDITIONS

MIN

2.4

TYP

MAX

UNITS

V

High Level Input Voltage

Low Level Input Voltage

Digital Input Current

Digital Input Capacitance

High Level Output Voltage

V

DD

V

DD

V

IN

= 5.25V

= 4.75V

= 0V to V

●

V

IH

IL

V

0.8

5

I

μA

pF

IN

DD

C

1.5

4.5

IN

V

OH

V

DD

V

DD

= 4.75V, I = –10μA

= 4.75V, I = –200μA

V

O

●

4

O

V

Low Level Output Voltage

V

= 4.75V, I = 160μA

0.5

V

OL

DD

O

●

0.10

0.4

10

15

= 4.75V, I = 1.6mA

O

I

OZ

Hi-Z Output Leakage D11 to D0, A0, A1, A2 , DIFF

V

= 0V to V , CS High

μA

pF

OUT

DD

C

Hi-Z Capacitance D11 to D0

Output Source Current

Output Sink Current

CS High (Note 9)

OZ

I

V

= 0V

–20

30

mA

SOURCE

SINK

OUT

V

= V

DD

The ● denotes the speciﬁcations which apply over the full

DIGITAL INPUTS AND DIGITAL OUTPUTS

operating temperature range, otherwise speciﬁcations are at T_A= 25°C. V_DD= 5V (Note 5)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

High Level Input Voltage

Low Level Input Voltage

Digital Input Current

Digital Input Capacitance

High Level Output Voltage

V

= 3.3V

= 2.7V

●

1.9

V

IH

IL

DD

IN

0.45

5

I

IN

= 0V to V

μA

pF

DD

C

V

1.5

2.5

IN

V

DD

V

DD

= 2.7V, I = –10μA

= 2.7V, I = –200μA

V

OH

O

●

2

O

V

Low Level Output Voltage

V

= 2.7V, I = 160μA

0.05

0.10

V

OL

DD

O

●

0.4

10

15

= 2.7V, I = 1.6mA

O

I

OZ

Hi-Z Output Leakage D11 to D0, A0, A1, A2 , DIFF

V

= 0V to V , CS High

μA

pF

OUT

DD

C

Hi-Z Capacitance D11 to D0

Output Source Current

Output Sink Current

CS High (Note 9)

OZ

I

V

= 0V

–10

15

mA

SOURCE

SINK

OUT

I

V

= V

DD

18523fa

4

LTC1852/LTC1853

The ● denotes the speciﬁcations which apply over the full operating temperature

POWER REQUIREMENTS

range, otherwise speciﬁcations are at T_A= 25°C. (Note 5)

SYMBOL

PARAMETER

CONDITIONS

(Note 10)

MIN

2.7

TYP

MAX

5.5

UNITS

V

Analog Positive Supply Voltage

Output Positive Supply Voltage

Positive Supply Current

●

V

DD

OV

DD

(Note 10)

2.7

5.5

I

DD

V

DD

V

DD

= OV = 5V, f = 400kHz

●

2

0.83

3

1.33

mA

DD

S

= OV = 2.7V, f = 250kHz

DD

S

P

DISS

Power Dissipation

V

DD

V

DD

= OV = 5V, f = 400kHz

●

10

2.25

15

4

mW

DD

S

= OV = 2.7V, f = 250kHz

DD

S

I

Power Down Positive Supply Current

Nap Mode

Sleep Mode

DDPD

mA

μA

SHDN = Low, CS = Low

SHDN = Low, CS = High

0.5

20

Power Down Power Dissipation

Nap Mode

Sleep Mode

V

= V = OV = 5V, f = 400kHz

DD DD DD S

mW

SHDN = Low, CS = Low

SHDN = Low, CS = High

2.5

0.1

Power Down Power Dissipation

Nap Mode

Sleep Mode

V

= V = OV = 3V, f = 250kHz

DD DD DD S

mW

SHDN = Low, CS = Low

SHDN = Low, CS = High

1.5

0.06

TIMING CHARACTERISTICS ^The● denotes the speciﬁcations which apply over the full operating temperature

range, otherwise speciﬁcations are at T_A= 25°C. (Note 5)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

f

Maximum Sampling Frequency

V

DD

V

DD

= 5.5V

= 2.7V

●

400

250

kHz

SAMPLE(MAX)

Acquisition + Conversion

Conversion Time

V

= 5.5V

= 2.7V

●

2.5

4.0

μs

DD

t

V

DD

V

DD

= 5.5V

= 2.7V

●

2.0

3.5

μs

CONV

t

Acquisition Time

(Note 13)

●

150

ns

ACQ

CS to RD Setup Time

(Notes 9, 10)

0

1

2

3

4

CS to CONVST Setup Time

CS to SHDN Setup Time

SHDN to CONVST Wake-Up Time

10

200

Nap Mode (Note 10)

Sleep Mode (Note 10)

200

10

ns

ms

t

CONVST Low Time

(Notes 10, 11)

●

50

ns

5

6

CONVST to BUSY Delay

C = 25pF

L

10

35

ns

60

t

Data Ready Before BUSY

20

15

ns

7

●

t

Delay Between Conversions

Wait Time RD After BUSY

Data Access Time After RD

(Note 10)

50

–5

ns

8

9

C = 25pF

L

20

25

10

35

45

ns

10

●

C = 100pF

L

45

60

ns

t

BUS Relinquish Time

30

35

40

ns

11

12

0°C to 70°C

–40°C to 85°C

●

RD Low Time

●

t

ns

10

18523fa

5

LTC1852/LTC1853

The ● denotes the speciﬁcations which apply over the full operating temperature

TIMING CHARACTERISTICS

range, otherwise speciﬁcations are at T_A= 25°C. (Note 5)

SYMBOL

PARAMETER

CONDITIONS

(Note 10)

MIN

50

10

50

10

TYP

MAX

UNITS

ns

t

CONVST High Time

Latch Setup Time

●

13

(Note 10)

ns

14

15

16

Latch Hold Time

(Notes 9, 10)

(Note 10)

ns

WR Low Time

ns

WR High Time

(Note 10)

ns

17

18

19

20

21

22

M1 to M0 Setup Time

M0 to BUSY Delay

M0 to WR (or RD) Setup Time

M0 High Pulse Width

RD High Time Between Readback Reads

Last WR (or RD) to M0

M0 to RD Setup Time

M0 to CONVST

(Notes 9, 10)

M1 High

ns

20

ns

(Notes 9, 10)

(Note 10)

●

t

ns

19

50

10

ns

(Note 10)

ns

(Note 10)

ns

23

(Notes 9, 10)

(Note 10)

t

ns

24

25

26

27

19

ns

Aperture Delay

–0.5

2

ns

Aperture Jitter

ps

RMS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All voltage values are with respect to ground with OGND and GND

wired together unless otherwise noted.

straight line passing through the actual end points of the transfer curve.

The deviation is measured from the center of the quantization band.

Note 8: Bipolar offset is the offset voltage measured from –0.5LSB when

the output code ﬂickers between 1111 1111 1111 and 0000 0000 0000.

For the LTC1853 and between 11 1111 1111 and 00 0000 0000 for the

LTC1852.

Note 3: When these pin voltages are taken below ground or above V

,

Note 9: Guaranteed by design, not subject to test.

Note 10: Recommended operating conditions.

Note 11: The falling CONVST edge starts a conversion. If CONVST returns

high at a critical point during the conversion it can create small errors.

For the best results, ensure that CONVST returns high either within 400ns

after the start of the conversion or after BUSY rises.

DD

they will be clamped by internal diodes. This product can handle input

currents of 100mA below ground or above V without latchup.

DD

Note 4: When these pin voltages are taken below ground, they will be

clamped by internal diodes. This product can handle input currents of

100mA below ground without latchup. These pins are not clamped to V

.

DD

Note 5: V = 5V, f

= 400kHz, t = t = 2ns unless otherwise

DD

SAMPLE

r f

Note 12: The analog input range is determined by the voltage on

REFCOMP. The gain error speciﬁcation is tested with an external 4.096V

but is valid for any value of REFCOMP greater than 2V and less than

speciﬁed.

Note 6: Linearity, offset and full-scale speciﬁcations apply for a single-

ended input on any channel with COM grounded.

(V – 0.5V.)

DD

Note 7: Integral nonlinearity is deﬁned as the deviation of a code from a

Note 13: MUX address is updated immediately after BUSY falls.

TYPICAL PERFORMANCE CHARACTERISTICS

8192 Point FFT with

f_IN= 39.599kHz

Differential Linearity

0

–20

1.0

0.5

0

–40

–60

–80

–0.5

–1.0

–100

–120

0

200

0

4096

FREQUENCY (kHz)

CODE

1852 F03

1852 F02

18523fa

6

LTC1852/LTC1853

PIN FUNCTIONS

CH0toCH7(Pins1to8):AnalogInputPins.Inputpinscan

be used single ended relative to the analog input common

pin or differentially in pairs (CH0 and CH1, CH2 and CH3,

CH4 and CH5, CH6 and CH7).

A2 /S5, A1 /S4, A0 /S3 (Pins 18 to 20): Three-

OUT OUT OUT

StateDigitalMUXAddressOutputs.ActivewhenRDislow.

Following a conversion, the MUX address of the present

conversion is available on these pins concurrent with the

conversionresult. InReadbackmode, theMUXaddressof

thecurrentsequencerlocation(S5-S3)isavailableonthese

COM(Pin9):AnalogInputCommonPin. Forsingle-ended

operation (DIFF = 0), COM is the “–” analog input. COM

is disabled when DIFF is high.

pins. The outputs swing between OV and OGND.

DD

D9/S2(Pin21,LTC1852):Three-StateDigitalDataOutput.

Active when RD is low. Following a conversion, bit 9 of the

present conversion is available on this pin. In Readback

mode, the unipolar/bipolar bit of the current sequencer

location (S2) is available on this pin. The output swings

REFOUT(Pin10):Internal2.5VReferenceOutput. Bypass

to analog ground plane with 1μF.

REFIN (Pin 11): Reference Mode Select/Reference Buffer

Input. REFIN selects the reference mode and acts as the

reference buffer input. REFIN tied to ground (Logic 0) will

produce 2.048V on the REFCOMP pin. REFIN tied to the

positive supply (Logic 1) disables the reference buffer

to allow REFCOMP to be driven externally. For voltages

between 1V and 2.6V, the reference buffer produces an

output voltage on the REFCOMP pin equal to 1.6384 times

the voltage on REFIN (4.096V on REFCOMP for a 2.5V

input on REFIN).

between OV and OGND.

DD

D11/S2(Pin21,LTC1853):Three-StateDigitalDataOutput.

Active when RD is low. Following a conversion, bit 11 of

thepresentconversionisavailableonthispin.InReadback

mode, the unipolar/bipolar bit of the current sequencer

location (S2) is available on this pin. The output swings

between OV and OGND.

DD

D8/S1(Pin22,LTC1852):Three-StateDigitalDataOutputs.

Active when RD is low. Following a conversion, bit 8 of the

present conversion is available on this pin. In Readback

mode, the gain bit of the current sequencer location (S1)

REFCOMP (Pin 12): Reference Buffer Output. REFCOMP

setsthefull-scaleinputspan.Thereferencebufferproduces

an output voltage on the REFCOMP pin equal to 1.6384

times the voltage on the REFIN pin (4.096V on REFCOMP

for a 2.5V input on REFIN). REFIN tied to ground will

produce 2.048V on the REFCOMP pin. REFCOMP can be

driven externally if REFIN is tied to the positive supply.

Bypass to analog ground plane with 10μF tantalum in

parallel with 0.1μF ceramic or 10μF ceramic.

is available on this pin. The output swings between OV

and OGND.

DD

D10/S1 (Pin 22, LTC1853): Three-State Digital Data

Outputs. Active when RD is low. Following a conversion,

bit 10 of the present conversion is available on this pin.

In Readback mode, the gain bit of the current sequencer

location (S1) is available on this pin. The output swings

GND (Pins 13, 16): Ground. Tie to analog ground plane.

V

(Pins 14, 15): Positive Supply. Bypass to analog

between OV and OGND.

DD

ground plane with 10μF tantalum in parallel with 0.1μF

D7/S0(Pin23,LTC1852):Three-StateDigitalDataOutputs.

Active when RD is low. Following a conversion, bit 7 of the

present conversion is available on this pin. In Readback

mode, the end of sequence bit of the current sequencer

location (S0) is available on this pin. The output swings

ceramic or 10μF ceramic.

DIFF /S6 (Pin 17): Three-State Digital Data Output.

OUT

Active when RD is low. Following a conversion, the

single-ended/differential bit of the present conversion is

availableonthispinconcurrentwiththeconversionresult.

In Readback mode, the single-ended/differential bit of the

current sequencer location (S6) is available on this pin.

between OV and OGND.

DD

The output swings between OV and OGND.

DD

18523fa

7

LTC1852/LTC1853

PIN FUNCTIONS

D9/S0(Pin23,LTC1853):Three-StateDigitalDataOutputs.

Active when RD is low. Following a conversion, bit 9 of the

present conversion is available on this pin. In Readback

mode, the end of sequence bit of the current sequencer

location (S0) is available on this pin. The output swings

UNI/BIP(Pin38):Unipolar/BipolarSelectInput. Logiclow

selects a unipolar input span, a high logic level selects a

bipolar input span.

A0 to A2 (Pins 39 to 41): MUX Address Input Pins.

DIFF (Pin 42): Single-Ended/Differential Select Input.

A low logic level selects single ended, a high logic level

selects differential.

between OV and OGND.

DD

D6 to D0 (Pins 24 to 30, LTC1852): Three-State Digital

Data Outputs. Active when RD is low. The outputs swing

WR (Pin 43): Write Input. In Direct Address mode, WR

lowenablestheMUXaddressandconﬁgurationinputpins

(Pins 37 to 42). WR can be tied low or the rising edge of

WR can be used to latch the data. In Program mode, WR

is used to program the sequencer. WR low enables the

MUXaddressandconﬁgurationinputpins(Pins37to42).

The rising edge of WR latches the data and increments

the counter to the next sequencer location.

between OV and OGND.

DD

D8 to D0 (Pins 24 to 32, LTC1853): Three-State Digital

Data Outputs. Active when RD is low. The outputs swing

between OV and OGND.

DD

NC (Pins 31 to 32, LTC1852): No Connect. There is no

internal connection to these pins.

BUSY (Pin 33): Converter Busy Output. The BUSY output

has two functions. At the start of a conversion, BUSY will

go low and remain low until the conversion is completed.

The rising edge may be used to latch the output data.

BUSY will also go low while the part is in Program/Read-

back mode (M1 high, M0 low) and remain low until M0

RD (Pin 44): Read Input. During normal operation, RD

enables the output drivers when CS is low. In Readback

mode (M1 high, M0 low), RD going low reads the cur-

rent sequencer location, RD high advances to the next

sequencer location.

is brought back high. The output swings between OV

and OGND.

DD

CONVST (Pin 45): Conversion Start Input. This active low

signal starts a conversion on its falling edge.

OGND (Pin 34): Digital Data Output Ground. Tie to analog

ground plane. May be tied to logic ground if desired.

CS (Pin 46): Chip Select Input. The chip select input must

belowfortheADCtorecognizetheCONVSTandRDinputs.

If SHDN is low, a low logic level on CS selects Nap mode;

a high logic level on CS selects Sleep mode.

OV (Pin 35): Digital Data Output Supply. Normally tied

DD

to 5V, can be used to interface with 3V digital logic. Bypass

toOGNDwith10μFtantaluminparallelwith0.1μFceramic

or 10μF ceramic.

SHDN (Pin 47): Power Shutdown Input. A low logic level

will invoke the Shutdown mode selected by the CS pin.

CS low selects Nap mode, CS high selects Sleep mode.

Tie high if unused.

M0 (Pin 36): Mode Select Pin 0. Used in conjunction with

M1 to select operating mode. See Table 5.

PGA (Pin 37): Gain Select Input. A high logic level selects

gain = 1, a low logic level selects gain = 2.

M1 (Pin 48): Mode Select Pin 1. Used in conjunction with

M0 to select operating mode. See Table 5.

18523fa

8

LTC1852/LTC1853

PIN FUNCTIONS

NOMINAL (V)

ABSOLUTE MAXIMUM (M)

MAX

1 to 8

9

NAME

DESCRIPTION

MIN

0

TYP

MAX

MIN

–0.3

CH0 to CH7

COM

Analog Inputs

V

+ 0.3

DD

Analog Input Common Pin

2.5V Reference Output

Reference Buffer Input

Reference Buffer Output

Ground

0

+ 0.3

10

REFOUT

REFIN

2.5

11

0

2.5

V

DD

12

REFCOMP

GND

4.096

13

0

5

0

14

V

Positive Supply

2.7

5.5

6

DD

15

Positive Supply

6

16

GND

DIFF /S6

Ground

V

+ 0.3

DD

17

Single-Ended/Differential Output

MUX Address Output

Data Output

OGND

0V

+ 0.3

OUT

DD

18

A2 /S5

OUT

0V

19

A1 /S4

OUT

20

A0 /S3

OUT

21

D9/S2 (LTC1852)

D11/S2 (LTC1853)

D8/S1 (LTC1852)

D10/S1 (LTC1853)

D7/S0 (LTC1852)

D9/S0 (LTC1853)

D6 to D0 (LTC1852)

D8 to D0 (LTC1853)

NC (LTC1852)

21

Data Output

22

Data Output

22

Data Output

23

Data Output

23

Data Output

24 to 30

24 to 32

31 to 32

33

Data Outputs

No Connect

BUSY

Converter Busy Output

Output Ground

OGND

0V

DD

–0.3

V

+ 0.3

DD

34

OGND

0

5

35

OV

Output Supply

2.7

0

5.5

6

DD

36

M0

Mode Select Pin 0

Gain Select Input

Unipolar/Bipolar Input

MUX Address Inputs

Single-Ended/Differential Input

Write Input, Active Low

Read Input, Active Low

Conversion Start Input, Active Low

Chip Select Input, Active Low

Shutdown Input, Active Low

Mode Select Pin 1

V

6

DD

37

PGA

0

DD

38

UNI/BIP

A0 to A2

DIFF

0

39 to 41

42

0

43

WR

0

44

RD

0

45

CONVST

CS

0

46

0

47

SHDN

M1

0

48

0

18523fa

9

LTC1852/LTC1853

APPLICATIONS INFORMATION

The LTC1852/LTC1853 are complete and very ﬂexible

data acquisition systems. They consist of a 10-bit/12-bit,

400ksps capacitive successive approximation A/D con-

verter with a wideband sample-and-hold, a conﬁgurable

8-channel analog input multiplexer, an internal reference

and reference buffer ampliﬁer, a 16-bit parallel digital

outputanddigitalcontrollogic, includingaprogrammable

sequencer.

DYNAMIC PERFORMANCE

Signal-to-(Noise + Distortion) Ratio

The signal-to-noise plus distortion ratio [S/(N + D)] is the

ratiobetweentheRMSamplitudeofthefundamentalinput

frequency and the RMS amplitude of all other frequency

components at the ADC output. The output is band lim-

ited to frequencies above DC to below half the sampling

frequency. The effective number of bits (ENOBs) is a

measurement of the resolution of an ADC and is directly

related to the S/(N + D) by the equation:

CONVERSION DETAILS

T

he core analog-to-digital converter in the LTC1852/

LTC1853 uses a successive approximation algorithm and

an internal sample-and-hold circuit to convert an analog

signal to a 10-bit/12-bit parallel output. Conversion start

is controlled by the CS and CONVST inputs. At the start

of the conversion, the successive approximation register

(SAR)isreset.Onceaconversioncycleisbegun,itcannot

be restarted. During the conversion, the internal differen-

tial capacitive DAC output is sequenced by the SAR from

the most signiﬁcant bit (MSB) to the least signiﬁcant bit

(LSB). The outputs of the analog input multiplexer are

ENOB = [S/(N + D) – 1.76]/6.02

whereENOBistheeffectivenumberofbitsandS/(N+D)is

expressedindB.Atthemaximumsamplingrateof400kHz,

the LTC1852/LTC1853 maintain near ideal ENOBs up to

and beyond the Nyquist input frequency of 200kHz.

Total Harmonic Distortion

Total harmonic distortion is the ratio of the RMS sum

of all harmonics of the input signal to the fundamental

itself. The out-of-band harmonics alias into the frequency

band between DC and half the sampling frequency. THD

is expressed as:

connected to the sample-and-hold capacitors (C_SAMPLE

)

during the acquire phase and the comparator offset is

nulled by the zeroing switches. In this acquire phase, a

minimum delay of 150ns will provide enough time for

the sample-and-hold capacitors to acquire the analog

signal. During the convert phase, the comparator zeroing

switches are open, putting the comparator into compare

mode. The input switches connect C_SAMPLEto ground,

transferring the differential analog input charge onto the

summing junction. This input charge is successively

compared with the binary weighted charges supplied by

the differential capacitive DAC. Bit decisions are made by

the high speed comparator. At the end of the conversion,

the differential DAC output balances the input charges.

The SAR contents (a 10-bit/12-bit data word), which

represents the difference of the analog input multiplexer

outputs, and the 4-bit address word are loaded into the

14-bit/16-bit output latches.

V2²+ V3²+ V4²+...Vn²

THD=20Log

V1

where V1 is the RMS amplitude of the fundamental

frequency and V2 through Vn are the amplitudes of the

second through nth harmonics. The LTC1852/LTC1853

have good distortion performance up to the Nyquist

frequency and beyond.

Intermodulation Distortion

If the ADC input signal consists of more than one spectral

component, the ADC transfer function nonlinearity can

produce intermodulation distortion (IMD) in addition to

THD. IMD is the change in one sinusoidal input caused

by the presence of another sinusoidal input at a different

frequency.

18523fa

10

LTC1852/LTC1853

APPLICATIONS INFORMATION

If two pure sine waves of frequencies fa and fb are applied

totheADCinput,nonlinearitiesintheADCtransferfunction

can create distortion products at the sum and difference

frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc.

For example, the 2nd order IMD terms include (fa fb).

If the two input sine waves are equal in magnitude, the

value (in decibels) of the 2nd order IMD products can be

expressed by the following formula:

inputs as shown in Table 1. Unused inputs (including

the COM in the differential case) should be grounded to

prevent noise coupling.

Table 1. Multiplexer Address Table

MUX ADDRESS

SINGLE-ENDED CHANNEL SELECTION

DIFF A2 A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM

0

1

0

1

0

1

0

1

0

1

0

1

0

1

–

+

Amplitude at fa± fb

(

)

IMD fa± fb =20Log

(

)

+

Amplitude at fa

+

Peak Harmonic or Spurious Noise

+

Thepeakharmonicorspuriousnoiseisthelargestspectral

component excluding the input signal and DC. This value

is expressed in decibels relative to the RMS value of a

full-scale input signal.

+

MUX ADDRESS

DIFFERENTIAL CHANNEL SELECTION

DIFF A2 A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

–

*

+

Full-Power and Full-Linear Bandwidth

–

+

The full-power bandwidth is that input frequency at which

theamplitudeofthereconstructedfundamentalisreduced

by 3dB for a full-scale input signal.

–

+

–

+

–

+

–

+

The full-linear bandwidth is the input frequency at which

the S/(N + D) has dropped to 68dB for the LTC1853 (11

effective bits) or 56dB for the LTC1852 (9 effective bits).

The LTC1852/LTC1853 have been designed to optimize

input bandwidth, allowing the ADC to undersample input

signalswithfrequenciesabovetheconverter’sNyquistfre-

quency. Thenoiseﬂoorstaysverylowathighfrequencies;

S/(N+D)becomesdominatedbydistortionatfrequencies

far beyond Nyquist.

–

+

–

+

*Not used in differential mode. Connect to AGND.

In addition to selecting the MUX channel, the LTC1852/

LTC1853 also allows the user to select between two gains

andunipolarorbipolarinputsforatotaloffourinputspans.

PGA high selects a gain of 1 (the input span is equal to the

voltage on REFCOMP). PGA low selects a gain of 2 where

the input span is equal to half of the voltage on REFCOMP.

UNI/BIP low selects a unipolar input span, UNI/BIP high

selects a bipolar input span. Table 2 summarizes the pos-

sible input spans.

ANALOG INPUT MULTIPLEXER

The analog input multiplexer is controlled using the

single-ended/differential pin (DIFF), three MUX address

pins (A2, A1, A0), the unipolar/bipolar pin (UNI/BIP) and

the gain select pin (PGA). The single-ended/differential

pin (DIFF) allows the user to conﬁgure the MUX as eight

single-ended channels relative to the analog input com-

mon pin (COM) when DIFF is low or as four differential

pairs (CH0 and CH1, CH2 and CH3, CH4 and CH5, CH6

and CH7) when DIFF is high. The channels (and polarity in

the differential case) are selected using the MUX address

Table 2. Input Span Table

INPUT SPAN

UNI/BIP

PGA

REFCOMP = 4.096V

0 – 2.048V

0 – 4.096V

1.024V

0

1

0

1

0

1

0 – REFCOMP/2

0 – REFCOMP

REFCOMP/4

REFCOMP/2

2.048V

18523fa

11

LTC1852/LTC1853

APPLICATIONS INFORMATION

The LTC1852/LTC1853 have a unique differential sample-

and-holdcircuitthatallowsrail-to-railinputs.TheADCwill

always convert the difference of the “+” and “–” inputs

independent of the common mode voltage. The common

mode rejection holds up to high frequencies. The only

input(s) must settle after the small current spike before

the next conversion starts (settling time must be less than

150ns for full throughput rate).

Choosing an Input Ampliﬁer

requirement is that both inputs can not exceed the AV

DD

Choosing an input ampliﬁer is easy if a few requirements

are taken into consideration. First, to limit the magnitude

of the voltage spike seen by the ampliﬁer from charging

the sampling capacitor, choose an ampliﬁer that has a low

output impedance (<100Ω) at the closed-loop bandwidth

frequency. For example, if an ampliﬁer is used in a gain

of +1 and has a unity-gain bandwidth of 50MHz, then the

output impedance at 50MHz should be less than 100Ω.

Thesecondrequirementisthattheclosed-loopbandwidth

must be greater than 10MHz to ensure adequate small-

signal settling for full throughput rate. The following list

is a summary of the op amps that are suitable for driving

the LTC1852/LTC1853, more detailed information is avail-

power supply voltage or ground. When a bipolar input

span is selected the “+” input can swing full scale rela-

tive to the “–” input but neither input can exceed AV or

DD

go below ground.

Integral nonlinearity errors (INL) and differential nonlin-

earity errors (DNL) areindependent of the common mode

voltage, however, the bipolar offset will vary. The change

in bipolar offset is typically less than 0.1% of the common

mode voltage.

SomeACapplicationsmayhavetheirperformancelimited

by distortion. Most circuits exhibit higher distortion when

signals approach the supply or ground. THD will degrade

as the inputs approach either power supply rail. Distor-

tion can be reduced by reducing the signal amplitude

and keeping the common mode voltage at approximately

midsupply.

™

able in the Linear Technology Databooks, the LinearView

CD-ROM and on our web site at www.linear-tech.com.

LT^®1360: 50MHz Voltage Feedback Ampliﬁer. 2.5V to

15V supplies. 5mA supply current. Low distortion.

LT1363:70MHzVoltageFeedbackAmpliﬁer. 2.5Vto 15V

supplies. 7.5mA supply current. Low distortion.

Driving the Analog Inputs

TheinputsoftheLTC1852/LTC1853areeasytodrive.Each

of the analog inputs can be used as a single-ended input

relative to the input common pin (CH0-COM, CH1-COM,

etc.) or in pairs (CH0 and CH1, CH2 and CH3, CH4 and

CH5, CH6 and CH7) for differential inputs. Regardless

of the MUX conﬁguration, the “+” and “–” inputs are

sampled at the same instant. Any unwanted signal that is

common mode to both inputs will be reduced by the com-

mon mode rejection of the sample-and-hold circuit. The

inputs draw only one small current spike while charging

the sample-and-hold capacitors at the end of conversion.

During conversion, the analog inputs draw only a small

leakage current. If the source impedance of the driving

circuit is low, then the LTC1852/LTC1853 inputs can be

driven directly. As source impedance increases, so will

acquisition time. For minimum acquisition time with high

source impedance, a buffer ampliﬁer should be used. The

only requirement is that the ampliﬁer driving the analog

LT1364/LT1365: Dual and Quad 70MHz Voltage Feedback

Ampliﬁers. 2.5V to 15V supplies. 7.5mA supply current

per ampliﬁer. Low distortion.

LT1468/LT1469:SingleandDual90MHzVoltageFeedback

Ampliﬁer. 5V to 15V supplies. 7mA supply current per

ampliﬁer. Lowest noise and low distortion.

LT1630/LT1631: Dual and Quad 30MHz Rail-to-Rail Volt-

age Feedback Ampliﬁers. Single 3V to 15V supplies.

3.5mA supply current per ampliﬁer. Low noise and low

distortion.

LT1632/LT1633:DualandQuad45MHzRail-to-RailVoltage

Feedback Ampliﬁers. Single 3V to 15V supplies. 4.3mA

supply current per ampliﬁer. Low distortion.

LT1806/LT1807: Single and Dual 325MHz Rail-to-Rail

Voltage Feedback Ampliﬁer. Single 3V to 5V supplies.

13mA supply current. Lowest distortion.

LinearView is a trademark of Linear Technology Corporation.

18523fa

12

LTC1852/LTC1853

APPLICATIONS INFORMATION

LT1809/LT1810: Single and Dual 180MHz Rail-to-Rail

Voltage Feedback Ampliﬁer. Single 3V to 15V supplies.

20mA supply current. Lowest distortion.

or DAC. If REFIN is tied low, the internal 2.5V reference

divided by 2 (1.25V) is connected internally to the input

of the reference buffer resulting in 2.048V on REFCOMP.

If REFIN is tied high, the reference buffer is disabled and

REFCOMP can be tied to REFOUT to achieve a 2.5V span

or driven with an external reference or DAC. Table 3 sum-

marizes the Reference modes.

LT1812/LT1813: Single and Dual 100MHz Voltage Feed-

back Ampliﬁer. Single 5V to 5V supplies. 3.6mA supply

current. Low noise and low distortion.

Input Filtering

Table 3. Reference Mode Table

MODE

REFIN

0V Input

REFCOMP

The noise and the distortion of the input ampliﬁer and

other circuitry must be considered since they will add to

the LTC1852/LTC1853 noise and distortion. Noisy input

circuitry should be ﬁltered prior to the analog inputs to

minimize noise. A simple 1-pole RC ﬁlter is sufﬁcient for

many applications. For instance, a 200Ω source resistor

and a 1000pF capacitor to ground on the input will limit

the input bandwidth to 800kHz.The capacitor also acts

as a charge reservoir for the input sample-and-hold and

isolates the ADC input from sampling glitch sensitive

circuitry. High quality capacitors and resistors should be

used since these components can add distortion. NPO

and silver mica type dielectric capacitors have excellent

linearity.Carbonsurfacemountresistorscanalsogenerate

distortion from self heating and from damage that may

occurduringsoldering.Metalﬁlmsurfacemountresistors

are much less susceptible to both problems.

REFIN Tied Low

REFIN is Buffer Input

2.048V Output

1v to 2.6 Input

1.6384V to 4.26V Output

(1.6384 • REFIN)

REFIN Tied High

5V Input

Input, 19.2kΩ to Ground

Full Scale and Offset

In applications where absolute accuracy is important,

offset and full-scale errors can be adjusted to zero dur-

ing a calibration sequence. Offset error must be adjusted

before full-scale error. Zero offset is achieved by adjust-

ing the offset applied to the “–” input. For single-ended

inputs, this offset should be applied to the COM pin. For

differential inputs, the “–” input is dictated by the MUX

address. For zero offset error, apply 0.5LSB (actual volt-

age will vary with input span selected) to the “+” input

and adjust the offset at the “–” input until the output code

ﬂickers between 0000 0000 0000 and 0000 0000 0001

for the LTC1853 and between 00 0000 0000 and 00 0000

0001 for the LTC1852.

REFERENCE

The LTC1852/LTC1853 includes an on-chip, temperature

compensated, curvature corrected, bandgap reference

that is factory trimmed to 2.500V and has a very ﬂexible

3-pininterface.REFOUTisthe2.5Vbandgapoutput,REFIN

is the input to the reference buffer and REFCOMP is the

reference buffer output. The input span is determined by

the voltage appearing on the REFCOMP pin as shown in

Table 2. The reference buffer has a gain of 1.6384 and

is factory trimmed by forcing an external 2.500V on the

REFIN pin and trimming REFCOMP to 4.096V. The 3-pin

interfaceallowsforthreepin-strappableReferencemodes

as well as two additional external Reference modes. For

voltages on the REFIN pin ranging from 1V to 2.6V, the

output voltage on REFCOMP will equal 1.6384 times the

voltage on the REFIN pin. In this mode, the REFIN pin can

be tied to REFOUT to use the internal 2.5V reference to get

4.096V on REFCOMP or driven with an external reference

As mentioned earlier, the internal reference is factory

trimmed to 2.500V. To make sure that the reference buffer

gain is not compensating for trim errors in the reference,

REFCOMPistrimmedto4.096Vwithanextremelyaccurate

external2.5VreferenceappliedtoREFIN.Likewise,tomake

sure that the full-scale gain trim is not compensating for

errors in the reference buffer gain, the input full-scale gain

is trimmed with an extremely accurate 4.096V reference

applied to REFCOMP (REFIN = 5V to disable the reference

buffer).Thisallowstheuseofeithera2.5Vreferenceapplied

to REFIN or a 4.096V reference applied to REFCOMP to

achieve accurate results. Full-scale errors can be trimmed

to zero by adjusting the appropriate reference voltage. For

unipolar inputs, an input voltage of FS – 1.5LSBs should

be applied to the “+” input and the appropriate reference

18523fa

13

LTC1852/LTC1853

APPLICATIONS INFORMATION

adjusted until the output code ﬂickers between 1111 1111

1110 and 1111 1111 1111 for the LTC1853 and between

11 1111 1110 and 11 1111 1111 for the LTC1852.

also function as output bits when reading the contents of

the programmable sequencer. During readback, a 7-bit

status word (S6-S0) containing the contents of the cur-

rent sequencer location is available when RD is low. The

individual bits of the status word are outlined in Figure 1.

During readback, the D8 to D0 pins (LTC1853) or D6 to

D0 pins (LTC1852) remain high impedance irrespective

of the state of RD.

Forbipolarinputs, aninputvoltageofFS–1.5LSBsshould

be applied to the “+” input and the appropriate reference

adjusted until the output code ﬂickers between 0111 1111

1110 and 0111 1111 1111 for the LTC1853 and between

01 1111 1110 and 01 1111 1111 for the LTC1852.

These adjustments as well as the factory trims affect all

channels. The channel-to-channel offset and gain error

matching are guaranteed by design to meet the speciﬁca-

tions in the Converter Characteristics table.

Unipolar Transfer Characteristic

(UNI/BIP = 0)

1111...1111

1111...1110

1111...1101

1000...0001

1000...0000

0111...1111

0111...1110

0000...0010

0000...0001

0000...0000

OUTPUT DATA FORMAT

The LTC1852/LTC1853 have a 14 bit/16-bit parallel out-

put. The output word normally consists of a 10-bit/12-bit

conversion result data word and a 4-bit address (three

address bits A2 , A1 , A0

and the DIFF

bit).

OUT

FS = V

REFCOMP

The output drivers are enabled when RD is low provided

the chip is selected (CS is low). All 14/16 data output pins

0

FS – 1LBS

18523 F01A

INPUT VOLTAGE (V)

and BUSY are supplied by OV and OGND to allow easy

DD

interface to 3V or 5V digital logic.

Bipolar Transfer Characteristic

(UNI/BIP = 1)

The data format of the conversion result is automatically

selected and determined by the UNI/BIP input pin. If

the UNI/BIP pin is low indicating a unipolar input span

(0 – REFCOMP assuming PGA = 1), the format for the

data is straight binary with 1 LSB = FS/4096 (1mV for

REFCOMP=4.096V).FortheLTC1853and1LSB=FS/1024

(4mV for REFCOMP = 4.096V) for the LTC1852.

0111...1111

0111...1110

0111...1101

0000...0001

0000...0000

1111...1111

1111...1110

1000...0010

1000...0001

1000...0000

BIPOLAR

ZERO

If the UNI/BIP pin is high indicating a bipolar input span

( REFCOMP/2forPGA=1),theformatforthedataistwo’s

complement binary with 1 LSB = [(+FS) – (–FS)]/4096

(1mV for REFCOMP = 4.096V). For the LTC1853 and 1LSB

= [(+FS) – (–FS)]/1024 (4mV for REFCOMP = 4.096V) for

the LTC1852.

V

REFCOMP

2

FS =

–FS

–1LBS 0 1LBS

FS – 1LBS

18523 F01B

INPUT VOLTAGE (V)

S6

S5

S4

S3

S2

S1

S0

In both cases, the code transitions occur midway be-

tween successive integer LSB values (i.e., –FS + 0.5LSB,

–FS + 1.5LSB, ... –1.5LSB, –0.5LSB, 0.5LSB, 1.5LSB, ...

FS – 1.5LSB, FS – 0.5LSB).

A2

A1

A0

PGA BIT

MUX ADDRESS

END OF

SINGLE-ENDED/

DIFFERENTIAL BIT

UNIPOLAR/

SEQUENCE BIT

BIPOLAR BIT

18523 F01

Thethreemostsigniﬁcantbitsofthedataword(D11, D10

and D9 for the LTC1853; D9, D8 and D7 for the LTC1852)

Figure 1. Readback Status Word

18523fa

14

LTC1852/LTC1853

APPLICATIONS INFORMATION

BOARD LAYOUT AND BYPASSING

whichever input is selected as the “–” input. Leads to the

inputs should be kept as short as possible.

ToobtainthebestperformancefromtheLTC1852/LTC1853,

a printed circuit board with ground plane is required. The

ground plane under the ADC area should be as free of

breaks and holes as possible, such that a low impedance

path between all ADC grounds and all ADC decoupling

capacitors is provided. It is critical to prevent digital noise

from being coupled to the analog inputs, reference or

analog power supply lines. Layout for the printed circuit

boardshouldensurethatdigitalandanalogsignallinesare

separated as much as possible. In particular, care should

be taken not to run any digital track alongside an analog

signal track or underneath the ADC.

SUPPLY BYPASSING

High quality, low series resistance ceramic 10μF bypass

capacitors should be used. Surface mount ceramic ca-

pacitors such as Murata GRM235Y5V106Z016 provide

excellent bypassing in a small board space. Alternatively,

10μF tantalum capacitors in parallel with 0.1μF ceramic

capacitorscanbeused.Bypasscapacitorsmustbelocated

as close to the pins as possible. The traces connecting the

pins and the bypass capacitors must be kept short and

should be made as wide as possible.

An analog ground plane separate from the logic system

ground should be established under and around the ADC.

Pin 34 (OGND), Pin 13 (GND), Pin 16 (GND) and all other

analog grounds should be connected to this single ana-

log ground point. The bypass capacitors should also be

connected to this analog ground plane. No other digital

groundsshouldbeconnectedtothisanaloggroundplane.

In some applications, it may be desirable to connect the

DIGITAL INTERFACE

Internal Clock

TheA/Dconverterhasaninternalclockthateliminatesthe

need of synchronization between the external clock and

the CS and RD signals found in other ADCs. The internal

clock is factory trimmed to achieve a typical conversion

time of 1400ns, and a maximum conversion time over

the full operating temperature range of 2μs. No external

adjustments are required. The guaranteed maximum

acquisition time is 150ns. In addition, a throughput

time of 2.5μs and a minimum sampling rate of 400ksps

is guaranteed.

OV to the logic system supply and OGND to the logic

DD

system ground. In these cases, OV should be bypassed

DD

to OGND instead of the analog ground plane.

Low impedance analog and digital power supply common

returns are essential to the low noise operation of the

ADC and the foil width for these tracks should be as wide

as possible. In applications where the ADC data outputs

and control signals are connected to a continuously ac-

tive microprocessor bus, it is possible to get errors in the

conversion results. These errors are due to feedthrough

from the microprocessor to the sucessive approximation

comparator. The problem can be eliminated by forcing the

microprocessor into a WAIT state during conversions or

by using three-state buffers to isolate the ADC bus. The

traces connecting the pins and bypass capacitors must be

kept short and should be made as wide as possible.

CS

t

3

SHDN

18523 F02

Figure 2. CS to SHDN Setup Timing

SHDN

t

4

The LTC1852/LTC1853 have differential inputs to mini-

mize noise coupling. Common mode noise on the “+”

and “–” inputs will be rejected by the input CMRR. The

LTC1852/LTC1853 will hold and convert the difference

between whichever input is selected as the “+” input and

CONVST

18523 F03

Figure 3. SHDN to CONVST Wake-Up Timing

18523fa

15

LTC1852/LTC1853

APPLICATIONS INFORMATION

the ADC has been selected (i.e., CS is low). Once initiated,

it cannot be restarted until the conversion is complete.

Converter status is indicated by the BUSY output. BUSY

is low during a conversion. If CONVST returns high at a

critical point during the conversion it can create small

errors. For the best results, ensure that CONVST returns

high either within 400ns after the start of the conversion

or after BUSY rises.

CS

t

2

CONVST

RD

t

1

18523 F04

Figure 4. CS to CONVST and RD Setup Timing

Figures 5 through 9 show several different modes

of operation. In modes 1a and 1b (Figures 5 and 6),

CS and RD are both tied low. The falling edge of

CONVST starts the conversion. The data outputs

are always enabled and data can be latched with the

BUSYrisingedge.Mode1ashowsoperationwithanarrow

logic low CONVST pulse. Mode 1b shows a narrow logic

high CONVST pulse.

Power Shutdown

The LTC1852/LTC1853 provide two power shutdown

modes, Nap and Sleep, to save power during inactive

periods. The Nap mode reduces the power to 2.5mW and

leaves only the digital logic and reference powered up.

The wake-up time from Nap to active is 200ns. In Sleep

mode, all bias currents are shut down and only leakage

current remains—about 20μA. Wake-up time from sleep

mode is much slower since the reference circuit must

power-up and settle to 0.005% for full 12-bit accuracy

(0.02%forfull10-bitaccuracy).Sleepmodewake-uptime

is dependent on the value of the capacitor connected to

the REFCOMP (Pin 12). The wake-up time is 10ms with

the recommended 10μF capacitor.

In mode 2 (Figure 7), CS is tied low. The falling edge of

CONVST signal again starts the conversion. Data out-

puts are in three-state until read by the MPU with the

RD signal.Mode 2 can be used for operation with a shared

MPU databus.

In slow memory and ROM modes (Figures 8 and 9),CS is

tied low and CONVST and RD are tied together. The MPU

starts the conversion and reads the output with the RD

signal. Conversions are started by the MPU or DSP (no

external sample clock).

Shutdown is controlled by Pin 47 (SHDN); the ADC is in

shutdown when it is low. The shutdown mode is selected

with Pin 46 (CS); low selects Nap (Figures 2 and 3).

In slow memory mode, the processor applies a logic low

to RD ( = CONVST), starting the conversion. BUSY goes

low, forcing the processor into a Wait state. The previous

conversion result appears on the data outputs. When

the conversion is complete, the new conversion results

Timing and Control

Conversionstartanddatareadoperationsarecontrolledby

threedigitalinputs:CONVST,CSandRD(Figure4).Alogic

“0” applied to the CONVST pin will start a conversion after

t

CONV

t

5

CONVST

BUSY

t

8

6

t

7

DATA

DATA (N – 1)

DATA N

18523 F05

Figure 5. Mode 1a CONVST Starts a Conversion. Data Outputs Always Enabled (CS = RD = 0)

18523fa

16

LTC1852/LTC1853

APPLICATIONS INFORMATION

t

8

CONV

t

13

t

5

CONVST

t

6

t

6

BUSY

t

7

DATA

DATA (N – 1)

DATA N

18523 F06

Figure 6. Mode 1b CONVST Starts a Conversion, RD = CS = 0

t

CONV

t

5

t

8

CONVST

BUSY

RD

t

13

6

t

9

t

12

t

10

t

11

DATA

DATA N

18523 F07

Figure 7. Mode 2 CONVST Starts a Conversion. Data is Read by RD, CS = 0

t

8

CONV

RD = CONVST

BUSY

t

11

t

6

t

10

t

7

DATA

DATA (N – 1)

DATA N

DATA (N + 1)

18523 F08

Figure 8. Slow Memory Mode Timing, CS = 0

t

8

CONV

CONVST

BUSY

t

6

t

11

t

10

DATA

DATA (N – 1)

DATA N

18523 F09

Figure 9. ROM Mode Timing, CS = 0

18523fa

17

LTC1852/LTC1853

APPLICATIONS INFORMATION

appear on the data outputs; BUSY goes high releasing the

processor, and the processor takes RD ( = CONVST) back

high and reads the new conversion data.

single-ended and differential inputs. For instance, if the

A0_OUTpin is tied to the DIFF input pin, the scan pattern

willconsistoffoursingle-endedinputsandtwodifferential

pairs (CH0-COM single-ended, CH1-COM single-ended,

CH2-CH3 differential, CH4-COM single-ended, CH5-COM

single-ended, CH6-CH7 differential, repeat).

In ROM mode, the processor takes RD ( = CONVST) low,

startingaconversionandreadingthepreviousconversion

result.Aftertheconversioniscomplete, theprocessorcan

read the new result and initiate another conversion.

The scan counter is reset to zero whenever the M0 pin

changes state so that the ﬁrst conversion after M0 rises

willbeMUXAddress000(CH0-COMsingle-endedorCH0-

CH1 differential depending on the state of the DIFF pin).

A conversion is initiated by the falling edge of CONVST.

After each conversion, the address counter is advanced

(by one if DIFF is low, by two if DIFF is high) and the MUX

address for the present conversion is available on the ad-

MODES OF OPERATION

Direct Address Mode

The simplest mode of operation is the Direct Address

mode. This mode is selected when both the M1 and M0

pins are low. In this mode, the address input pins directly

control the MUX and the conﬁguration input pins directly

control the input span. The address and conﬁguration

input pins are enabled when WR is low. WR can be tied

low if the pins will be constantly driven or the rising edge

of WR can be used to latch and hold the inputs for as long

as WR is held high.

dress output pins (DIFF , A2

to A0 ) along with

OUT

the conversion result.

Program/Readback Mode

The LTC1852 and LTC1853 include a sequencer that can

be programmed to run a sequence of up to 16 locations

containing a MUX address and input conﬁguration. The

MUX address and input conﬁguration for each location

are programmed using the DIFF, A2 to A0, UNI/BIP and

PGA pins and are stored in memory along with an end-of-

sequence (EOS) bit that is generated automatically. The

six input address and conﬁguration bits plus the EOS bit

can be read back by accessing the 7-bit readback status

word(S6-S0)throughthedataoutputpins.Thesequencer

memory is a 16 × 7 block of memory represented by the

block diagram in Figure 10.

Scan Mode

Scan mode is selected when M1 is low and M0 is high.

This mode allows the converter to scan through all of

the input channels sequentially and repeatedly without

the user having to provide an address. The address

input pins (A2 to A0) are ignored but the DIFF, PGA and

UNI/BIP pins are still enabled when WR is low. As in the

direct address mode, WR can be held low or the rising

edge of WR can be used to latch and hold the information

on these pins for as long as WR is held high. The DIFF

pin selects the scan pattern. If DIFF is held low, the scan

pattern will consist of all eight channels in succession,

single-ended relative to COM (CH0-COM, CH1-COM,

CH2-COM, CH3-COM, CH4-COM, CH5-COM, CH6-COM,

CH7-COM, repeat). At the maximum conversion rate the

throughput rate for each channel would be 400ksps/8 or

50ksps. If DIFF is held high, the scan pattern will consist

of four differential pairs (CH0-CH1, CH2-CH3, CH4-CH5,

CH6-CH7, repeat). At the maximum conversion rate, the

throughput rate for each pair would be 400ksps/4 or

100ksps. It is possible to drive the DIFF input pin while

the part is in Scan mode to achieve combinations of

DIFF

A2

A1

A0

UNI/BIP

PGA

EOS

LOCATION 0000

LOCATION 0001

LOCATION 0010

•

LOCATION 1110

LOCATION 1111

18523 F10

Figure 10. Sequencer Memory Block Diagram

18523fa

18

LTC1852/LTC1853

APPLICATIONS INFORMATION

and advance the pointer to the next location. A logic 1

on the D9/S0 (D7/S0) pin indicates the last location in

the current sequence but all 16 locations can be read by

continuing to clock RD. After 16 reads, the pointer is reset

to location 0000. When all programming and/or reading

of the sequencer memory is complete, M0 is taken high.

BUSYwillcomebackhighenablingCONVSTandindicating

that the part is ready to start a conversion.

The sequencer is accessed by taking the M1 mode pin

high. With M1 high, the sequencer memory is accessed

by taking the M0 mode pin low. This will cause BUSY to

go low, disabling conversions during the programming

and readback of the sequencer. The sequencer is reset

to location 0000 whenever M1 or M0 changes state. One

of these signals should be cycled prior to any read or

write operation to guarantee that the sequencer will be

programmed or read starting at location 0000.

Sequence Run Mode

The sequencer is programmed sequentially starting from

location 0000. RD and WR should be held high, the ap-

propriatesignalsappliedtotheDIFFpin, theA2toA0MUX

address pins, the UNI/BIP pin and the PGA pin and WR

taken low to write to the memory. WR going high will latch

the data into memory and advance the pointer to the next

sequencerlocation.Upto16locationscanbeprogrammed

and the last location written before M0 is taken back high

will be the last location in the sequence. After 16 writes,

the pointer is reset to location 0000 and any subsequent

writes will erase all of the previous contents and start a

new sequence.

Once the sequencer is programmed, M0 is taken high.

BUSY will also come back high enabling CONVST and

the next falling CONVST will begin a conversion using the

MUX address and input conﬁguration stored in location

0000 of the sequencer memory. After each conversion,

the sequencer pointer is advanced by one and the MUX

address ( the actual channel or channels being converted,

not the sequencer pointer) for the present conversion

is available on the address output pins along with the

conversion result. When the sequencer ﬁnishes convert-

ing the last programmed location, the sequencer pointer

will return to location 0000 for the next conversion. The

sequencer will also reset to location 0000 anytime the M1

or M0 pin changes state.

The sequencer memory can be read by holding WR high

and strobing RD. Taking RD low accesses the sequencer

memory and enables the data output pins. The sequencer

should be reset to location 0000 before beginning a read

operation (by applying a positive pulse to MO). The seven

The contents of the sequencer memory will be retained

as long as power is contiuously applied to the part. This

allows the user to switch from Sequence Run mode to

either Direct Address or Scan Mode and back without

losing the programmed sequence. The part can also be

disabled using CS or shutdown in Nap or Sleep mode

withoutlosingtheprogrammedsequence.Table5outlines

theoperationalmodesoftheLTC1852/LTC1853.Figures11

and 12 show the timing diagrams for writing to, reading

from and running a sequence.

output bits will be available on the DIFF /S6, A2 /S5,

OUT

A1 /S4, A0 /S3, D11/S2, D10/S1 and D9/S0 pins

OUT

(LTC1853)orDIFF /S6,A2 /S5,A1 /S4,A0 /S3,

OUT

D9/S2, D8/S1 and D7/S0 pins (LTC1852). The D8 to D0

(LTC1853) or D6 to D0 (LTC1852) data output pins will

remain high impedance during readback. RD going high

will return the data output pins to a high impedance state

Table 5

OPERATION MODE

M1

M0

WR

RD

COMMENTS

Direct Address

0

OE

Address and Conﬁguration are Driven from External Pins

Address and Conﬁguration are Latched on Rising Edge of WR or Falling Edge of CONVST

Scan

0

1

0

OE

Address is Provided by Internal Scan Counter, Conﬁguration is Driven from External Pins

Conﬁguraton is Latched on Rising Edge of WR or Falling Edge of CONVST

Program

Readback

Sequence Run

1

0

1

Write Sequencer Location, WR Low Enables Inputs, Rising Edge of WR Latches Data and

Advances to Next Location

1

Read Sequencer Location, Falling Edge of RD Enables Output, Rising Edge of RD

Advances to Next Location

X

OE

Run Programmed Sequence, Falling Edge of CONVST Starts Conversion and Advances to

Next Location

18523fa

19

LTC1852/LTC1853

APPLICATIONS INFORMATION

18523fa

20

LTC1852/LTC1853

APPLICATIONS INFORMATION

18523fa

21

LTC1852/LTC1853

TYPICAL APPLICATIONS

LTC1853 Hardwired for 8-Channel Single-Ended Scan with Unipolar 0V to 4.096V Operation

5V

10μF

0.1μF

14

15

V

DD

48

36

47

46

45

44

43

42

41

40

39

38

37

M1

M0

LTC1853

5V

SHDN

CS

1

2

3

4

5

6

7

8

9

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

COM

CONVST

RD

CONTROL LOGIC

AND

PROGRAMMABLE

SEQUENCER

CONVERT

CLOCK

WR

DIFF

A2

INPUT

A1

CONFIGURATION:

ALL 8 CHANNELS

SINGLE ENDED

TO COM

A0

8-CHANNEL

MULTIPLEXER

INTERNAL

CLOCK

UNI/BIP

PGA

5V

CH0–CH7:

0V TO 4.096V

OV

DD

35

2.7V TO V

DD

BUSY 33

DIFF /S6 17

0.1μF

10μF

OUT

A2 /S5 18

OUT

A1 /S4 19

OUT

A0 /S3 20

OUT

D11/S2 21

D10/S1 22

D9/S0 23

D8 24

2.5V

1μF

10 REFOUT

2.5V

REFERENCE

12-BIT

SAMPLING

ADC

+

–

DATA

LATCHES

OUTPUT

DRIVERS

D7 25

11 REFIN

D6 26

REF AMP

D5 27

D4 28

1.6384X

D3 29

4.096V

REFCOMP

12

D2 30

0.1μF

10μF

D1 31

D0 32

OGND 34

GND

16

18523 TA01

13

18523fa

22

LTC1852/LTC1853

TYPICAL APPLICATIONS

LTC1853 Hardwired for 4-Channel Differential Scan with Bipolar 1.024V Operation

5V

10μF

0.1μF

14

15

V

DD

48

36

47

46

45

44

43

42

41

40

39

38

37

M1

M0

LTC1853

5V

SHDN

CS

1

2

3

4

5

6

7

8

9

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

COM

CONVST

RD

+

–

+

CONTROL LOGIC

AND

PROGRAMMABLE

SEQUENCER

CONVERT

CLOCK

WR

DIFF

A2

5V

A1

–

+

INPUT

A0

8-CHANNEL

MULTIPLEXER

CONFIGURATION:

4 DIFFERENTIAL

CHANNELS: ±1.024V

INTERNAL

CLOCK

UNI/BIP

PGA

5V

–

+

–

OV

DD

35

3V TO 5V

0.1μF

BUSY 33

10μF

DIFF /S6 17

OUT

A2 /S5 18

OUT

A1 /S4 19

OUT

A0 /S3 20

OUT

D11/S2 21

D10/S1 22

D9/S0 23

D8 24

2.5V

10 REFOUT

2.5V

REFERENCE

12-BIT

SAMPLING

ADC

+

–

DATA

LATCHES

OUTPUT

DRIVERS

1μF

D7 25

11 REFIN

D6 26

REF AMP

D5 27

D4 28

1.6384X

D3 29

4.096V

REFCOMP

12

D2 30

0.1μF

10μF

D1 31

D0 32

OGND 34

GND

16

18523 TA02

13

PACKAGE DESCRIPTION

FW Package

48-Lead Plastic TSSOP (6.1mm)

(Reference LTC DWG # 05-08-1651 Rev A)

12.40 – 12.60*

(.488 – .496)

48

25

0.95 ±0.10

44

42

41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

48 47 46 45

43

8.4 ±0.10

6.2 ±0.10

7.9 – 8.3

(.311 – .327)

1

24

0.32 ±0.05

0.50 BSC

5

7

8

1

2

3

4

6

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

RECOMMENDED SOLDER PAD LAYOUT

1.10

(.0433)

MAX

6.0 – 6.2**

(.236 – .244)

0.25

REF

0° – 8°

NOTE:

-T-

-C-

1. CONTROLLING DIMENSION: MILLIMETERS

0.10 C

FW48 TSSOP REV A 1005

0.50

(.0197)

BSC

0.17 – 0.27

(.0067 – .0106)

TYP

MILLIMETERS

2. DIMENSIONS ARE IN

(INCHES)

0.09 – 0.20

(.0035 – .008)

0.45 – 0.75

(.018 – .029)

0.05 – 0.15

(.002 – .006)

3. DRAWING NOT TO SCALE

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE

**

DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE

18523fa

InformationfurnishedbyLinearTechnologyCorporationisbelievedtobeaccurateandreliable.However,

no responsibility is assumed for its use. Linear Technology Corporation makes no representation that

the interconnection of its circuits as described herein will not infringe on existing patent rights.

23

LTC1852/LTC1853

TYPICAL APPLICATION

Data buffering using two IDT7202LA15 1k x 9-bit FIFOs

allowsrapidcollectionof1024samplesandsimpleinterface

to low power, low speed, 8-bit microcontrollers. Data and

channelinformationareclockedinsimultaneouslyandread

out as two bytes using READ HIGH FIFO and READ LOW

FIFO lines. In the event of bus contention, resistors limit

peak output current. If both FIFOs are read completely or

reset before a burst of conversions, the empty, half full,

and full ﬂags from only one FIFO need to be monitored.

Theretransmitinputsmayalsobetiedtogether.Retransmit

may be used to read data repeatedly, allowing a memory

limited processor to perform transform and ﬁltering func-

tions that would otherwise be difﬁcult.

0.1μF

INPUT

5V

CONFIGURATION:

ALL 8 CHANNELS

SINGLE ENDED TO COM

CH0–CH7: 0V TO 4.096V

28

5V

IDT7202LA15

13

18

17

16

12

11

10

9

10μF

0.1μF

8-BIT

10μF

2

24

25

26

27

3

D8

Q8

Q7

Q6

Q5

Q4

Q3

Q2

Q1

Q0

R

8 × 1k

DATA BUS

OV

14

15

DD

35

D7

D6

D5

D4

D3

D2

D1

D0

WR

FF

D7

D6

D5

D4

D3

D2

D1

D0

V

DD

48

36

47

46

45

44

43

42

41

40

39

38

37

M1

M0

LTC1853

5V

SHDN

CS

1

2

3

4

5

6

7

8

9

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

COM

CONVST

RD

4

CONTROL LOGIC

AND

PROGRAMMABLE

SEQUENCER

5

WR

6

DIFF

A2

15

21

20

23

1

READ_HIGH_FIFO

8

A1

EF

HIGH_FIFO_EMPTY

22

A0

RS

HF

HIGH_FIFO_HALF_FULL

HIGH BYTE_FIFO_RETRANSMIT

8-CHANNEL

MULTIPLEXER

INTERNAL

CLOCK

UNI/BIP

PGA

RT

XI

7

GND

5V

14

BUSY 33

DIFF /S6 17

OUT

A2 /S5 18

HIGH_FIFO_FULL_FLAG

LOW_FIFO_FULL_FLAG

FIFO_RESET

OUT

A1 /S4 19

OUT

A0 /S3 20

OUT

0.1μF

D11/S2 21

D10/S1 22

D9/S0 23

D8 24

10 REFOUT

2.5V

REFERENCE

12-BIT

SAMPLING

ADC

5V

+

–

DATA

LATCHES

2.5V

OUTPUT

DRIVERS

28

IDT7202LA15

2

24

25

26

27

3

13

19

18

17

16

12

11

10

9

D8

D7

D6

D5

D4

D3

D2

D1

D0

WR

FF

Q8

Q7

Q6

Q5

Q4

Q3

Q2

Q1

Q0

R

8 × 1k

D7 25

11 REFIN

D6 26

REF AMP

D5 27

1μF

D4 28

1.6384X

D3 29

4

D2 30

5

D1 31

6

D0 32

1

15

21

20

23

OGND 34

READ_LOW_FIFO

GND

13

GND

16

REFCOMP

8

EF

LOW_FIFO_EMPTY

LOW_FIFO_HALF_FULL

12

22

4.096V

RS

HF

RT

GND

14

*CONVERT

CLOCK

UP TO 1024

LOW BYTE_FIFO_RETRANSMIT

0.1μF

10μF

XI

7

18523 TA03

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90dB SINAD, 220mW Power Dissipation, Pin Compatible with LTC1608

Pin-Compatible, Programmable Multiplexer and Sequencer

LTC1850/LTC1851 10-Bit/12, 8-Channel, 1.25Msps ADCs

18523fa

LT 0108 REV A • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

24

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(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC1852CFW
厂家：	Linear
描述：	8-Channel, 10-Bit/12-Bit, 400ksps, Low Power, Sampling ADCs 8通道， 10位/ 12位， 400ksps ，低功耗，采样ADC
文件：	总24页 (文件大小：237K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC1852CFW [Linear]

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