LTC1773EMS-PBF [Linear]
Synchronous Step-Down DC/DC Controller; 同步降压型DC / DC控制器
| 型号： | LTC1773EMS-PBF |
| 厂家： | 
Linear |
| 描述： | Synchronous Step-Down DC/DC Controller |
| 文件： | 总20页 (文件大小：285K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1773
Synchronous Step-Down
DC/DC Controller
U
FEATURES
DESCRIPTIO
The LTC®1773 is a current mode synchronous buck regu-
lator controller that drives external complementary power
MOSFETs using a fixed frequency architecture. The oper-
ating supply range is from 2.65V to 8.5V, making it
suitable for 1- or 2-cell lithium-ion battery powered appli-
cations. BurstMode® operationprovideshighefficiencyat
low load currents. 100% duty cycle provides low dropout
operation which extends operating time in battery-oper-
ated systems.
■
High Efficiency: Up to 95%
■
Constant Frequency 550kHz Operation
■
VIN from 2.65V to 8.5V
■
VOUT from 0.8V to VIN
OPTI-LOOP® Compensation Minimizes COUT
■
■
Synchronizable up to 750kHz
■
Selectable Burst Mode Operation
■
Low Quiescent Current: 80µA
■
Low Dropout Operation: 100% Duty Cycle
■
Secondary Winding Regulation
Soft-Start
The operating frequency is internally set at 550kHz, allow-
ing the use of small surface mount inductors. For switch-
ing-noisesensitiveapplications, itcanbesynchronizedup
to 750kHz. Peak current limit is user programmable with
an external high side sense resistor. A SYNC/FCB control
pin guarantees regulation of secondary windings regard-
less of load on the main output by forcing continuous
operation. Burst Mode operation is inhibited during syn-
chronization or when the SYNC/FCB pin is pulled low to
reducenoiseandRFinterference. Soft-startisprovidedby
an external capacitor.
■
■
Current Mode Operation for Excellent Line and
Load Transient Response
■
Low Shutdown IQ = 10µA
■
±1.5% Reference Accuracy
■
Precision 2.5V Undervoltage Lockout
■
Available in 10-LUead MSOP
APPLICATIO S
■
Cellular Telephones
■
RF PA Supplies
Synchronous rectification increases efficiency and elimi-
nates the need for a Schottky diode, saving components
and board space. The LTC1773 comes in a 10-lead MSOP
package.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
OPTI-LOOP and Burst Mode are registered trademarks of Linear Technology Corporation.
Protected by U.S. Patents, including 5481178, 6580258, 6304066, 6127815.
■
Portable Instruments
■
Wireless MODEMS
■
Distributed Power Systems
■
Notebook and Palm Top Computers, PDAs
■
Single and Dual Cell Lithium-Ion Powered Devices
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TYPICAL APPLICATIO
V
IN
2.65V TO 8.5V
High Efficiency
100
+
V
= 3.3V
IN
95
90
85
80
75
70
65
60
55
V
R
C
SYNC/FCB
IN
SENSE
IN
68µF
0.025Ω
V
IN
= 5V
RUN/SS SENSE–
0.1µF
L1
3µH
V
= 8V
IN
I
TH
TG
V
OUT
2.5V
LTC1773
GND
47pF
30k
SW
BG
220pF
V
FB
+
Si9801DY
169k
C
OUT
180µF
L = SUMIDA CDRH6D28-3R0
80.6k
1
10
100
1000 5000
1773 F01
OUTPUT CURRENT (mA)
1773 F1b
Figure 1. Step-Down Converter
1773fb
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LTC1773
W W
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U
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ABSOLUTE AXI U RATI GS
(Note 1)
PACKAGE/ORDER I FOR ATIO
ORDER PART
Input Supply Voltage ..............................–0.3V to 10.0V
TOP VIEW
NUMBER
I
TH Voltage ................................................–0.3V to 2.5V
I
1
2
3
4
5
10 SW
RUN/SS, VFB, SENSE– Voltages .................. –0.3V to VIN
SYNC/FCB Voltage ...................................... –0.3V to VIN
BG, TG Voltages...........................................–0.3V to VIN
SW Voltage ...................................................–5V to 11V
Operating Ambient Temperature Range
TH
RUN/SS
9
8
7
6
SENSE–
LTC1773EMS
SYNC/FCB
V
TG
BG
IN
V
GND
FB
MS PART MARKING
LTMV
MS PACKAGE
10-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA = 120°C/W
(Note 2) ...............................................–40°C to 85°C
Junction Temperature (Note 3)............................. 125°C
Storage Temperature Range ..................–65°C to 150°C
Lead Temperature (Soldering, 10 sec.)................. 300°C
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The
●
denotes specifications which apply over the full operating
temperature range, T = 25°C. V = 5V unless otherwise specified.
A
IN
SYMBOL
PARAMETER
CONDITIONS
(Note 4)
MIN
TYP
20
MAX
60
UNITS
nA
I
Feedback Current
VFB
V
Regulated Feedback Voltage
∆Output Overvoltage Lockout
Reference Voltage Line Regulation
Output Voltage Load Regulation
(Note 4)
●
0.788
40
0.80
60
0.812
80
V
FB
∆V
∆V
∆V
= V
– V
FB
mV
%/V
%
OVL
OVL
OVL
V
= 2.7V to 8.5V (Note 4)
at 1.0V (Note 4)
0.002
0.2
0.02
0.8
FB
IN
TH
TH
V
I
I
LOADREG
at 0.6V (Note 4)
–0.2
–0.8
%
I
Input DC Bias Current
Normal Mode
(Note 5)
S
V
V
V
V
= 5V, V = OPEN, V = OPEN
400
80
600
µA
µA
µA
µA
V
IN
ITH
SYNC/MODE
Burst Mode Operation
Shutdown
= 0V, V = 5V, V
= OPEN
SYNC/MODE
ITH
IN
= 0V, 2.7V < V < 8.5V
10
30
5
RUN/SS
RUN/SS
IN
Shutdown
= 0V, V < 2.4V
2
IN
V
RUN/SS Threshold
Soft-Start Current Source
Auxiliary Feedback Threshold
SYNC/FCB Pull-Up Current
Oscillator Frequency
0.4
0.75
0.76
0.1
0.7
1.5
0.8
0.4
550
55
1.0
2.5
0.84
1.0
600
RUN/SS
I
V
V
V
V
V
V
V
= 0V
µA
V
RUN/SS
RUN/SS
V
Ramping Negative
= 0V
SYNC/FCB
SYNC/FCB
OSC
SYNC/FCB
SYNC/FCB
I
f
µA
kHz
kHz
V
= 0.8V
500
FB
FB
IN
IN
= 0V
V
Undervoltage Lockout
Ramping Down from 3V
Ramping Up from 0V
●
●
●
2.35
85
2.5
2.65
100
45
2.65
2.8
UVLO
V
∆
)
Maximum Current Sense Voltage
115
160
150
180
150
mV
ns
ns
ns
ns
VSENSE(MAX
TG t
TG t
Top Gate Drive Rise Time
Top Gate Drive Fall Time
Bottom Gate Drive Rise Time
Bottom Gate Drive Fall Time
C
C
C
C
= 3000pF (Note 6)
= 3000pF (Note 6)
= 3000pF (Note 6)
= 3000pF (Note 6)
r
f
LOAD
LOAD
LOAD
LOAD
48
BG t
BG t
80
r
45
f
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LTC1773
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note3:T iscalculatedfromtheambienttemperatureT andpowerdissipation
J A
P according to the following formula:
D
LTC1773: T = T + (P • 120°C/W)
J
A
D
Note 4: The LTC1773 is tested in a feedback loop which servos V to the
FB
Note 2: The LTC1773 is guaranteed to meet performance specifications from
0°C to 70°C. Specifications over the –40°C to 85°C operating temperature
range are assured by design, characterization and correlation with statistical
process controls.
balance point for the error amplifier (V = 0.8V)
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency.
Note 6: Rise and fall times are measured using 10% and 90% levels.
ITH
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TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency vs Load Current
Efficiency vs Load Current
Efficiency vs Input Voltage
100
95
90
85
80
75
V
V
= 5V
V = 2.5V
OUT
IN
OUT
V
= 2.5V
OUT
100
90
80
70
60
50
100
90
80
70
60
50
= 2.5V
SEE FIGURE 1
SEE FIGURE 1
SEE FIGURE 1
V
= 3.3V
IN
I
= 1A
OUT
V
= 5V
IN
V
= 8V
Burst Mode
OPERATION
IN
SYNC(750kHz)
I
= 100mA
OUT
FORCED CONTINUOUS
100 1000 5000
OUTPUT CURRENT (mA)
2
4
6
INPUT VOLTAGE (V)
8
10
1
10
1
10
100
1000
10,000
OUTPUT CURRENT (mA)
1773 G03
1773 G01
1773 G02
V -V
Dropout Voltage
Input and Shutdown Currents
vs Input Voltage
IN OUT
vs Load Current
Load Regulation
500
450
400
350
300
250
200
150
100
50
400
350
300
250
200
150
100
50
0
–0.05
–0.10
–0.15
–0.20
–0.25
–0.30
R
= 0.025Ω
SENSE
R
= 0.025Ω
SENSE
SEE FIGURE 1
V
= 1.8V
OUT
Si9801DY
SYNC TO 750kHz
V
= 1.8V
OUT
Si9801DY
= 0.025Ω
R
SENSE
L = CDRH6D28-3RO
Burst Mode OPERATION
SHUTDOWN
0
0
2
4
6
8
10
0
500
1000
1500
2000
2500
2.0
LOAD CURRENT (A)
3.0 3.5
0
0.5
1.0 1.5
2.5
INPUT VOLTAGE (V)
LOAD CURRENT (mA)
1773 G06
1773 G05
1773 G16
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LTC1773
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TYPICAL PERFOR A CE CHARACTERISTICS
Maximum Current Sense
Threshold vs V
Maximum Current Sense
Threshold vs Temperature
Maximum Current Sense
Threshold vs V
RUN/SS
ITH
120
100
80
60
40
20
0
120
100
80
60
40
20
0
105
100
95
Burst Mode
OPERATION
FORCED
CONTINUOUS
85
2.5
(V)
3.5
4.0
0.5 1.0
1.5 2.0
V
3.0
–60 –40 –20
0
20 40
80 100 120 140
60
0
0.8
1.2 1.4
0.2 0.4 0.6
1.0
1.6
TEMPERATURE (°C)
V
(V)
RUN/SS
ITH
1773 G07
1773 G08
1773 G09
RUN/SS Pin Current vs
Temperature
Oscillator Frequency vs
Temperature
Burst Mode Operation
2.5
2.0
1.5
1.0
0.5
560
550
540
530
520
I
= 100mA
LOAD
SEE FIGURE 9
V
OUT
20mV/DIV
I
L
500mA/DIV
1773 G12
V
V
= 5V
= 2.5V
20µs/DIV
–60 –40 –20
0
20 40 60 80 100 120 140
IN
OUT
–60 –40 –20
0
20 40 60 80 100 120 140
TEMPERATURE (°C)
TEMPERATURE (°C)
1773 G11
1773 G10
Load Step (Burst Mode
Operation)
Load Step (Continuous
Mode)
Start-Up
SEE FIGURE 9
SEE FIGURE 9
SEE FIGURE 9
V
OUT
2V/DIV
V
OUT
V
OUT
100mV/DIV
100mV/DIV
V
RUN/SS
1V/DIV
I
L
I
I
L
L
2A/DIV
2A/DIV
2A/DIV
1773 G14
1773 G15
1773 G13
V
V
= 5V
100µs/DIV
V
V
= 5V
40ms/DIV
IN
OUT
V
V
= 5V
100µs/DIV
IN
OUT
IN
OUT
= 2.5V
= 2.5V
= 2.5V
100mA TO 5A LOAD STEP
100mA TO 5A LOAD STEP
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LTC1773
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PIN FUNCTIONS
ITH (Pin 1): Error Amplifier Compensation Point. The
current comparator threshold increases with this control
voltage. Nominal voltage range for this pin is 0V to 1.2V.
Under high duty cycle and nearing current limit, ITH can
swing up to 2.4V.
VFB (Pin 4): Feedback Pin. Receives the feedback voltage
fromanexternalresistivedivideracrosstheoutput.Donot
use more than 0.01µF of feedforward capacitance from FB
to the output.
GND (Pin 5): Ground Pin.
RUN/SS (Pin 2): Combination of Soft-Start and Run
Control Inputs. A capacitor to ground at this pin sets the
ramptimetofullcurrentoutput. Thetimeisapproximately
0.8s/µF. Forcing this pin below 0.4V shuts down all the
circuitry.
BG (Pin 6): Bottom Gate Driver of External N-Channel
Power MOSFET. This pin swings from 0V to VIN.
TG (Pin 7): Top Gate Driver of External P-Channel Power
MOSFET. This pin swings from 0V to VIN.
VIN (Pin 8) : Main Supply Pin. Must be closely decoupled
SYNC/FCB (Pin 3): Multifunction Pin. This pin performs
three functions: 1) secondary winding feedback input, 2)
external clock synchronization and 3) Burst Mode opera-
tion or forced continuous mode select. For secondary
winding applications, connect to a resistive divider from
the secondary output. To synchronize with an external
clock, apply a TTL/CMOS compatible clock with a fre-
quency between 585kHz and 750kHz. To select Burst
Mode operation, tie SYNC/FCB to VIN. Grounding this pin
forces continuous operation.
to GND (pin 5).
SENSE–(Pin 9): The Negative Input to the Current Com-
parator. A sense resistor between this pin and VIN sets the
peak current in the top switch. Connect this pin to the
source of the external P-Channel power MOSFET.
SW (Pin 10): Switch Node Connection to Inductor. This
pin connects to the drains of the external main and
synchronous power MOSFET switches.
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FUNCTIONAL DIAGRA
Y
Y = “0” ONLY WHEN X IS A CONSTANT “1”
BURST
DEFEAT
0.4µA
X
SLOPE
COMP
V
8
9
IN
SYNC/FCB
3
OSC
0.4V
–
SENSE
–
+
0.6V
–
SYNC
DEFEAT
EN
+
–
V
0.8V
4
–
+
FB
+
SLEEP
I
COMP
+
–
50mV
FREQ
0.22V
SHIFT
EA
BURST
COMP
1.5µA
I
TH
1
0.8V REF
S
R
Q
Q
RUN/
2
SOFT-START
TG
7
RUN/SS
SWITCHING
LOGIC
UVLO
TRIP = 2.5V
AND
ANTI
SHOOT-THRU
–
BLANKING
CIRCUIT
OVDET
0.86V
+
BG
6
SHUTDOWN
+
–
SW
10
I
RCMP
–
0.8V
GND
5
FCB
+
1773 FD
Figure 2.
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LTC1773
U
(Refer to Functional Diagram)
OPERATIO
Main Control Loop
secondary winding regulation as described in Auxiliary
Winding Control Using SYNC/FCB Pin in the Applications
Information section.
The LTC1773 uses a constant frequency, current mode
step-downarchitecturetodriveanexternalpairofcomple-
mentary power MOSFETs. During normal operation, the
externaltopP-channelpowerMOSFETturnsoneachcycle
when the oscillator sets the RS latch, and turns off when
the current comparator ICOMP resets the RS latch. The
peak inductor current at which ICOMP resets the RS latch
is controlled by the voltage on the ITH pin, which is the
output of error amplifier EA. The VFB pin, described in the
Pin Functions section, allows EA to receive an output
feedback voltage from an external resistive divider. When
the load current increases, it causes a slight decrease in
the feedback voltage relative to the 0.8V reference, which
in turn causes the ITH voltage to increase until the average
inductor current matches the new load current. While the
top P-channel MOSFET is off, the bottom N-channel
MOSFET is turned on until either the inductor current
starts to reverse, as indicated by the current reversal
comparator IRCMP, or the beginning of the next cycle.
When the converter operates in Burst Mode operation the
peak current of the inductor is set to approximately a third
of the maximum peak current value during normal opera-
tioneventhoughthevoltageattheITH pinindicatesalower
value. The voltage at the ITH pin drops when the inductor’s
average current is greater than the load requirement. As
the ITH voltage drops below 0.22V, the BURST compara-
tor trips, causing the internal sleep line to go high and turn
off both power MOSFETs.
The circuit enters sleep mode with both power MOSFETs
turned off. In sleep mode, the internal circuitry is partially
turned off, reducing the quiescent current to about 80µA.
The load current is now being supplied from the output
capacitor. When the output voltage drops, causing ITH to
rise above 0.27V, the internal sleep line goes low, and the
LTC1773 resumes normal operation. The next oscillator
cycle will turn on the external top MOSFET and the switch-
ing cycle repeats.
The main control loop is shut down by pulling the RUN/SS
pin low. Releasing RUN/SS allows an internal 1.5µA
current source to charge the external soft-start capacitor
CSS. When CSS reaches 0.7V, the main control loop is
enabled with the internal buffered ITH voltage clamped at
approximately 5% of its maximum value. As CSS contin-
ues to charge, the internal buffered ITH is gradually re-
leased allowing normal operation to resume.
Short-Circuit Protection
Whentheoutputisshortedtoground, thefrequencyofthe
oscillator is reduced to about 55kHz, 1/10 the nominal
frequency. This frequency foldback ensures that the in-
ductorcurrenthasmoretimetodecay, therebypreventing
runaway. The oscillator’s frequency will gradually in-
crease to 550kHz after VFB rises above 0.4V.
An overvoltage comparator, 0V, guards against transient
overshoots (>7.5%) as well as other more serious condi-
tions that may overvoltage the output. In this case, the top
MOSFETisturnedoffandthebottomMOSFETisturnedon
until the overvoltage condition is cleared.
Frequency Synchronization
The LTC1773 can be synchronized with an external TTL/
CMOS compatible clock signal. The frequency range of
this signal must be from 585kHz to 750kHz. Do not
synchronizetheLTC1773below585kHzasthismaycause
abnormal operation and an undesired frequency spec-
trum. The top MOSFET turn-on follows the rising edge of
the external source.
Burst Mode Operation
The LTC1773 is capable of Burst Mode operation in which
the external power MOSFETs operate intermittently based
on load demand. To enable Burst Mode operation, simply
allow the SYNC/FCB pin to float or connect it to a logic
high. To disable Burst Mode operation and force continu-
ous mode, connect the SYNC/FCB pin to GND. The thresh-
old voltage between Burst Mode operation and forced
continuous mode is 0.8V. This can be used to assist in
When the LTC1773 is clocked by an external source, Burst
Mode operation is disabled; the LTC1773 then operates in
PWM pulse skipping mode preventing current reversal. In
this mode, when the output load is very low, current
comparatorICOMP remainstrippedformorethanonecycle
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LTC1773
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OPERATIO (Refer to Functional Diagram)
andforcesthemainswitchtostayoffforthesamenumber
of cycles. Increasing the output load current slightly,
above the minimum required for discontinuous conduc-
tion mode, allows constant frequency PWM.
Low Supply Operation
The LTC1773 is designed to operate down to a 2.65V
supply voltage. For proper operation at this low input
voltage, sub-logic level MOSFETs are required. When the
value of the output voltage is very close to the input
voltage, the converter is running at high duty cycles or in
dropout where the main switch is on continuously. See
Efficiency Considerations in the Applications Information
section.
Frequency synchronization is inhibited when the feedback
voltage, VFB, is below 0.6V. This prevents the external
clock from interfering with the frequency foldback for
short-circuit protection.
Dropout Operation
Slope Compensation and Inductor Peak Current
When the input supply voltage decreases toward the
output voltage, the duty cycle increases toward the maxi-
mum on-time. Further reduction of the supply voltage
forces the main switch to remain on for more than one
cycle until it reaches 100% duty cycle. The output voltage
will then be determined by the input voltage minus the IR
voltage drop across the external P-channel MOSFET,
sense resistor, and the inductor.
Slope compensation provides stability by preventing
subharmonic oscillations. It works by internally adding a
ramptotheinductorcurrentsignalatdutycyclesinexcess
of30%.Thiscausestheinternalcurrentcomparatortotrip
earlier. The ITH clamp level is also reached earlier than
conditions in which the duty cycle is below 30%. As a
result, the maximum inductor peak current is lower for
VOUT/VIN > 0.3 than when VOUT/VIN < 0.3.
Undervoltage Lockout
To compensate for this loss in maximum inductor peak
current during high duty cycles, the LTC1773 uses a
patent pending scheme that raises the ITH clamp level
(proportional to the amount of slope compensation) when
duty cycle is above 30%.
A precisionundervoltagelockoutshutsdowntheLTC1773
when VIN drops below 2.5V, making it ideal for single
lithium-ionbattery applications.Inshutdown,theLTC1773
draws only several microamperes, which is low enough to
preventdeepdischargeandpossibledamagetothelithium-
ion battery that’s nearing its end of charge. A 150mV
hysteresis ensures reliable operation with noisy supplies.
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APPLICATIONS INFORMATION
The basic LTC1773 application circuit is shown in
average output current IMAX equal to the peak value less
Figure 1. External component selection is driven by the
half the peak-to-peak ripple current ∆IL.
load requirement and begins with the selection of RSENSE
.
Allowing a margin for variations in the LTC1773 and
external component values yields:
Once RSENSE is known, L can be chosen, followed by the
external power MOSFETs. Finally, CIN and COUT are se-
lected.
RSENSE = 70mV/IMAX
Inductor Value Calculation
RSENSE Selection for Output Current
The inductor selection will depend on the operating fre-
quency of the LTC1773. The internal preset frequency is
550kHz, but can be externally synchronized up to 750kHz.
RSENSE is chosen based on the required output current.
The LTC1773 current comparator has a maximum thresh-
old of 100mV/RSENSE. The current comparator threshold
sets the peak of the inductor current, yielding a maximum
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LTC1773
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APPLICATIONS INFORMATION
The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. However, oper-
ating at a higher frequency generally results in lower
efficiencybecauseofexternalMOSFETgatechargelosses.
inductor ripple current and consequent output voltage
ripple. Do not allow the core to saturate!
Molypermalloy (from Magnetics, Inc.) is a very good, low
losscorematerialfortoroids,butitismoreexpensivethan
ferrite. A reasonable compromise from the same manu-
facturer is Kool Mµ. Toroids are very space efficient,
especially when you can use several layers of wire. Be-
cause they generally lack a bobbin, mounting is more
difficult. However, new designs for surface mount are
available which do not increase the height significantly.
Theinductorvaluehasadirecteffectonripplecurrent.The
ripple current, ∆IL, decreases with higher inductance or
frequency and increases with higher VIN or VOUT
.
⎛
⎞
1
VOUT
V
IN
∆IL =
VOUT 1–
⎜
⎟
(1)
⎝
⎠
f L
( )( )
Power MOSFET and Schottky Diode Selection
Two external power MOSFETs must be selected for use
with the LTC1773: a P-channel MOSFET for the top (main)
switch, and an N-channel MOSFET for the bottom (syn-
chronous) switch.
Accepting larger values of ∆IL allows the use of lower
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is 30% to 40% of IMAX. Remember,
the maximum ∆IL occurs at the maximum input voltage.
The peak-to-peak gate drive levels are set by the VIN
voltage. Therefore, for VIN > 5V, logic-level threshold
MOSFETs should be used. But, for VIN < 5V, sub-logic
level threshold MOSFETs (VGS(TH) < 3V) should be used.
In these applications, make sure that the VIN to the
LTC1773 is less than 8V because the absolute maximum
VGS rating of the majority of these sub-logic threshold
MOSFETs is 8V.
The inductor value also has an effect on Burst Mode
operation. The transition to low current operation begins
when the inductor current peaks fall to approximately 1/3
its original value. Lower inductor values (higher ∆IL) will
causethistooccuratlowerloadcurrents,whichcancause
a dip in efficiency in the upper range of low current
operation. In Burst Mode operation, lower inductance
values will cause the burst frequency to increase.
SelectioncriteriaforthepowerMOSFETsincludethe“ON”
resistance RDS(ON), reverse transfer capacitance CRSS
,
Inductor Core Selection
input voltage, maximum output current, and total gate
charge. When the LTC1773 is operating in continuous
mode the duty cycles for the top and bottom MOSFETs are
given by:
Once the value for L is known, the type of inductor must be
selected. High efficiency converters generally cannot af-
ford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite, molypermalloy,
or Kool Mµ® cores. Actual core loss is independent of core
size for a fixed inductor value, but it is very dependent on
inductance selected. As inductance increases, core losses
go down. Unfortunately, increased inductance requires
more turns of wire and therefore copper losses will in-
crease. Ferrite designs have very low core losses and are
preferred at high switching frequencies, so design goals
canconcentrateoncopperlossandpreventingsaturation.
Ferrite core material saturates “hard”, which means that
inductance collapses abruptly when the peak design cur-
rent is exceeded. This results in an abrupt increase in
Main Switch Duty Cycle = VOUT/VIN
Synchronous Switch Duty Cycle = (VIN – VOUT)/VIN
The MOSFET power dissipations at maximum output
current are given by:
VOUT
V
IN
2
PMAIN
=
I
1+ δ R
+
(
MAX) (
)
DSON
2
K V
I
C
f
(
IN) ( MAX)( RSS)( )
1773fb
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RMS capacitor current is given by:
V – VOUT
2
IN
P
SYNC
=
I
1+ δ R
(
MAX) (
)
DS ON
(
)
V
IN
1 2
V
V – V
OUT
(
)
]
[
OUT IN
CIN required IRMS ≅ IMAX
where δ is the temperature dependency of RDS(ON) and K
is a constant inversely related to the gate drive current.
V
IN
This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT/2. This simple worst-case condition is
commonly used for design because even significant de-
viations do not offer much relief. Note that capacitor
manufacturer’s ripple current ratings are often based on
2000hoursoflife.Thismakesitadvisabletofurtherderate
the capacitor, or choose a capacitor rated at a higher
temperaturethanrequired.Severalcapacitorsmayalsobe
paralleled to meet size or height requirements in the
design. Always consult the manufacturer if there is any
question.
BothMOSFETshaveI2RlosseswhilethetopsideP-channel
equation includes an additional term for transition losses,
whicharehighestathighinputvoltages. Thesynchronous
MOSFETlossesaregreatestathighinputvoltageorduring
a short-circuit when the duty cycle in this switch is nearly
100%.
The term (1 + δ) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs temperature curve, but
δ = 0.005/°C can be used as an approximation for low
voltageMOSFETs.CRSS isusuallyspecifiedintheMOSFET
characteristics. The constant K = 1.7 can be used to
estimate the contributions of the two terms in the main
switch dissipation equation.
C
OUT Selection
The selection of COUT is driven by the required effective
series resistance (ESR). Typically, once the ESR require-
ment is satisfied the capacitance is adequate for filtering.
The output ripple (∆VOUT) is determined by:
Typical gate charge for the selected P-channel MOSFET
should be less than 30nC (at 4.5VGS) while the turn-off
delay should be less than 150ns. However, due to differ-
encesintestandspecificationmethodsofvariousMOSFET
manufacturers, the P-channel MOSFET ultimately should
be evaluated in the actual LTC1773 application circuit to
ensure proper operation.
⎛
⎞
1
∆VOUT ≅ ∆IL ESR +
⎜
⎟
8fCOUT
⎝
⎠
where f = operating frequency, COUT = output capacitance
and ∆IL = ripple current in the inductor. The output ripple
is highest at maximum input voltage since ∆IL increases
with input voltage. With ∆IL = 0.4IOUT(MAX) and allowing
for 2/3 of the ripple due to ESR, the output ripple will be
less than 50mV at max VIN assuming:
A Schottky diode can be placed in parallel with the syn-
chronous MOSFET to improve efficiency. It conducts
during the dead-time between the conduction of the two
power MOSFETs. This prevents the body diode of the
bottom MOSFET from turning on and storing charge
during the dead-time, which could cost as much as 1% in
efficiency. A 1A Schottky is generally a good size for 5A to
8A regulators due to the relatively small average current.
Larger diodes result in additional transition losses due to
their larger junction capacitance. The diode may be omit-
ted if the efficiency loss can be tolerated.
COUT required ESR < 2 RSENSE
COUT > 1/(8fRSENSE
)
ThefirstconditionrelatestotheripplecurrentintotheESR
of the output capacitance while the second term guaran-
tees that the output voltage does not significantly dis-
chargeduringtheoperatingfrequencyperiodduetoripple
current. The choice of using smaller output capacitance
increases the ripple voltage due to the discharging term
but can be compensated for by using capacitors of very
low ESR to maintain the ripple voltage at or below 50mV.
CIN Selection
Incontinuousmode,thesourcecurrentofthetopMOSFET
is a square wave of duty cycle VOUT/VIN. To prevent large
voltage transients, a low ESR input capacitor sized for the
maximum RMS current must be used. The maximum
1773fb
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TheITH pinOPTI-LOOPcompensationcomponentscanbe
optimized to provide stable, high performance transient
response regardless of the output capacitors selected.
Run/Soft-Start Function
The RUN/SS pin is a dual purpose pin that provides the
soft-startfunctionandameanstoshutdowntheLTC1773.
Soft-start reduces surge currents from VIN by gradually
increasing the internal current limit. Power supply se-
quencing can also be accomplished using this pin.
Manufacturers such as Nichicon, United Chemicon and
Sanyoshouldbeconsideredforhighperformancethrough-
hole capacitors. The OS-CON semiconductor dielectric
capacitor available from Sanyo has the lowest ESR/size
ratio of any aluminum electrolytic at a somewhat higher
price. Once the ESR requirement for COUT has been met,
the RMS current rating generally far exceeds the
An internal 1.5µA current source charges up an external
capacitor CSS. When the voltage on RUN/SS reaches 0.7V
the LTC1773 begins operating. As the voltage on RUN/SS
continues to ramp from 0.7V to 1.8V, the ITH clamp is also
ramped at a proportionally linear rate. Depending on the
external RSENSE used, the peak inductor current, and thus
the internal current limit, rises with the RUN/SS voltage.
The output current thus ramps up slowly, charging the
output capacitor. If RUN/SS has been pulled all the way to
ground, there will be a delay before the current starts
increasing and is given by:
I
RIPPLE(P-P) requirement.
In surface mount applications multiple capacitors may
have to be paralleled to meet the ESR or RMS current
handling requirements of the application. Aluminum elec-
trolytic and dry tantalum capacitors are both available in
surfacemountconfigurations. Inthecaseoftantalum, itis
critical that the capacitors are surge tested for use in
switching power supplies. An excellent choice is the AVX
TPS series of surface mount tantalum, available in case
heights ranging from 2mm to 4mm. Other capacitor types
include Sanyo OS-CON and POSCAP, Nichicon PL series,
Panisonic SP series and Sprague 593D and 595D series.
Consult the manufacturer for other specific recommenda-
tions.
0.7CSS
tDELAY
=
= 0.47s /µF CSS
(
)
1.5µA
Pulling the RUN/SS pin below 0.4V puts the LTC1773 into
a low quiescent current shutdown mode (IQ < 10µA). This
pin can be driven directly from logic as shown in Figure 4.
Diode D1 in Figure 4 reduces the start delay but allows CSS
to ramp up slowly providing the soft-start function. This
diode can be deleted if soft-start is not needed.
Output Voltage Programming
The output voltage is set by a resistive divider according
to the following formula:
3.3V OR 5V
RUN/SS
RUN/SS
D1
⎛
⎞
R2
R1
VOUT = 0.8V 1+
(2)
⎜
⎟
C
SS
⎝
⎠
C
SS
The external resistive divider is connected to the output as
shown in Figure 3, allowing remote voltage sensing.
1773 F04
Figure 4. RUN/SS Pin Interfacing
0.8V ≤ V
≤ 8.5V
OUT
Auxiliary Winding Control Using SYNC/FCB Pin
R2
The SYNC/FCB pin can be used as a secondary feedback
to provide a means of regulating a flyback winding output.
When this pin drops below its ground referenced 0.8V
threshold, continuous mode operation is forced. In con-
tinuous mode, the P-channel main and N-channel syn-
chronous switches are switched continuously regardless
V
FB
LTC1773
R1
GND
1773 F03
Figure 3. Setting the LTC1773 Output Voltage
of the load on the main output.
1773fb
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Synchronous switching removes the normal limitation
that power must be drawn from the inductor primary
winding in order to extract power from auxiliary windings.
With continuous synchronous operation, power can be
drawn from the auxiliary windings without regard to the
primary output load.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
lossesinLTC1773circuits:VIN quiescentcurrent, external
power MOSFET gate charge current, I2R losses, and
topside MOSFET transition losses.
1. The VIN quiescent current is due to the DC bias current
as given in the electrical characteristics, it excludes
MOSFETdriverandcontrolcurrents.VIN currentresults
in a small loss which increases with VIN.
Thesecondaryoutputvoltageissetbytheturnsratioofthe
transformerinconjunctionwithapairofexternalresistors
returned to the SYNC/FCB pin as shown in Figure 5. The
secondary regulated voltage, VSEC, in Figure 5 is given by:
2. The external MOSFET gate charge current results from
switching the gate capacitance of the external power
MOSFET switches. Each time the gate is switched from
high to low to high again, a packet of charge dQ moves
from VIN to ground. The resulting dQ/dt is the current
out of VIN; it is typically larger than the DC bias current.
In continuous mode, IGATECHG = f(QT + QB) where QT
and QB are the gate charges of the external main and
synchronous switches. Both the DC bias and gate
charge losses are proportional to VIN and thus their
effects will be more pronounced at higher supply volt-
ages.
R4
R3
⎛
⎝
⎞
⎟
⎠
VSEC ≅ N + 1 V
− VDIODE > 0.8V 1+
(
)
⎜
OUT
where N is the turns ratio of the transformer and VOUT is
the main output voltage sensed by VFB.
V
V
IN
SEC
+
LTC1773
TG
L1
1:N
1µF
3. I2R losses are calculated from the resistances of the
R4
R3
V
OUT
SYNC/FCB
external RSENSE, the external power MOSFETs (RSW
)
SW
BG
and the external inductor (RL). In continuous mode, the
average output current flowing through inductor L is
“chopped” between the main switch and the synchro-
nous switch. Thus, the series resistance looking into
the SW pin from L is a function of both top and bottom
MOSFET RDS(ON) and the duty cycle (DC), as follows:
+
C
OUT
1773 F05
Figure 5. Secondary Output Loop Connection
RSW = (RDS(ON)TOP +RSENSE) • DC + RDS(ON)BOT • (1 – DC)
The RDS(ON) for both the top and bottom MOSFETs can
be obtained from the MOSFET manufactures’s
datasheets. Thus, to obtain I2R losses, simply add RSW
and RL together and multiply their sum by the square of
the average output current.
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
oftenusefultoanalyzeindividuallossestodeterminewhat
is limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
4. Transition losses apply to the topside MOSFET and
increase when operating at high input voltages and
higher operating frequencies. Transition losses can be
estimated from:
Efficiency = 100% – (L1 + L2 + L3 + ...)
whereL1, L2, etc. aretheindividuallossesasapercentage
of input power.
Transition Loss = 2(VIN)2IO(MAX) RSS
(f)
C
1773fb
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APPLICATIONS INFORMATION
Other losses including CIN and COUT ESR dissipative
losses, and inductor core losses, generally account for
less than 2% total additional loss.
bandwidth of the loop will be increased by decreasing CC.
If RC is increased by the same factor that CC is decreased,
the zero frequency will be kept the same, thereby keeping
the phase shift the same in the most critical frequency
range of the feedback loop. The output voltage settling
behavior is related to the stability of the closed-loop
system and will demonstrate the actual overall supply
performance. For a detailed explanation of optimizing the
compensation components, including a review of control
loop theory, refer to Application Note 76.
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
equal to (∆ILOAD)(ESR), where ESR is the effective series
resistance of COUT. ∆ILOAD also begins to charge or dis-
chargeCOUT, whichgeneratesafeedbackerrorsignal. The
regulator loop then returns VOUT to its steady-state value.
During this recovery time, VOUT can be monitored for
overshoot or ringing. OPTI-LOOP compensation allows
the transient response to be optimized over a wide range
of output capacitance and ESR values. The availability of
the ITH pin not only allows optimization of control loop
behavior but also provides a DC coupled and an AC filtered
closed-loop response test point. The DC step, rise time
and settling at this test point reflects the closed loop
response. Assuming a predominantly second order sys-
tem, phase margin and/or damping factor can be esti-
mated using the percentage of overshoot seen at this pin.
The bandwidth can also be estimated by examining the
rise time at the pin. The ITH external components shown in
the Figure 1 circuit will provide an adequate starting point
for most applications.
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
dischargedbypasscapacitorsareeffectivelyputinparallel
with COUT, causing a rapid drop in VOUT. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25)(CLOAD).
Thus a 10µF capacitor would require a 250µs rise time,
limiting the charging current to about 200mA.
Minimum On-Time Considerations
Minimum on-time, tON(MIN), is the smallest amount of
time that the LTC1773 is capable of turning the top
MOSFET on and off again. It is determined by internal
timing delays and the gate charge required to turn on the
top MOSFET. The minimum on-time for the LTC1773 is
about 250ns. Low duty cycle and high frequency synchro-
nous applications may approach this minimum on-time
limit and care should be taken to ensure that:
The ITH series RC-CC filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and the
particular output capacitor type and value have been
determined. The output capacitors need to be decided
upon because the various types and values determine the
loop feedback factor gain and phase. An output current
pulseof20%to100%offullloadcurrenthavingarisetime
of 1µs to 10µs will produce output voltage and ITH pin
waveforms that will give a sense of the overall loop
stability without breaking the feedback loop. The initial
outputvoltagestepmaynotbewithinthebandwidthofthe
feedback loop, so the standard second order overshoot/
DC ratio cannot be used to determine phase margin. The
gain of the loop will be increased by increasing RC, and the
VOUT
tON(MIN)
<
f •V
IN
Ifthedutycyclefallsbelowwhatcanbeaccommodatedby
the minimum on-time, the LTC1773 will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple current and ripple voltage will increase.
If an application can operate close to the minimum on-
time limit, an inductor must be chosen that has low
enough inductance to provide sufficient ripple amplitude
to meet the minimum on-time requirement. As a general
rule, keep the inductor ripple current equal or greater than
30% of the IOUT(MAX) at VIN(MAX).
1773fb
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PC Board Layout Checklist
Design Example
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1773. These items are also illustrated graphically in
the layout diagram of Figure 6. Check the following in your
layout:
As a design example, assume the LTC1773 is used in a
single lithium-ion battery powered cellular phone applica-
tion. The VIN will be operating from a maximum of 4.2V
down to about 2.7V. The load current requirement is a
maximum of 2A but most of the time it will be on standby
mode, requiring only 2mA. Efficiency at both low and high
load currents is important. Output voltage is 2.5V. With
this information we can calculate RSENSE to be around
33mΩ. For the inductor L, using equation (1),
1) Are the signal and power grounds segregated? The
LTC1773 signal ground consists of the resistive divider,
the compensation network and CSS. The power ground
consists of the (–) plate of CIN, the (–) plate of COUT, the
source of the external synchronous NMOS, and Pin 5 of
the LTC1773. The power ground traces should be kept
short, direct and wide. Connect the synchronous
MOSFETs source directly to the input capacitor ground.
⎛
⎞
1
VOUT
V
IN
L =
VOUT 1–
⎜
⎟
(3)
⎝
⎠
f ∆IL
( )(
)
Substituting VOUT = 2.5V, VIN = 4.2V, ∆IL = 800mA and
f = 550kHz in equation (3) gives:
2) Does the VFB pin connect directly to the feedback
resistors? The resistive divider of R1 and R2 must be
connectedbetweenthe(+)plateofCOUT andsignalground.
Be careful locating the feedback resistors too far away
from the LTC1773. The VFB line should not be routed close
to any other nodes with high slew rates.
⎛
⎞
2.5V
550kHz(800mA)
2.5V
4.2V
L =
1–
= 2.3µH
⎜
⎟
⎝
⎠
A 2.5µH inductor works well for this application. For good
efficiency choose a 4A inductor with less than 0.1Ω series
resistance.
3) Does the (+) terminal of CIN connect to VIN as closely as
possible? This capacitor provides the AC current to the
external power MOSFETs.
CIN will require an RMS current rating of at least 1A at
temperature and COUT will require an ESR of less than
0.066Ω. In most applications, the requirements for these
capacitors are fairly similar.
4) Keep the switching nodes SW, TG and BG away from
sensitive small-signal nodes, especially from the voltage
and current sensing feedback pins.
C
C2
+
C
C1
R
C
1
2
3
4
5
10
9
R
I
SW
SENSE
TH
+
RUN/SS SENSE–
LTC1773
SYNC/FCB
C
IN
D1
Q2
V
IN
8
C
SS
V
Q1
IN
R1
7
V
TG
BG
FB
–
6
GND
R2
–
BOLD LINES INDICATE
HIGH CURRENT PATHS
V
C
OUT
OUT
L1
+
+
1773 F06
Figure 6. LTC1773 Layout Diagram
1773fb
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APPLICATIONS INFORMATION
For the selection of the external MOSFETs, the RDS(ON)
must be guaranteed at 2.5V since the LTC1773 has to
operate down to 2.7V. This requirement can be met by the
Si9801DY.
⎛
⎞
VOUT
0.8
R2 =
– 1 R1= 171k;use 169k
⎜
⎟
⎝
⎠
Figure 7 shows the complete circuit along with its effi-
ciency curve.
Forthefeedbackresistors,chooseR1=80.6k.R2canthen
be calculated from equation (2) to be:
33pF
2.7V ≤ V ≤ 4.2V
IN
200pF
30k
1
2
3
4
5
10
9
I
SW
R
SENSE
0.033Ω
TH
RUN/SS SENSE–
LTC1773
V
2.5V
2A
OUT
8
0.1µF
V
IN
V
L1
2.5µH
SYNC/FCB
IN
7
V
TG
BG
FB
+
C
IN
150µF
6
GND
6.3V
+
C
OUT
Si9801DY
220µF
6.3V
169k
1%
80.6k
1%
C
C
: SANYO POSCAP 6TPA150M
IN
1773 F07a
: AVX TPSD227M006R0100
OUT
L1: CDRH5D28
R
: IRC LR1206-01-R033-F
SENSE
Figure 7. Single Lithium-Ion to 2.5V/2A Regulator
Efficiency Curve for Figure 7
100
V
= 2.5V
OUT
95
90
85
80
75
70
V
= 3.3V
IN
1
10
100
1000
5000
OUTPUT CURRENT (mA)
1773 F1b
1773fb
14
LTC1773
U
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33pF
2.7V ≤ V ≤ 8.4V
IN
200pF
MBR0530LT1
LTC1773
30k
1
V
OUT2
10
9
5V
I
SW
R
SENSE
TH
100mA
0.033Ω
2
+
+
RUN/SS SENSE–
22µF
L1
5µH
1:1
6.2V
0.1µF
3
4
5
8
V
SYNC/FCB
IN
422k
V
2.5V
2A
OUT1
7
+
C
V
TG
BG
IN
FB
100µF
6
10V
GND
80.6k
169k
1%
C
OUT
Si9801DY
220µF
6.3V
80.6k
1%
C
C
: SANYO POSCAP 10TPA100M
OUT
L1: COILTRONICS CTX5-4/BH ELECTRONICS 511-0033
R : IRC LR1206-01-R033-F
SENSE
IN
1773 TA01
: AVX TPSD227M006R0100
Figure 8. Dual Output 2.5V/2A and 5V/100mA Application
33pF
30k
2.7V ≤ V ≤ 5.5V
IN
200pF
LTC1773
1
10
9
I
R
SENSE
SW
TH
0.015Ω
2
3
4
5
RUN/SS SENSE–
V
Si9803DY
V
2.5V
5A
OUT
0.1µF
8
V
SYNC/FCB
IN
L1
2.8µH
IN
7
V
TG
+
FB
C
IN
150µF
Si9804DY
6
6.3V
GND
BG
+
C
OUT
220µF
6.3V
×3
169k
1%
80.6k
1%
C
C
: SANYO POSCAP 6TPA150M
: AVX TPSD227M006R0100
L1: TOKO D104C 919AS-2R8M
: DALE WSL-2010
IN
OUT
1773 TA02
R
SENSE
Figure 9. Single Lithium-Ion to 2.5V/5A Regulator
Efficiency Curve for Figure 9
100
95
V
IN
= 3.3V
90
85
80
75
70
65
60
V
= 5V
IN
1
10000
10
100
(mA)
1000
I
OUT
1773 • G17
1773fb
15
LTC1773
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TYPICAL APPLICATIONS
33pF
2.7V ≤ V ≤ 4.2V
IN
200pF
LTC1773
30k
1
2
3
4
5
10
9
R
I
SW
SENSE
TH
0.025Ω
RUN/SS SENSE–
Si9803DY
V
3.3V
1A
OUT
8
0.1µF
V
IN
L1
2µH
SYNC/FCB
V
IN
47µF
7
TG
BG
V
+
C
FB
IN
+
150µF
6
Si9804DY
6.3V
GND
+
C
OUT
220µF
6.3V
249k
1%
L1
2µH
80.6k
1%
C
C
: SANYO POSCAP 6TPA150M
IN
1773 TA03
: AVX TPSD227M006R0100
OUT
L1: COILTRONICS CTX2-4/BH ELECTRONICS 511-1010
R
: IRC LR1206-01-R033-F
SENSE
Figure 10. Single Lithium-Ion to 3.3V/1A Synchronous Zeta Converter
Efficiency Curve for Figure 10
100
V
= 5V
V
= 3.3V
IN
= 4V
OUT
V
90
80
70
60
50
40
30
20
IN
V
= 3.3V
IN
V
IN
= 2.7V
0.001
0.01
0.1
1.0
OUTPUT CURRENT (A)
1773 G18
1773fb
16
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U
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2.7V ≤ V ≤ 4.2V
IN
47pF
30k
LTC1773
1
2
3
4
5
10
9
I
R
SW
TH
SENSE
0.05Ω
220pF
RUN/SS SENSE–
V
2.5V
1A
OUT
0.1µF
8
750kHz CLK
V
SYNC/FCB
IN
C
L1
3µH
+
IN
47µF
7
6.3V
V
TG
BG
FB
6
100pF
GND
4.7µF
6.3V
169k
1%
Si6803DQ
C
100pF
+
OUT
80.6k
1%
47µF
0.1µF
6.3V
C
, C : SANYO POSCAP 6TPA47M
IN OUT
1773 TA06
L1: SUMIDA CDRH5D28 3R0
: IRC LR1206-01-R050-J
R
SENSE
Figure 11. 750kHz Single Lithium-Ion to 2.5V/1A Regulator
V
OUT3
2.5V
150mA
LT1762-2.5
1
2
8
5
IN
OUT
1µF
10µF
SENSE
0.01µF
3
V
1.8V
6A
OUT1
SHDN
BYP
GND
V
OUT2
3.3V
1A
47pF
3.3V ≤ V ≤ 6V
IN
220pF
30k
LTC1773
1
2
3
4
5
10
9
MBRM120T3
I
R
SENSE
0.01Ω
SW
TH
RUN/SS SENSE–
V
C
+
SEC
47µF
0.1µF
8
6.3V
+
C
SYNC/FCB
IN
IN
150µF
7
6.3V
V
TG
FB
249k
1%
T1
6
100pF
2.44µH
GND
BG
1:1
100k
1%
80.6k
1%
0.1µF
Si7540DP
C
OUT
100pF
+
680µF
4V
D2*
MBRS340T3
80.6k
1%
×2
1773 TA07
C
C
: PANASONIC SPECIAL POLYMER
IN
: KEMET T510687K004AS
OUT
*NOTE: D2 NOT NECESSARY.
IF REMOVED, EFFICIENCY DROPS BY 1%
T1: BH ELECTRONICS 510-1007
R
: IRC LR2512-01-R010-J
SENSE
C
SEC
: TAIYO YUDEN LMK432F476ZM
Figure 12. Triple Output 1.8V/6A, 2.5V/150mA,and 3.3V/1A Application
1773fb
17
LTC1773
U
TYPICAL APPLICATIONS
2.7V ≤ V ≤ 6V
IN
47pF
LTC1773
30k
1
10
9
I
TH
R
SENSE
0.068Ω
SW
D1
MMSD914T1
220pF
0.1µF
2
3
4
5
RUN/SS SENSE–
V
V
OUT
8
2V
C
SYNC/FCB
IN
L1
4.2µH
IN
+
800mA
47µF
7
6.3V
V
FB
TG
6
100pF
GND
BG
4.7µF
6.3V
118k
1%
Si9801DY
C
100pF
+
OUT
D2*
MBR0530LT1
80.6k
1%
47µF
0.1µF
6.3V
*NOTE: D2 NOT NECESSARY.
IF REMOVED, EFFICIENCY DROPS BY 1%
C
, C : SANYO POSCAP 6TPA47M
IN OUT
1773 TA05
L1: SUMIDA CDRH5D28 4R2
: IRC LR1206-01-R068-F
R
SENSE
Figure 13. Single Lithium-Ion to 2V/800mA Regulator with
Current Foldback
2.7V ≤ V ≤ 6V
IN
47pF
LTC1773
10
30k
1
2
3
4
5
I
R
SENSE
0.01Ω
SW
TH
220pF
9
8
7
6
RUN/SS SENSE–
V
V
1.8V
7A
OUT
0.1µF
+
C
SYNC/FCB
IN
L1
1µH
IN
150µF
6.3V
V
TG
FB
100pF
GND
BG
4.7µF
6.3V
100k
1%
0.1µF
Si7540DP
C
OUT
100pF
+
680µF
4V
80.6k
1%
D2*
MBRS340T3
×2
*NOTE: D2 NOT NECESSARY.
IF REMOVED, EFFICIENCY DROPS BY 1%
C
C
: PANASONIC SPECIAL POLYMER
IN
1773 TA08
: KEMET T510687K004AS
OUT
L1: TOKO TYPE D104C 919AS-1RON
R
: IRC LR2512-01-R010-J
SENSE
Figure 14. 3.3V to 1.8V/7A Regulator
1773fb
18
LTC1773
U
TYPICAL APPLICATIONS
33pF
4.5V ≤ V ≤ 5.5V
IN
200pF
LTC1773
30k
1
2
3
4
5
10
9
I
SW
R
SENSE
0.04Ω
TH
RUN/SS SENSE–
V
V
1.8V
2A
OUT
0.1µF
8
V
SYNC/FCB
IN
L1
2.5µH
IN
7
V
TG
FB
C
IN
47µF
6
10V
GND
BG
C
OUT
Si9942DY
47µF
10V
100k
1%
80.6k
1%
C
, C : TAIYO YUDEN LMK550BJ476MM
IN OUT
1773 TA09
L1: CDRH5D28
: IRC LR1206-01-R040-F
R
SENSE
Figure 15. 5V to 1.8V/2A Regulator with Ceramic Capacitors
U
PACKAGE DESCRIPTIO
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
0.889 ± 0.127
(.035 ± .005)
5.23
(.206)
MIN
3.20 – 3.45
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
(.126 – .136)
0.497 ± 0.076
(.0196 ± .003)
10 9
8
7 6
REF
0.50
(.0197)
BSC
0.305 ± 0.038
(.0120 ± .0015)
TYP
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
RECOMMENDED SOLDER PAD LAYOUT
DETAIL “A”
0.254
(.010)
0° – 6° TYP
1 2
3
4 5
GAUGE PLANE
0.86
(.034)
REF
1.10
(.043)
MAX
0.53 ± 0.152
(.021 ± .006)
DETAIL “A”
SEATING
PLANE
0.18
(.007)
0.17 – 0.27
(.007 – .011)
TYP
0.127 ± 0.076
(.005 ± .003)
MSOP (MS) 0603
0.50
(.0197)
BSC
NOTE:
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
1773fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
19
LTC1773
U
TYPICAL APPLICATIO
33pF
4.5V ≤ V ≤ 5.5V
IN
200pF
LTC1773
30k
V
OUT2
+
C
IN
1
2
3
4
5
10
9
R
SENSE
3.3V
I
SW
150µF
TH
0.050Ω
500mA
6.3V
RUN/SS SENSE–
L1
10µH
3:1
+
+
C
OUT2
Si2302DS
150µF
0.1µF
8
6.3V
V
V
IN
SYNC/FCB
IN
V
2.5V
1A
OUT1
7
V
TG
BG
FB
6
D1
GND
C
OUT1
Si6801DY
150µF
47k
6.3V
40.2k
1%
169k
1%
249k
1%
0.1µF
C
, C
SENSE
, C
: SANYO POSCAP 6TPA150M
IN OUT1 OUT2
1773 TA04
R
: IRC LR1206-01-R050-F
D1: BAS16
Figure 16. Dual Output Synchronous Buck Converter
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
V : 2V to 10V, 550kHz, Burst Mode Operation, Synchronizable
LTC1622
Low Voltage Current Mode Step-Down DC/DC Controller
IN
LTC1627/LTC1707 Low Voltage, Monolithic Synchronous Step-Down Regulator
Low Supply Voltage Range: 2.65V to 8V, I
to 0.5A
OUT
LTC1735
High Efficiency Synchronous Step-Down Switching Controller
High Efficiency Synchronous Step-Down Switching Controller
Burst Mode Operation, 16-Pin Narrow SO, Fault Protection
LTC1735-1
Output Fault Protection 16-Pin GN, Burst Mode Operation,
Power Good
LTC1771
LTC1772/B
LTC1778
LTC1779
LTC1877
LTC1878
LTC3404
Low Quiescent Current Step-Down DC/DC Controller
SOT-23 Low Voltage Step-Down Controller
V : 2.8V to 18V, 10µA I , MS8 Package
IN Q
6-Pin SOT-23, 2V ≤ V ≤ 10V, 550kHz
IN
Wide Operating Range/Step-Down Controller, No R
SOT-23 Current Mode Step-Down Converter
V up to 36V, Current Mode, Power Good
IN
SENSE
250mA Output Current, 2.5V ≤ V ≤ 9.8V, Up to 94% Efficiency
IN
High Efficiency Monolithic Synchronous Step-Down Regulator
High Efficiency Monolithic Synchronous Step-Down Regulator
1.4MHz Monolithic Synchronous Step-Down Regulator
V
V
from 2.65V to 10V, 10µA I , 550kHz, I
to 600mA,MS8
IN
IN
Q
OUT
from 2.65V to 7V, 10µA I , 550kHz, I
to 600mA,MS8
OUT
Q
Up to 95% Efficiency, I
= 600mA at V = 3.3V
IN
OUT
No Schottky Diode Required, 8-Lead MSOP
1773fb
LT 1106 REV B • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
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© LINEAR TECHNOLOGY CORPORATION 2006
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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