LTC1775CGN [Linear]
High Power No RSENSE TM Current Mode Synchronous Step-Down Switching Regulator; 高功率无检测电阻TM电流模式同步降压型开关稳压器
| 型号： | LTC1775CGN |
| 厂家： | 
Linear |
| 描述： | High Power No RSENSE TM Current Mode Synchronous Step-Down Switching Regulator |
| 文件： | 总24页 (文件大小：292K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1775
High Power
No R
TM Current Mode
SENSE
Synchronous Step-Down
Switching Regulator
U
DESCRIPTIO
FEATURES
The LTC®1775 is a synchronous step-down switching
regulator controller that drives external N-channel power
MOSFETs using few external components. Current mode
control with MOSFET VDS sensing eliminates the need for
a sense resistor and improves efficiency. Largely similar
to the LTC1625, the LTC1775 has twice the maximum
sensevoltageforhighcurrentapplications. Thefrequency
of a nominal 150kHz internal oscillator can be synchro-
nized to an external clock over a 1.5:1 frequency range.
Burst ModeTM operation at low load currents reduces
switchinglossesandlowdropoutoperationextendsoper-
ating time in battery-powered systems. A forced continu-
ous mode control pin can assist secondary winding
regulation by disabling Burst Mode operation when the
main output is lightly loaded.
■
Highest Efficiency Current Mode Controller
■
No Sense Resistor Required
■
300mV Maximum Current Sense Voltage
■
Stable High Current Operation
■
Dual N-Channel MOSFET Synchronous Drive
■
Wide VIN Range: 4V to 36V
■
Wide VOUT Range: 1.19V to VIN
■
±1% 1.19V Reference
■
Programmable Fixed Frequency with Injection Lock
■
Very Low Drop Out Operation: 99% Duty Cycle
■
Forced Continuous Mode Control Pin
■
Optional Programmable Soft Start
■
Pin Selectable Output Voltage
■
Foldback Current Limit
■
Output Overvoltage Protection
■
Logic Controlled Micropower Shutdown: IQ < 30µA
Fault protection is provided by foldback current limiting
and an output overvoltage comparator. An external ca-
pacitor attached to the RUN/SS pin provides soft start
capability for supply sequencing. A wide supply range
allowsoperationfrom4V(4.3VforLTC1775I)to36Vatthe
input and 1.19V to VIN at the output.
■
Available in 16-Lead Narrow SSOP and SO Packages
U
APPLICATIO S
■
Notebook Computers
■
Automotive Electronics
■
Battery Chargers
Distributed Power Systems
, LTC and LT are registered trademarks of Linear Technology Corporation.
No RSENSE and Burst Mode are trademarks of Linear Technology Corporation.
■
U
TYPICAL APPLICATION
Efficiency vs Load Current
100
LTC1775
V
IN
V
= 10V
f = 150kHz
FCB = INTV
IN
5V TO
28V
SYNC
V
IN
V
OUT
= 5V
C
IN
+
C
0.1µF
95
90
85
80
75
70
SS
TK
CC
22µF
30V
×4
M1
RUN/SS
TG
SUD50N03-10
L1
6µH
V
= 3.3V
OUT
V
3.3V
10A
OUT
V
SW
PROG
C
0.33µF
B
BOOST
+
C
OUT
D1
MBRS340
R
C
D
B
680µF
10k
CMDSH-3
6.3V
I
INTV
CC
TH
C
C
2.2nF
M2
SGND
BG
SUD50N03-10
+
C
VCC
4.7µF
V
PGND
OSENSE
1775 F01
0.01
0.1
1
10
LOAD CURRENT (A)
Figure 1. High Efficiency Step-Down Converter
1775 F01b
1
LTC1775
W W U W
U W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
ORDER PART
NUMBER
Input Supply Voltage (VIN, TK) ................. 36V to –0.3V
Boosted Supply Voltage (BOOST)............. 42V to –0.3V
Boosted Driver Voltage (BOOST – SW) ...... 7V to –0.3V
Switch Voltage (SW) ....................................36V to –5V
EXTVCC Voltage ...........................................7V to –0.3V
TOP VIEW
EXTV
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
IN
SYNC
RUN/SS
FCB
TK
LTC1775CGN
LTC1775CS
LTC1775IGN
LTC1775IS
SW
TG
I
TH Voltage................................................2.7V to –0.3V
I
BOOST
TH
FCB, RUN/SS, SYNC Voltages .....................7V to –0.3V
VOSENSE, VPROG Voltages ........(INTVCC + 0.3V) to –0.3V
Peak Driver Output Current < 10µs (TG, BG) ............ 2A
INTVCC Output Current ........................................ 50mA
Operating Ambient Temperature Range
SGND
INTV
CC
V
BG
OSENSE
GN PART MARKING
V
PGND
PROG
1775
1775I
GN PACKAGE
S PACKAGE
16-LEAD NARROW
PLASTIC SSOP
16-LEAD PLASTIC SO
LTC1775C .............................................. 0°C to 70°C
LTC1775I (Note 5).............................. –40°C to 85°C
Junction Temperature (Note 2)............................. 125°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
TJMAX = 125°C, θJA = 130°C/W (GN)
TJMAX = 125°C, θJA = 110°C/W (S)
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VIN = 15V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Main Control Loop
I V
IN OSENSE
Feedback Current
V
PROG
Pin Open, I = 1.19V (Note 3)
10
50
nA
TH
V
Regulated Output Voltage
1.19V (Adjustable) Selected
3.3V Selected
I
= 1.19V (Note 3)
TH
OUT
V
V
V
Pin Open
= 0V
●
●
●
1.178
3.220
4.900
1.190
3.300
5.000
1.202
3.380
5.100
V
V
V
PROG
PROG
PROG
5V Selected
= INTV
CC
V
V
V
Reference Voltage Line Regulation
V
V
= 4V to 20V, I = 1.19V (Note 3),
0.001
0.01
%/V
LINEREG
IN
TH
Pin Open
PROG
Output Voltage Load Regulation
I
I
= 2V (Note 3)
= 0.5V (Note 3)
●
●
– 0.020
0.035
–0.2
0.2
%
%
LOADREG
TH
TH
Forced Continuous Threshold
Forced Continuous Bias Current
Output Overvoltage Lockout
V
V
V
Ramping Negative
= 1.19V
●
1.16
1.24
1.19
–1
1.22
–2
V
µA
V
FCB
FCB
FCB
I
FCB
V
Pin Open
1.28
1.32
OVL
PROG
I
V
Input Current
PROG
PROG
3.3V V
V
PROG
V
PROG
= 0V
= 5V
–3.5
3.5
–7
7
µA
µA
OUT
5V V
OUT
I
Input DC Supply Current
Normal Mode
Q
EXTV = 5V (Note 4)
500
15
µA
µA
CC
Shutdown
V
= 0V, 4V < V < 15V
30
2
RUN/SS
IN
V
RUN/SS Pin Threshold
●
0.8
–1.2
260
1.4
–2.5
300
V
µA
RUN/SS
I
Soft Start Current Source
Maximum Current Sense Threshold
V
V
= 0V
–4
340
RUN/SS
RUN/SS
∆V
= 1V, V
Pin Open
PROG
mV
SENSE(MAX)
OSENSE
2
LTC1775
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VIN = 15V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
TG Transition Time
Rise Time
(Note 6)
TG t
TG t
C
C
= 3300pF
= 3300pF
50
50
150
150
ns
ns
R
F
LOAD
LOAD
Fall Time
BG Transition Time
Rise Time
(Note 6)
BG t
BG t
C
= 3300pF
= 3300pF
50
50
150
150
ns
ns
R
F
LOAD
LOAD
Fall Time
C
Internal V Regulator
CC
V
V
V
V
Internal V Voltage
6V < V < 30V, V = 4V
EXTVCC
●
●
5.0
5.2
–0.2
180
4.7
5.4
–1
V
%
INTVCC
LDOINT
LDOEXT
EXTVCC
CC
IN
INTV Load Regulation
I
I
I
= 20mA, V
= 20mA, V
= 20mA, V
= 4V
CC
CC
CC
CC
EXTVCC
EXTVCC
EXTVCC
EXTV Voltage Drop
= 5V
300
mV
V
CC
EXTV Switchover Voltage
Ramping Positive
4.5
CC
Oscillator
f
Oscillator Freqency
SYNC = 0V
135
150
1.5
0.9
50
165
1.2
kHz
OSC
f /f
Maximum Synchronized Frequency Ratio
SYNC Pin Threshold (Figure 4)
SYNC Pin Input Resistance
H
OSC
V
Ramping Positive
V
SYNC
R
kΩ
SYNC
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 4: Typical in application circuit with EXTV tied to V
= 5V,
OUT
CC
I
= 0A and FCB = INTV . Dynamic supply current is higher due
OUT CC
to the gate charge being delivered at the switching frequency. See
Applications Information.
Note 2: T is calculated from the ambient temperature T and power
J
A
dissipation P according to the following formula:
D
Note 5: Minimum input supply voltage is 4.3V at –40°C for industrial
grade parts.
Note 6: Rise and fall times are measured at 10% to 90% levels.
LTC1775CGN/LTC1775IGN: T = T + (P • 130°C/W)
J
A
D
LTC1775CS/LTC1775IS: T = T + (P • 110°C/W)
J
A
D
Note 3: The LTC1775 is tested in a feedback loop that adjusts V
to
OSENSE
achieve a specified error amplifier output voltage (I ).
TH
3
LTC1775
TYPICAL PERFOR A CE CHARACTERISTICS
U W
Efficiency vs Load Current
Efficiency vs Input Voltage
Efficiency vs Input Voltage
100
90
80
70
60
50
100
95
90
85
80
75
70
100
95
90
85
80
75
70
I
= 5A
LOAD
I
= 5A
LOAD
I
= 500mA
LOAD
I
= 500mA
LOAD
CONTINUOUS
MODE
BURST
MODE
V
V
= 10V
OUT
EXTV = V
CC
IN
= 5V
V
= 5V
V
= 3.3V
OUT
FIGURE 1 CIRCUIT
OUT
OUT
FIGURE 1 CIRCUIT
0.01
0.1
1.0
0
10
15
20 25 30
0.001
5
10
0
10
15
20
25
30
5
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
LOAD CURRENT (A)
1775 • G01
1775 • G02
1775 • G03
V
IN – VOUT Dropout Voltage
Load Regulation
ITH Pin Voltage vs Load Current
vs Load Current
3.0
2.5
2.0
1.5
1.0
0.5
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
400
300
200
100
0
FIGURE 1 CIRCUIT
FIGURE 1 CIRCUIT
OUT
FIGURE 1 CIRCUIT
V
V
= 20V
V
= 5V, 5% DROP
IN
OUT
= 5V
CONTINUOUS
MODE
BURST
MODE
8
12
14
0
2
4
6
10
0
2
4
6
8
10
4
6
8
0
2
10
LOAD CURRENT (A)
LOAD CURRENT (A)
CURRENT LOAD (A)
1775 • G05
1775 • G04
1775 • G06
Input and Shutdown Current
vs Input Voltage
EXTVCC Switch Drop
INTVCC Load Regulation
vs INTVCC Load Current
1.0
0.5
60
1200
1000
800
600
400
200
0
500
400
300
200
100
0
V
IN
= 15V
V
= 15V
IN
EXTV = 5V
CC
EXTV OPEN
CC
50
40
30
20
10
0
SHUTDOWN
0
EXTV = 5V
CC
–0.5
–1.0
10
20
30
40
0
20
INPUT VOLTAGE (V)
30
35
50
0
5
10
15
25
10
30
0
20
40
50
INTV LOAD CURRENT (mA)
INTV LOAD CURRENT (mA)
CC
CC
1775 • G08
1775 • G07
1775 • G09
4
LTC1775
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Maximum Current Sense Voltage
vs Temperature
Oscillator Frequency
vs Temperature
Maximum Current Sense Voltage
vs Duty Cycle
320
310
300
290
280
350
300
250
200
150
100
50
300
250
200
150
100
50
SYNC = 1.5V
SYNC = 0V
0
0
60
TEMPERATURE (°C)
110 135
0.2
0.4
DUTY CYCLE
0.8
1.0
–40 –15
10
35
85
0
0.6
60
110 135
–40 –15
10
35
85
TEMPERATURE (°C)
1775 • G11
1775 • G10
1775 • G12
RUN/SS Pin Current vs
Temperature
Soft Start
FCB Pin Current vs Temperature
0
–0.5
–1.0
–1.5
–2.0
0
–1
–2
–3
–4
–5
RUN/SS
5V/DIV
V
OUT
5V/DIV
I
L
5A/DIV
V
V
= 20V
20ms/DIV
60
TEMPERATURE (°C)
110 135
–40 –15
10
35
85
60
TEMPERATURE (°C)
110 135
IN
–40 –15
10
35
85
= 5V
OUT
R
LOAD
= 0.5Ω
1775 • G13
1775 • G14
FIGURE 1 CIRCUIT
1530 G16
Transient Response
(Burst Mode Operation)
Transient Response
Burst Mode Operation
V
OUT
V
V
OUT
100mV
/DIV
OUT
50mV
/DIV
100mV
/DIV
I
TH
100mV
/DIV
I
L
5A/DIV
I
L
I
L
5A/DIV
2A/DIV
V
V
I
= 20V
= 5V
LOAD
FIGURE 1 CIRCUIT
100µs/DIV
V
V
I
= 20V
= 5V
OUT
LOAD
FIGURE 1 CIRCUIT
200µs/DIV
V
V
I
= 20V
= 5V
LOAD
FIGURE 1 CIRCUIT
20µs/DIV
IN
OUT
IN
IN
OUT
= 2A TO 8A
= 100mA TO 2A
= 100mA
1530 G18
1530 G17
1530 G15
5
LTC1775
U
U
U
PI FU CTIO S
EXTVCC (Pin 1): INTVCC Switch Input. When the EXTVCC
voltage is above 4.7V, the switch closes and supplies
INTVCC power from EXTVCC. Do not exceed 7V at this pin.
Leaving VPROG open allows the output voltage to be set by
an external resistive divider between the output and
VOSENSE
.
SYNC (Pin 2): Synchronization Input for Internal Oscilla-
tor.Theoscillatorwillnominallyrunat150kHzwhenopen,
225kHz when tied above 1.2V, and will lock over a 1.5:1
clock frequency range.
PGND (Pin 9): Driver Power Ground. Connects to the
source of the bottom N-channel MOSFET, the (–) terminal
of CVCC and the (–) terminal of CIN.
BG (Pin 10): Bottom Gate Drive. Drives the gate of the
bottom N-channel MOSFET between ground and INTVCC.
RUN/SS (Pin 3): Run Control and Soft Start Input. A
capacitor to ground at this pin sets the ramp time to full
current output (approximately 1s/µF). Forcing this pin
below 1.4V shuts down the device.
INTVCC (Pin 11): Internal 5.2V Regulator Output. The
driver and control circuits are powered from this voltage.
Decouple this pin to power ground with a minimum of
4.7µF tantalum or other low ESR capacitor.
FCB (Pin 4): Forced Continuous Input. Tie this pin to
ground to force synchronous operation at low load
currents, to a resistive divider from the secondary output
when using a secondary winding, or to INTVCC to enable
Burst Mode operation at low load currents.
BOOST (Pin 12): Topside Floating Driver Supply. The (+)
terminalofthebootstrapcapacitorconnectshere.Thispin
swings from a Schottky diode drop below INTVCC to VIN +
INTVCC.
ITH (Pin 5): Error Amplifier Compensation Point. The
current comparator threshold increases with this control
voltage, forcing inductor current to be roughly propor-
tional to VITH. Nominal voltage range for this pin is 0V to
2.4V.
TG (Pin 13): Top Gate Drive. Drives the top N-channel
MOSFET with a voltage swing equal to INTVCC superim-
posed on the switch node voltage.
SW (Pin 14): Switch Node. The (–) terminal of the boot-
strap capacitor connects here. This pin swings from a
diode drop below ground up to VIN.
SGND (Pin 6): Signal Ground. Connect to the (–) terminal
of COUT
.
TK (Pin 15): Top MOSFET Kelvin Sense. MOSFET VDS
sensingrequiresthispintoberoutedtothedrainofthetop
MOSFET separately from VIN.
VOSENSE (Pin 7): Output Voltage Sense. Feedback input
from the remotely sensed output voltage or from an
external resistive divider across the output.
VIN (Pin 16): Main Supply Input. Decouple this pin to
ground with an RC filter (1Ω, 0.1µF) for applications
above 3A.
VPROG (Pin 8): Output Voltage Programming. When
VOSENSE is connected to the output, VPROG < 0.8V selects
a 3.3V output and VPROG > 3.5V selects a 5V output.
6
LTC1775
U
U
W
FU CTIO AL DIAGRA
TK
15
V
IN
SYNC
2
+
TA
×5.5
+
C
IN
–
–
INTV
INTV
CC
CC
BA
×5.5
0.95V
+
I
TH
5
+
0.7V
–
OSC
+
–
REV
R
C
I
2
+
–
S
Q
R
C
C1
TOP
I
1
I
THB
BOOST
12
+
–
0.5V
–
+
SLEEP
0.6V
C
B
B
TG
13
CL
SWITCH
LOGIC/
DROPOUT
COUNTER
M1
Ω
SW
14
g
= 1m
V
m
–
FB
INTV
CC
SHUTDOWN
D
B
EA
+
11
1.19V
+
OVERVOLTAGE
FCNT
+
0.6V
–
C
VCC
BG
10
V
IN
–
+
M2
3µA
PGND
9
RUN/SS
3
6V
C
SS
1.19V
REF
–
V
1.28V
IN
16
OV
+
5.2V
LDO REG
1.19V
+
–
4.7V
+
–
SGND
6
F
INTV
CC
1µA
L1
V
V
FCB
EXTV
CC
8
7
4
1
PROG
OSENSE
V
C
OUT
OUT
+
1775 BD
7
LTC1775
U
OPERATIO
Main Control Loop
will attempt to turn on the top MOSFET continuously
(‘’dropout’’). A dropout counter detects this condition and
forces the top MOSFET to turn off for about 500ns every
tenth cycle to recharge the bootstrap capacitor.
The LTC1775 is a constant frequency, current mode
controller for DC/DC step-down converters. In normal
operation, the top MOSFET is turned on when the RS latch
is set by the on-chip oscillator and is turned off when the
current comparator I1 resets the latch. While the top
MOSFET is turned off, the bottom MOSFET is turned on
until either the inductor current reverses, as determined
by the current reversal comparator I2, or the next cycle
begins. Inductor current is measured by sensing the VDS
potential across the conducting MOSFET. The output of
the appropriate sense amplifier (TA or BA) is selected by
the switch logic and applied to the current comparator.
The voltage on the ITH pin sets the comparator threshold
corresponding to peak inductor current. The error ampli-
fier EA adjusts this voltage by comparing the feedback
signal VFB from the output voltage with the internal 1.19V
reference. The VPROG pin selects whether the feedback
voltage is taken directly from the VOSENSE pin or is derived
from an on-chip resistive divider. When the load current
increases, it causes a drop in the feedback voltage relative
to the reference. The ITH voltage then rises until the
average inductor current again matches the load current.
An overvoltage comparator OV guards against transient
overshoots and other conditions that may overvoltage the
output. In this case, the top MOSFET is turned off and the
bottom MOSFET is turned on until the overvoltage condi-
tion is cleared.
Foldback current limiting for an output shorted to ground
is provided by a transconductance amplifer CL. As VFB
drops below 0.6V, the buffered ITH input to the current
comparator is gradually pulled down to a 0.95V clamp.
This reduces peak inductor current to about one fifth of its
maximum value.
Low Current Operation
The LTC1775 is capable of Burst Mode operation at low
load currents. If the error amplifier drives the ITH voltage
below 0.95V, the buffered ITH input to the current com-
paratorwillremainclampedat0.95V.Theinductorcurrent
peak is then held at approximately 60mV/RDS(ON)(TOP). If
ITH then drops below 0.5V, the Burst Mode comparator B
will turn off both MOSFETs. The load current will be
supplied solely by the output capacitor until ITH rises
above the 50mV hysteresis of the comparator and switch-
ing is resumed. Burst Mode operation is disabled by
comparator F when the FCB pin is brought below 1.19V.
This forces continuous operation and can assist second-
ary winding regulation.
The internal oscillator can be synchronized to an external
clock applied to the SYNC pin and can lock to a frequency
between 100% and 150% of its nominal 150kHz rate.
When the SYNC pin is left open, it is pulled low internally
and the oscillator runs at its normal rate. If this pin is taken
above 1.2V, the oscillator will run at its maximum 225kHz
rate.
Pulling the RUN/SS pin low forces the controller into its
shutdown state and turns off both MOSFETs. Releasing
the RUN/SS pin allows an internal 3µA current source to
charge up an external soft start capacitor CSS. When this
voltage reaches 1.4V, the controller begins switching, but
with the ITH voltage clamped at approximately 0.8V. As
CSS continuestocharge,theclampisraiseduntilfullrange
operation is restored.
INTVCC/EXTVCC Power
Power for the top and bottom MOSFET drivers and most
of the internal circuitry of the LTC1775 is derived from the
INTVCC pin. When the EXTVCC pin is left open, an internal
5.2V low dropout regulator supplies the INTVCC power
from VIN. If EXTVCC is raised above 4.7V, the internal
regulator is turned off and an internal switch connects
EXTVCC to INTVCC. This allows a high efficiency source,
suchastheprimaryorasecondaryoutputoftheconverter
itself, to provide the INTVCC power.
The top MOSFET driver is powered from a floating boot-
strap capacitor CB. This capacitor is normally recharged
from INTVCC through a diode DB when the top MOSFET is
turned off. As VIN decreases towards VOUT, the converter
8
LTC1775
W U U
APPLICATIO S I FOR ATIO
U
ThebasicLTC1775applicationcircuitisshowninFigure1.
External component selection is primarily determined by
themaximumloadcurrentandbeginswiththeselectionof
thesenseresistanceforthedesiredcurrentlevel.Sincethe
LTC1775 senses current using the on-resistance of the
power MOSFET, the maximum application current prima-
rily determines the choice of MOSFET. The operating
frequency and the inductor are chosen based largely on
the desired amount of ripple current. Finally, CIN is se-
lected for its ability to handle the RMS current into the
converter and COUT is chosen with low enough ESR to
meet the output voltage ripple specification.
The ρT is a normalized term accounting for the significant
variation in RDS(ON) with temperature, typically about
0.4%/°C as shown in Figure 2. Junction to ambient tem-
perature TJA is around 20°C in most applications. For a
maximumambienttemperatureof70°C, usingρ90°C 1.3
intheaboveequationisareasonablechoice.Thisequation
is plotted in Figure 3 to illustrate the dependence of
maximum output current on RDS(ON). Some popular
MOSFETs are shown as data points.
2.0
1.5
1.0
0.5
0
Power MOSFET Selection
The LTC1775 requires two external N-channel power
MOSFETs, one for the top (main) switch and one for the
bottom (synchronous) switch. Important parameters for
the power MOSFETs are the breakdown voltage V(BR)DSS
threshold voltage VGS(TH), on-resistance RDS(ON), reverse
transfer capacitance CRSS and maximum current ID(MAX)
,
.
50
100
–50
150
0
JUNCTION TEMPERATURE (°C)
The gate drive voltage is set by the 5.2V INTVCC supply.
Consequently, logic level threshold MOSFETs must be
used in LTC1775 applications. If low input voltage opera-
tion is expected (VIN < 5V), then sub-logic level threshold
MOSFETs should be used. Pay close attention to the
V(BR)DSS specification for the MOSFETs as well; many of
the logic level MOSFETs are limited to 30V or less.
1775 F02
Figure 2. RDS(ON) vs Temperature
25
20
15
10
5
IRL3803
The MOSFET on-resistance is chosen based on the
required load current. The maximum average output cur-
rent IO(MAX) is equal to the peak inductor current less half
the peak-to-peak ripple current ∆IL. The peak inductor
current is inherently limited in a current mode controller
by the current threshold ITH range. The corresponding
maximum VDS sense voltage is about 300mV under nor-
mal conditions. The LTC1775 will not allow peak inductor
current to exceed 300mV/RDS(ON)(TOP). The following
equation is a good guide for determining the required
RDS(ON)(MAX) at 25°C (manufacturer’s specification), al-
lowing some margin for ripple current, current limit and
variationsintheLTC1775andexternalcomponentvalues:
SUD50N03-10
FDS8936A
Si9936
0
0
0.02
0.04
0.06
0.08
0.10
R
(Ω)
DS(ON)
1775 F03
Figure 3. Maximum Output Current vs RDS(ON) at VGS = 4.5V
The 300mV maximum sense voltage of the LTC1775
allows a large current to be obtained from power MOSFET
switches. It also causes a significant amount of power
dissipationinthoseswitchesandcarefulattentionmustbe
240mV
RDS(ON)(MAX)
I
(
ρ
( )
)
O(MAX)
T
9
LTC1775
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APPLICATIO S I FOR ATIO
paid to the resulting thermal issues. Under DC conditions,
the maximum power that can be dissipated by a MOSFET
switch limits the current through it:
Operating Frequency and Synchronization
The choice of operating frequency and inductor value is a
trade-off between efficiency and component size. Low
frequency operation improves efficiency by reducing
MOSFET switching losses, both gate charge loss and
transition loss. However, lower frequency operation
requires more inductance for a given amount of ripple
current.
TJ(MAX) – TA
P
IDS(MAX)
=
=
RDS(ON)
θJA RDS(ON) ρTJ(MAX)
For example, the SUD50N03-10 with TJ(MAX) = 175°C,
TA =70°, θJA = 30° C/W, RDS(ON) = 0.019Ω, ρTJ(MAX) = 1.8
can operate with a maximum DC current of 10A. In a
switching application, the actual power dissipation is
increased by the transition losses and is reduced by the
switch duty cycle. When the LTC1775 is operating in
continuous mode, the duty cycles for the MOSFETs are:
The internal oscillator runs at a nominal 150kHz frequency
when the SYNC pin is left open or connected to ground.
Pulling the SYNC pin above 1.2V will increase the fre-
quency by 50%. The oscillator will injection lock to a clock
signal applied to the SYNC pin with a frequency between
165kHz and 200kHz. The clock high level must exceed
1.2V for at least 1µs and no longer than 4µs as shown in
Figure 4. The top MOSFET turn-on will synchronize with
the rising edge of the clock.
VOUT
TopDutyCycle =
VIN
VIN – VOUT
BottomDutyCycle =
VIN
1µs < t < 4µs
ON
7V
The MOSFET power dissipations at maximum output
current are:
1.2V
(IO(MAX)2)(ρT(TOP))(RDS(ON)
)
VOUT
V
IN
PTOP
=
2
1775 F04
+ (k)(V )(IO(MAX))(CRSS)(f)
IN
0
5µs < t < 6µs
Figure 4. SYNC Clock Waveform
(IO(MAX)2)(ρT(BOT))(RDS(ON)
)
VIN – VOUT
PBOT
=
VIN
Inductor Value Selection
Given the desired input and output voltages, the inductor
value and operating frequency directly determine the
ripple current:
Both MOSFETs have I2R losses and the PTOP equation
includesanadditionaltermfortransitionlosses, whichare
largest at high input voltages. The constant k = 1.7 can be
usedtoestimatetheamountoftransitionloss. Thebottom
MOSFETlossesaregreatestathighinputvoltageorduring
a short circuit when the duty cycle is nearly 100%. The
temperature rise of the MOSFETs depends on the effective
thermal resistance θJA of the heat sink used in the applica-
tion. Check the temperature of the MOSFET when testing
applications and use appropriate heat sinking such as
board power planes to spread the heat.
VOUT
(f)(L)
VOUT
V
IN
∆IL =
1–
Lower ripple current reduces losses in the inductor, ESR
losses in the output capacitors and output voltage ripple.
Thus, highest efficiency operation is obtained at low
frequency with small ripple current. To achieve this, how-
ever, requires a large inductor.
10
LTC1775
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A reasonable starting point is to choose a ripple current
that is about 40% of IO(MAX). Note that the largest ripple
current occurs at the highest VIN. To guarantee that ripple
current does not exceed a specified maximum, the induc-
tor should be chosen according to:
U
sense resistance determine the maximum allowed peak
inductor current. The corresponding output current limit
is:
300mV
1
ILIMIT
=
– ∆IL
2
R
ρ
( )
(
)
DS(ON)
T
VOUT
(f)(∆IL(MAX)
VOUT
V
IN(MAX)
The current limit value should be checked to ensure that
ILIMIT(MIN) > IO(MAX). The minimum value of current limit
generally occurs with the largest VIN at the highest ambi-
enttemperature,conditionswhichcausethehighestpower
dissipation in the top MOSFET. Note that it is important to
check for self-consistency between the assumed junction
temperature of the top MOSFET and the resulting value of
L ≥
1–
)
Burst Mode Operation Considerations
The choice of RDS(ON) and inductor value also determines
the load current at which the LTC1775 enters Burst Mode
operation. When bursting, the controller clamps the peak
inductor current to approximately:
I
LIMIT which heats the junction.
Caution should be used when setting the current limit
based upon RDS(ON) of the MOSFETs. The maximum
current limit is determined by the minimum MOSFET on-
resistance. Data sheets typically specify nominal and
maximum values for RDS(ON), but not a minimum. A
reasonable, but perhaps overly conservative, assumption
is that the minimum RDS(ON) lies the same amount below
the typical value as the maximum RDS(ON) lies above it.
Consult the MOSFET manufacturer for further guidelines.
60mV
RDS(ON)
IBURST(PEAK)
=
Thecorrespondingaveragecurrentdependsontheamount
of ripple current. Lower inductor values (higher ∆IL) will
reduce the load current at which Burst Mode operation
begins.
The output voltage ripple can increase during Burst Mode
operation if ∆IL is substantially less than IBURST. This will
primarily occur when the duty cycle is very close to unity
(VIN is close to VOUT) or if very large value inductors are
chosen. This is generally only a concern in applications
with VOUT ≥ 5V. At high duty cycles, a skipped cycle
causes the inductor current to quickly descend to zero.
However, it takes multiple cycles to ramp the current back
up to IBURST(PEAK). During this interval, the output capaci-
tor must supply the load current and enough charge may
be lost to cause significant droop in the output voltage. It
The LTC1775 includes current foldback to help further
limit load current when the output is shorted to ground. If
the output falls by more than half, then the maximum
sense voltage is progressively lowered from 300mV to
about 80mV. Under short-circuit conditions with very low
dutycycle, theLTC1775willbeginskippingcyclesinorder
to limit the short-circuit current. In this situation the
bottom MOSFET RDS(ON) will control the inductor current
valley rather than the top MOSFET controlling the inductor
current peak. The short-circuit ripple current is deter-
mined by the minimum on-time tON(MIN) of the LTC1775
(approximately 0.5µs), the input voltage, and inductor
value:
is a good idea to keep ∆IL comparable to IBURST(PEAK)
.
Otherwise, one might need to increase the output capaci-
tance in order to reduce the voltage ripple or else disable
Burst Mode operation by forcing continuous operation
with the FCB pin.
∆IL(SC) = tON(MIN) VIN/L.
The resulting short-circuit current is:
Fault Conditions: Current Limit and Output Shorts
80mV
1
ISC
=
+ ∆IL(SC)
The LTC1775 current comparator can accommodate a
maximum sense voltage of 300mV. This voltage and the
2
R
ρ
T
( )
(
)
DS(ON)(BOT)
11
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APPLICATIO S I FOR ATIO
Normally,thetopandbottomMOSFETswillbeofthesame
type. A bottom MOSFET with lower RDS(ON) than the top
may be chosen if the resulting increase in short-circuit
current is tolerable. However, the bottom MOSFET should
neverbechosentohaveahighernominalRDS(ON) thanthe
top MOSFET.
regulators. The diode may be omitted if the efficiency loss
can be tolerated.
Parasitic Lead Inductance Effects
Because the LTC1775 is designed to operate with rela-
tively large currents through single (or multiple) MOSFET
switches, theleadinductanceofthesepowerswitchescan
become a significant concern. The table below shows
typical values of lead inductance for some common pack-
ages:
Inductor Core Selection
Once the value for L is known, the type of inductor must be
selected. High efficiency converters generally cannot
affordthecorelossfoundinlowcostpowderedironcores,
forcing the use of more expensive ferrite, molypermalloy
or Kool Mµ® cores. Actual core loss is independent of core
size for a fixed inductor value, but it is very dependent on
the inductance selected. As inductance increases, core
losses go down. Unfortunately, increased inductance
requires more turns of wire and therefore copper losses
will increase.
MOSFET Package
TO-220
Lead Inductance
4nH to 12nH
4nH
DDPAK
DPAK
1.5nH
SO-8
1nH
Of particular concern are switches in TO-220 packages
which can have a series inductance of between 4nH and
12nH depending upon the depth of insertion into the
circuit board. When the main (top) switch is turned on, the
lead inductance LP forms a voltage divider with the power
inductor L1. The voltage VLP across this parasitic adds to
the voltage from the switch on-resistance and increases
the current sense voltage.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that induc-
tance collapses rapidly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
VLP = (VIN – VOUT)LP/L1
Molypermalloy (from Magnetics, Inc.) is a very good, low
losscorematerialfortoroids,butitismoreexpensivethan
ferrite. A reasonable compromise from the same manu-
facturer is Kool Mµ. Toroids are very space efficient,
especially when you can use several layers of wire.
Because they generally lack a bobbin, mounting is more
difficult. However, designsforsurfacemountareavailable
which do not increase the height significantly.
The result is lower value of current limit than would have
beenexpectedotherwise. Forexample, a10nHleadinduc-
tance with a 5µH power inductor has 50mV across it when
VIN = 30V and VOUT = 5V. Thus, the 300mV current limit
will be reached when the switch voltage due to on-
resistance is only 250mV, a 17% reduction. This effect is
most noticeable at higher input voltages.
Lead inductance also reduces the benefit of the Schottky
diode D1 by delaying commutation of the inductor current
from the diode over to the synchronous (bottom) switch.
With the diode forward biased when the synchronous
switch turns on, there is only about 500mV applied across
the lead and trace inductance between the switch and the
diode. It takes about 400ns to commutate a 20A current in
this case. This delay reduces efficiency and can also
increase the foldback current limit of the LTC1775. The
Schottky Diode Selection
The Schottky diode D1 shown in Figure 1 conducts during
the dead time between the conduction of the power
MOSFETs. This prevents the body diode of the bottom
MOSFET from turning on and storing charge during the
dead time, which could cost as much as 1% in efficiency.
A 1A Schottky diode is generally a good size for 3A to 5A
Kool Mµ is a registered trademark of Magnetics, Inc.
12
LTC1775
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Schottky diode must be placed next to the synchronous
switch to minimize this effect. One also might consider
usingapowerswitchwithanintegratedSchottkydiode, or
omitting the diode altogether in high current applications.
U
parallel with OS-CON capacitors is recommended to re-
duce the effect of their lead inductance.
In surface mount applications, multiple capacitors placed
in parallel may be required to meet the ESR, RMS current
handling and load step requirements. Dry tantalum, spe-
cial polymer and aluminum electrolytic capacitors are
available in surface mount packages. Special polymer
capacitors offer very low ESR but have lower capacitance
density than other types. Tantalum capacitors have the
highest capacitance density but it is important to only use
types that have been surge tested for use in switching
power supplies. Several excellent surge-tested choices
are the AVX TPS and TPSV or the KEMET T510 series.
Aluminumelectrolyticcapacitorshavesignificantlyhigher
ESR,butcanbeusedincost-drivenapplicationsproviding
that consideration is given to ripple current ratings and
longtermreliability.OthercapacitortypesincludeNichicon
PL, NEC Neocap, Panasonic SP and Sprague 595D series.
CIN and COUT Selection
In continuous mode, the drain current of the top MOSFET
is approximately a square wave of duty cycle VOUT/VIN. To
prevent large input voltage transients, a low ESR input
capacitor sized for the maximum RMS current must be
used. The maximum RMS current is given by:
1/2
VOUT
V
IN
V
IN
VOUT
IRMS IO(MAX)
−1
This formula has a maximum at VIN = 2VOUT, where IRMS
= IO(MAX)/2. This simple worst-case condition is com-
monlyusedfordesignbecauseevensignificantdeviations
do not offer much relief. Note that ripple current ratings
from capacitor manufacturers are often based on only
2000hoursoflife.Thismakesitadvisabletofurtherderate
the capacitor or to choose a capacitor rated at a higher
temperaturethanrequired.Severalcapacitorsmayalsobe
placedinparalleltomeetsizeorheightrequirementsinthe
design.
INTVCC Regulator
An internal P-channel low dropout regulator produces the
5.2V supply which powers the drivers and internal cir-
cuitry within the LTC1775. The INTVCC pin can supply a
maximum RMS current of 50mA and must be bypassed to
ground with a minimum of 4.7µF tantalum or low ESR
electrolytic capacitance. Good bypassing is necessary to
supplythehightransientcurrentsrequiredbytheMOSFET
gate drivers.
The selection of COUT is primarily determined by the ESR
required to minimize voltage ripple. The output ripple
∆VOUT is approximately bounded by:
High input voltage applications in which large MOSFETs
arebeingdrivenathighfrequenciesmaycausetheLTC1775
to exceed its maximum junction temperature rating. Most
of the supply current drives the MOSFET gates unless an
external EXTVCC source is used. The junction temperature
can be estimated from the equations given in Note 2 of the
Electrical Characteristics. For example, the LTC1775CGN
is limited to less than 14mA from a 30V supply:
1
∆VOUT ≤ ∆IL ESR +
(8)(f)(COUT
)
Since ∆IL increases with input voltage, the output ripple is
highestatmaximuminputvoltage.Typically,oncetheESR
requirement is satisfied the capacitance is adequate for
filtering and has the required RMS current rating.
Manufacturers such as Nichicon, United Chemicon and
Sanyoshouldbeconsideredforhighperformancethrough-
hole capacitors. The OS-CON (organic semiconductor
dielectric) capacitor available from Sanyo has the lowest
product of ESR and size of any aluminum electrolytic at a
somewhathigherprice. Anadditionalceramiccapacitorin
TJ = 70°C + (14mA)(30V)(130°C/W) = 125°C
Topreventthemaximumjunctiontemperaturefrombeing
exceeded, the input supply current must be checked when
operating in continuous mode at high VIN. Relief can be
provided by using the EXTVCC pin to provide the gate drive
current.
13
LTC1775
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APPLICATIO S I FOR ATIO
EXTVCC Connection
V
≈ 2(V
– V ) < 7V
OUT D
PUMP
+
1µF
V
C
The LTC1775 contains an internal P-channel MOSFET
switch connected between the EXTVCC and INTVCC pins.
Whenever the EXTVCC pin is above 4.7V the internal 5.2V
regulator shuts off, the switch closes and INTVCC power is
supplied via EXTVCC until EXTVCC drops below 4.5V. This
allows the MOSFET gate drive and control power to be
derived from the output or other external source during
normal operation. When the output is out of regulation
(start-up,shortcircuit)powerissuppliedfromtheinternal
regulator. Do not apply greater than 7V to the EXTVCC pin
and ensure that EXTVCC ≤ VIN.
IN
+
BAT85
BAT85
IN
V
IN
BAT85
L1
0.22µF
TK
TG
LTC1775
VN2222LL
SW
EXTV
CC
V
OUT
+
C
OUT
BG
PGND
1775 F05b
Figure 5b: Capacitive Charge Pump for EXTVCC
Significant efficiency gains can be realized by powering
INTVCC from the output, since the VIN current supplying
the driver and control currents will be scaled by a factor of
DutyCycle/Efficiency.For5Vregulatorsthissimplymeans
connecting the EXTVCC pin directly to VOUT. However, for
3.3V and other lower voltage regulators, additional cir-
cuitry is required to derive INTVCC power from the output.
3. EXTVCC connectedtoanoutput-derivedboostnetwork.
For 3.3V and other low voltage regulators, efficiency
gains can still be realized by connecting EXTVCC to an
output-derived voltage which has been boosted to
greater than 4.7V. This can be done with either an
inductive boost winding as shown in Figure 5a or a
capacitive charge pump as shown in Figure 5b.
The following list summarizes the four possible connec-
tions for EXTVCC:
4. EXTVCC connected to an external supply. If an external
supply is available in the 5V to 7V range (EXTVCC < VIN),
it may be used to power EXTVCC.
1. EXTVCC left open (or grounded). This will cause INTVCC
tobepoweredfromtheinternal5.2Vregulatorresulting
in a low current efficiency penalty of up to 10% at high
input voltages.
Figure 6 shows how one can easily generate a suitable
EXTVCC voltage from VIN. This circuit still derives the gate
drive current from VIN, but it removes the power dissipa-
tionfromtheLTC1775internalregulatorandincreasesthe
gate drive voltage.
2. EXTVCC connected directly to VOUT. This is the normal
connection for a 5V regulator and provides the highest
efficiency.
V
IN
V
C
IN
+
R1
V
IN
SEC
V
IN
Q1
TK
1N4148
D1
6.8V
EXTV
TG
CC
•
OPTIONAL
EXTV
+
LTC1775
EXTV
1775 F06
C
SEC
CC
SW
1µF
CC
CONNECTION
5V < V < 7V
V
OUT
R4
R3
•
Figure 6. EXTVCC Power Supplied from VIN
SEC
T1
1:N
+
C
FCB
OUT
Note that RDS(ON) also varies with the gate drive level. If
gate drives other than the 5.2V INTVCC are used, this must
BG
SGND
PGND
1775 F05a
be accounted for when selecting the MOSFET RDS(ON)
.
Particular care should be taken with applications where
EXTVCC is connected to the output. When the output
Figure 5a: Secondary Output Loop and EXTVCC Connection
14
LTC1775
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APPLICATIO S I FOR ATIO
U
voltage is between 4.7V and 5.2V, INTVCC will be con-
nected to the output and the gate drive is reduced. The
resulting increase in RDS(ON) will also lower the current
limit. Even applications with VOUT > 5.2V will traverse this
region during start-up and must take into account the
reduced current limit.
reduce the signal swing at the gate by a diode drop. Thus,
the LTC1775 requires an increased EXTVCC voltage of
about 6V (such as provided by the Figure 6 circuit) when
using this driver.
Output Voltage Programming
The LTC1775 has a pin selectable output voltage deter-
mined by the VPROG pin as follows:
Topside MOSFET Driver Supply (CB, DB)
An external bootstrap capacitor (CB in the functional dia-
gram) connected to the BOOST pin supplies the gate drive
voltage for the topside MOSFET. This capacitor is charged
through diode DB from INTVCC when the SW node is low.
NotethatthevoltageacrossCB isaboutadiodedropbelow
INTVCC. When the top MOSFET turns on, the switch node
voltage rises to VIN and the BOOST pin rises to approxi-
mately VIN + INTVCC. During dropout operation, CB sup-
plies the top driver for as long as ten cycles between re-
freshes. Thus, the boost capacitance needs to store about
100 times the gate charge required by the top MOSFET. In
many applications 0.1µF to 0.47µF is adequate.
V
V
OUT
PROG
0V
3.3V
5V
INTV
CC
Open
Adjustable
Remote sensing of the output voltage is provided by the
VOSENSE pin. For fixed 3.3V and 5V output applications an
internal resistive divider is used and the VOSENSE pin is
connected directly to the output voltage as shown in
Figure 8a. When using an external resistive divider, the
VPROG pin is left open and the VOSENSE pin is connected to
feedback resistors as shown in Figure 8b. The output
voltage is set by the divider as:
When adjusting the gate drive level , the final arbiter is the
total input current for the regulator. If you make a change
and the input current decreases, then you improved the
efficiency. If there is no change in input current, then there
is no change in efficiency.
R2
VOUT = 1.19V 1+
R1
CONNECT FOR
External Gate Drive Buffer
LTC1775
V
= 5V
OUT
V
V
INTV
CC
PROG
CONNECT FOR
= 3.3V
The LTC1775 drivers are adequate for driving up to about
30nC into MOSFET switches. When using large single, or
multiple, MOSFET switches, external buffers may be re-
quired to provide additional gate drive capability. Special
purpose gate driver circuits such as the LTC1693 are ideal
insuchcases.Alternately,theexternalbuffercircuitshown
in Figure 7 can be used. Note that the bipolar devices
V
OUT
V
OSENSE
OUT
+
C
OUT
SGND
1775 F08a
Figure 8a. Fixed 3.3V or 5V VOUT
BOOST
INTV
CC
V
OUT
LTC1775
OPEN
V
V
PROG
Q1
Q3
FMMT619
FMMT619
R2
R1
GATE
OF M1
GATE
OF M2
+
TG
BG
C
OUT
OSENSE
Q2
FMMT720
Q4
FMMT720
SGND
SW
PGND
1775 F07
1775 F08b
Figure 7. Optional External Gate Driver
Figure 8b. Adjustable VOUT
15
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Run/Soft Start Function
In addition to providing a logic input to force continuous
operation, the FCB pin provides a means to regulate a
flyback winding output. It can force continuous synchro-
nous operation when needed by the flyback winding,
regardless of the main output load.
The RUN/SS pin is a dual purpose pin that provides a soft
startfunctionandameanstoshutdowntheLTC1775.Soft
start reduces surge currents from VIN by gradually in-
creasing the controller’s current limit ITH(MAX). This pin
can also be used for power supply sequencing.
The secondary output voltage VSEC is normally set as
shown in Figure 5a by the turns ratio N of the transformer:
Pulling the RUN/SS pin below 1.4V puts the LTC1775 into
alowquiescentcurrentshutdown(IQ<30µA).Thispincan
be driven directly from logic as shown in Figure 9. Releas-
ing the RUN/SS pin allows an internal 3µA current source
to charge up the soft-start capacitor CSS. If RUN/SS has
been pulled all the way to ground there is a delay before
starting of approximately:
VSEC (N + 1)VOUT
However, if the controller goes into Burst Mode operation
and halts switching due to a light main load current, then
VSEC will droop. An external resistor divider from VSEC to
the FCB pin sets a minimum voltage VSEC(MIN)
:
R4
VSEC(MIN) 1.19V 1+
R3
1.4V
3µA
tDELAY
=
CSS = 0.5s /µF C
SS
(
)
If VSEC drops below this level, the FCB voltage forces
continuous operation until VSEC is again above its
minimum.
When the voltage on RUN/SS reaches 1.4V the LTC1775
begins operating with a clamp on ITH at 0.8V. As the
voltage on RUN/SS increases to approximately 3.1V, the
clamp on ITH is raised until its full 2.4V range is restored.
This takes an additional 0.5s/µF. During this time the load
currentwillbefoldedbacktoapproximately80mV/RDS(ON)
until the output reaches half of its final value.
Minimum On-Time Considerations
Minimum on-time tON(MIN) is the smallest amount of time
that the LTC1775 is capable of turning the top MOSFET on
and off again. It is determined by internal timing delays and
the amount of gate charge required to turn on the top
MOSFET. Low duty cycle applications may approach this
minimum on-time limit and care should be taken to ensure
that:
Diode D1 in Figure 9 reduces the start delay while allowing
CSS to charge up slowly for the soft start function. This
diodeandCSS canbedeletedifsoftstartisnotneeded.The
RUN/SS pin has an internal 6V zener clamp (See Func-
tional Diagram).
VOUT
(V )(f)
IN
3.3V
OR 5V
tON(MIN)
<
RUN/SS
RUN/SS
D1
Ifthedutycyclefallsbelowwhatcanbeaccommodatedby
the minimum on-time, the LTC1775 will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple current and ripple voltage will increase.
C
SS
C
SS
1775 F09
Figure 9. RUN/SS Pin Interfacing
Theminimumon-timefortheLTC1775isgenerallyabout
0.5µs. However, as the peak sense voltage (IL(PEAK) •
RDS(ON)) decreases, the minimum on-time gradually
increases up to about 0.7µs. This is of particular concern
in forced continuous applications with low ripple current
at light loads. If the duty cycle drops below the minimum
on-time limit in this situation, a significant amount of
FCB Pin Operation
When the FCB pin drops below its 1.19V threshold,
continuous synchronous operation is forced. In this case,
the top and bottom MOSFETs continue to be driven
regardless of the load on the main output. Burst Mode
operation is disabled and current reversal under light
loads is allowed in the inductor.
16
LTC1775
W U U
APPLICATIO S I FOR ATIO
U
cycle skipping can occur with correspondingly larger
losses ranging from 2% to 8% as the output current
increases from 0.5A to 2A for a 5V output. I2R losses
cause the efficiency to drop at high output currents.
current and voltage ripple.
Efficiency Considerations
3. Transition losses apply only to the topside MOSFET,
and only when operating at high input voltages (typi-
cally 20V or greater). Transition losses can be esti-
mated from:
The efficiency of a switching regulator is equal to the
output power divided by the input power (×100%). Per-
cent efficiency can be expressed as:
Transition Loss = (1.7)(VIN2)(IO(MAX))(CRSS)(f)
%Efficiency = 100% – (L1 + L2 + L3 + ...)
whereL1, L2, etc. aretheindividuallossesasapercentage
of input power. It is often useful to analyze individual
losses to determine what is limiting the efficiency and
which change would produce the most improvement.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC1775 circuits:
4. LTC1775 VIN supply current. The VIN current is the DC
supplycurrenttothecontrollerexcludingMOSFETgate
drive current. Total supply current is typically about
850µA. If EXTVCC is connected to 5V, the LTC1775 will
drawonly330µAfromVIN andtheremaining520µAwill
come from EXTVCC. VIN current results in a small
(<1%) loss which increases with VIN.
1. INTVCC current. This is the sum of the MOSFET driver
and control currents. The driver current results from
switching the gate capacitance of the power MOSFETs.
Each time a MOSFET gate is switched on and then off,
a packet of gate charge Qg moves from INTVCC to
ground. The resulting current out of INTVCC is typically
much larger than the control circuit current. In continu-
ous mode, IGATECHG = f(Qg(TOP) + Qg(BOT)).
Other losses including CIN and COUT ESR dissipative
losses, Schottky conduction losses during dead time and
inductor core losses, generally account for less than 2%
total additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
equal to (∆ILOAD)(ESR), where ESR is the effective series
resistance of COUT, and COUT begins to charge or dis-
charge. The regulator loop acts on the resulting feedback
errorsignaltoreturnVOUT toitssteady-statevalue. During
this recovery time VOUT can be monitored for overshoot or
ringing which would indicate a stability problem. The ITH
pin external components shown in Figure 1 will provide
adequate compensation for most applications.
By powering EXTVCC from an output-derived source,
the additional VIN current resulting from the driver and
control currents will be scaled by a factor of Duty Cycle/
Efficiency. For example, in a 20V to 5V application at
400mA load, 10mA of INTVCC current results in ap-
proximately 3mA of VIN current. This reduces the loss
from 10% (if the driver was powered directly from VIN)
to about 3%.
2. DC I2R Losses. Since there is no separate sense resis-
tor, DC I2R losses arise only from the resistances of the
MOSFETs and inductor. In continuous mode the aver-
age output current flows through L, but is “chopped”
between the top MOSFET and the bottom MOSFET. If
A second, more severe transient is caused by connecting
loads with large (>1µF) supply bypass capacitors. The
dischargedbypasscapacitorsareeffectivelyputinparallel
with COUT, causing a rapid drop in VOUT. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive in order
to limit the inrush current to the load.
thetwoMOSFETshaveapproximatelythesameRDS(ON)
,
then the resistance of one MOSFET can simply be
summed with the resistance of L to obtain the DC I2R
loss. For example, if each RDS(ON) = 0.05Ω and RL =
0.15Ω, then the total resistance is 0.2Ω. This results in
17
LTC1775
W U U
U
APPLICATIO S I FOR ATIO
Automotive Considerations: Plugging into the
Design Example
Cigarette Lighter
As a design example, take a supply with the following
specifications: VIN = 6V to 22V (15V nominal), VOUT = 5V,
As battery-powered devices go mobile, there is a natural
interest in plugging into the cigarette lighter in order to
conserve or even recharge battery packs during opera-
tion. But before you connect, be advised: you are plug-
ging into the supply from hell. The main power line in an
automobile is the source of a number of nasty potential
transients, including load dump, reverse and double
battery.
I
O(MAX) = 10A. The required RDS(ON) can immediately be
estimated:
240mV
(10A)(1.3)
RDS(ON)
=
= 0.018Ω
A 0.019Ω Siliconix SUD50N03-10 MOSFET (θJA
30°C/W) is close to this value.
=
Load dump is the result of a loose battery cable. When the
cablebreaksconnection,thefieldcollapseinthealternator
can cause a positive spike as high as 60V which takes
several hundred milliseconds to decay. Reverse battery is
just what it says, while double battery is a consequence of
tow truck operators finding that a 24V jump start cranks
cold engines faster than 12V.
For 40% ripple current at maximum VIN the inductor
should be:
5V
5V
22V
L ≥
1–
= 6.4µH
(150kHz)(0.4)(10A)
Choosing a Magnetics 55380-A2 core with 8 turns of 15
gauge wire yields a 6µH inductor. The resulting maximum
ripple current will be:
The network shown in Figure 10 is the most straightfor-
ward approach to protect a DC/DC converter from the
ravages of an automotive power line. The series diode
prevents current from flowing during reverse battery,
while the transient suppressor clamps the input voltage
during load dump. Note that the transient suppressor
should not conduct during double-battery operation, but
must still clamp the input voltage below breakdown of the
converter. Although the LTC1775 has a maximum input
voltage of 36V, most applications will be limited to 30V by
5V
5V
22V
∆IL(MAX)
=
1–
= 4.3A
(150kHz)(6µH)
Next, check that the minimum value of the current limit is
acceptable. Assume a junction temperature about 20°C
above the 70°C ambient with ρ90°C = 1.3.
300mV
(0.019Ω)(1.3)
1
2
the MOSFET V(BR)DSS
.
ILIMIT
≥
–
4.3A =10A
Now double-check the assumed TJ:
50A I
12V
PK
2
RATING
5V
22V
PTOP
=
10A 1.3 0.019Ω +
(
) ( )(
)
V
IN
TRANSIENT VOLTAGE
SUPPRESSOR
GENERAL INSTRUMENT
1.5KA24A
2
LTC1775
1.7 22V 10A 170pF 150kHz
(
)(
) (
)(
)(
)
= 0.56W + 0.21W = 0.77mW
PGND
1775 F10
TJ = 70°C + (0.77W)(30°C/W) = 93°C
Since ρ(93°C) ρ(90°C), the solution is self-consistent.
Figure 10. Automotive Application Protection
18
LTC1775
W U U
APPLICATIO S I FOR ATIO
U
A short circuit to ground will result in a folded back
CIN is chosen for an RMS current rating of at least 5A at
temperature. COUT is chosen with an ESR of 0.013Ω for
low output ripple. The output ripple in continuous mode
will be highest at the maximum input voltage and is
approximately:
current of:
80mV
1 (15V)(0.5µs)
ISC
=
+
= 6.2A
(0.013Ω)(1.1)
2
6µH
∆VO = (∆IL(MAX))(ESR) = (4.3A)(0.013Ω) = 56mV
with a typical value of RDS(ON) and ρ(50°C) = 1.1. The
resulting power dissipated in the bottom MOSFET is:
The complete circuit is shown in Figure 11.
15V –5V
PBOT
=
(6.2A)2(1.1)(0.013Ω) =0.37W
15V
which is less than under full load conditions.
V
IN
6V TO 22V
R
F
1Ω
C
IN
LTC1775
+
+
C
1
16
22µF
30V
×4
F
V
EXTV
V
IN
OUT
CC
0.1µF
2
3
15
14
M1
SUD50N03-10
SYNC
TK
L1
6µH
RUN/SS
SW
V
OUT
4
5
13
12
C
C
C1
SS
INTV
5V
FCB
TG
R
CC
C
2.2nF
0.1µF
10A
10k
I
BOOST
TH
D1
MBRS340
C
C2
D
B
C
B
220pF
CMDSH-3
6
11
0.33µF
SGND
INTV
CC
+
C
OUT
680µF
7
8
10
9
M2
SUD50N03-10
6.3V
V
V
BG
OSENSE
+
C
VCC
PGND
PROG
4.7µF
1775 F11
C
C
: SANYO 30SC22M
OUT
L1: MAGENTICS 55380-A2, 8 TURNS, 15 GAUGE
IN
: SANYO 6SP680M
Figure 11. 5V/10A Fixed Output from Design Example
19
LTC1775
W U U
U
APPLICATIO S I FOR ATIO
4) Keep the switch node SW away from sensitive small-
signal nodes. Ideally the switch node should be placed
on the opposite side of the power MOSFETs from the
LTC1775.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1775. These items are also illustrated graphically in
the layout diagram of Figure 12. Check the following in
your layout:
5) Connect the INTVCC decoupling capacitor CVCC closely
to the INTVCC pin and the power ground pin. This
capacitor carries the MOSFET gate drive current.
1) Connect the TK lead directly to the drain of the topside
MOSFET. Then connect the drain to the (+) plate of CIN.
This capacitor provides the AC current to the top
MOSFET.
6) Does the VOSENSE pin connect as close as possible to
the load? In adjustable applications, the resistive di-
vider (R1, R2) must be connected between the load and
signal ground. Place the divider near the LTC1775 in
order to keep the high impedance VOSENSE node short.
2) Thepowergroundpinconnectsdirectlytothesourceof
thebottomN-channelMOSFET.Thenconnectthesource
totheanodeoftheSchottkydiode(ifused)and(–)plate
of CIN, which should have as short lead lengths as
possible.
7) For applications with multiple switching power con-
vertersconnectedtothesameVIN, ensurethattheinput
filtercapacitancefortheLTC1775isnotsharedwiththe
other converters. AC input current from another con-
verter will cause substantial input voltage ripple that
may interfere with proper operation of the LTC1775. A
few inches of PC trace or wire (LTRACE ≈ 100nH)
between CIN and the VIN supply is sufficient to prevent
sharing.
3) The LTC1775 signal ground pin should connect to the
(–)plateofCOUT. Connectthe(–)plateofCOUT topower
ground at the source of the bottom MOSFET. All small-
signal components (R2, CSS, CC, etc.) should return
directly to SGND.
L
TRACE
OPTIONAL 5V EXTV
CC
+
LTC1775
CC
CONNECTION
16
1
EXTV
V
IN
2
3
15
14
EXT
CLK
C
SS
SYNC
TK
M1
RUN/SS
SW
L1
4
5
13
12
INTV
FCB
TG
CC
C
C
V
C1
B
IN
R
C
I
BOOST
TH
C
D
VCC
B
6
11
SGND
INTV
CC
+
+
R2
7
8
10
9
D1
M2
C
V
BG
IN
OSENSE
OPEN
V
PGND
–
–
PROG
R1
OUTPUT DIVIDER
REQUIRED
V
OUT
C
OUT
+
WITH V
OPEN
PROG
+
1775 F12
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 12. LTC1775 Layout Diagram
20
LTC1775
U
TYPICAL APPLICATIO S
3.3V/5A Fixed Output
V
IN
5V TO 28V
R
F
1Ω
C
IN
LTC1775
CC
+
C
F
1
16
22µF
30V
×2
0.1µF
EXTV
V
IN
2
3
15
14
M1
Si4412DY
SYNC
TK
L1
10µH
RUN/SS
SW
C
C1
2.2nF
V
3.3V
5A
OUT
4
5
13
12
C
R
SS
0.1µF
C
INTV
FCB
TG
CC
10k
I
TH
BOOST
D1
C
C2
220pF
D
B
CMDSH-3
C
B
MBRS140T3
0.1µF
C
6
11
OUT
SGND
INTV
CC
+
100µF
10V
0.065Ω
×4
7
8
10
9
M2
Si4412DY
V
V
BG
OSENSE
+
C
VCC
4.7µF
PGND
PROG
1775 TA01
C
: SANYO 30SC22M
OUT
IN
C
: AVX TPSD107M010R0065
L1: SUMIDA CDRH-125
5V/20A Fixed Output
R
F
1Ω
V
IN
6V TO 28V
C
F
LTC1775
16
C
IN
+
1
0.1µF
22µF
30V
×8
6V
EXTV
V
IN
CC
2
3
15
14
M1
IRL3803
SYNC
TK
RUN/SS
SW
Q2
FMMT720
C
SS
4
5
6
7
8
13
12
11
10
9
0.1µF
L1
3.7µH
INTV
FCB
TG
CC
C
C
B
C1
V
OUT
Q1
FMMT619
R
C
2.2nF
0.47µF
5V
10k
20A
I
BOOST
TH
D1
MBRD835L
C
C2
D
B
220pF
CMDSH-3
SGND
INTV
CC
C
OUT
+
+
Q3
680µF
6.3V
×2
C
VCC
4.7µF
FMMT619
M2
IRL3803
V
BG
OSENSE
Q4
FMMT720
V
PGND
PROG
1775 TA02
C
OUT
: SANYO 30SC22M
IN
C
: SANYO 6SP680M
L1: MAGNETICS 55206-A2, 3.7µH, 6 TURNS, 13 GAUGE
21
LTC1775
U
TYPICAL APPLICATIO S
–5V/2.5A Positive to Negative Converter
R
F
1Ω
V
IN
5V TO 10V
C
F
0.1µF
1
16
EXTV
V
IN
CC
C
+
IN
M1
Si4412DY
2
3
15
14
220µF
SYNC
TK
16V
L1
RUN/SS
SW
12µH
C
C
C1
B
LTC1775
4
5
13
12
C
R
SS
2.2nF
C
0.22µF
FCB
TG
0.1µF
10k
I
TH
BOOST
C
D
D
1
C2
B
220pF
C
CMDSH-3
MBR140T3
+
OUT
6
7
11
10
680µF
SGND
INTV
CC
6.3V
M2
Si4412DY
V
BG
OSENSE
+
C
VCC
4.7µF
V
OUT
8
9
–5V
V
PROG
PGND
2.5A
1775 TA04
C
C
: SANYO 16SV220M
OUT
L1: 12µH, 5A
IN
: SANYO 6SP680M
12V Output, Single Inductor, Buck/Boost Converter
R
F
1Ω
V
IN
6V TO 18V
C
F
1
16
EXTV
V
0.1µF
CC
IN
C
IN
+
+
C
SS
22µF
50V
×2
2
3
15
14
M1
0.1µF
SYNC
TK
Si4410DY
D2
RUN/SS
SW
L1
13µH
MBRD835L
C
C1
V
LTC1775
OUT
4
5
13
12
R
2.2nF
C
OPEN
FCB
TG
12V
20k
I
BOOST
TH
C
VCC
D
B
C
C2
C
M3
Si4410DY
B
4.7µF
CMDSH-3
220pF
C
OUT
150µF
16V
0.33µF
6
11
SGND
INTV
CC
+
7
8
10
9
M2
Si4410DY
×2
V
V
BG
OSENSE
R1
11k
V
I
IN OUT
PGND
PROG
R2
100k
D1
MBRS340
6.0 2.6
12 4.0
18 4.8
C
C
: UNITED CHEMICON THCR70E1H226ZT-CBU
OUT
L1: 13µH/11A
IN
1775 TA05
: SANYO 165A-150M
22
LTC1775
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
GN Package
16-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
0.189 – 0.196*
(4.801 – 4.978)
0.009
(0.229)
REF
16 15 14 13 12 11 10 9
0.229 – 0.244
(5.817 – 6.198)
0.150 – 0.157**
(3.810 – 3.988)
1
2
3
4
5
6
7
8
0.015 ± 0.004
(0.38 ± 0.10)
× 45°
0.053 – 0.068
(1.351 – 1.727)
0.004 – 0.0098
(0.102 – 0.249)
0.007 – 0.0098
(0.178 – 0.249)
0° – 8° TYP
0.016 – 0.050
(0.406 – 1.270)
0.0250
(0.635)
BSC
0.008 – 0.012
(0.203 – 0.305)
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
GN16 (SSOP) 1098
S Package
16-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.386 – 0.394*
(9.804 – 10.008)
16
15
14
13
12
11
10
9
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
5
7
8
1
2
3
4
6
0.010 – 0.020
(0.254 – 0.508)
× 45°
0.053 – 0.069
(1.346 – 1.752)
0.004 – 0.010
(0.101 – 0.254)
0.008 – 0.010
(0.203 – 0.254)
0° – 8° TYP
0.050
(1.270)
BSC
0.014 – 0.019
(0.355 – 0.483)
TYP
0.016 – 0.050
(0.406 – 1.270)
S16 1098
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
23
LTC1775
U
TYPICAL APPLICATIO S
2.5V/5A Adjustable Output
V
IN
5V TO 25V
R
F
1Ω
C
IN
LTC1775
CC
+
C
F
1
16
15µF
35V
×3
EXTV
V
0.1µF
IN
2
3
15
14
M1
1/2 FDS8936A
SYNC
TK
L1
6.1µH
RUN/SS
SW
C
C1
V
2.5V
5A
OUT
4
5
13
12
C
R
SS
2.2nF
C
INTV
C2
FCB
TG
CC
0.1µF
10k
R2
11k
1%
I
BOOST
TH
D1
MBRS140
C
D
B
C
B
220pF
CMDSH-3
C
0.22µF
OUT
+
6
11
680µF
4V
SGND
INTV
CC
7
8
10
9
R1
10k
1%
M2
1/2 FDS8936A
×2
V
V
BG
OSENSE
+
C
VCC
OPEN
PGND
PROG
4.7µF
1775 TA03
C
: KEMET T495X156M035AS
OUT
IN
C
: KEMET T510X687K004AS
L1: SUMIDA CDRH127-6R1
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1339
High Power Synchronous DC/DC Controller
60V Maximum Input Voltage
LTC1436A-PLL
LTC1438
High Efficiency Low Noise Synchronous Step-Down Controller
Dual High Efficiency Step-Down Controller
PLL Synchronization and Auxiliary Linear Regulator
Power-On Reset and Low-Battery Comparator
LTC1530
High Power Synchronous Step-Down Controller
SO-8 with Current Limit, No R
Frequency Ideal for 5V to 3.3V
Saves Space, Fixed
SENSE
LTC1538-AUX
LTC1625
Dual High Efficiency Step-Down Controller
5V Standby Output and Auxiliary Linear Regulator
Burst Mode Operation, 16-Lead GN Package
No R
Current Mode Synchronous Step-Down Controller
SENSE
LTC1628
Dual High Efficiency 2-Phase Step-Down Controller
PolyPhaseTM High Efficiency Step-Down Controller
3.3V Input High Power Step-Down Controller
Antiphase Drive, Standby 5V and 3.3V LDO, Fault Protection,
V
Up to 36V
IN
LTC1629
LTC1649
LTC1702
LTC1735
Current Mode Ensures Accurate Current Sharing,
Expandable Up to 200A, V Up to 36V
IN
2.7V to 5V Input, 90% Efficiency, Ideal for 3.3V to 1.xV – 2.xV
Up to 20A
Dual 2-Phase High Frequency, High Efficiency Voltage Mode
Synchronous Step-Down Controller
500kHz; V Up to 7V; V
, V
as Low as 2.x, 1.x,
IN
OUT1 OUT2
I
, I
as High as 20A; No Sense Resistor Required
OUT1 OUT2
High Efficiency Synchronous Step-Down Controller
Output Fault Protection, 16-Pin GN Package, 4V ≤ V ≤ 36V
IN
PolyPhase is a trademark of Linear Technology Corporation.
1775f LT/TP 0500 4K • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
●
●
LINEAR TECHNOLOGY CORPORATION 1999
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
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Linear
LTC1775IGN#TR
LTC1775 - High Power No RSENSE Current Mode Synchronous Step-Down Switching Regulator; Package: SSOP; Pins: 16; Temperature Range: -40°C to 85°C
Linear
LTC1775IGN#TRPBF
LTC1775 - High Power No RSENSE Current Mode Synchronous Step-Down Switching Regulator; Package: SSOP; Pins: 16; Temperature Range: -40°C to 85°C
Linear
LTC1775IS#PBF
LTC1775 - High Power No RSENSE Current Mode Synchronous Step-Down Switching Regulator; Package: SO; Pins: 16; Temperature Range: -40°C to 85°C
Linear
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