LTC1753CSW [Linear]
5-Bit Programmable Synchronous Switching Regulator Controller for Pentium III Processor; 5位可编程同步开关稳压控制器，用于奔腾III处理器
| 型号： | LTC1753CSW |
| 厂家： | 
Linear |
| 描述： | 5-Bit Programmable Synchronous Switching Regulator Controller for Pentium III Processor |
| 文件： | 总24页 (文件大小：272K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1753
5-Bit Programmable
Synchronous Switching
Regulator Controller for
Pentium® III Processor
U
FEATURES
DESCRIPTIO
The LTC®1753 is a high power, high efficiency switching
regulator controller optimized for 5V input to a digitally
programmable 1.3V-3.5V output. The internal 5-bit DAC
programs the output voltage from 1.3V to 2.05V in 50mV
incrementsandfrom2.1Vto3.5Vin100mVincrements. The
precision internal reference and an internal feedback system
provide an output accuracy of ±1.5% at room temperature
and typically ±2% over temperature, load current and line
voltage shifts. The LTC1753 uses a synchronous switching
architecture with two external N-channel output devices,
providing high efficiency and eliminating the need for a high
power,highcostP-channeldevice.Additionally,itsensesthe
output current across the on-resistance of the upper N-
channel FET, providing an adjustable current limit without an
external low value sense resistor.
■
5-Bit Digitally Programmable 1.3V to 3.5V Fixed
Output Voltage, VRM 8.4 Compliant
■
Fast Transient Response: 0% to 100% Duty Cycle
■
Phase Lead Compensation for Remote Sensing
■
Overtemperature Protection
■
Flags for Power Good and Overvoltage Fault
■
19A Output Current Capability from a 5V Supply
■
Dual N-Channel MOSFET Synchronous Driver
■
Initial Output Accuracy: ±1.5%
■
Excellent Output Accuracy: ±2% Typ Over Line,
Load and Temperature Variations
High Efficiency: Over 95% Possible
■
■
Adjustable Current Limit Without External Sense
Resistors
■
Available in 2O-Lead SSOP and SW Packages
The LTC1753 free-runs at 300kHz and can be synchronized
to a faster external clock if desired. It provides a phase lead
compensation scheme and under harsh loading conditions,
the PWM duty cycle can be momentarily forced to 0% or
100% to reduce the output voltage recovery time.
U
APPLICATIO S
Power Supply for Pentium® III, AMD-K6®-2, SPARC,
ALPHA and PA-RISC Microprocessors
High Power 5V to 1.3V-3.5V Regulators
■
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
Pentium is a registered trademark of Intel Corporation.
AMD-K6 is a registered trademark of Advanced Micro Devices, Inc.
U
TYPICAL APPLICATIO
PV
CC
12V
V
IN
5V
+
+
+
C
**
IN
0.1µF
10µF
0.1µF
10µF
1200µF
× 4
600Ω
5.6k
5.6k
Q1A*
V
†
I
CC
PV
CC
MAX
L
O
Q1*
Q2*
PWRGD
FAULT
G1
1.3µH
18A
V
OUT
20Ω
1.3V TO
3.5V
14A
I
FB
CPU
5
VID0 TO VID4
OUTEN
LTC1753
††
C
+
OUT
Q2A*
2700µF
× 5
G2
V
FB
NC
COMP
SS
SGND
GND
SENSE
R
C
15k
C1
150pF
C
SS
0.1µF
C
C
* SILICONIX SUD50N03-10
** SANYO 10MV1200GX
† PANASONIC ETQP 6FIR3LFA
†† SANYO 6MV2700GX
1µF
4700pF
1753 F01
Figure 1. 5V to 1.3V-3.5V Supply Application
1
LTC1753
W W
U W
U W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
TOP VIEW
Supply Voltage
ORDER PART
NUMBER
V
CC ........................................................................ 7V
1
2
G1
20
19
18
17
16
15
14
13
12
11
G2
OUTEN
VID0
PV
CC
PVCC ................................................................... 14V
Input Voltage
3
GND
LTC1753CG
LTC1753CSW
4
VID1
SGND
IFB (Note 2)............................................ PVCC + 0.3V
5
VID2
V
CC
IMAX ........................................................ –0.3V to 9V
All Other Inputs ...................... –0.3V to (VCC + 0.3V)
Digital Output Voltage................................. –0.3V to 9V
6
VID3
SENSE
7
VID4
I
MAX
8
PWRGD
FAULT
I
FB
IFB Input Current (Notes 2, 3) .......................... –100mA
9
SS
Junction Temperature.......................................... 125°C
Operating Temperature Range ..................... 0°C to 70°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec.)................. 300°C
10
V
COMP
FB
G PACKAGE
SW PACKAGE
20-LEAD PLASTIC SSOP 20-LEAD PLASTIC SO
TJMAX = 125°C, θJA = 100°C/ W (G)
TJMAX = 125°C, θJA = 100°C/ W (SW)
Consult factory for Industrial and Military grade parts.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 5V, PVCC = 12V, unless otherwise noted. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
6
UNITS
V
Supply Voltage
●
●
4.5
V
V
CC
PV
CC
Supply Voltage for G1, G2
Internal Feedback Voltage
13.2
V
1.3V Output Voltage
2.1V Initial Output Voltage
3.5V Initial Output Voltage
0.5
0.8
1.34
V
V
V
FB
V
1.3V Initial Output Voltage
1.8V Initial Output Voltage
2.8V Initial Output Voltage
3.5V Initial Output Voltage
1.3V Initial Output Voltage
1.8V Initial Output Voltage
2.8V Initial Output Voltage
3.5V Initial Output Voltage
With Respect to Rated Output Voltage (Figure 2)
–20 (–1.5%)
– 27 (–1.5%)
– 42 (–1.5%)
– 52 (–1.5%)
–26 (–2%)
– 36 (–2%)
– 56 (–2%)
– 70 (–2%)
20 (+1.5%)
27 (+1.5%)
42 (+ 1.5%)
52 (+1.5%)
26 (+2%)
36 (+2%)
56 (+2%)
70 (+2%)
mV
mV
mV
mV
mV
mV
mV
mV
OUT
●
●
●
●
∆V
OUT
Output Load Regulation
Output Line Regulation
I
V
= 0 to 14A (Figure 2)
OUT
–5
±1
mV
mV
= 4.75V to 5.25V, I
= 0 (Figure 2)
IN
OUT
V
Positive Power Good Trip Point
Negative Power Good Trip Point
% Above Output Voltage (Note 4) (Figure 2)
% Below Output Voltage (Note 4) (Figure 2)
●
●
3
–3
6
%
%
PWRGD
–6
8
V
FAULT Trip Point
% Above Output Voltage (Note 4) (Figure 2)
●
13
18
%
FAULT
I
I
f
Operating Supply Current
Shutdown Supply Current
OUTEN = V = 5V (Note 5)(Figure 3)
OUTEN = 0, VID0 to VID4 Floating (Figure 3)
●
●
800
130
1200
250
µA
µA
CC
CC
Supply Current
PV = 12V, OUTEN = V (Note 6) (Figure 3)
15
1
mA
µA
PVCC
OSC
CC
CC
PV = 12V, OUTEN = 0, VID0 to VID4 Floating
CC
Internal Oscillator Frequency
(Figure 4)
(Note 11)
(Note 11)
●
250
300
1.8
2.8
350
kHz
V
V
V
V
V
at Minimum Duty Cycle
at Maximum Duty Cycle
SAWL
SAWH
COMP
COMP
V
2
LTC1753
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
CC = 5V, PVCC = 12V, unless otherwise noted. (Note 3)
V
SYMBOL
PARAMETER
CONDITIONS
(Note 7)
MIN
40
TYP
54
MAX
UNITS
dB
G
Error Amplifier Open-Loop DC Gain
Error Amplifier Transconductance
Error Amplifier –3dB Bandwidth
●
●
ERR
g
(Note 7)
0.9
1.6
400
190
–12
60
2.3
millimho
kHz
mERR
BW
COMP = Open (Note 11)
ERR
IMAX
I
I
I
I
Sink Current
V
V
V
= V
CC
●
●
●
150
–16
30
230
–8
µA
MAX
IMAX
Soft-Start Source Current
= 0V, V
= 0V, V = V
CC
µA
SS
SS
IMAX
IFB
Maximum Soft-Start Sink Current
Under Current Limit
= V , V
= V , V = 0V
150
µA
SSIL
SENSE
OUT IMAX
CC IFB
(Notes 8, 9), V = V
SS
CC
I
Soft-Start Sink Current Under Hard
Current Limit
V
= 0V, V
= V , V = 0V
●
20
45
mA
SSHIL
SENSE
IMAX
CC IFB
t
t
t
t
Hard Current Limit Hold Time
Power Good Response Time↑
Power Good Response Time↓
FAULT Response Time
V
V
V
V
= 0V, V
= 4V, V ↓ from 5V
500
1
µs
ms
µs
µs
V
SSHIL
SENSE
SENSE
SENSE
SENSE
IMAX
IFB
↑ from 0V to Rated V
●
●
●
●
●
●
●
●
●
0.5
200
200
1.6
2
PWRGD
PWRBAD
FAULT
OUT
↓ from Rated V
↑ from Rated V
to 0V
500
500
1.7
1000
1000
1.8
OUT
OUT
to V
CC
V
V
Overtemperature Driver Disable
Shutdown
OUTEN↓, VID0 to VID4 = 0 (Note 10) (Figure 3)
OTDD
SHDN
OUTEN↓, VID0 to VID4 = 0 (Note 10) (Figure 3)
0.8
V
t , t
Driver Rise and Fall Time
Driver Nonoverlap Time
(Figure 4)
(Figure 4)
90
150
ns
ns
V
r
f
t
30
2
100
NOL
V
V
VID0 to VID4 Input High Voltage
VID0 to VID4 Input Low Voltage
SENSE Input Resistance
IH
IL
0.8
V
R
R
108
20
kΩ
kΩ
SENSE
VID
VID0 to VID4 Internal Pull-Up
Resistance
●
●
10
10
I
Digital Output Sink Current
mA
SINK
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
the LTC1753 operating frequency, supply voltage and the external FETs
used.
Note 2: When I is taken below GND, it will be clamped by an internal diode.
This pin can handle input currents greater than 100mA below GND without
Note 7: The open-loop DC gain and transconductance from the SENSE pin to
FB
COMP pin will be (G )(1.26/3.3) and (g )(1.26/3.3) respectively.
mERR
ERR
latchup. In the positive direction, it is not clamped to V or PV
.
CC
CC
Note 8: The current limiting amplifier can sink but cannot source current.
Note 3: All currents into device pins are positive; all currents out of the
device pins are negative. All voltages are referenced to ground unless
otherwise specified.
Under normal (not current limited) operation, the output current will be zero.
Note 9: Under typical soft current limit, the net soft-start discharge current
will be 60µA (I ) + [–12µA(I )] 48µA. The soft-start sink-to-source
SSIL
SS
Note 4: The Power Good and FAULT trip thresholds are tested at the 1.8V
output voltage code. The Power Good and FAULT trip thresholds are
guaranteed by design for all other output voltage codes to the same
specification.
current ratio is designed to be 5:1.
Note 10: When VID0 to VID4 are all HIGH, the LTC1753 will be forced to
shut down internally. The OUTEN trip voltages are guaranteed by design for
all other input codes.
Note 5: The LTC1753 goes into the shutdown mode if VID0 to VID4 are
floating. Due to the internal pull-up resistors, there will be an additional
0.25mA/pin if any of the VID0 to VID4 pins are pulled low.
Note 11: This parameter is guaranteed by design and correlation and is not
tested in production.
Note 6: Supply current in normal operation is dominated by the current
needed to charge and discharge the external FET gates. This will vary with
3
LTC1753
TYPICAL PERFOR A CE CHARACTERISTICS
U W
Typical 1.3V VOUT Distribution
Typical 2.8V VOUT Distribution
Efficiency vs Load Current
100
90
80
70
60
50
40
30
20
10
0
50
40
30
50
40
30
TOTAL SAMPLE SIZE = 500
TOTAL SAMPLE SIZE = 500
A
B
25°C
REFER TO TYPICAL APPLICATION
CIRCUIT FIGURE 1
25°C
100°C
V
C
= 5V, PV = 12V, V
= 2.8V,
100°C
IN
OUT
CC
OUT
= 330µF ×7, L = 2µH
O
20
10
0
20
10
0
A: Q1 = 1 × SUD50N03-10
Q2 = 1 × SUD50N03-10
B: Q1 = 2 × SUD50N03-10
Q2 = 1 × SUD50N03-10
NO FAN
2
Q1 IS MOUNTED ON 1IN COPPER AREA
0
2
4
6
8
10
12
14
1.275 1.285
1.295
1.305 1.315 1.325
2.75
2.77
2.79
2.81
2.83
2.85
0.3
LOAD CURRENT (A)
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
1753 G03
1753 G01
1753 G02
Line Regulation
Output Temperature Drift
Load Regulation
2.860
2.850
2.840
2.830
2.820
2.810
2.800
2.790
2.780
2.770
2.760
2.750
2.740
2.825
2.820
2.815
2.810
2.805
2.800
2.795
2.790
2.785
2.780
2.775
2.825
2.820
2.815
2.810
2.805
2.800
2.795
2.790
2.785
2.780
2.775
REFER TO TYPICAL APPLICATION
CIRCUIT FIGURE 1
REFER TO TYPICAL APPLICATION
CIRCUIT FIGURE 1
V
IN
= 5V, PV = 12V, T = 25°C
OUTPUT = NO LOAD
CC
A
T
= 25°C
A
–50
0
25
50
75 100 125
–25
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14
4.75
4.85
4.95
5.05
5.15
5.25
TEMPERATURE (°C)
OUTPUT CURRENT (A)
INPUT VOLTAGE (V)
1753 G06
1753 G04
1753 G05
Error Amplifier Open-Loop
DC Gain vs Temperature
Overtemperature Driver Disable
vs Temperature
Error Amplifier Transconductance
vs Temperature
1.80
1.78
1.76
1.74
1.72
1.70
1.68
1.66
1.64
1.62
1.60
60
55
50
45
2.3
2.1
1.9
1.7
1.5
1.3
1.1
40
0.9
–50
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
–25
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
TEMPERATURE (°C)
TEMPERATURE (°C)
1753 G07
1753 G09
1753 G08
4
LTC1753
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Oscillator Frequency
IMAX Sink Current
Soft-Start Source Current
vs Temperature
vs Temperature
vs Temperature
350
340
330
320
310
300
290
280
270
260
250
220
210
200
190
180
170
160
150
–8
–9
–10
–11
–12
–13
–14
–15
–16
75 100
TEMPERATURE (°C)
125
–50
0
25
50
75 100 125
–50 –25
0
25
50
–25
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
TEMPERATURE (°C)
1753 G10
1753 G11
1753 G12
PVCC Supply Current
vs Gate Capacitance
VCC Operating Supply Current
vs Temperature
VCC Shutdown Supply Current
vs Temperature
1.2
1.1
250
70
60
PV = 12V
CC
V
f
= 5V
= 300kHz
CC
OSC
T
= 25°C
A
225
200
1.0
0.9
0.8
0.7
0.6
50
175
150
125
100
75
40
30
20
10
0.5
50
0
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
–25
0
50
75 100 125
2000
4000
8000
–50
25
0
6000
TEMPERATURE (°C)
GATE CAPACITANCE (pF)
1753 G13
1753 G14
1753 G15
Output Over Current Protection
Transient Response, VOUT = 2.8V
3.0
2.5
Q1 CASE = 90°C, V
Q1 = 2 × MTD20N03HDL
Q2 = 1 × MTD20N03HDL
= 2.8V
OUT
VOUT
50mV/DIV
2.0
R
= 2.7k, R = 20Ω,
IMAX
IFB
SS CAP = 0.01µF
10
1.5
1.0
ILOAD
5A/DIV
0
SHORT-CIRCUIT
CURRENT
1753 G17
0.5
0
50µs/DIV
0
2
4
6
8
10 12 14 16 18
OUTPUT CURRENT (A)
1753 G16
5
LTC1753
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Expanded View of Undershoot
Illustrates 100% Duty Cycle
Operation, VOUT = 2.8V
Expanded View of Overshoot
Illustrates 0% Duty Cycle
Operation, VOUT = 2.8V
VOUT
20mV/DIV
VOUT
20mV/DIV
G1
10V/DIV
G1
10V/DIV
1753 G18
1753 G19
5µs/DIV
5µs/DIV
U
U
U
PI FU CTIO S
G2 (Pin 1): Gate Drive for the Lower N-Channel MOSFET,
Q2. ThisoutputwillswingfromPVCC toGND. Itwillalways
be low when G1 is high or when the output is disabled. To
prevent undershoot during a soft-start cycle, G2 is held
low until G1 first goes high.
the SENSE pin, the initial output voltage can be raised
slightly. Since the internal divider has a nominal imped-
ance of 108kΩ, a 1100Ω series resistor will raise the
nominal output voltage by 1%. If an external resistor is
used,thevalueofthe1µFcapacitorontheSENSEpinmust
be greatly reduced or loop phase margin will suffer. Set a
time constant for the RC combination of approximately
0.1µs. So, for example, with a 1100Ω resistor, set
C=90pF. Useastandard100pFcapacitor. Inaddition, LTC
recommendsthatthe1µFcapacitorbeconnectedfromthe
top of the additional external resistor directly to SGND.
PVCC (Pin 2): Power Supply for G1 and G2. PVCC must be
connected to a potential of at least VIN + VGS(ON)Q1. For
normal applications, connect PVCC to a 12V power supply
or generate PVCC using a simple charge pump.
GND (Pin 3): Power Ground. GND should be connected to
a low impedance ground plane in close proximity to the
source of Q2.
IMAX (Pin 7): Current Limit Threshold. Current limit is set
by the voltage drop across an external resistor connected
betweenthedrainofQ1andIMAX.Thereisa190µAinternal
SGND (Pin 4): Signal Ground. SGND is connected to the
low power internal circuitry and should be connected to
the negative terminal of the output capacitor where it
returns to the ground plane. GND and SGND should be
shorted directly at the LTC1753.
pull-down at IMAX
.
IFB (Pin 8): Current Limit Sense Pin. Connect to the
switching node between the source of Q1 and the drain of
Q2. If IFB drops below IMAX when G1 is on, the LTC1753
will go into current limit. The current limit circuit can be
disabled by floating IMAX and shorting IFB to VCC.
VCC (Pin 5): Power Supply. Power for the internal low
power circuity. VCC should be wired separately from the
drain of Q1 if they share the same supply. A 10µF bypass
capacitor is recommended from this pin to SGND.
SS (Pin 9): Soft-Start. Connect to an external capacitor to
implement a soft-start function. During moderate over-
loadconditions, thesoft-startcapacitorwillbedischarged
slowly in order to reduce the duty cycle. In hard current
limit, the soft-start capacitor will be forced low immedi-
ately and the LTC1753 will rerun a complete soft-start
cycle. CSS mustbeselectedsuchthatduringpower-upthe
current through Q1 will not exceed the current limit value.
SENSE(Pin6):OutputVoltagePin.Connecttothepositive
terminal of the output capacitor. There is an internal 108k
resistor connected from this pin to SGND. SENSE is a very
sensitivepin;foroptimumperformance,connectanexter-
nal 1µF capacitor from this pin to SGND. By connecting a
small external resistor between the output capacitor and
6
LTC1753
U
U
U
PI FU CTIO S
PWRGD (Pin 13): Power Good. This is an open-drain
signal to indicate validity of output voltage. A high indi-
cates that the output has settled to within ±3% of the rated
outputformorethan1ms.PWRGDwillgolowiftheoutput
is out of regulation for more than 500µs. If OUTEN = 0,
PWRGD pulls low.
COMP (Pin 10): External Compensation. The COMP pin is
connected directly to the output of the error amplifier and
the input of the PWM comparator. An RC+C network is
used at this node to compensate the feedback loop to
provide optimum transient response.
V
FB (Pin 11): Voltage Feedback. VFB is the tap point of the
VID0, VID1, VID2, VID3, VID4 (Pins 18, 17, 16, 15, 14):
Digital Voltage Select. TTL inputs used to set the regulated
output voltage required by the processor (Table 2). There
is an internal 20kΩ pull-up at each pin. When all five VIDn
pins are high or floating, the chip will shut down.
internal resistor divider connected from SENSE to SGND.
During rapid and heavy output loading conditions, a small
capacitor between the SENSE and VFB pin creates a feed-
forward path that reduces the transient recovery time. For
applications where extremely low output ripple is re-
quired, low ESR capacitors are typically used. In this case,
a small capacitor between SENSE and VFB helps to com-
pensate the switching loop. This pin can be left floating,
but should be isolated from high current switching nodes.
OUTEN (Pin 19): Output Enable. TTL input which enables
the output voltage. The external MOSFET temperature can
be monitored with an external thermistor as shown in
Figure 11. When the OUTEN input voltage drops below
1.7V, the drivers are internally disabled to prevent the
MOSFETs from heating further. If OUTEN is less than 1.2V
for longer than 30µs, the LTC1753 will enter shutdown
mode. The internal oscillator can be synchronized to a
faster external clock by applying the external clocking
signal to the OUTEN pin. (See Applications Information.)
FAULT (Pin 12): Overvoltage Fault. FAULT is an open-
drain output. If VOUT reaches 13% above the nominal
output voltage, FAULT will go low and G1 and G2 will be
disabled. Once triggered, the LTC1753 will remain in this
state until the power supply is recycled or the OUTEN pin
is toggled. If OUTEN = 0, FAULT floats or is pulled high by
an external resistor.
G1 (Pin 20): Gate Drive for the Upper N-Channel MOSFET,
Q1. ThisoutputwillswingfromPVCC toGND. Itwillalways
be low when G2 is high or the output is disabled.
7
LTC1753
W
BLOCK DIAGRA
113% V
+
REF
FC
12 FAULT
DELAY
13
2
PWRGD
–
DISDR
LOGIC
OUTEN 19
SYSTEM
POWER
DOWN
PV
CC
–
R
S
20 G1
PWM
+
10
9
COMP
SS
I
1
G2
SS
Q
SS
11
V
FB
BG
ERR
+
MIN
MAX
6
SENSE
–
+
–
+
–
18 VID0
17
V
REF
V
– 3%
V
+ 3%
REF
REF
VID1
66.5k
41.5k
16 VID2
15 VID3
8
–
+
I
FB
CC
14
VID4
V
I
7
REF
MAX
I
MAX
DAC
0.5V
0.7V
/
REF
REF
+
–
MHCL
HCL MONO
LVC
1553 BD
8
LTC1753
TEST CIRCUITS
V
CC
5V
PV
CC
12V
V
IN
5V
C
**
IN
+
+
+
1200µF
× 4
0.1µF
0.1µF
3k
3k
10µF
10µF
Q1A*
Q2A*
V
I
PV
CC
CC
FB
G1
100pF
100pF
†
L
O
OUTEN
Q1*
Q2*
1.3µH
15A
PWRGD
FAULT
I
NC
NC
V
MAX
OUT
††
+
LTC1753
C
OUT
2700µF
VID0 TO VID4
VID0 TO VID4
× 5
G2
FB
V
COMP
SS
SGND
GND
SENSE
R
C
15k
C1
150pF
0.1µF
C
C
* SILICONIX Si4410
1µF
** SANYO 10MV1200GX
† PANASONIC ETQP 6FIR3LFA
†† SANYO 6MV2700GX
4700pF
1753 F02
Figure 2
V
CC
+
VID0 VID1 VID2 VID3 VID4
V
CC
10µF
0.1µF
PV
CC
V
CC
VID0 VID1 VID2 VID3 VID4
OUTEN
I
FB
PV
CC
+
G1
NC
0.1µF
10µF
NC
PWRGD
LTC1753
FAULT
I
NC
NC
NC
MAX
NC
NC
G2
COMP
V
FB
SS
NC
SGND
GND
SENSE
1573 F03
Figure 3
V
5V
PV
CC
12V
CC
t
r
t
f
+
+
90%
50%
10%
90%
50%
0.1µF
0.1µF
10µF
10µF
PV
V
CC
CC
10%
G1
G2
G1 RISE/FALL
G2 RISE/FALL
I
FB
5000pF
5000pF
NC
V
LTC1753
FB
t
t
NOL
NOL
V
SENSE
SGND
OUT
GND
50%
50%
1753 F04
Figure 4
9
LTC1753
U
U
FU CTIO TABLES
Table 1. PWRGD and FAULT Logic
INPUT
Table 2. Rated Output Voltage (cont)
INPUT PIN
OUTPUT*
RATED OUTPUT
VOLTAGE (V)
OUTEN
V
**
FAULT
PWRGD
SENSE
V
V
V
V
V
ID4
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ID3
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
ID2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
ID1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
ID0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
X
1
1
1
0
0
1
1.90
1.95
2.00
2.05
SHDN
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
< 97%
> 97%
< 103%
>103%
> 113%
1
1
1
0
0
0
Table 2. Rated Output Voltage
INPUT PIN
RATED OUTPUT
VOLTAGE (V)
V
V
V
V
V
ID4
0
ID3
1
1
ID2
1
ID1
1
1
ID0
1
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
1.80
1.85
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
3.4
3.5
* With external pull-up resistor
** With respect to the output voltage selected in Table 2
X Don’t care
W U U
U
APPLICATIO S I FOR ATIO
OVERVIEW
controlled current source. Under severe overloads or
output short circuit conditions, the chip will be repeatedly
forced into soft-start until the short is removed, prevent-
ing the external components from being damaged. Under
outputovervoltageconditions, theMOSFETdriverswillbe
disabled permanently until the chip power supply is
recycled or the OUTEN pin is toggled.
The LTC1753 is a voltage feedback, synchronous switch-
ing regulator controller (see Block Diagram) designed for
use in high power, low voltage step-down (buck) convert-
ers. It includes an on-chip DAC to control the output
voltage, a PWM generator, a precision reference trimmed
to ±1%, two high power MOSFET gate drivers and all the
necessary feedback and control circuitry to form a com- OUTEN can optionally be connected to an external nega-
plete switching regulator circuit.
tive temperature coefficient (NTC) thermistor placed near
theexternalMOSFETsorthemicroprocessor.Twothresh-
old levels are provided internally. When OUTEN drops to
1.7V, the G1 and G2 pins will be forced low. If OUTEN is
pulled below 1.2V, the LTC1753 will go into shutdown
mode, cutting the supply current to a minimum. If thermal
shutdown is not required, OUTEN can be connected to a
The LTC1753 includes a current limit sensing circuit that
uses the upper external power MOSFET as a current
sensing element, eliminating the need for an external
sense resistor. Once the current comparator, CC, detects
an overcurrent condition, the duty cycle is reduced by
discharging the soft-start capacitor through a voltage-
10
LTC1753
W U U
APPLICATIO S I FOR ATIO
U
conventional TTL enable signal. The free-running 300kHz
PWM frequency can be synchronized to a faster external
clock connected to OUTEN. Adjusting the oscillator fre-
quency can add flexibility in the external component
selection. See the Clock Synchronization section.
Similarly, the MAX comparator forces the output to 0%
duty cycle if VFB is more than 3% above the internal
reference. To prevent these two comparators from trig-
geringduetonoise,outputvoltageripplemustbecontrolled
with sufficient output bypassing to prevent jitter. In addi-
tion, the MIN and MAX comparators’ response times are
deliberately controlled so that they take about one micro-
second to respond. These two comparators help prevent
extreme output perturbations with fast output transients,
while allowing the main feedback loop to be optimally
compensated for stability.
Output regulation can be monitored with the PWRGD pin
which in turn monitors the internal MIN and MAX com-
parators. If the output is ±3% beyond the selected value
for more than 500µs, the PWRGD output will be pulled
low. Once the output has settled within ±3% of the se-
lected value for more than 1ms, PWRGD will return high.
Soft-Start and Current Limit
THEORY OF OPERATION
Primary Feedback Loop
TheLTC1753includesasoft-startcircuitwhichisusedfor
initial start-up and during current limit operation. The SS
pin requires an external capacitor to GND with the value
determined by the required soft-start time. An internal
12µA current source is included to charge the external SS
capacitor. During start-up, the COMP pin is clamped to a
diode drop above the voltage at the SS pin. This prevents
the error amplifier, ERR, from forcing the loop to 100%
duty cycle. The LTC1753 will begin to operate at low duty
cycleastheSSpinrisesaboveabout1.2V(VCOMP ≈1.8V).
As SS continues to rise, QSS turns off and the error
amplifierbeginstoregulatetheoutput. TheMINcompara-
tor is disabled when soft-start is active to prevent it from
overriding the soft-start function.
The regulator output voltage at the SENSE pin is divided
down internally by a resistor divider with a total resistance
of approximately 108k. This divided down voltage is
subtracted from a reference voltage supplied by the DAC
output. Theresultingerrorvoltageisamplifiedbytheerror
amplifierandtheoutputiscomparedtotheoscillatorramp
waveform by the PWM comparator. This PWM signal
controls the external MOSFETs through G1 and G2. The
resulting chopped waveform is filtered by LO and COUT
closingtheloop.Loopfrequencycompensationisachieved
with an external RC + C network at the COMP pin, which is
connected to the output node of the transconductance
amplifier. In low output ripple voltage applications, low
ESR output capacitors are typically used. Under this
condition, a capacitor between the SENSE and VFB pins
helps compensate the switching loop. For heavy transient
outputloadingapplications, asmallcapacitorbetweenthe
SENSE and VFB pin acts as a feedforward path and helps
reduce the transient recovery time.
The LTC1753 includes yet another feedback loop to con-
trol operation in current limit. Just before every falling
edge of G1, the current comparator, CC, samples and
holds the voltage drop measured across the external
MOSFET, Q1, at the IFB pin. CC compares the voltage at IFB
to the voltage at the IMAX pin. As the peak current rises, the
measured voltage across Q1 increases due to the drop
across the RDS(ON) of Q1. When the voltage at IFB drops
below IMAX, indicating that Q1’s drain current has ex-
ceeded the maximum level, CC starts to pull current out of
the external soft-start capacitor, cutting the duty cycle and
controlling the output current level. The CC comparator
pulls current out of the SS pin in proportion to the voltage
difference between IFB and IMAX. Under minor overload
conditions, the SS pin will fall gradually, creating a time
delay before current limit takes effect. Very short, mild
MIN, MAX Feedback Loops
Two additional comparators in the feedback loop provide
high speed fault correction in situations where the ERR
amplifiermaynotrespondquicklyenough. MINcompares
the feedback signal VFB to a voltage 3% below the internal
reference. If VFB is lower than the threshold of this com-
parator, the MIN comparator overrides the ERR
amplifier and forces the loop to 100% duty cycle.
11
LTC1753
APPLICATIO S I FOR ATIO
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Table 3. Recommended RIMAX Resistor (kΩ) vs Maximum Operating Load Current and External MOSFET Q1
MAXIMUM OPERATING
LOAD CURRENT (A)
Si4410
(TWO IN PARALLEL)
MTD20N03
(TWO IN PARALLEL)
Si4410
820
1.2k
—
SUD50N03
680
8
430
560
680
820
910
1.2k
1k
10
12
14
16
18
820
1.2k
1.5k
1.8k
2.0k
2.2k
1k
—
1.2k
1.5k
—
—
—
V
IN
overloads may not affect the output voltage at all. More
significant overload conditions will allow the SS pin to
reach a steady state, and the output will remain at a
reduced voltage until the overload is removed. Serious
overloads will generate a large overdrive at CC, allowing it
to pull SS down quickly and preventing damage to the
output components.
+
+
LTC1753
R
C
IMAX
IN
V
I
MAX
7
+
–
190µA
Q1
G1
20Ω
CC
I
FB
8
L
O
OUT
G2
Q2
C
OUT
By using the RDS(ON) of Q1 to measure the output current,
the current limiting circuit eliminates an expensive dis-
cretesenseresistorthatwouldotherwiseberequired.This
helps minimize the number of components in the high
current path. Due to switching noise and variation of
RDS(ON), the actual current limit trip point is not highly
accurate. The current limiting circuitry is primarily meant
to prevent damage to the power supply circuitry during
fault conditions. The exact current level where the limiting
circuitbeginstotakeeffectwillvaryfromunittounitasthe
RDS(ON) of Q1 varies.
1753 F05
Figure 5. Current Limit Setting
fOSC = LTC1753 oscillator frequency = 300kHz
LO = Inductor value
RDS(ON)Q1 = Hot on-resistance of Q1 at ILMAX
IIMAX = Internal 190µA sink current at IMAX
OUTEN and Thermistor Input
The LTC1753 includes a low power shutdown mode,
controlled by the logic at the OUTEN pin. A high at OUTEN
allows the part to operate normally. A low level at OUTEN
stops all internal switching, pulls COMP and SS to ground
internally and turns Q1 and Q2 off. PWRGD is pulled low,
and FAULT is left floating. In shutdown, the LTC1753
quiescent current drops to about 130µA. The residual
current is used to keep the thermistor sensing circuit at
OUTEN alive. Note that the leakage current of the external
MOSFETs may add to the total shutdown current con-
sumed by the circuit, especially at elevated temperatures.
For a given current limit level, the external resistor from
IMAX to VIN can be determined by:
I
(
R
)(
)
LMAX
DS(ON)Q1
R
=
IMAX
I
where,
I
RIPPLE
I
=I
+
LMAX LOAD
2
ILOAD = Maximum load current
IRIPPLE = Inductor ripple current
OUTEN is designed with two thresholds to allow it to also
be utilized for overtemperature protection. The power
MOSFET operating temperature can be monitored with an
externalnegativetemperaturecoefficient(NTC)thermistor
V − V
V
(
)(
)
IN
OUT OUT
=
f
L
V
IN
(
)( )(
)
OSC
O
12
LTC1753
W U U
APPLICATIO S I FOR ATIO
U
mounted next to the external MOSFET which is expected
to run the hottest––often the high-side device, Q1. Elec-
trically, the thermistor should form a voltage divider with
another resistor, R1, connected to VCC. Their midpoint
should be connected to OUTEN (see Figure 6). As the
temperature increases, the OUTEN pin voltage is reduced.
Undernormaloperatingconditions,theOUTENpinshould
stay above 1.7V and all circuits will function normally. If
the temperature gets abnormally high, the OUTEN pin
voltage will eventually drop below 1.7V, the LTC1753
disables both FET drivers. If OUTEN decreases below
1.2V,theLTC1753entersshutdownmode.Toactivateany
ofthesethreemodes, theOUTENvoltagemustdropbelow
the respective threshold for longer than 30µs.
MOSFET Gate Drive
Power for the internal MOSFET drivers is supplied by
PVCC.Thissupplymustbeabovetheinputsupplyvoltage
by at least one power MOSFET VGS(ON) for efficient
operation. For a typical application, PVCC should be con-
nected to a 12V power supply.
If the OUTEN pin is low, G1 and G2 are both held low to
prevent output voltage undershoot. As VCC and PVCC
power up from a 0V condition, an internal undervoltage
lockout circuit prevents G1 and G2 from going high until
V
CC reaches about 3.5V. If VCC powers up while PVCC is at
ground potential, the SS is forced to ground potential
internally. SS clamps the COMP pin low and prevents the
drivers from turning on. On power-up or recovery from
thermal shutdown, the drivers are designed such that G2
is held low until G1 first goes high.
V
IN
V
Q1
G1
G2
CC
L
O
LTC1753
OUTEN
V
OUT
R1
+
Power MOSFETs
Q2
C
OUT
R2
NTC THERMISTOR
MOUNT IN CLOSE
THERMAL PROXIMITY
TO Q1
Two N-channel power MOSFETs are required for most
LTC1753 circuits. Logic level MOSFETs should be used
and they should be selected based on on-resistance and
GATE threshold voltage considerations. RDS(ON) should
be chosen based on input and output voltage, allowable
power dissipation and maximum required output current.
GATE threshold voltages for logic level MOSFETs are
lower than standard MOSFETs. A MOSFET whose RDS(ON)
is rated at VGS = 4.5V does not necessarily have a logic
level MOSFET GATE threshold voltage. Using standard
MOSFETs instead of logic level MOSFETs can cause start-
up problems, especially if PVCC is derived from a charge
pumpscheme. InatypicalLTC1753buckconvertercircuit
the average inductor current is equal to the output load
current. This current is always flowing through either Q1
or Q2 with the power dissipation split up according to the
duty cycle:
1753 F06
Figure 6. OUTEN Pin as a Thermistor Input
Clock Synchronization
The internal oscillator can be synchronized to an external
clock by applying the external clocking signal to the
OUTEN pin. The synchronizing range extends from the
initial operating frequency up to 500kHz. If the external
frequency is much higher than the natural free-running
frequency, the peak-to-peak sawtooth amplitude within
theLTC1753willdecrease. Sincetheloopgainisinversely
proportional to the amplitude of the sawtooth, the com-
pensation network may need to be adjusted slightly. Note
that the temperature sensing circuitry does not operate
when external synchronization is used.
V
V
OUT
DC Q1 =
( )
IN
V − V
(
)
IN
OUT
V
V
OUT
DC Q2 = 1−
=
( )
V
IN
IN
13
LTC1753
W U U
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APPLICATIO S I FOR ATIO
The RDS(ON) required for a given conduction loss can now
5V 1.39W
( )(
)
)
be calculated by rearranging the relation P = I2R.
R
=
=
= 0.019Ω
DS ON Q1
(
)
2
2.8V 11.2A
(
)(
V
P
P
(
)
IN MAX Q1
MAX Q1
( )
( )
5V 1.39W
( )(
)
R
=
=
=
DS ON Q1
(
)
R
= 0.025Ω
2
)
2
)
DS ON Q2
(
)
2
DC Q1 I
V
I
( ) (
]
(
)(
MAX
OUT MAX
[
5V − 2.8V 11.2A
(
)(
)
V
P
P
(
)
IN MAX Q2
MAX Q2
(
)
(
)
Note also that while the required RDS(ON) values suggest
large MOSFETs, the dissipation numbers are only 1.39W
per device or less––large TO-220 packages and heat sinks
are not necessarily required in high efficiency applica-
tions.SiliconixSi4410DYorInternationalRectifierIRF7413
(both in SO-8) or Siliconix SUD50N03 or Motorola
MTD20N03HDL (both in D PAK) are small footprint sur-
facemountdeviceswithRDS(ON) valuesbelow0.03Ωat5V
of gate drive that work well in LTC1753 circuits. With
higher output voltages, the RDS(ON) of Q1 may need to be
significantly lower than that for Q2. These conditions can
often be met by paralleling two MOSFETs for Q1 and using
a single device for Q2. Note that using a higher PMAX value
R
=
DS ON Q2
(
)
2
)
2
)
DC Q2 I
V − V
I
( ) (
(
)(
MAX
IN
OUT MAX
[
]
PMAX should be calculated based primarily on required
efficiency or allowable thermal dissipation. A typical high
efficiency circuit designed with a 5V input and a 2.8V,
11.2A output might allow no more than 4% efficiency loss
at full load for each MOSFET. Assuming roughly 90%
efficiency at this current level, this gives a PMAX value of:
[(2.8)(11.2A/0.9)(0.04)] = 1.39W per FET
and a required RDS(ON) of:
Table 4. Recommended MOSFETs for LTC1753 Applications
TYPICAL INPUT
CAPACITANCE
R
DS(ON)
PARTS
AT 25°C (mΩ)
RATED CURRENT (A)
C
(pF)
θ
(°C/W)
T
(°C)
JMAX
ISS
JC
Siliconix SUD50N03-10
D-PAK
19
15 at 25°C
10 at 100°C
3200
2700
880
1.8
175
Siliconix Si4410DY
SO-8
20
35
8
10 at 25°C
8 at 75°C
—
150
150
150
150
150
175
175
150
ON Semiconductor MTD20N03HDL
D PAK
20 at 25°C
16 at 100°C
1.67
25
Fairchild FDS6670A
SO-8
13 at 25°C
3200
2070
4025
1600
3300
1750
Fairchild FDS6680
SO-8
10
7.5
14
28
37
11.5 at 25°C
25
ON Semiconductor MTB75N03HDL
DD PAK
75 at 25°C
59 at 100°C
1.0
1.8
1.0
2.08
IR IRL3103S
DD PAK
56 at 25°C
40 at 100°C
IR IRLZ44
TO-220
50 at 25°C
36 at 100°C
Fuji 2SK1388
TO-220
35 at 25°C
Note: Please refer to the manufacturer’s data sheet for testing conditions
and detail information.
14
LTC1753
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APPLICATIO S I FOR ATIO
U
intheRDS(ON) calculationswillgenerallydecreaseMOSFET
cost and circuit efficiency while increasing MOSFET heat
sink requirements.
V − V
V
(
)(
)
IN
OUT OUT
I
=
RIPPLE
f
(
L
V
IN
)( )(
)
OSC
O
fOSC = LTC1753 oscillator frequency = 300kHz
Inductor Selection
LO = Inductor value
TheinductorisoftenthelargestcomponentintheLTC1753
design and should be chosen carefully. Inductor value and
type should be chosen based on output slew rate require-
ments, output ripple requirements and expected peak
current. Inductor value is primarily controlled by the
required current slew rate. The maximum rate of rise of
current in the inductor is set by its value, the input-to-
output voltage differential and the maximum duty cycle of
the LTC1753. In a typical 5V input, 2.8V output applica-
tion, the maximum current slew rate will be:
Solving this equation with our typical 5V to 2.8V applica-
tion with a 2µH inductor, we get:
2.2 0.56
(
)(
)
= 2A
P-P
300kHz 2µH
Peak inductor current at 11.2A load:
2A
2
11.2A +
= 12.2A
V − V
(
)
IN
OUT
1.83
L
A
µs
DC
=
MAX
The ripple current should generally be between 10% and
40% of the output current. The inductor must be able to
withstand this peak current without saturating, and the
copper resistance in the winding should be kept as low as
possible to minimize resistive power loss. Note that in
circuits not employing the current limit function, the
current in the inductor may rise above this maximum
L
where L is the inductor value in µH. With proper frequency
compensation,thecombinationoftheinductorandoutput
capacitor will determine the transient recovery time. In
general, a smaller value inductor will improve transient
responseattheexpenseofincreasedoutputripplevoltage
and inductor core saturation rating. A 2µH inductor would under short circuit or fault conditions; the inductor should
be sized accordingly to withstand this additional current.
Inductorswithgradualsaturationcharacteristicsareoften
the best choice.
have a 0.9A/µs rise time in this application, resulting in a
5.5µsdelayinrespondingtoa5Aloadcurrentstep.During
this5.5µs,thedifferencebetweentheinductorcurrentand
the output current must be made up by the output capaci-
tor, causing a temporary voltage droop at the output. To
minimize this effect, the inductor value should usually be
in the 1µH to 5µH range for most typical 5V input LTC1753
circuits. To optimize performance, different combinations
of input and output voltages and expected loads may
require different inductor values.
Input and Output Capacitors
A typical LTC1753 design puts significant demands on
both the input and the output capacitors. During constant
load operation, a buck converter like the LTC1753 draws
square waves of current from the input supply at the
switchingfrequency. Thepeakcurrentvalueisequaltothe
output load current plus 1/2 peak-to-peak ripple current,
and the minimum value is zero. Most of this current is
suppliedbytheinputbypasscapacitor. TheresultingRMS
current flow in the input capacitor will heat it up, causing
premature capacitor failure in extreme cases. Maximum
RMS current occurs with 50% PWM duty cycle, giving an
RMS current value equal to IOUT/2. A low ESR input
capacitor with an adequate ripple current rating must be
used to ensure reliable operation.
Once the required value is known, the inductor core type
can be chosen based on peak current and efficiency
requirements. Peak current in the inductor will be equal to
the maximum output load current plus half of the peak-to-
peak inductor ripple current. Ripple current is set by the
inductor value, the input and output voltage and the
operating frequency. The ripple current is approximately
equal to:
15
LTC1753
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APPLICATIO S I FOR ATIO
Note that capacitor manufacturers’ ripple current ratings
are often based on only 2000 hours (three months)
lifetime at rated temperature. Further derating of the input
capacitor ripple current beyond the manufacturer’s speci-
fication is recommended to extend the useful life of the
circuit. Lower operating temperature will have the largest
effect on capacitor longevity.
feature 2.3A allowable ripple current at 85°C; three in
parallel at the input (to withstand the input ripple current)
will meet the above requirements. Similarly, AVX
TPSE337M006R0100 (330µF/6V) have a rated maximum
ESR of 0.1Ω; seven in parallel will lower the net output
capacitor ESR to 0.014Ω. For low cost application, Sanyo
MV-GX series of capacitors can be used with acceptable
performance. The small size, low profile Sanyo OS-CON
4SP820McomeswithextremelylowESR(typically0.008Ω
at room temperature). This is an excellent choice for
output capacitor usage. However, due to the low ESR, it
requires attention to frequency compensation. Refer to
the Feedback Loop Compensation section for details.
The output capacitor in a buck converter sees much less
ripplecurrentundersteady-stateconditionsthantheinput
capacitor. Peak-to-peak current is equal to that in the
inductor, usually 10% to 40% of the total load current.
Output capacitor duty places a premium not on power
dissipation but on ESR. During an output load transient,
the output capacitor must supply all of the additional load
current demanded by the load until the LTC1753 can
adjust the inductor current to the new value. Output
capacitor ESR results in a step in the output voltage equal
to the ESR value multiplied by the change in load current.
An 11A load step with a 0.05Ω ESR output capacitor will
result in a 550mV output voltage shift; this is 19.6% of the
output voltage for a 2.8V supply! Because of the strong
relationship between output capacitor ESR and output
load transient response, the output capacitor is usually
chosenforESR,notforcapacitancevalue;acapacitorwith
suitable ESR will usually have a larger capacitance value
than is needed for energy storage.
Feedback Loop Compensation
TheLTC1753voltagefeedbackloopiscompensatedatthe
COMP pin, attached to the output node of the internal gm
error amplifier. The feedback loop can generally be com-
pensated properly with an RC + C network from COMP to
GND as shown in Figure 7a.
1µF
6
SENSE
R2
C2
LTC1753
V
FB
–
+
11
COMP
10
ERR
Electrolytic capacitors rated for use in switching power
supplies with specified ripple current ratings and ESR can
be used effectively in LTC1753 applications. OS-CON
electrolytic capacitors from Sanyo and other manufactur-
ers give excellent performance and have a very high
performance/size ratio for electrolytic capacitors. Surface
mount applications can use either electrolytic or dry
tantalum capacitors. Tantalum capacitors must be surge
tested and specified for use in switching power supplies.
Low cost, generic tantalums are known to have very short
lives followed by explosive deaths in switching power
supply applications. AVX TPS series surface mount
devices are popular surge tested tantalum capacitors that
work well in LTC1753 applications.
R1
R
C
C1
DAC
C
C
1753 F07a
Figure 7a. Compensation Pin Hook-Up
Loop stability is affected by the values of the inductor,
outputcapacitor, outputcapacitorESR, FETRDS(ON), error
amplifier transconductance and error amplifier compen-
sation network. The inductor and the output capacitor
create a double pole at the frequency:
A common way to lower ESR and raise ripple current
capabilityistoparallelseveralcapacitors.AtypicalLTC1753
application might exhibit 5A input ripple current. Sanyo
OS-CON part number 10SA220M (220µF/10V) capacitors
1
O
f
LC
=
2π√(L )(C
)
OUT
16
LTC1753
W U U
APPLICATIO S I FOR ATIO
U
poor load transient response despite the improvement in
output voltage ripple.
The ESR of the output capacitor forms a zero at the
frequency:
To resolve this problem, a small capacitor can be con-
nected between the SENSE and VFB pins to create a pole-
zero pair in the loop compensation. The zero location is
prior to the pole location and thus, phase lead can be
added to boost the phase margin at the loop crossover
frequency. The pole and zero locations are located at:
1
f
=
ESR
2π(ESR)(C
)
OUT
The compensation network at the error amplifier output is
to provide enough phase margin at the 0dB crossover
frequency for the overall closed-loop transfer function.
The zero and pole from the compensation network are:
1
1
f
=
and f
=
ZC2
PC2
1
1
C
2π(R2)(C2)
2π(R12)(C2)
f =
Z
f =
P
and
respectively.
2π(R )(C )
2π(R )(C1)
C
C
whereR12istheparallelcombinationresistanceofR1and
R2. Choose C2 so that the zero is located at a lower
frequency compared to fCO and the pole location is high
enough that the closed loop has enough phase margin for
stability. Figure 7c shows the Bode plot using phase lead
compensation around the LTC1753 internal resistor
divider network.
Figure 7b shows the Bode plot of the overall transfer
function.
The compensation value used in this design is based on
the following criteria: fSW = 12fCO, fZ = fLC and fP = 5fCO. At
the loop crossover frequency fCO, the attenuation due the
LC filter and the input resistor divider is compensated by
the gain of the PWM modulator and the gain of the error
amplifier (gmERR)(RC).
Although a mathematical approach to frequency compen-
sation can be used, the added complication of input and/
or output filters, unknown capacitor ESR, and gross
operating point changes with input voltage, load current
variations, all suggest a more practical empirical method.
Thiscanbedonebyinjectingatransientcurrentattheload
and using an RC network box to iterate toward the final
compensation values, or by obtaining the optimum loop
When low ESR output capacitors (Sanyo OS-CON) are
used, the ESR zero can be high enough in frequency that
it provides little phase boost at the loop crossover fre-
quency. Therefore, inadequate phase margin is obtained
for the system. This causes loop stability problems and
f
f
= LTC1753 SWITCHING
FREQUENCY
= CLOSED-LOOP CROSSOVER
FREQUENCY
f
f
= LTC1753 SWITCHING
FREQUENCY
= CLOSED-LOOP CROSSOVER
FREQUENCY
SW
CO
SW
CO
f
Z
f
Z
–20dB/DECADE
–20dB/DECADE
f
CO
f
P
f
P
f
PC2
f
f
FREQUENCY
LC
ESR
f
f
FREQUENCY
LC
ZC2
f
CO
f
ESR
1753 F07b
1753 F07c
Figure 7b. Bode Plot of the LTC1753 Overall Transfer Function
Figure 7c. Bode Plot of the LTC1753 Overall Transfer Function
Using a Low ESR Output Capacitor
17
LTC1753
W U U
U
APPLICATIO S I FOR ATIO
response using a network analyzer to find the actual loop
poles and zeros.
Table 7 shows the suggested compensation component
value for a 5V application based on the Sanyo OS-CON
4SP820M low ESR output capacitors
Table 5 shows the suggested compensation components
for 5V input applications based on the inductor and output
capacitor values. The values were calculated using mul-
tiple paralleled 330µF AVX TPS series surface mount
tantalum capacitors as the output capacitor. The optimum
component values might deviate from the suggested
values slightly because of board layout and operating
condition differences.
Table 7. Suggested Compensation Network for 5V Input
Application Using Multiple Paralleled 820µF Sanyo OS-CON
4SP820M Output Capacitors
L (
µ
H)
C
(
µ
F)
R (k
Ω)
C (
µ
F)
C1 (pF)
220
150
82
C2 (pF)
270
270
270
270
270
270
270
270
270
O
O
C
C
1
1640
2460
4100
1640
2460
4100
1640
2460
4100
5.6
9.1
15
16
24
39
33
47
82
0.01
1
1
0.0047
0.0047
0.0047
0.0033
0.0022
0.0033
0.0022
0.0022
2.7
2.7
2.7
5.6
5.6
5.6
82
Table 5. Suggested Compensation Network for 5V Input
Application Using Multiple Paralleled 330µF AVX TPS Output
Capacitors
56
33
L
(
µ
H)
C (
µ
F)
R (k
Ω)
C (
µ
F)
C1 (pF)
680
330
120
220
120
47
O
O
C
C
39
1
1
1
990
1980
4950
990
1.8
3.6
9.1
5.1
10
0.022
0.01
27
15
0.01
2.7
2.7
2.7
5.6
5.6
5.6
0.01
Remote Sense Considerations
1980
4950
990
0.01
In some installations such as Intel Slot 2 designs, the
regulatorisbynecessityarelativelylongdistancefromthe
load. It is desirable in these instances to connect the
regulator sense connection at the load rather than directly
at the regulator output. This forces the supply voltage to
beregulatedattheloadwhich, afterall, isthedesiredpoint
to control. In most cases no problems will be encountered
as a result of doing this. However, care must be exercised
if the power path is long or the capacitance at the load is
very large.
24
0.0047
0.01
10
120
56
1980
4950
20
0.0047
0.0033
51
22
An alternate output capacitor is the Sanyo MV-GX series.
Using multiple parallel 1500µF Sanyo MV-GX capacitors
for the output capacitor, Table 6 shows the suggested
compensation component value for a 5V input application
based on the inductor and output capacitor values.
The power distribution path has some finite amount of
inductance. There will also be a significant amount of
capacitance at the load as the local bypass. These two
circuit elements constitute a second order, lowpass filter
and the SENSE lead connects to the output of this filter. As
is true for any LC filter, there is 180° of phase shift at a
frequency beyond the double pole. If the resonant fre-
quency of the filter falls below the regulator’s feedback
loop crossover frequency, the loop will likely oscillate.
Table 6. Suggested Compensation Network for 5V Input
Application Using Multiple Paralleled 1500µF Sanyo MV-GX
Output Capacitors
L
(
µ
H)
C (
µ
F)
R (k
Ω)
C (
µ
F)
C1 (pF)
270
220
150
100
82
O
O
C
C
1
1
1
4500
6000
9000
4500
6000
9000
4500
6000
9000
4.3
5.6
8.2
11
15
22
24
30
47
0.022
0.015
0.01
2.7
2.7
2.7
5.6
5.6
5.6
0.01
0.01
0.01
56
There are a couple of measures that may be taken to
alleviate this problem. The first is to minimize the induc-
tance of the power path. Therefore, it is desirable to make
the power trace as wide as possible and as short as
0.01
56
0.0047
0.0047
39
27
18
LTC1753
W U U
APPLICATIO S I FOR ATIO
U
possible. It should also be located as close as possible
above (or below) the power ground plane. Some of the
phase shift problem can be solved by taking the AC
feedback locally at the regulator output while still taking
the DC feedback at the point of load. This permits accurate
DC regulation while still maintaining reasonable phase
margin. This is done by connecting the top of phase lead
capacitor, C2, locally at the regulator output while con-
necting the SENSE pin to the load. The corner frequency
1/(2π • R2 • C2) must be significantly less than the
resonant frequency of the parasitic inductance and the
output capacitance 1/(2π • √LDIST • CLOAD). Certain board
layouts may require RC2, a small series resistor, to de-
crease the slew rate of the feedforward path. In general, an
empirical approach to compensating this type of loop will
bebestsinceitwillbeverydifficulttoestimatetheparasitic
inductance of the power path analytically. It should be
noted that if the circuit can have a wide range of output
capacitance, this can be dangerous technique to employ
since the double-pole frequency will move as the load
capacitance changes. Be sure to verify stability with all
possible combinations of output capacitance.
VID0 to VID4, PWRGD and FAULT
Thedigitalinputs(VID0toVID4)programtheinternalDAC
which in turn controls the output voltage. These digital
input controls are intended to be static and are not
designed for high speed switching. Forcing VOUT to step
from a high to a low voltage by changing the VIDn pins
quickly can cause FAULT to trip.
Figure 9 shows the relationship between the VOUT voltage,
PWRGDandFAULT.TopreventPWRGDfrominterrupting
theCPUunnecessarily,theLTC1753hasabuilt-intPWRBAD
delay to prevent noise at the SENSE pin from toggling
PWRGD. The internal time delay is designed to take about
500µs for PWRGD to go low and 1ms for it to recover.
Once PWRGD goes low, the internal circuitry watches for
the output voltage to exceed 113% of the rated voltage. If
this happens, FAULT will be triggered. Once FAULT is
triggered, G1 and G2 will be forced low immediately and
the LTC1753 will remain in this state until VCC power
supply is recycled or OUTEN is toggled.
13%
V
OUT
3%
Q1
L
O
RATED V
OUT
L
DIST
–3%
t
LOAD
+
1µF
t
FAULT
C
OUT
PWRBAD
Q2
+
t
PWRGD
C
LOAD
PWRGD
FAULT
SENSE
6
1µF
R
C2
1753 F09
C2
LTC1753
R2
R1
V
FB
Figure 9. PWRGD and FAULT
–
+
11
COMP
10
ERR
R
C
C1
DAC
C
C
1753 F08
Figure 8. Feedback Connections for Remote Sense Applications
19
LTC1753
W U U
U
APPLICATIO S I FOR ATIO
LAYOUT CONSIDERATIONS
3. The small signal resistors and capacitors for frequency
compensation and soft-start should be located very
close to their respective pins and the ground ends
connected to the signal ground pin through a separate
trace. Do not connect these parts to the ground plane!
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1753. These items are also illustrated graphically in
the layout diagram of Figure 10. The thicker lines show the
high current paths. Note that at 10A current levels or
above, current density in the PC board itself is a serious
concern. Traces carrying high current should be as wide
as possible. For example, a PCB fabricated with 2oz
4. The VCC and PVCC decoupling capacitors should be as
close to the LTC1753 as possible. The 10µF bypass
capacitors shown at VCC and PVCC will help provide
optimum regulation performance.
copper requires a minimum trace width of 0.15
carry 10A.
" to
5. The (+) plate of CIN should be connected as close as
possible to the drain of the upper MOSFET. An addi-
tional 1µF ceramic capacitor between VIN and power
ground is recommended.
1. In general, layout should begin with the location of the
power devices. Be sure to orient the power circuitry so
that a clean power flow path is achieved. Conductor
widths should be maximized and lengths minimized.
After you are satisfied with the power path, the control
circuitry should be laid out. It is much easier to find
routes for the relatively small traces in the control
circuits than it is to find circuitous routes for high
current paths.
6. The SENSE and VFB pins are very sensitive to pickup
fromtheswitchingnode.Careshouldbetakentoisolate
SENSEandVFB frompossiblecapacitivecouplingtothe
inductor switching signal. A 1µF is required between
the SENSE pin and the SGND pin next to the LTC1753.
If PWRGD or FAULT are in the wrong logic state for
nonobviousreasons,checkthelayoutoftheSENSEand
VFB traces carefully. The 1µF capacitor should be
mounted as close to the SENSE pin as possible. In
addition, if feedforward compensation is in use, a
resistor in series with the feedforward capacitor might
be required. Finally, a low value resistor may be placed
between the output voltage and the SENSE pin (and the
1µF capacitor). This RC will help filter high frequency
spikes.
2. The GND and SGND pins should be shorted directly at
the LTC1753. This helps to minimize internal ground
disturbances in the LTC1753 and prevents differences
in ground potential from disrupting internal circuit
operation. This connection should then tie into the
groundplaneatasinglepoint,preferablyatafairlyquiet
point in the circuit such as close to the output capaci-
tors. This is not always practical, however, due to
physical constraints. Another reasonably good point to
make this connection is between the output capacitors
and the source connection of the low side FET Q2. Do
not tie this single point ground in the trace run between
the low side FET source and the input capacitor ground,
as this area of the ground plane will be very noisy.
7. OUTEN is a high impedance input and should be
externally pulled up to a logic HIGH for normal
operation.
8. Kelvin sense IMAX and IFB at Q1’s drain and source pins.
20
LTC1753
W U U
APPLICATIO S I FOR ATIO
U
V
IN
Q1
L
O
1
20
19
18
17
16
15
14
13
12
11
LTC1753
G2
PV
G1
V
OUT
PV
CC
2
3
4
OUTEN
VID0
CC
+
0.1µF
0.1µF
10µF
10µF
VID0
VID1
VID2
VID3
VID4
+
+
+
GND
C
C
IN
Q2
OUT
VID1
SGND
5.6k
VID2
5
6
5.6k
V
CC
VID3
SENSE
VID4
R
IMAX
BOLD LINES INDICATE
HIGH CURRENT PATHS
7
8
I
I
MAX
R
IFB
PWRGD
FAULT
FB
= GROUND PLANE
9
SS
1753 F10
10
COMP
V
FB
C
SS
C2
R
C
C1
1µF
C
C
Figure 10. LTC1753 Layout Diagram
21
LTC1753
U
PACKAGE DESCRIPTIO
Dimension in inches (millimeters) unless otherwise noted.
G Package
20-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
7.07 – 7.33*
(0.278 – 0.289)
20 19 18 17 16 15 14 13 12 11
7.65 – 7.90
(0.301 – 0.311)
5
7
8
1
2
3
4
6
9 10
5.20 – 5.38**
(0.205 – 0.212)
1.73 – 1.99
(0.068 – 0.078)
0° – 8°
0.65
(0.0256)
BSC
0.13 – 0.22
0.55 – 0.95
(0.005 – 0.009)
(0.022 – 0.037)
0.05 – 0.21
(0.002 – 0.008)
0.25 – 0.38
(0.010 – 0.015)
NOTE: DIMENSIONS ARE IN MILLIMETERS
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.152mm (0.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE
G20 SSOP 1098
22
LTC1753
U
PACKAGE DESCRIPTIO
Dimension in inches (millimeters) unless otherwise noted.
SW Package
20-Lead Plastic Small Outline (Wide 0.300)
(LTC DWG # 05-08-1620)
0.496 – 0.512*
(12.598 – 13.005)
19 18
16 14 13 12 11
20
17
15
0.394 – 0.419
(10.007 – 10.643)
NOTE 1
0.291 – 0.299**
(7.391 – 7.595)
2
3
5
7
8
9
10
1
4
6
0.037 – 0.045
(0.940 – 1.143)
0.093 – 0.104
(2.362 – 2.642)
0.010 – 0.029
(0.254 – 0.737)
× 45°
0° – 8° TYP
0.050
(1.270)
BSC
0.004 – 0.012
0.009 – 0.013
(0.102 – 0.305)
NOTE 1
0.016 – 0.050
(0.406 – 1.270)
(0.229 – 0.330)
0.014 – 0.019
S20 (WIDE) 1098
(0.356 – 0.482)
TYP
NOTE:
1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
23
LTC1753
U
TYPICAL APPLICATIO
V
IN
5V
+
C
**
+
IN
1N5817
1200µF
× 3
0.1µF
10µF
820Ω
5.6k
5.6k
0.1µF
V
I
PV
CC
CC
†
MAX
L
O
PWRGD
FAULT
Q1*
1.3µH
14A
G1
20Ω
V
OUT
CPU
I
5
FB
14A
††
LTC1753
C
+
VID0 TO VID4
OUTEN
OUT
2700µF
G2
Q2*
5V
× 5
V
FB
1.8k
DALE
COMP
SGND
GND SENSE
SS
270pF
R
15k
C1
150pF
C
NTHS-1206N02
MOUNT THERMISTER
IN CLOSE THERMAL
PROXIMITY TO Q1
C
C
* SILICONIX Si4410
C
SS
1µF
** SANYO 10MV1200GX
† PANASONIC ETQP 6FIR3LFA
†† SANYO 6MV2700GX
4700pF 0.1µF
1753 F11
Figure 11. Single Supply LTC1753 5V to 1.3V-3.5V Application with Thermal Monitor
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No R
and PolyPhase are trademarks of Linear Technology Corporation.
SENSE
1753f LT/TP 0400 4K • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
●
●
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
LINEAR TECHNOLOGY CORPORATION 1998
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