LTC1660CGN [Linear]
Micropower Octal 8-Bit and 10-Bit DACs; 微八路8位和10位DAC
| 型号： | LTC1660CGN |
| 厂家： | 
Linear |
| 描述： | Micropower Octal 8-Bit and 10-Bit DACs |
| 文件： | 总16页 (文件大小：212K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1665/LTC1660
Micropower Octal
8-Bit and 10-Bit DACs
U
FEATURES
DESCRIPTIO
The 8-bit LTC®1665 and 10-bit LTC1660 integrate eight
accurate, serially addressable digital-to-analog convert-
ers (DACs) in tiny 16-pin narrow SSOP packages. Each
buffered DAC draws just 56µA total supply current, yet is
capable of supplying DC output currents in excess of
5mA and reliably driving capacitive loads to 1000pF.
Sleep mode further reduces total supply current to 1µA.
■
Tiny: 8 DACs in the Board Space of an SO-8
Micropower: 56µA per DAC Plus
■
1µA Sleep Mode for Extended Battery Life
Pin Compatible 8-Bit LTC1665 and 10-Bit LTC1660
Wide 2.7V to 5.5V Supply Range
Rail-to-Rail Voltage Outputs Drive 1000pF
Reference Range Includes Supply for Ratiometric
0V-to-VCC Output
■
■
■
■
Linear Technology’s proprietary, inherently monotonic
voltage interpolation architecture provides excellent lin-
earity while allowing for an exceptionally small external
form factor.
■
Reference Input Impedance is Constant—
Eliminates External Buffer
U
APPLICATIO S
Ultralow supply current, power-saving Sleep mode and
extremelycompactsizemaketheLTC1665andLTC1660
idealforbattery-poweredapplications,whiletheireaseof
use,highperformanceandwidesupplyrangemakethem
excellent choices as general purpose converters.
, LTC and LT are registered trademarks of Linear Technology Corporation.
■
Mobile Communications
■
Remote Industrial Devices
■
Automatic Calibration for Manufacturing
■
Portable Battery-Powered Instruments
■
Trim/Adjust Applications
W
BLOCK DIAGRA
LTC1665 Differential Nonlinearity (DNL)
0.5
V
V
= 5V
REF
CC
0.4
0.3
= 4.096V
GND
1
16
15
V
V
CC
0.2
DAC A
DAC B
DAC C
DAC D
DAC H
DAC G
DAC F
DAC E
V
V
V
V
2
0.1
OUT A
OUT H
0
–0.1
–0.2
–0.3
–0.4
–0.5
V
OUT G
V
OUT F
V
OUT E
3
4
14
13
OUT B
OUT C
0
64
128
192
255
CODE
1665/60 G09
LTC1660 Differential Nonlinearity (DNL)
1
V
V
= 5V
REF
CC
0.8
0.6
= 4.096V
5
6
7
8
12
11
10
9
OUT D
0.4
REF
CLR
D
0.2
0
CONTROL
LOGIC
ADDRESS
DECODER
CS/LD
SCK
–0.2
–0.4
–0.6
–0.8
–1
OUT
SHIFT REGISTER
D
IN
1665/60 BD
0
256
512
768
1023
CODE
1665/60 G13
1
LTC1665/LTC1660
W
U
W W W
U
/O
ABSOLUTE AXI U RATI GS
PACKAGE RDER I FOR ATIO
(Note 1)
VCC to GND .............................................. –0.2V to 7.5V
Logic Inputs to GND ................................ –0.2V to 7.5V
ORDER PART
TOP VIEW
NUMBER
VOUT A, VOUT B…VOUT H
,
1
2
3
4
5
6
7
8
V
V
V
V
V
16
15
14
13
12
11
10
9
GND
CC
LTC1665CGN
LTC1665CN
LTC1665IGN
LTC1665IN
LTC1660CGN
LTC1660CN
LTC1660IGN
LTC1660IN
REF to GND ................................. –0.2V to (VCC + 0.2V)
Maximum Junction Temperature ......................... 125°C
Operating Temperature Range
LTC1665C/LTC1660C ............................ 0°C to 70°C
LTC1665I/LTC1660I .......................... –40°C to 85°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................ 300°C
V
V
V
V
OUT H
OUT G
OUT F
OUT E
OUT A
OUT B
OUT C
OUT D
REF
CLR
D
CS/LD
SCK
OUT
D
IN
GN PACKAGE
N PACKAGE
16-LEAD PLASTIC SSOP
16-LEAD PDIP
GN PART MARKING
TJMAX = 125°C, θJA = 150°C/W (GN)
JMAX = 125°C, θJA = 100°C/W (N)
T
1665
1660
1665I 1660I
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications
are at TA = 25°C. VCC = 2.7V to 5.5V, VREF ≤ VCC, VOUT unloaded, unless otherwise noted.
LTC1665
TYP
LTC1660
TYP
SYMBOL PARAMETER
Accuracy
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
Resolution
●
●
●
●
●
●
●
●
8
8
10
10
Bits
Bits
Monotonicity
V
V
V
≤ V – 0.1V (Note 2)
CC
REF
REF
REF
DNL
INL
Differential Nonlinearity
≤ V – 0.1V (Note 2)
±0.1
±0.2
±10
±15
±1
±0.5
±1.0
±30
±0.2 ±0.75
LSB
CC
Integral Nonlinearity
Offset Error
≤ V – 0.1V (Note 2)
±0.6
±10
±15
±3
±2.5
±30
LSB
CC
V
(Note 7)
mV
OS
V
Temperature Coefficient
µV/°C
LSB
OS
FSE
Full-Scale Error
V
V
= 5V, V = 4.096V
±4
±15
CC
REF
Full-Scale Error Temperature Coefficient
Power Supply Rejection
±30
0.045
±30
0.18
µV/°C
LSB/V
PSR
= 2.5V
REF
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications
are at TA = 25°C. VCC = 2.7V to 5.5V, VREF ≤ VCC, VOUT unloaded, unless otherwise noted.
SYMBOL PARAMETER
Reference Input
CONDITONS
MIN
TYP
MAX
UNITS
Input Voltage Range
●
●
0
V
V
kΩ
pF
CC
Resistance
Not in Sleep Mode
(Note 6)
35
65
15
Capacitance
I
Reference Current
Sleep Mode
●
0.001
1
µA
REF
Power Supply
V
Positive Supply Voltage
Supply Current
For Specified Performance
●
2.7
5.5
V
CC
I
V
CC
V
CC
= 5V (Note 3)
= 3V (Note 3)
●
●
●
450
340
1
730
550
3
µA
µA
µA
CC
Sleep Mode (Note 3)
2
LTC1665/LTC1660
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications
are at TA = 25°C. VCC = 2.7V to 5.5V, VREF ≤ VCC, VOUT unloaded, unless otherwise noted.
SYMBOL PARAMETER
DC Performance
CONDITIONS
MIN
TYP
MAX
UNITS
Short-Circuit Current Low
Short-Circuit Current High
AC Performance
V
V
= 0V, V = 5.5V, V = 5.1V, Code = Full Scale
●
●
10
10
30
27
100
120
mA
mA
OUT
OUT
CC
REF
= V = 5.5V, V = 5.1V, Code = 0
CC
REF
Voltage Output Slew Rate
Rising (Notes 4, 5)
Falling (Notes 4, 5)
0.60
0.25
V/µs
V/µs
Voltage Output Settling Time
Capacitive Load Driving
To ±0.5LSB (Notes 4, 5)
30
µs
1000
pF
Digital I/O
V
Digital Input High Voltage
Digital Input Low Voltage
V
V
= 2.7V to 5.5V
= 2.7V to 3.6V
●
●
2.4
2.0
V
V
IH
CC
CC
V
V
V
= 4.5V to 5.5V
= 2.7V to 5.5V
●
●
0.8
0.6
V
V
IL
CC
CC
V
V
Digital Output High Voltage
Digital Output Low Voltage
Digital Input Leakage
I
I
= –1mA, D
Only
●
●
●
●
V – 1
CC
V
V
OH
OL
OUT
OUT
OUT
= 1mA, D
Only
0.4
±10
10
OUT
I
V
= GND to V
CC
µA
pF
LK
IN
C
Digital Input Capacitance
(Note 6)
IN W U
The ● denotes specifications which apply over the full operating temperature
TI I G CHARACTERISTICS
range, otherwise specifications are at TA = 25°C. (See Figure 1)
SYMBOL PARAMETER
= 4.5V to 5.5V
CONDITIONS
MIN
TYP
MAX
UNITS
V
CC
t
t
t
t
t
t
t
t
t
t
t
D
D
Valid to SCK Setup
Valid to SCK Hold
●
●
●
●
●
●
●
●
●
●
●
40
0
15
–11
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
IN
IN
2
SCK High Time
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
30
30
80
30
80
5
3
SCK Low Time
7
4
CS/LD Pulse Width
LSB SCK High to CS/LD High
CS/LD Low to SCK High
30
4
5
6
26
26
0
7
D
OUT
Propagation Delay
C = 15pF (Note 6)
LOAD
80
8
SCK Low to CS/LD Low
CLR Pulse Width
(Note 6)
(Note 6)
(Note 6)
20
100
30
9
37
0
10
11
CS/LD High to SCK Positive Edge
SCK Frequency
Continuous Square Wave (Note 6)
Continuous 23% Duty Cycle Pulse (Note 6)
Gated Square Wave (Note 6)
●
●
●
5.00
7.69
16.7
MHz
MHz
MHz
V
= 2.7V to 5.5V
CC
t
t
t
t
t
D
Valid to SCK Setup
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
●
●
●
●
●
60
0
20
–14
8
ns
ns
ns
ns
ns
1
IN
IN
D
Valid to SCK Hold
2
3
4
5
SCK High Time
SCK Low Time
50
50
100
12
30
CS/LD Pulse Width
3
LTC1665/LTC1660
W U
The ● denotes specifications which apply over the full operating temperature
TI I G CHARACTERISTICS
range, otherwise specifications are at TA = 25°C. (See Figure 1)
SYMBOL PARAMETER
CONDITIONS
(Note 6)
MIN
50
TYP
5
MAX
UNITS
ns
t
t
t
t
t
t
LSB SCK High to CS/LD High
CS/LD Low to SCK High
●
●
●
●
●
●
6
(Note 6)
100
5
27
47
0
ns
7
D
OUT
Propagation Delay
C = 15pF (Note 6)
LOAD
150
ns
8
SCK Low to CS/LD Low
CLR Pulse Width
(Note 6)
(Note 6)
(Note 6)
30
ns
9
120
30
41
0
ns
10
11
CS/LD High to SCK Positive Edge
SCK Frequency
ns
Continuous Square Wave (Note 6)
Continuous 28% Duty Cycle Pulse
Gated Square Wave
●
●
●
3.85
5.55
10
MHz
MHz
MHz
Note 1: Absolute maximum ratings are those values beyond which the life
of a device may be impaired.
Note 2: Nonlinearity and monotonicity are defined from code 4 to code
255 for the LTC1665 and from code 20 to code 1023 for the LTC1660.
See Applications Information.
Note 5: V = V = 5V. DAC switched between 0.1V and 0.9V ,
CC REF FS FS
i.e., codes 26 and 230 for the LTC1665 or codes 102 and 922 for the
LTC1660.
Note 6: Guaranteed by design and not production tested.
Note 7: Measured at code 4 for the LTC1665 and code 20 for the
Note 3: Digital inputs at 0V or V
.
CC
LTC1660.
Note 4: Load is 10kΩ in parallel with 100pF.
U W
(LTC1665/LTC1660)
TYPICAL PERFOR A CE CHARACTERISTICS
Midscale Output Voltage
vs Load Current
Midscale Output Voltage
vs Load Current
3
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2
2
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
V
= V
CC
V
= V
CC
REF
REF
CODE = 128 (LTC1665)
CODE = 512 (LTC1660)
CODE = 128 (LTC1665)
CODE = 512 (LTC1660)
V
= 3.6V
CC
V
V
= 5.5V
= 5V
CC
V
= 3V
CC
CC
V
CC
= 2.7V
V
CC
= 4.5V
SOURCE
–10
SINK
10
SOURCE
–15 –12 –8 –4
SINK
4
–30
–20
0
20
30
0
8
12 15
I
(mA)
I
(mA)
OUT
OUT
1665/60 G01
1665/60 G02
4
LTC1665/LTC1660
U W
TYPICAL PERFOR A CE CHARACTERISTICS
(LTC1665/LTC1660)
Minimum VOUT vs
Load Current (Output Sinking)
Minimum Supply Headroom vs
Load Current (Output Sourcing)
1400
1200
1000
800
600
400
200
0
1400
1200
1000
800
600
400
200
0
V
= 5V
V
= 4.096V
OUT
CC
REF
CODE = 0
∆V
< 1LSB
125°C
CODE = 255 (LTC1665)
CODE = 1023 (LTC1660)
125°C
25°C
25°C
–55°C
–55°C
0
2
4
6
8
10
0
2
4
6
8
10
|I
|
(mA) (Sourcing)
|I
|
(mA) (Sinking)
OUT
OUT
1665/60 G03
1665/60 G04
Supply Current vs Temperature
Large-Signal Step Response
Supply Current vs Logic Input Voltage
5
4
3
2
1
0
500
480
460
440
420
400
380
360
340
320
300
2
1.6
1.2
0.8
0.4
0
V
CC
= V
= 5V
ALL DIGITAL INPUTS
SHORTED TOGETHER
REF
10% TO
90% STEP
V
V
= 5.5V
= 4.5V
CC
CC
V
CC
= 3.6V
V
CC
= 2.7V
0
20
40
60
80
100
–55 –35 –15
5
25 45 65 85 105 125
0
1
2
3
4
5
TIME (µs)
TEMPERATURE (°C)
LOGIC INPUT VOLTAGE (V)
1665/60 G05
1665/60 G06
1665/60 G07
U W
(LTC1665)
TYPICAL PERFOR A CE CHARACTERISTICS
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
1
0.8
0.5
0.4
V
V
= 5V
REF
V
V
= 5V
REF
CC
CC
= 4.096V
= 4.096V
0.6
0.3
0.4
0.2
0.2
0.1
0
0
–0.2
–0.4
–0.6
–0.8
–1
–0.1
–0.2
–0.3
–0.4
–0.5
0
64
128
192
255
0
64
128
192
255
CODE
CODE
1665/60 G09
1665/60 G08
5
LTC1665/LTC1660
U W
(LTC1665)
TYPICAL PERFOR A CE CHARACTERISTICS
Load Regulation vs Output Current
Load Regulation vs Output Current
V
= V
= 3V
V
= V
= 5V
REF
0.5
0.25
0
CC
REF
0.5
0.25
0
CC
CODE = 128
CODE = 128
–0.25
–0.5
–0.25
–0.5
SOURCE
SINK
SOURCE
–1
SINK
–500
0
500
–2
0
1
2
I
(µA)
I
(mA)
OUT
OUT
1665/60 G11
1665/60 G10
U W
(LTC1660)
TYPICAL PERFOR A CE CHARACTERISTICS
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
2.5
2.0
1
0.8
V
V
= 5V
REF
V
V
= 5V
REF
CC
CC
= 4.096V
= 4.096V
1.5
0.6
1.0
0.4
0.5
0.2
0
0
–0.5
–1.0
–1.5
–2.0
–2.5
–0.2
–0.4
–0.6
–0.8
–1
0
256
512
768
1023
0
256
512
768
1023
CODE
CODE
1665/60 G13
1665/60 G12
Load Regulation vs Output Current
Load Regulation vs Output Current
V
= V
= 5V
REF
V
= V
= 3V
2
1.5
1
2
1.5
1
CC
CODE = 512
CC
REF
CODE = 512
0.5
0
0.5
0
–0.5
–1
–0.5
–1
–1.5
–2
–1.5
–2
SOURCE
–1
SINK
SOURCE
SINK
–2
0
1
2
–500
0
500
I
(mA)
I
(µA)
OUT
OUT
1665/60 G14
1665/60 G15
6
LTC1665/LTC1660
U
U
U
PIN FUNCTIONS
(LTC1665/LTC1660)
GND (Pin 1): System Ground.
SCK (Pin 8): Serial Interface Clock Input. CMOS and TTL
compatible.
VOUT A to VOUT H (Pins 2-5 and 12-15): DAC Analog
Voltage Outputs. The output range is
DIN (Pin 9): Serial Interface Data Input. Data on the DIN pin
is shifted into the 16-bit register on the rising edge of SCK.
CMOS and TTL compatible.
255
256
0 to
0 to
VREF for the LTC1665
VREF for the LTC1660
DOUT (Pin 10): Serial Interface Data Output. Data appears
1023
1024
on DOUT 16 positive SCK edges after being applied to DIN.
MaybetiedtoDIN ofanotherLTC1665/LTC1660fordaisy-
chain operaton. CMOS and TTL compatible.
REF (Pin 6): Reference Voltage Input. 0V ≤ VREF ≤ VCC.
CLR (Pin 11): Asynchronous Clear Input. All internal shift
and DAC registers are cleared to zero at the falling edge of
the CLR signal, forcing the analog outputs to zero scale.
CMOS and TTL compatible.
CS/LD (Pin 7): Serial Interface Chip Select/Load Input.
WhenCS/LDislow, SCKisenabledforshiftingdataonDIN
into the register. When CS/LD is pulled high, SCK is
disabled and data is loaded from the shift register into the
specified DAC register(s), updating the analog output(s).
CMOS and TTL compatible.
VCC (Pin 16): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V.
W
BLOCK DIAGRA
GND
1
2
16
15
V
V
CC
DAC A
DAC B
DAC C
DAC D
DAC H
DAC G
DAC F
DAC E
V
V
V
V
OUT A
OUT H
V
V
V
3
4
14
13
OUT B
OUT C
OUT G
OUT F
OUT E
5
6
7
8
12
11
10
9
OUT D
REF
CLR
CONTROL
LOGIC
ADDRESS
DECODER
CS/LD
SCK
D
D
OUT
SHIFT REGISTER
IN
1665/60 BD
7
LTC1665/LTC1660
W U
W
TI I G DIAGRA
t
1
t
t
t
3
t
4
6
2
SCK
t
t
11
9
D
IN
A1
X1
A3
A2
X0
t
t
7
5
CS/LD
t
8
D
A2
A1
X1
X0
A3
A3
OUT
1665/60 F01
Figure 1
U
OPERATIO
Serial Interface
Transfer Function
Referring to Figure 2a (2b): With CS/LD held low, data on
the DIN input is shifted into the 16-bit shift register on the
positive edge of SCK. The 4-bit DAC address, A3-A0, is
loaded first (see Table 2), then the 8-bit (10-bit) input
code, D7-D0 (D9-D0), ordered MSB-to-LSB in each case.
Four(two)don’t-carebits,X3-X0(X1-X0),areloadedlast.
Whenthefull16-bitinputwordhasbeenshiftedin, CS/LD
is pulled high, loading the DAC register with the word and
causing the addressed DAC output(s) to update. The
clockisdisabledinternallywhenCS/LDishigh. Note: SCK
must be low before CS/LD is pulled low.
The transfer function is
k
256
k
VOUT(IDEAL)
VOUT(IDEAL)
=
=
VREF for theLTC1665
VREF for theLTC1660
1024
where k is the decimal equivalent of the binary DAC input
code and VREF is the voltage at REF (Pin 6).
Power-On Reset
The buffered serial output of the shift register is available
on the DOUT pin, which swings from GND to VCC. Data
appearsonDOUT 16positiveSCKedgesafterbeingapplied
to DIN.
The LTC1665 clears the outputs to zero scale when power
isfirstapplied,makingsysteminitializationconsistentand
repeatable.
Power Supply Sequencing
Multiple LTC1665/LTC1660’s can be controlled from a
single 3-wire serial port (i.e., SCK, DIN and CS/LD) by
using the included “daisy-chain” facility. A series of m
chips is configured by connecting each DOUT (except the
last) to DIN of the next chip, forming a single 16m-bit shift
register. The SCK and CS/LD signals are common to all
The voltage at REF (Pin 6) should be kept within the range
–0.2V ≤ VREF ≤ VCC + 0.2V (see Absolute Maximum
Ratings). Particular care should be taken to observe these
limitsduringpowersupplyturn-onandturn-offsequences,
when the voltage at VCC (Pin 16) is in transition.
8
LTC1665/LTC1660
U
OPERATIO
SCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
X3
X2
X1
X0
D
IN
ADDRESS/CONTROL
INPUT CODE
DON’T CARE
INPUT WORD W
0
(ENABLE CLK)
(UPDATE OUTPUT)
CS/LD
D
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
X3
X2
X1
X0
A3
OUT
INPUT WORD W
INPUT WORD W
–1
0
1665/60 F02a
Figure 2a. LTC1665 Register Loading Sequence
SCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A3
A2
A1
A0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X1
X0
D
IN
ADDRESS/CONTROL
INPUT CODE
DON’T CARE
INPUT WORD W
0
(ENABLE CLK)
(UPDATE OUTPUT)
CS/LD
D
A3
A2
A1
A0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X1
X0
A3
OUT
INPUT WORD W
INPUT WORD W
–1
0
1665/60 F02b
Figure 2b. LTC1660 Register Loading Sequence
Table 1a. LTC1665 Input Word
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 X3 X2 X1 X0
chips in the chain. In use, CS/LD is held low while m
16-bit words are clocked to DIN of the first chip; CS/LD is
then pulled high, updating all of them simultaneously.
Address/Control
Input Code
Don’t Care
Sleep Mode
Table 1b. LTC1660 Input Word
A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X1 X0
DAC address 1110b is reserved for the special Sleep
instruction(seeTable2). Inthismode, thedigitalinterface
stays active while the analog circuits are disabled; static
power consumption is thus virtually eliminated. The refer-
ence input and analog outputs are set in a high impedance
Address/Control
Input Code
Don’t
Care
9
LTC1665/LTC1660
U
OPERATIO
Table 2. DAC Address/Control Functions
Voltage Outputs
ADDRESS/CONTROL
Each of the eight rail-to-rail output amplifiers contained in
these parts can source or sink up to 5mA. The outputs
swing to within a few millivolts of either supply rail when
unloadedandhaveanequivalentoutputresistanceof85Ω
when driving a load to the rails. The output amplifiers are
stable driving capacitive loads up to 1000pF.
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DAC STATUS
No Change
Load DAC A
Load DAC B
Load DAC C
Load DAC D
Load DAC E
Load DAC F
Load DAC G
Load DAC H
No Change
No Change
No Change
No Change
No Change
No Change
SLEEP STATUS
Wake
Wake
Wake
Wake
Wake
A small resistor placed in series with the output can be
used to achieve stability for any load capacitance. A 1µF
load can be successfully driven by inserting a 20Ω resis-
tor; a 2.2µF load needs only a 10Ω resistor. In either case,
larger values of resistance, capacitance or both may be
safely substituted for the values given.
Wake
Wake
Wake
Wake
Wake
Wake
Wake
Rail-to-Rail Output Considerations
Wake
In any rail-to-rail output voltage DAC, the output is limited
to voltages within the supply range.
Wake
Sleep
Wake
If the DAC offset is negative, the output for the lowest
codes limits at 0V as shown in Figure 3b.
Load ALL DACs
with Same
8/10-Bit Code
Similarly, limiting can occur near full scale when the REF
pin is tied to VCC. If VREF = VCC and the DAC full-scale error
(FSE) is positive, the output for the highest codes limits at
VCC as shown in Figure 3c. No full-scale limiting can occur
if VREF is less than VCC – FSE.
state and all DAC settings are retained in memory so that
when Sleep mode is exited, the outputs of DACs not
updated by the Wake command are restored to their last
active state.
Sleep mode is initiated by performing a load sequence to
address 1110b (the DAC input word D7-D0 [D9-D0] is
ignored). Once in Sleep mode, a load sequence to any
other address (including “No Change” addresses 0000b
and 1001-1101b) causes the LTC1665/LTC1660 to Wake.
It is possible to keep one or more chips of a daisy chain in
continuous Sleep mode by giving the Sleep instruction to
these chips each time the active chips in the chain are
updated.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
10
LTC1665/LTC1660
U
OPERATIO
POSITIVE
FSE
V
= V
CC
REF
OUTPUT
VOLTAGE
INPUT CODE
(c)
V
REF
= V
CC
OUTPUT
VOLTAGE
0
128
255
INPUT CODE
(a)
OUTPUT
VOLTAGE
0V
NEGATIVE
OFFSET
INPUT CODE
(b)
1665/60 F03
Figure 3. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative
Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When VREF = VCC
11
LTC1665/LTC1660
U
TYPICAL APPLICATIONS
A Low Power Quad Trim Circuit with Coarse/Fine Adjustment
3.3V
4
3.3V
R1
R2
0.1µF
0.1µF
R2
R1
U1
V
V
CC
GND
–
–
1
2
16
15
13
12
LTC1665
2
14
1
U2A
U2D
LT1491
R1
R1
LT®1491
COARSE
COARSE
V
OUT1
V
OUT4
V
V
V
+ 3
+
OUT A
OUT H
OUT G
OUT F
OUT E
DAC A
DAC B
DAC C
DAC D
DAC H
DAC G
DAC F
DAC E
11
0.1µF
0.1µF
R2
FINE
R2
FINE
V
V
V
OUT B
OUT C
R1
R2
R2
R1
3
4
14
13
–
6
–
9
8
7
U2B
LT1491
U2C
LT1491
R1
R1
COARSE
COARSE
V
V
OUT2
+ 5
10
+
OUT3
0.1µF
0.1µF
R2
FINE
R2
FINE
3.3V
0.1µF
V
OUT D
5
6
7
8
12
11
10
9
2
1
REF
CLR
LTC1258-2.5
4
CONTROL
LOGIC
ADDRESS
DECODER
D
OUT
IN
CS/LD
SCK
TO OTHER
LTC1665s
3-WIRE
D
SHIFT REGISTER
SERIAL
INTERFACE
1665/60 TA01
R2 >> R1
= V
R1
V
+
V
OUT B
OUT 1
OUT A
)
)
R2
Similarly V
, V
, V
OUT 2 OUT 3 OUT 4
Example: For R1 = 110Ω and R2 = 11k,
= V + 0.01 V
V
OUT 1
OUT A
OUT B
12
LTC1665/LTC1660
U
TYPICAL APPLICATIONS
An 8-Channel Bipolar Output Voltage Circuit Configuration
5V
R
R
R
R
0.1µF
0.1µF
0.1µF
+
+
V
V
4
S
S
U1
V
V
CC
GND
4
–
–
1
2
16
15
LTC1660
2
2
3
1
1
V
′
V
′
U2A
LT1491
U3A
LT1491
OUT A
±5V
OUT H
±5V
V
+
3
OUT A
OUT H
+
DAC A
DAC H
0.1µF
0.1µF
11
R
11
–
–
V
V
S
S
R
R
R
R
R
R
R
R
R
–
–
6
5
6
5
7
8
7
V
V
V
′
V
′
U2B
LT1491
U3B
LT1491
OUT B
OUT G
±5V
±5V
V
V
V
V
V
OUT B
OUT G
OUT F
OUT E
+
+
DAC B
DAC C
DAC D
DAC G
DAC F
DAC E
3
4
14
13
R
R
–
9
–
9
8
′
V
′
U2C
LT1491
U3C
LT1491
OUT C
OUT F
±5V
±5V
OUT C
+
10
10
+
–
+
–
13
13
12
14
14
′
V
′
U2D
LT1491
U3D
LT1491
OUT D
OUT E
±5V
±5V
V
OUT D
12
+
5
6
7
8
12
11
10
9
REF
CLR
D
CONTROL
LOGIC
ADDRESS
DECODER
CS/LD
CLK
CODE
0
512
V
OUT X
– 5V
0V
OUT
3-WIRE
SERIAL
D
IN
SHIFT REGISTER
INTERFACE
1023 +4.99V
1665/60 TA01
13
LTC1665/LTC1660
U
PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted.
GN Package
16-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
0.189 – 0.196*
(4.801 – 4.978)
0.009
(0.229)
REF
16 15 14 13 12 11 10 9
0.229 – 0.244
(5.817 – 6.198)
0.150 – 0.157**
(3.810 – 3.988)
1
2
3
4
5
6
7
8
0.015 ± 0.004
(0.38 ± 0.10)
× 45°
0.053 – 0.068
(1.351 – 1.727)
0.004 – 0.0098
(0.102 – 0.249)
0.007 – 0.0098
(0.178 – 0.249)
0° – 8° TYP
0.016 – 0.050
(0.406 – 1.270)
0.0250
(0.635)
BSC
0.008 – 0.012
(0.203 – 0.305)
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
GN16 (SSOP) 1098
14
LTC1665/LTC1660
U
PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
N Package
16-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.770*
(19.558)
MAX
14
12
10
9
8
15
13
11
16
0.255 ± 0.015*
(6.477 ± 0.381)
2
1
3
4
6
5
7
0.300 – 0.325
0.130 ± 0.005
0.045 – 0.065
(7.620 – 8.255)
(3.302 ± 0.127)
(1.143 – 1.651)
0.020
(0.508)
MIN
0.065
(1.651)
TYP
0.009 – 0.015
(0.229 – 0.381)
+0.035
–0.015
0.325
0.125
(3.175)
MIN
0.018 ± 0.003
(0.457 ± 0.076)
0.100
(2.54)
BSC
+0.889
8.255
(
)
–0.381
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
N16 1098
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
15
LTC1665/LTC1660
U
TYPICAL APPLICATION
A Pin Driver VH and VL Adjustment Circuit for ATE Applications
5V
0.1µF
11
16
6
V
CLR
V
REF
H
CC
(FROM MAIN DAC)
U1 LTC1660
10V
0.1µF
1
R
F
R
G
5k
50k
V
A
V
B
V
C
V
D
3
2
′
DAC H
DAC A
V
H
2
3
4
5
+
U2A
LT1369
QUAD
′
V
= V + ∆V
H
H
H
′
V
L
0.1µF
–
R
G
0.1µF
50k
–5V
DAC G
DAC F
DAC E
DAC B
DAC C
DAC D
R
F
5k
V
L
V
V
H
(FROM MAIN DAC)
L
R
F
5k
V
OUT
R
50k
G
PIN DRIVER
(1 OF 2)
5
6
+
′
V
= V + ∆V
L L
U2B
L
7
LT1369
QUAD
0.1µF
–
LOGIC
DRIVE
R
50k
R
F
5k
G
1665/60 TA03
CS/LD
7
9
8
D
IN
V = V = 2.5V
A
C
SCK
GND
1
′
R
V
V
= V +
F
H
H
(V – V )
A
B
R
G
′
R
= V +
F
L
L
(V – V )
C
D
CODE A CODE B ∆V , ∆V
H
L
R
G
512
512
512
1023 –250mV
Note: DACs E Through H Can Be
Configured for a Second Pin Driver
With U2C and U2D of the LT1369
For Resistor Values Shown:
Adjustment Range = ±250mV
Adjustment Step Size = 500µV
512
0
0
+250mV
RELATED PARTS
PART NUMBER
LTC1661
DESCRIPTION
Dual 10-Bit V
COMMENTS
DAC in 8-Lead MSOP Package
V
V
= 2.7V to 5.5V Micropower Rail-to-Rail Output
OUT
CC
CC
LTC1663
Single 10-Bit V
DAC in SOT-23 Package
= 2.7V to 5.5V, Internal Reference, 60µA
OUT
LTC1446/LTC1446L
Dual 12-Bit V
DACs in SO-8 Package with Internal Reference
LTC1446: V = 4.5V to 5.5V, V
= 0V to 4.095V
OUT
OUT
CC
OUT
LTC1446L: V = 2.7V to 5.5V, V
= 0V to 2.5V
CC
LTC1448
Dual 12-Bit V
Dual 12-Bit V
DAC in SO-8 Package
V
= 2.7V to 5.5V, External Reference Can Be Tied to V
CC CC
OUT
LTC1454/LTC1454L
DACs in SO-16 Package with Added Functionality LTC1454: V = 4.5V to 5.5V, V
= 0V to 4.095V
= 0V to 2.5V
OUT
CC
OUT
LTC1454L: V = 2.7V to 5.5V, V
CC
OUT
LTC1458/LTC1458L
Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality
Dual 12-Bit I DAC in SO-16 Package
LTC1458: V = 4.5V to 5.5V, V
= 0V to 4.095V
OUT
CC
OUT
LTC1458L: V = 2.7V to 5.5V, V
= 0V to 2.5V
CC
LTC1590
LTC1659
V
= 4.5V to 5.5V, 4-Quadrant Multiplication
CC
OUT
Single Rail-to-Rail 12-Bit V
DAC in 8-Lead MSOP Package
Low Power Multiplying V
DAC. Output Swings from
OUT
OUT
V
: 2.7V to 5.5V
GND to REF. REF Input Can Be Tied to V
CC
CC
LT1460
Micropower Precision Series Reference, 2.5V, 5V, 10V Versions
0.075% Max, 10ppm/°C Max, Only 130µA Supply Current
166560f LT/TP 0999 4K • PRINTED IN THE USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
16
●
●
LINEAR TECHNOLOGY CORPORATION 1999
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
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