LTC1660IGN#PBF [Linear]
LTC1660 - Micropower Octal 10-Bit DACs; Package: SSOP; Pins: 16; Temperature Range: -40°C to 85°C;
| 型号： | LTC1660IGN#PBF |
| 厂家： | 
Linear |
| 描述： | LTC1660 - Micropower Octal 10-Bit DACs; Package: SSOP; Pins: 16; Temperature Range: -40°C to 85°C 光电二极管 转换器 |
| 文件： | 总18页 (文件大小：239K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1665/LTC1660
Micropower Octal
8-Bit and 10-Bit DACs
DESCRIPTION
The 8-bit LTC®1665 and 10-bit LTC1660 integrate eight
accurate, serially addressable digital-to-analog convert-
ers (DACs) in tiny 16-pin narrow SSOP packages. Each
buffered DAC draws just 56μA total supply current, yet
is capable of supplying DC output currents in excess
of 5mA and reliably driving capacitive loads to 1000pF.
Sleep mode further reduces total supply current to 1μA.
FEATURES
n
Tiny: 8 DACs in the Board Space of an SO-8
n
Micropower: 56μA per DAC Plus
1μA Sleep Mode for Extended Battery Life
n
Pin Compatible 8-Bit LTC1665 and 10-Bit LTC1660
n
Wide 2.7V to 5.5V Supply Range
n
Rail-to-Rail Voltage Outputs Drive 1000pF
n
Reference Range Includes Supply for Ratiometric
0V-to-V Output
CC
LinearTechnology’sproprietary,inherentlymonotonicvolt-
age interpolation architecture provides excellent linearity
whileallowingforanexceptionallysmallexternalformfactor.
n
Reference Input Impedance is Constant—
Eliminates External Buffer
APPLICATIONS
Ultralow supply current, power-saving Sleep mode and
extremelycompactsizemaketheLTC1665andLTC1660
ideal for battery-powered applications, while their ease
of use, high performance and wide supply range make
them excellent choices as general purpose converters.
n
Mobile Communications
n
Remote Industrial Devices
n
Automatic Calibration for Manufacturing
Portable Battery-Powered Instruments
n
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
n
Trim/Adjust Applications
LTC1665 Differential Nonlinearity (DNL)
BLOCK DIAGRAM
0.5
V
V
= 5V
REF
CC
0.4
0.3
= 4.096V
GND
1
16
15
V
V
CC
0.2
DAC A
DAC B
DAC C
DAC D
DAC H
DAC G
DAC F
DAC E
V
V
V
V
2
0.1
OUT A
OUT H
0
–0.1
–0.2
–0.3
–0.4
–0.5
V
OUT G
V
OUT F
V
OUT E
3
4
14
13
OUT B
OUT C
0
64
128
192
255
CODE
166560 G09
LTC1660 Differential Nonlinearity (DNL)
1
V
V
= 5V
REF
CC
0.8
0.6
= 4.096V
5
6
7
8
12
11
10
9
OUT D
0.4
REF
CLR
0.2
0
CONTROL
LOGIC
ADDRESS
DECODER
CS/LD
SCK
D
D
–0.2
–0.4
–0.6
–0.8
–1
OUT
SHIFT REGISTER
IN
166560 BD
0
256
512
768
1023
CODE
166560 G13
166560fa
1
LTC1665/LTC1660
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
V
to GND ............................................... –0.2V to 7.5V
CC
1
2
3
4
5
6
7
8
V
V
V
V
V
16
15
14
13
12
11
10
9
GND
CC
Logic Inputs to GND ................................. –0.2V to 7.5V
V
V
V
V
OUT H
OUT G
OUT F
OUT E
OUT A
OUT B
OUT C
V
, V
, V
,
OUT A OUT B OUT H
REF to GND .................................–0.2V to (V + 0.2V)
CC
Maximum Junction Temperature .......................... 125°C
Operating Temperature Range
OUT D
REF
CLR
LTC1665C/LTC1660C.............................. 0°C to 70°C
LTC1665I/LTC1660I ............................ –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
D
CS/LD
OUT
D
SCK
IN
GN PACKAGE
16-LEAD PLASTIC SSOP
N PACKAGE
16-LEAD PDIP
T
= 125°C, θ = 150°C/W (GN)
JA
= 125°C, θ = 100°C/W (N)
JMAX
T
JMAX
JA
ORDER INFORMATION
LEAD FREE FINISH
LTC1665CGN#PBF
LTC1665IGN#PBF
LTC1660CGN#PBF
LTC1660IGN#PBF
LTC1665CN#PBF
LTC1665IN#PBF
LTC1660CN#PBF
LTC1660IN#PBF
TAPE AND REEL
LTC1665CGN#PBF
LTC1665IGN#PBF
LTC1660CGN#PBF
LTC1660IGN#PBF
LTC1665CN#PBF
LTC1665IN#PBF
LTC1660CN#PBF
LTC1660IN#PBF
PART MARKING*
1665
PACKAGE DESCRIPTION
16-Lead Plastic SSOP
16-Lead Plastic SSOP
16-Lead Plastic SSOP
16-Lead Plastic SSOP
16-Lead Plastic PDIP
16-Lead Plastic PDIP
16-Lead Plastic PDIP
16-Lead Plastic PDIP
TEMPERATURE RANGE
0°C to 70°C
1665I
–40°C to 85°C
0°C to 70°C
1660
1660I
–40°C to 85°C
0°C to 70°C
LTC1665CN
LTC1665IN
LTC1660CN
LTC1660IN
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping
container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
166560fa
2
LTC1665/LTC1660
ELECTRICAL CHARACTERISTICS The l denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VREF ≤ VCC, VOUT unloaded, unless otherwise noted.
LTC1665
TYP
LTC1660
TYP
SYMBOL PARAMETER
Accuracy
CONDITIONS
MIN
MAX
MIN
MAX UNITS
l
l
l
l
l
l
l
l
Resolution
8
8
10
10
Bits
Bits
Monotonicity
V
V
V
≤ V – 0.1V (Note 2)
CC
REF
REF
REF
DNL
INL
Differential Nonlinearity
≤ V – 0.1V (Note 2)
0.1
0.2
10
0.5
1.0
30
0.2
0.6
10
0.75
2.5
30
LSB
LSB
CC
Integral Nonlinearity
Offset Error
≤ V – 0.1V (Note 2)
CC
V
OS
(Note 7)
mV
V
OS
Temperature Coefficient
15
15
μV/°C
LSB
FSE
Full-Scale Error
V
CC
= 5V, V = 4.096V
1
4
3
15
REF
Full-Scale Error Temperature Coefficient
Power Supply Rejection
30
30
μV/°C
LSB/V
PSR
V
REF
= 2.5V
0.045
0.18
The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 2.7V to 5.5V, VREF ≤ VCC, VOUT unloaded, unless otherwise noted.
SYMBOL PARAMETER
Reference Input
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
Input Voltage Range
0
V
CC
V
kΩ
pF
Resistance
Not in Sleep Mode
(Note 6)
35
65
15
Capacitance
l
l
I
Reference Current
Sleep Mode
0.001
1
μA
REF
Power Supply
V
Positive Supply Voltage
Supply Current
For Specified Performance
2.7
5.5
V
CC
l
l
l
I
V
V
= 5V (Note 3)
= 3V (Note 3)
450
340
1
730
530
3
μA
μA
μA
CC
CC
CC
Sleep Mode (Note 3)
DC Performance
Short-Circuit Current Low
l
l
V
= 0V, V = 5.5V, V = 5.1V, Code = Full
10
10
30
27
100
120
mA
mA
OUT
CC
REF
Scale
Short-Circuit Current High
AC Performance
V
= V = 5.5V, V = 5.1V, Code = 0
OUT CC REF
Voltage Output Slew Rate
Rising (Notes 4, 5)
Falling (Notes 4, 5)
0.60
0.25
V/μs
V/μs
Voltage Output Settling Time
Capacitive Load Driving
To 0.5LSB (Notes 4, 5)
30
μs
pF
1000
Digital I/O
l
l
V
Digital Input High Voltage
Digital Input Low Voltage
V
V
= 2.7V to 5.5V
= 2.7V to 3.6V
2.4
2.0
V
V
IH
CC
CC
l
l
V
V
V
= 4.5V to 5.5V
= 2.7V to 5.5V
0.8
0.6
V
V
IL
CC
CC
l
l
l
l
V
V
Digital Output High Voltage
Digital Output Low Voltage
Digital Input Leakage
I
I
= –1mA, D
Only
V – 1
CC
V
V
OH
OUT
OUT
OUT
= 1mA, D
Only
0.4
10
10
OL
OUT
I
LK
V
= GND to V
CC
μA
pF
IN
C
IN
Digital Input Capacitance
(Note 6)
166560fa
3
LTC1665/LTC1660
TIMING CHARACTERISTICS The l denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (See Figure 1)
SYMBOL PARAMETER
= 4.5V to 5.5V
CONDITIONS
MIN
TYP
MAX
UNITS
V
CC
l
l
l
l
l
l
l
l
l
l
l
t
t
t
t
t
t
t
t
t
t
t
D
D
Valid to SCK Setup
Valid to SCK Hold
40
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
IN
IN
2
SCK High Time
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
30
30
80
30
80
5
3
SCK Low Time
4
CS/LD Pulse Width
LSB SCK High to CS/LD High
CS/LD Low to SCK High
5
6
7
D
OUT
Propagation Delay
C = 15pF (Note 6)
LOAD
80
8
SCK Low to CS/LD Low
CLR Pulse Width
(Note 6)
(Note 6)
(Note 6)
20
100
30
9
10
11
CS/LD High to SCK Positive Edge
SCK Frequency
l
l
l
Continuous Square Wave (Note 6)
Continuous 23% Duty Cycle Pulse (Note 6)
Gated Square Wave (Note 6)
5.00
7.69
16.7
MHz
MHz
MHz
V
= 2.7V to 5.5V
CC
l
l
l
l
l
l
l
l
l
l
l
t
t
t
t
t
t
t
t
t
t
t
D
Valid to SCK Setup
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
IN
IN
D
Valid to SCK Hold
2
SCK High Time
50
50
100
50
100
5
3
SCK Low Time
4
CS/LD Pulse Width
LSB SCK High to CS/LD High
CS/LD Low to SCK High
5
6
7
D
OUT
Propagation Delay
C = 15pF (Note 6)
LOAD
150
8
SCK Low to CS/LD Low
CLR Pulse Width
(Note 6)
(Note 6)
(Note 6)
30
120
30
9
10
11
CS/LD High to SCK Positive Edge
SCK Frequency
l
l
l
Continuous Square Wave (Note 6)
Continuous 28% Duty Cycle Pulse
Gated Square Wave
3.85
5.55
10
MHz
MHz
MHz
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 4: Load is 10kΩ in parallel with 100pF.
Note 5: V = V = 5V. DAC switched between 0.1V and 0.9V ,
FS
i.e., codes 26 and 230 for the LTC1665 or codes 102 and 922 for the
LTC1660.
CC
REF
FS
Note 2: Nonlinearity and monotonicity are defined from code 4 to code
255 for the LTC1665 and from code 20 to code 1023 for the LTC1660.
See Applications Information.
Note 6: Guaranteed by design and not production tested.
Note 7: Measured at code 4 for the LTC1665 and code 20 for the
LTC1660.
Note 3: Digital inputs at 0V or V
.
CC
166560fa
4
LTC1665/LTC1660
TYPICAL PERFORMANCE CHARACTERISTICS
(LTC1665/LTC1660)
Midscale Output Voltage
vs Load Current
Midscale Output Voltage
vs Load Current
Minimum Supply Headroom
vs Load Current (Output Sourcing)
1400
1200
1000
800
600
400
200
0
3
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2
2
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
V
REF
= V
CC
V
= V
CC
V
= 4.096V
OUT
REF
REF
CODE = 128 (LTC1665)
CODE = 512 (LTC1660)
CODE = 128 (LTC1665)
CODE = 512 (LTC1660)
ΔV
< 1LSB
CODE = 255 (LTC1665)
CODE = 1023 (LTC1660)
V
CC
= 3.6V
125°C
25°C
V
V
= 5.5V
= 5V
CC
CC
V
CC
= 3V
–55°C
V
CC
= 2.7V
V
CC
= 4.5V
SOURCE
SINK
10
SOURCE
–15 –12 –8 –4
SINK
4
–30
–20
–10
I
0
20
30
0
8
12 15
0
2
4
6
8
10
(mA)
I
(mA)
|I
OUT
|
(mA) (SOURCING)
OUT
OUT
166560 G01
166560 G02
166560 G03
Minimum VOUT
vs Load Current (Output Sinking)
Large-Signal Step Response
1400
1200
1000
800
600
400
200
0
5
4
3
2
1
0
V
= 5V
V
CC
= V
= 5V
REF
CC
CODE = 0
10% TO
90% STEP
125°C
25°C
–55°C
0
2
4
6
8
10
0
20
40
60
80
100
|
I
|
(mA) (SINKING)
TIME (μs)
OUT
166560 G04
166560 G05
Supply Current
vs Logic Input Voltage
Supply Current vs Temperature
500
480
460
440
420
400
380
360
340
320
300
2
1.6
1.2
0.8
0.4
0
ALL DIGITAL INPUTS
SHORTED TOGETHER
V
V
= 5.5V
= 4.5V
CC
CC
V
CC
= 3.6V
V
CC
= 2.7V
–55 –35 –15
5
25 45 65 85 105 125
0
1
2
3
4
5
TEMPERATURE (°C)
LOGIC INPUT VOLTAGE (V)
166560 G06
166560 G07
166560fa
5
LTC1665/LTC1660
TYPICAL PERFORMANCE CHARACTERISTICS
(LTC1665)
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
1
0.5
0.4
V
V
= 5V
REF
V
V
= 5V
REF
CC
CC
0.8
0.6
= 4.096V
= 4.096V
0.3
0.4
0.2
0.2
0.1
0
0
–0.2
–0.4
–0.6
–0.8
–1
–0.1
–0.2
–0.3
–0.4
–0.5
0
64
128
192
255
0
64
128
192
255
CODE
CODE
166560 G09
1665/60 G08
Load Regulation vs Output Current
Load Regulation vs Output Current
V
= V
= 3V
REF
V
= V
= 5V
REF
0.5
0.25
0
0.5
0.25
0
CC
CC
CODE = 128
CODE = 128
–0.25
–0.5
–0.25
–0.5
SOURCE
–1
SINK
SOURCE
SINK
–2
0
1
2
–500
0
500
I
(mA)
I
(μA)
OUT
OUT
166560 G10
166560 G11
166560fa
6
LTC1665/LTC1660
TYPICAL PERFORMANCE CHARACTERISTICS
(LTC1660)
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
2.5
1
0.8
V
V
= 5V
REF
V
V
= 5V
REF
CC
CC
2.0
1.5
= 4.096V
= 4.096V
0.6
1.0
0.4
0.5
0.2
0
0
–0.5
–1.0
–1.5
–2.0
–2.5
–0.2
–0.4
–0.6
–0.8
–1
0
256
512
768
1023
0
256
512
768
1023
CODE
CODE
166560 G13
166560 G12
Load Regulation vs Output Current
Load Regulation vs Output Current
V
= V
= 5V
V
= V
= 3V
REF
2
1.5
1
2
1.5
1
CC
REF
CC
CODE = 512
CODE = 512
0.5
0
0.5
0
–0.5
–1
–0.5
–1
–1.5
–2
–1.5
–2
SOURCE
–1
SINK
SOURCE
SINK
–2
0
1
2
–500
0
500
I
(mA)
I
(μA)
OUT
OUT
166560 G14
166560 G15
166560fa
7
LTC1665/LTC1660
PIN FUNCTIONS (LTC1665/LTC1660)
GND (Pin 1): System Ground.
SCK (Pin 8): Serial Interface Clock Input. CMOS and TTL
compatible.
V
to V
(Pins 2-5 and 12-15): DAC Analog Volt-
OUT H
OUT A
age Outputs. The output range is
D (Pin 9): Serial Interface Data Input. Data on the D
IN IN
pin is shifted into the 16-bit register on the rising edge of
SCK. CMOS and TTL compatible.
255
256
⎛
⎞
0 to
0 to
VREF for the LTC1665
⎜
⎝
⎟
⎠
D
(Pin 10): Serial Interface Data Output. Data appears
OUT
on D
16 positive SCK edges after being applied to D .
1023
1024
⎛
⎞
OUT
IN
VREF for the LTC1660
⎟
⎜
⎝
MaybetiedtoD ofanotherLTC1665/LTC1660fordaisy-
chain operation. CMOS and TTL compatible.
⎠
IN
REF (Pin 6): Reference Voltage Input. 0V ≤ V ≤ V .
REF
CC
CLR (Pin 11): Asynchronous Clear Input. All internal shift
and DAC registers are cleared to zero at the falling edge of
the CLR signal, forcing the analog outputs to zero scale.
CMOS and TTL compatible.
CS/LD (Pin 7): Serial Interface Chip Select/Load Input.
When CS/LD is low, SCK is enabled for shifting data on
D into the register. When CS/LD is pulled high, SCK is
disabled and data is loaded from the shift register into the
specified DAC register(s), updating the analog output(s).
CMOS and TTL compatible.
IN
V
(Pin 16): Supply Voltage Input. 2.7V ≤ V ≤ 5.5V.
CC
CC
BLOCK DIAGRAM
GND
1
2
16
15
V
V
CC
DAC A
DAC B
DAC C
DAC D
DAC H
DAC G
DAC F
DAC E
V
V
V
V
OUT A
OUT H
V
V
V
3
4
14
13
OUT B
OUT C
OUT G
OUT F
OUT E
5
6
7
8
12
11
10
9
OUT D
REF
CLR
CONTROL
LOGIC
ADDRESS
DECODER
CS/LD
SCK
D
D
OUT
SHIFT REGISTER
IN
166560 BD
166560fa
8
LTC1665/LTC1660
TIMING DIAGRAM
t
1
t
t
2
t
3
t
4
6
SCK
t
9
t
11
D
IN
A3
A2
A1
X1
X0
t
5
t
7
CS/LD
t
8
D
A2
A1
X1
X0
A3
A3
OUT
166560 F01
Figure 1
OPERATION
Transfer Function
Serial Interface
The transfer function is:
Referring to Figure 2a (2b): With CS/LD held low, data
on the DIN input is shifted into the 16-bit shift register on
the positive edge of SCK. The 4-bit DAC address, A3-A0,
is loaded first (see Table 2), then the 8-bit (10-bit) input
code, D7-D0 (D9-D0), ordered MSB-to-LSB in each case.
Four(two)don’t-carebits,X3-X0(X1-X0),areloadedlast.
Whenthefull16-bitinputwordhasbeenshiftedin, CS/LD
is pulled high, loading the DAC register with the word
and causing the addressed DAC output(s) to update. The
clockisdisabledinternallywhenCS/LDishigh. Note:SCK
must be low before CS/LD is pulled low.
k
256
⎛
⎞
VOUT(IDEAL)
=
VREF for theLTC1665
⎜
⎝
⎟
⎠
k
⎛
⎞
VOUT(IDEAL)
=
VREF for theLTC1660
⎟
⎜
⎝
⎠
1024
where k is the decimal equivalent of the binary DAC input
code and V is the voltage at REF (Pin 6).
REF
Power-On Reset
The LTC1665 clears the outputs to zero scale when power
is first applied, making system initialization consistent
and repeatable.
The buffered serial output of the shift register is available
on the D
pin, which swings from GND to V . Data
OUT
CC
appears on D
16 positive SCK edges after being ap-
OUT
plied to D .
IN
Power Supply Sequencing
Multiple LTC1665/LTC1660’s can be controlled from a
The voltage at REF (Pin 6) should be kept within the range
single 3-wire serial port (i.e., SCK, D and CS/LD) by
IN
–0.2V ≤ V ≤ V + 0.2V (see Absolute Maximum Rat-
REF
CC
using the included “daisy-chain” facility. A series of m
ings). Particular care should be taken to observe these
chips is configured by connecting each D
(except the
OUT
limitsduringpowersupplyturn-onandturn-offsequences,
last) to D of the next chip, forming a single 16m-bit
IN
when the voltage at V (Pin 16) is in transition.
CC
shift register. The SCK and CS/LD signals are common
to all chips in the chain. In use, CS/LD is held low while m
16-bit words are clocked to D of the first chip; CS/LD
IN
is then pulled high, updating all of them simultaneously.
166560fa
9
LTC1665/LTC1660
OPERATION
SCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
X3
X2
X1
X0
D
IN
ADDRESS/CONTROL
INPUT CODE
DON’T CARE
INPUT WORD W
0
(ENABLE CLK)
(UPDATE OUTPUT)
CS/LD
D
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
X3
X2
X1
X0
A3
OUT
INPUT WORD W
INPUT WORD W
–1
0
166560 F02a
Figure 2a. LTC1665 Register Loading Sequence
SCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A3
A2
A1
A0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X1
X0
D
IN
ADDRESS/CONTROL
INPUT CODE
DON’T CARE
INPUT WORD W
0
(ENABLE CLK)
(UPDATE OUTPUT)
CS/LD
D
A3
A2
A1
A0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X1
X0
A3
OUT
INPUT WORD W
INPUT WORD W
–1
0
166560 F02b
Figure 2b. LTC1660 Register Loading Sequence
Table 1a. LTC1665 Input Word
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 X3 X2 X1 X0
Sleep Mode
DACaddress1110 isreservedforthespecialSleepinstruc-
b
tion (see Table 2). In this mode, the digital interface stays
active while the analog circuits are disabled; static power
consumption is thus virtually eliminated. The reference
input and analog outputs are set in a high impedance state
and all DAC settings are retained in memory so that when
Sleep mode is exited, the outputs of DACs not updated by
the Wake command are restored to their last active state.
ADDRESS/CONTROL
INPUT CODE
DON’T CARE
Table 1b. LTC1660 Input Word
A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X1 X0
ADDRESS/CONTROL
INPUT CODE
DON’T
CARE
166560fa
10
LTC1665/LTC1660
OPERATION
Table 2. DAC Address/Control Functions
ADDRESS/CONTROL
Voltage Outputs
Each of the eight rail-to-rail output amplifiers contained
in these parts can source or sink up to 5mA. The outputs
swing to within a few millivolts of either supply rail when
unloadedandhaveanequivalentoutputresistanceof85Ω
when driving a load to the rails. The output amplifiers are
stable driving capacitive loads up to 1000pF.
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DAC STATUS
No Change
Load DAC A
Load DAC B
Load DAC C
Load DAC D
Load DAC E
Load DAC F
Load DAC G
Load DAC H
No Change
No Change
No Change
No Change
No Change
No Change
SLEEP STATUS
Wake
Wake
Wake
Wake
Wake
A small resistor placed in series with the output can be
used to achieve stability for any load capacitance. A 1μF
load can be successfully driven by inserting a 20Ω resis-
tor; a 2.2μF load needs only a 10Ω resistor. In either case,
larger values of resistance, capacitance or both may be
safely substituted for the values given.
Wake
Wake
Wake
Wake
Wake
Wake
Wake
Rail-to-Rail Output Considerations
Wake
In any rail-to-rail output voltage DAC, the output is limited
to voltages within the supply range.
Wake
Sleep
Wake
If the DAC offset is negative, the output for the lowest
codes limits at 0V as shown in Figure 3b.
Load ALL DACs
with Same
8/10-Bit Code
Similarly, limiting can occur near full scale when the REF
Sleep mode is initiated by performing a load sequence
pin is tied to V . If V = V and the DAC full-scale error
CC
REF
CC
to address 1110 (the DAC input word D7-D0 [D9-D0]
b
(FSE) is positive, the output for the highest codes limits
is ignored). Once in Sleep mode, a load sequence to any
at V as shown in Figure 3c. No full-scale limiting can
CC
other address (including “No Change” addresses 0000
b
occur if V is less than V – FSE.
REF
CC
and 1001-1101 ) causes the LTC1665/LTC1660 to Wake.
b
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting
can occur.
It is possible to keep one or more chips of a daisy chain
in continuous Sleep mode by giving the Sleep instruction
to these chips each time the active chips in the chain are
updated.
166560fa
11
LTC1665/LTC1660
OPERATION
POSITIVE
FSE
V
REF
= V
CC
OUTPUT
VOLTAGE
INPUT CODE
(c)
V
REF
= V
CC
OUTPUT
VOLTAGE
0
128
255
INPUT CODE
(a)
OUTPUT
VOLTAGE
0V
NEGATIVE
OFFSET
INPUT CODE
(b)
166560 F03
Figure 3. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative
Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When VREF = VCC
166560fa
12
LTC1665/LTC1660
TYPICAL APPLICATIONS
A Low Power Quad Trim Circuit with Coarse/Fine Adjustment
3.3V
3.3V
R1
R2
0.1μF
CC
0.1μF
R2
R1
4
U1
V
GND
–
–
1
2
16
15
13
12
LTC1665
2
14
1
U2A
U2D
LT1491
R1
R1
LT®1491
COARSE
COARSE
V
V
OUT4
V
V
V
V
OUT1
+ 3
+
OUT A
OUT H
OUT G
OUT F
OUT E
DAC A
DAC B
DAC C
DAC D
DAC H
DAC G
DAC F
DAC E
11
0.1μF
0.1μF
R2
FINE
R2
FINE
V
V
V
OUT B
OUT C
R1
R2
R2
R1
3
4
14
13
–
6
–
9
8
7
U2B
U2C
LT1491
R1
COARSE
R1
COARSE
LT1491 + 5
10
+
V
OUT3
V
OUT2
0.1μF
0.1μF
R2
FINE
R2
FINE
3.3V
0.1μF
V
OUT D
5
6
7
8
12
11
10
9
2
LTC1258-2.5
1
REF
CLR
4
CONTROL
LOGIC
ADDRESS
DECODER
D
OUT
IN
CS/LD
TO OTHER
LTC1665s
3-WIRE
SERIAL
D
SCK
SHIFT REGISTER
INTERFACE
166560 TA01
R2 >> R1
= V
R1
V
+
V
OUT B
OUT 1
OUT A
ꢀ
ꢀ
R2
Similarly V
, V
, V
OUT 2 OUT 3 OUT 4
Example: For R1 = 110Ω and R2 = 11k,
= V + 0.01 V
V
OUT 1
OUT A
OUT B
166560fa
13
LTC1665/LTC1660
TYPICAL APPLICATIONS
An 8-Channel Bipolar Output Voltage Circuit Configuration
5V
R
R
R
R
0.1μF
0.1μF
0.1μF
+
+
V
V
4
S
S
U1
V
V
GND
CC
4
–
–
2
1
2
16
15
LTC1660
2
1
1
V
´
V
´
U2A
LT1491 + 3
U3A
OUT A
5V
OUT H
5V
LT1491
V
OUT A
OUT H
3 +
DAC A
DAC H
0.1μF
0.1μF
11
R
11
–
–
V
V
S
S
R
R
R
R
R
R
R
R
R
–
6
–
6
7
8
7
V
V
V
´
V
V
V
´
U2B
LT1491 + 5
U3B
LT1491
OUT B
OUT G
5V
5V
V
V
V
OUT G
V
OUT F
V
OUT E
OUT B
5 +
DAC B
DAC C
DAC D
DAC G
DAC F
DAC E
3
4
14
13
R
R
–
9
–
9
8
´
´
´
U2C
LT1491 + 10
U3C
LT1491
OUT C
OUT F
5V
5V
OUT C
10 +
–
13
–
13
14
14
´
U2D
LT1491 + 12
U3D
LT1491
OUT D
OUT E
5V
5V
V
OUT D
12 +
5
6
7
8
12
11
10
9
REF
CLR
CONTROL
LOGIC
ADDRESS
DECODER
CS/LD
CODE
0
512
V
D
OUT X
– 5V
0V
OUT
3-WIRE
SERIAL
D
IN
CLK
SHIFT REGISTER
INTERFACE
1023 +4.99V
166560 TA04
166560fa
14
LTC1665/LTC1660
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
GN Package
16-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG #05-08-1641)
.189 – .196*
.045 .005
(4.801 – 4.978)
.009
(0.229)
REF
16 15 14 13 12 11 10 9
.254 MIN
.150 – .165
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.0165 .0015
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
2
3
4
5
6
7
8
.015 .004
(0.38 0.10)
w 45s
.0532 – .0688
(1.35 – 1.75)
.004 – .0098
(0.102 – 0.249)
.007 – .0098
(0.178 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.0250
(0.635)
BSC
.008 – .012
GN16 (SSOP) 0204
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
166560fa
15
LTC1665/LTC1660
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
N Package
16-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510 Rev I)
.770ꢀ
(19.553ꢂ
MAX
14
12
10
9
3
15
1ꢁ
11
16
.255 .015ꢀ
(6.477 0.ꢁ31ꢂ
2
1
ꢁ
4
6
5
7
.ꢁ00 – .ꢁ25
(7.620 – 3.255ꢂ
.1ꢁ0 .005
(ꢁ.ꢁ02 0.127ꢂ
.045 – .065
(1.14ꢁ – 1.651ꢂ
.020
(0.503ꢂ
MIN
.065
(1.651ꢂ
TYP
.003 – .015
(0.20ꢁ – 0.ꢁ31ꢂ
+.0ꢁ5
–.015
.ꢁ25
.120
(ꢁ.043ꢂ
MIN
.013 .00ꢁ
(0.457 0.076ꢂ
.100
(2.54ꢂ
BSC
+0.339
3.255
ꢁ
ꢀ
–0.ꢁ31
N16 REV I 0711
NOTE:
INCHES
MILLIMETERS
1. DIMENSIONS ARE
ꢀTHESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mmꢂ
166560fa
16
LTC1665/LTC1660
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
1/12
Removed Typical values in Timing Characteristics
3, 4
166560fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
17
LTC1665/LTC1660
TYPICAL APPLICATION
A Pin Driver VH and VL Adjustment Circuit for ATE Applications
5V
0.1μF
11
16
6
V
CLR
V
REF
H
CC
(FROM MAIN DAC)
U1 LTC1660
10V
0.1μF
1
R
F
R
G
5k
50k
V
A
V
B
V
C
V
D
3
2
´
DAC H
DAC A
V
H
2
3
4
5
+
U2A
LT1369
QUAD
´
V
= V + ΔV
H
H
H
´
V
L
0.1μF
–
R
G
0.1μF
50k
–5V
DAC G
DAC F
DAC E
DAC B
DAC C
DAC D
R
F
5k
V
L
V
V
H
(FROM MAIN DAC)
L
R
F
5k
V
OUT
R
50k
G
PIN DRIVER
(1 OF 2)
5
6
+
´
V
L
= V + V
L L
U2B
LT1369
QUAD
7
0.1μF
–
LOGIC
DRIVE
R
50k
R
F
5k
G
166560 TA03
CS/LD
7
9
8
D
IN
V = V = 2.5V
A
C
SCK
GND
1
´
R
V
V
= V +
F
H
H
(V – V )
A
B
R
G
´
R
= V +
F
L
L
(V – V )
C
D
CODE A CODE B ΔV , ΔV
H
L
R
G
512
512
512
1023 –250mV
Note: DACs E Through H Can Be
Configured for a Second Pin Driver
With U2C and U2D of the LT1369
For Resistor Values Shown:
Adjustment Range = 250mV
Adjustment Step Size = 500μV
512
0
0
+250mV
RELATED PARTS
PART NUMBER
LTC1661
DESCRIPTION
Dual 10-Bit V
COMMENTS
DAC in 8-Lead MSOP Package
V
CC
V
CC
= 2.7V to 5.5V Micropower Rail-to-Rail Output
= 2.7V to 5.5V, Internal Reference, 60μA
OUT
LTC1663
Single 10-Bit V
DAC in SOT-23 Package
OUT
LTC1446/
LTC1446L
Dual 12-Bit V
DACs in SO-8 Package with Internal Reference
DAC in SO-8 Package
LTC1446: V = 4.5V to 5.5V, V
= 0V to 4.095V
OUT
OUT
CC
OUT
LTC1446L: V = 2.7V to 5.5V, V
= 0V to 2.5V
CC
LTC1448
Dual 12-Bit V
Dual 12-Bit V
V = 2.7V to 5.5V, External Reference Can Be Tied to V
CC CC
OUT
LTC1454/
LTC1454L
DACs in SO-16 Package with Added Functionality LTC1454: V = 4.5V to 5.5V, V
= 0V to 4.095V
OUT
CC
OUT
LTC1454L: V = 2.7V to 5.5V, V
= 0V to 2.5V
CC
OUT
LTC1458/
LTC1458L
Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality
Dual 12-Bit I DAC in SO-16 Package
LTC1458: V = 4.5V to 5.5V, V
= 0V to 4.095V
OUT
CC
OUT
LTC1458L: V = 2.7V to 5.5V, V
= 0V to 2.5V
CC
LTC1590
LTC1659
V
CC
= 4.5V to 5.5V, 4-Quadrant Multiplication
OUT
Single Rail-to-Rail 12-Bit V
DAC in 8-Lead MSOP Package
Low Power Multiplying V
DAC. Output Swings from GND to
OUT
OUT
V
: 2.7V to 5.5V
REF. REF Input Can Be Tied to V
CC
CC
LT1460
Micropower Precision Series Reference, 2.5V, 5V, 10V Versions
0.075% Max, 10ppm/°C Max, Only 130μA Supply Current
166560fa
LT 0112 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
18
●
●
© LINEAR TECHNOLOGY CORPORATION 1999
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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