LTC1659IS8 [Linear]
12-Bit Rail-to-Rail Micropower DAC in MSOP Package; 12位轨至轨微DAC ，采用MSOP封装
| 型号： | LTC1659IS8 |
| 厂家： | 
Linear |
| 描述： | 12-Bit Rail-to-Rail Micropower DAC in MSOP Package |
| 文件： | 总12页 (文件大小：135K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1659
12-Bit Ra il-to -Ra il
Mic ro p o we r DAC in
MSOP Pa c ka g e
U
DESCRIPTION
FEATURES
The LTC®1659 is a single supply, rail-to-rail voltage out-
put, 12-bit digital-to-analog converter (DAC) in an MSOP
package. It includes a rail-to-rail output buffer amplifier
and an easy-to-use 3-wire cascadable serial interface.
■
8-Lead MSOP Package
12-Bit Resolution
Supply Operation: 3V to 5V
Buffered True Rail-to-Rail Voltage Output
■
■
■
■
Output Swings from 0V to V
REF
TheLTC1659outputswings from0VtoREF.TheREFinput
can be tied to V which can range from 2.7V to 5.5V. This
allows a rail-to-rail output swing from 0V to V . The
LTC1659 draws only 250µA from a 5V supply.
■
■
VREF Can Tie to V
CC
CC
Schmitt Trigger On Clock Input Allows Direct
Optocoupler Interface
CC
■
■
■
■
Power-On Reset Clears DAC to 0V
3-Wire Cascadable Serial Interface
Maximum DNL Error: 0.5LSB
Low Cost
Its guaranteed±0.5LSBmaximumDNLmakes theLTC1659
excel in calibration, control and trim/adjust applications.
The low power supply current and the small MSOP pack-
age make the LTC1659 ideal for battery-powered applica-
tions.
U
APPLICATIONS
, LTC and LT are registered trademarks of Linear Technology Corporation.
■
Digital Calibration
Industrial Process Control
Automatic Test Equipment
Cellular Telephones
■
■
■
U
TYPICAL APPLICATION
Functional Block Diagram: 12-Bit Rail-to-Rail DAC
Differential Nonlinearity
vs Input Code
2.7V TO 5.5V
8
6
0.5
V
CC
REF
2
1
D
IN
+
–
V
OUT
RAIL-TO-RAIL
VOLTAGE
OUTPUT
7
CLK
12-BIT
SHIFT
REG
µP
12-BIT
DAC
3
CS/LD
AND
0
DAC
LATCH
4
D
OUT
POWER-ON
RESET
TO
OTHER
DACS
–0.5
GND
1659 TA01
0
512 1024 1536 2048 2560 3072 3584 4095
CODE
5
1659 TA02
1
LTC1659
W W
U W
ABSOLUTE MAXIMUM RATINGS
V to GND ...............................................–0.5V to 7.5V
CC
Operating Temperature Range
Logic Inputs to GND .................................–0.5V to 7.5V
LTC1659CS8 ........................................... 0°C to 70°C
LTC1659IS8 ....................................... –40°C to 85°C
LTC1659CMS8 (Note 1) .......................... 0°C to 70°C
Lead Temperature (Soldering, 10 sec).................. 300°C
VOUT ............................................... –0.5V to V + 0.5V
CC
Maximum Junction Temperature .......................... 125°C
Storage Temperature Range ................. –65°C to 150°C
W
U
/O
PACKAGE RDER I FOR ATIO
ORDER PART
ORDER PART
TOP VIEW
NUMBER
NUMBER
TOP VIEW
CLK
1
2
3
4
V
CC
8
7
6
5
CLK 1
8 V
CC
D
IN
V
OUT
LTC1659CS8
LTC1659IS8
LTC1659CMS8
D
IN
2
7 V
OUT
6 REF
5 GND
CS/LD 3
CS/LD
REF
D
OUT
4
D
OUT
GND
S8 PART MARKING
MS8 PART MARKING
LTCK
MS8 PACKAGE
8-LEAD PLASTIC MSOP
S8 PACKAGE
8-LEAD PLASTIC SO
1659
1659I
T
JMAX = 125°C, θJA = 150°C/W
TJMAX = 125°C, θJA = 206°C/W
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
V
CC = 2.7V to 5.5V, VOUT unloaded, REF ≤ V , TA = TMIN to TMAX, unless otherwise noted.
CC
SYMBOL PARAMETER
DAC
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution
●
●
●
12
12
Bits
Bits
LSB
Monotonicity
DNL
INL
Differential Nonlinearity
V
REF
≤ V – 0.1V (Note 2)
±0.5
CC
Integral Nonlinearity
V
V
REF
≤ V – 0.1V (Note2), T = 25°C
±5.0
±5.5
LSB
LSB
REF
CC
A
≤ V – 0.1V (Note 2)
●
●
CC
V
OS
Offset Error
Measured at Code 20, T = 25°C
Measured at Code 20
±12
±18
mV
mV
A
V TC
OS
Offset Error Temperature
Coefficient
±15
µV/°C
V
FS
Full-Scale Voltage
T = 25°C, REF = 4.096V (Note 6)
REF = 4.096V (Note 6)
4.070
4.060
4.095
4.095
4.120
4.130
V
V
A
●
V TC
FS
Full-Scale Voltage
10
ppm/°C
Temperature Coefficient
2
LTC1659
ELECTRICAL CHARACTERISTICS
V
CC = 2.7V to 5.5V, VOUT unloaded, REF ≤ V , TA = TMIN to TMAX, unless otherwise noted.
CC
SYMBOL PARAMETER
Power Supply
CONDITIONS
MIN
TYP
MAX
UNITS
V
Positive Supply Voltage
Supply Current
For Specified Performance
(Note 5)
●
●
2.7
5.5
V
CC
I
CC
240
450
µA
Op Amp DC Performance
Short-Circuit Current Low
V
Shorted to GND
●
●
●
70
65
40
0.1
120
120
150
1.5
mA
mA
OUT
Short-Circuit Current High
Output Impedance to GND
Output Line Regulation
V
Shorted to V
OUT CC
Input Code = 0
Ω
Input Code = 4095, V = 4.5V to 5.5V
LSB/V
CC
AC Performance
Voltage Output Slew Rate
(Note 3)
●
0.5
1.0
14
V/µs
µs
Voltage Output Settling Time (Notes 3, 4) to ±0.5LSB
Digital Feedthrough
0.3
nV•s
Reference Input
R
REF Input Resistance
REF Input Range
●
●
17
0
28
40
kΩ
IN
REF
(Notes 6, 7)
V
CC
V
Digital I/O
V
Digital Input High Voltage
Digital Input Low Voltage
Digital Output High Voltage
Digital Output Low Voltage
Digital Input High Voltage
Digital Input Low Voltage
Digital Output High Voltage
Digital Output Low Voltage
Digital Input Leakage
V
= 5V
●
●
●
●
●
●
●
●
●
●
2.4
V
V
IH
CC
V
IL
V
CC
= 5V
0.8
0.4
0.6
V
OH
V
CC
= 5V, I
= 5V, I
= 3V
= –1mA, D
Only
V – 1.0
CC
V
OUT
OUT
V
OL
V
CC
= 1mA, D Only
OUT
V
OUT
V
IH
V
CC
2.0
V
V
IL
V
CC
= 3V
V
V
OH
V
CC
= 3V, I
= 3V, I
= –1mA, D
Only
V – 0.7
CC
V
OUT
OUT
V
OL
V
CC
= 1mA, D Only
OUT
0.4
±10
10
V
OUT
I
V
IN
= GND to V
CC
µA
pF
LEAK
C
IN
Digital Input Capacitance
(Note 7)
3
LTC1659
ELECTRICAL CHARACTERISTICS
V
CC = 2.7V to 5.5V, VOUT unloaded, REF ≤ V , TA = TMIN to TMAX, unless otherwise noted.
CC
SYMBOL PARAMETER
Switching (V = 4.5 to 5.5V)
CONDITIONS
MIN
TYP
MAX
UNITS
CC
t
t
t
t
t
t
t
t
t
D
Valid to CLK Setup
Valid to CLK Hold
●
●
●
●
●
●
●
●
●
40
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
2
3
4
5
6
7
8
9
IN
D
IN
CLK High Time
(Note 7)
(Note 7)
(Note 7)
(Note 7)
(Note 7)
40
40
50
40
20
5
CLK Low Time
CS/LD Pulse Width
LSB CLK to CS/LD
CS/LD Low to CLK
D
OUT
Output Delay
C
LOAD
= 15pF
150
CLK Low to CS/LD Low
(Note 7)
20
Switching (V = 2.7 to 5.5V)
CC
t
t
t
t
t
t
t
t
t
D
Valid to CLK Setup
Valid to CLK Hold
●
●
●
●
●
●
●
●
●
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
2
3
4
5
6
7
8
9
IN
D
IN
CLK High Time
(Note 7)
(Note 7)
(Note 7)
(Note 7)
(Note 7)
60
60
80
60
30
10
30
CLK Low Time
CS/LD Pulse Width
LSB CLK to CS/LD
CS/LD Low to CLK
D
OUT
Output Delay
C
LOAD
= 15pF
220
CLK Low to CS/LD Low
(Note 7)
The
●
denotes specifications which apply over the full operating
Note 3: Load is 5kΩ in parallel with 100pF.
Note 4: DAC switched between all 1s and the code corresponding to V
temperature range.
OS
Note 1: The LTC1659CMS8 is designed, characterized and expected to
meet industrial temperature limits, but is not tested at –40°C and 85°C.
Consult factory for guaranteed I-grade MSOP parts. However, these parts
are guaranteed for commercial temperature limits of 0°C to 70°C.
for the part.
Note 5: Digital inputs at 0V or V .
CC
Note 6: V can only swing from (GND +
V
OS
) to (V
–
V
OS
) when
OUT
CC
output is unloaded.
Note 2: Nonlinearity is defined from code 20 to code 4095 (full scale). See
Applications Information.
Note 7: Guaranteed by design. Not subject to test.
4
LTC1659
W
U
TYPICAL PERFORMANCE CHARACTERISTICS
Minimum Output Voltage
vs Output Sink Current
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
0.5
5
4
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
CODE = ALL ZEROS
V
CC
= 5V
3
2
1
0
0
125°C
25°C
–1
–2
–3
–4
–5
–55°C
–0.5
0
512 1024 1536 2048 2560 3072 3584 4095
CODE
0
512 1824 1536 2048 2560 3072 3584 4095
CODE
0
5
10
15
OUTPUT SINK CURRENT (mA)
LTC1659 • TPC02
LTC1659 • TPC01
LTC1659 • TPC03
Supply Headroom for
Full Output Swing vs Load Current
Supply Current
vs Logic Input Voltage
Supply Current vs Temperature
300
290
280
270
260
250
240
230
220
0.6
0.5
0.4
0.3
0.2
0.1
0
∆ V
< 1 LSB
V
CC
= 5V
125°C
2
1.6
1.2
0.8
0.4
0
OUT
CODE = ALL 1s
= 4.095V
V
OUT
25°C
V
= 5.5V
= 5.0V
= 4.5V
CC
–55°C
V
CC
V
CC
0
5
10
15
0
1
2
3
4
5
–55 –35 –15
5
25 45 65 85 105 125
LOAD CURRENT (mA)
LOGIC INPUT VOLTAGE (V)
TEMPERATURE (C)
LTC1659 • TPC04
LTC1659 • TPC05
LTC1659 • TPC06
5
LTC1659
U
U
U
PIN FUNCTIONS
CLK (Pin 1): Serial Interface Clock. Internal Schmitt trig-
DOUT (Pin 4): Output of the Shift Register which Becomes
ger on this input allows direct optocoupler interface.
Valid on the Rising Edge of the Serial Clock.
D (Pin 2): Serial Interface Data. Data on the D pin is
GND (Pin 5): Ground.
IN
IN
latchedintotheshiftregisterontherisingedgeoftheserial
clock.
REF (Pin 6): Reference Input. This pin can be tied to V .
The output will swing from 0V to REF. The typical input
resistance is 28k.
CC
CS/LD (Pin 3): Serial Interface Enable and Load Control.
When CS/LD is low the CLK signal is enabled, so the data
can be clocked in. When CS/LD is pulled high, data is
loaded from the shift register into the DAC register,
updating the DAC output and the CLK is disabled
internally.
VOUT (Pin 7): Buffered DAC Output.
V (Pin 8): Positive Supply Input. 2.7V ≤ VCC ≤ 5.5V.
CC
Requires a bypass capacitor to ground.
W
BLOCK DIAGRA
CLK
V
CC
1
8
LD
D
IN
2
12-BIT
DAC
12-BIT
SHIFT
REGISTER
+
–
DAC
REGISTER
V
OUT
7
3
CS/LD
POWER-ON
RESET
REF
6
5
D
OUT
GND
4
1659 BD
6
LTC1659
W U
W
TI I G DIAGRA
t
t
t
t
2
1
6
7
CLK
t
t
3
4
t
9
B11
MSB
B0
PREVIOUS WORD
B0
LSB
B10
B1
D
IN
CS/LD
t
t
5
8
B11
B11
PREVIOUS WORD
D
OUT
B1
B10
B0
CURRENT WORD
1659 TD
U U
DEFI ITIO S
Differential Nonlinearity (DNL): The difference between
the measured change and the ideal 1LSB change for any
twoadjacentcodes. TheDNLerrorbetweenanytwocodes
is calculated as follows:
than zero. The INL error at a given input code is calculated
as follows:
INL = [VOUT – VOS – (V – VOS)(code/4095)]/LSB
FS
Where VOUT is the output voltage of the DAC measured at
the given input code.
DNL = (∆VOUT – LSB)/LSB
Where ∆VOUT is the measured voltage difference between
two adjacent codes.
Least Significant Bit (LSB): The ideal voltage difference
between two successive codes.
DigitalFeedthrough: Theglitchthatappears attheanalog
outputcausedbyACcouplingfromthedigitalinputs when
they change state. The area of the glitch is specified in
(nV)(sec).
LSB = VREF/4096
Resolution (n): Defines the number of DAC output states
(2n) that divide the full-scale range. Resolution does not
imply linearity.
Full-Scale Error (FSE): The deviation of the actual full-
scale voltage from ideal. FSE includes the effects of offset
and gain errors (see Applications Information).
Voltage Offset Error (VOS): Nominally, the voltage at the
output when the DAC is loaded with all zeros. A single
supply DAC can have a true negative offset, but the output
cannot go below zero (see Applications Information).
Integral Nonlinearity (INL): The deviation from a straight
line passing through the endpoints of the DAC transfer
curve(EndpointINL). Becausetheoutputcannotgobelow
zero, the linearity is measured between full scale and the
lowest code which guarantees the output will be greater
For this reason, single supply DAC offset is measured at
the lowest code that guarantees the output will be greater
than zero.
7
LTC1659
U
OPERATIO
Serial Interface
Voltage Output
The data on the D input is loaded into the shift register
The LTC1659’s rail-to-rail buffered output can source or
sink 5mA over the entire operating temperature range
while pulling to within 300mV of the positive supply
voltage or ground. The output swings to within a few
millivolts of either supply rail when unloaded and has an
equivalentoutputresistanceof40Ωwhendrivingaloadto
the rails. The output can drive 1000pF without going into
oscillation.
IN
ontherisingedgeoftheclock.TheMSBis loadedfirst.The
DAC register loads the data from the shift register when
CS/LD is pulled high. The CLK is disabled internally when
CS/LD is high. Note: CLK must be low before CS/LD is
pulled low to avoid an extra internal clock pulse.
The buffered output of the 12-bit shift register is available
on the DOUT pin which swings from GND to V .Multiple
CC
LTC1659s may be daisy-chained together by connecting
The output swings from 0V to the voltage at the REF pin,
the DOUT pin to the D pin of the next chip, while the CLK i.e., there is a gain of 1 from the REF to VOUT. Please note
IN
andCS/LDsignals remaincommontoallchips inthedaisy if REF is tied to V the output can only swing to (V
–
CC
CC
chain. The serial data is clocked to all of the chips, then the
CS/LD signal is pulled high to update all of them
simultaneously.
V ). See Applications Information.
OS
8
LTC1659
U
W U U
APPLICATIONS INFORMATION
Rail-to-Rail Output Considerations
VCC as shown is Figure 1(c). No full-scale limiting can
occur if VREF is less than V – FSE.
CC
In any rail-to-rail DAC, the output swing is limited to
voltages within the supply range.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
If the DAC offset is negative, the output for the lowest
codes limits at 0V as shown in Figure 1(b).
Similarly, limiting can occur near full scale when the REF
pin is tied to V . If VREF = V and the DAC full-scale error
CC
CC
(FSE) is positive, the output for the highest codes limits at
POSITIVE
FSE
V
REF
= V
CC
OUTPUT
VOLTAGE
INPUT CODE
(c)
V
REF
= V
CC
OUTPUT
VOLTAGE
0
2048
4095
INPUT CODE
(a)
OUTPUT
VOLTAGE
0V
NEGATIVE
OFFSET
INPUT CODE
(b)
1659 F01
Figure 1. Effects of Rail-to-Rail Operation on a DAC Transfer Curve
(a) Overall Transfer Function
(b) Effect of Negative Offset for Codes Near Zero Scale
(c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When VREF = VCC
9
LTC1659
TYPICAL APPLICATION
U
12-Bit, 3V to 5V Single Supply, Rail-to-Rail Voltage Output DAC
2.7V TO 5.5V
0.1µF
V
CC
REF
D
IN
CLK
CS/LD
OUTPUT
0V TO REF
µP
V
OUT
LTC1659
GND
D
OUT
TO NEXT DAC FOR
DAISY-CHAINING
1659 TA03
U
PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted.
MS8 Package
8-Lead Plastic MSOP
(LTC DWG # 05-08-1660)
0.118 ± 0.004*
(3.00 ± 0.102)
8
7
6
5
0.118 ± 0.004**
(3.00 ± 0.102)
0.192 ± 0.004
(4.88 ± 0.10)
1
2
3
4
0.040 ± 0.006
(1.02 ± 0.15)
0.034 ± 0.004
(0.86 ± 0.102)
0.007
(0.18)
0° – 6° TYP
SEATING
PLANE
0.012
(0.30)
REF
0.021 ± 0.006
(0.53 ± 0.015)
0.006 ± 0.004
(0.15 ± 0.102)
MSOP (MS8) 1197
0.0256
(0.65)
TYP
*
DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
10
LTC1659
U
PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted.
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
7
5
8
6
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
1
3
4
2
0.010 – 0.020
(0.254 – 0.508)
× 45°
0.053 – 0.069
(1.346 – 1.752)
0.004 – 0.010
(0.101 – 0.254)
0.008 – 0.010
(0.203 – 0.254)
0°– 8° TYP
0.016 – 0.050
0.406 – 1.270
0.050
(1.270)
TYP
0.014 – 0.019
(0.355 – 0.483)
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
SO8 0996
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofits circuits as describedhereinwillnotinfringeonexistingpatentrights.
11
LTC1659
U
TYPICAL APPLICATION
Digitally Programmable Current Source
5V
V + 6V TO 100V
S
FOR R ≤ 50Ω
L
0.1µF
D
• 5
IN
R
L
I
=
≈ 0mA TO 10mA
V
CC
REF
OUT
CLK
4096 • R
A
µP
LTC1659
GND
+
D
V
OUT
IN
CS/LD
Q1
2N3440
LT1077
–
R
A
510Ω
5%
1659 TA04
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LTC1458: V = 4.5V to 5.5V, V = 0V to 4.095V
CC OUT
LTC1458L: V = 2.7V to 5.5V, V = 0V to 2.5V
CC
OUT
1659f LT/TP 0498 4K • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 1997
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
12
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(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
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