LTC1604IG [Linear]
High Speed, 16-Bit, 333ksps Sampling A/D Converter with Shutdown; 高速， 16位， 333ksps的采样A / D转换器，带有关断
| 型号： | LTC1604IG |
| 厂家： | 
Linear |
| 描述： | High Speed, 16-Bit, 333ksps Sampling A/D Converter with Shutdown |
| 文件： | 总20页 (文件大小：381K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1604
High Speed, 16-Bit, 333ksps
Sampling A/D Converter
with Shutdown
U
DESCRIPTION
FEATURES
The LTC®1604 is a 333ksps, 16-bit sampling A/D con-
verter that draws only 220mW from ±5V supplies. This
high performance device includes a high dynamic range
sample-and-hold, a precision reference and a high speed
parallel output. Two digitally selectable power shutdown
modes provide power savings for low power systems.
■
A Complete, 333ksps 16-Bit ADC
■
90dB S/(N+D) and –100dB THD (Typ)
■
Power Dissipation: 220mW (Typ)
■
No Pipeline Delay
■
No Missing Codes over Temperature
■
Nap (7mW) and Sleep (10µW) Shutdown Modes
■
Operates with Internal 15ppm/°C Reference
or External Reference
The LTC1604’s full-scale input range is ±2.5V. Outstand-
ing AC performance includes 90dB S/(N+D) and –100dB
THD at a sample rate of 333ksps.
■
■
■
■
True Differential Inputs Reject Common Mode Noise
5MHz Full Power Bandwidth
±2.5V Bipolar Input Range
36-Pin SSOP Package
Theuniquedifferentialinputsample-and-holdcanacquire
single-ended or differential input signals up to its 15MHz
bandwidth. The 68dB common mode rejection allows
users to eliminate ground loops and common mode noise
by measuring signals differentially from the source.
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APPLICATIONS
■
Telecommunications
The ADC has µP compatible,16-bit parallel output port.
Thereisnopipelinedelayinconversionresults. Aseparate
convert start input and a data ready signal (BUSY) ease
connections to FlFOs, DSPs and microprocessors.
■
Digital Signal Processing
■
Multiplexed Data Acquisition Systems
High Speed Data Acquisition
Spectrum Analysis
Imaging Systems
■
■
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
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TYPICAL APPLICATION
5V 10µF
2.2µF
10µF
5V 10µF
10Ω
LTC1604 4096 Point FFT
+
+
+
3
10
36
35
9
0
V
AV
AV
DD
DV
DD
DGND
REF
DD
SHDN
CS
33
32
31
30
27
–20
–40
CONTROL
LOGIC
AND
TIMING
µP
CONTROL
LINES
CONVST
RD
REFCOMP
7.5k
4
2.5V
REF
1.75X
–60
+
4.375V
BUSY
47µF
–80
OV
DD
29
28
5V OR
+
3V
–100
–120
–140
10µF
+
OGND
1
2
A
IN
+
–
DIFFERENTIAL
ANALOG INPUT
±2.5V
16-BIT
SAMPLING
ADC
OUTPUT
BUFFERS
B15 TO B0
16-BIT
–
A
IN
PARALLEL
BUS
D15 TO D0
0
20 40 60 80 100
120
140 160
11 TO 26
AGND AGND AGND AGND
V
SS
34
FREQUENCY (kHz)
1604 TA01
5
6
7
8
1604 TA02
10µF
+
–5V
1
LTC1604
W W
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ABSOLUTE MAXIMUM RATINGS
AVDD = DVDD = OVDD = VDD (Notes 1, 2)
PACKAGE/ORDER INFORMATION
ORDER
PART NUMBER
TOP VIEW
+
Supply Voltage (VDD)................................................ 6V
Negative Supply Voltage (VSS)................................ –6V
Total Supply Voltage (VDD to VSS) .......................... 12V
Analog Input Voltage
(Note 3) ......................... (VSS – 0.3V) to (VDD + 0.3V)
VREF Voltage (Note 4) ................. –0.3V to (VDD + 0.3V)
REFCOMP Voltage (Note 4) ......... –0.3V to (VDD + 0.3V)
Digital Input Voltage (Note 4) ....................–0.3V to 10V
Digital Output Voltage.................. –0.3V to (VDD + 0.3V)
Power Dissipation............................................. 500mW
Operating Temperature Range
A
A
1
2
3
4
5
6
7
8
9
36 AV
35 AV
IN
DD
–
IN
DD
V
34
V
SS
REF
LTC1604CG
LTC1604IG
LTC1604ACG
LTC1604AIG
REFCOMP
AGND
33 SHDN
32 CS
AGND
31 CONV
30 RD
AGND
AGND
29 OV
DD
DV
DD
28 OGND
27 BUSY
26 D0
25 D1
24 D2
23 D3
22
DGND 10
D15 (MSB) 11
D14 12
D13 13
D12 14
D11
15
D4
D10 16
D9 17
21 D5
20 D6
19 D7
LTC1604C............................................... 0°C to 70°C
LTC1604I............................................ –40°C to 85°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
D8 18
G PACKAGE
36-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 95°C/W
Consult factory for Military grade parts.
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CO VERTER
CHARACTERISTICS With Internal Reference (Notes 5, 6)
LTC1604
LTC1604A
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Bits
Resolution (No Missing Codes)
Integral Linearity Error
Transition Noise
Offset Error
●
●
15
16
16
16
(Note 7)
(Note 8)
(Note 9)
(Note 9)
±1
±4
±0.5
0.7
±2
LSB
0.7
LSB
●
±0.05 ±0.125
±0.05 ±0.125
%
Offset Tempco
0.5
0.5
ppm/°C
Full-Scale Error
Internal Reference
External Reference
±0.125 ±0.25
±0.25
±0.125 ±0.25
±0.25
%
%
Full-Scale Tempco
I
(Reference) = 0, Internal Reference
OUT
±15
±15
ppm/°C
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A ALOG I PUT
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
IN
Analog Input Range (Note 2)
4.75 ≤ V ≤ 5.25V, –5.25 ≤ V ≤ –4.75V,
SS
±2.5
V
DD
SS
–
+
V
≤ (A , A ) ≤ AV
IN IN DD
I
Analog Input Leakage Current
Analog Input Capacitance
CS = High
●
±1
µA
IN
C
Between Conversions
During Conversions
43
5
pF
pF
IN
t
t
t
Sample-and-Hold Acquisition Time
380
–1.5
5
ns
ns
ACQ
AP
Sample-and-Hold Acquisition Delay Time
Sample-and-Hold Acquisition Delay Time Jitter
Analog Input Common Mode Rejection Ratio
ps
jitter
RMS
–
+
CMRR
–2.5V < (A = A ) < 2.5V
68
dB
IN
IN
2
LTC1604
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(Note 5)
DY A IC ACCURACY
LTC1604
MIN TYP MAX
LTC1604A
MIN TYP MAX UNITS
SYMBOL PARAMETER
CONDITIONS
S/N
Signal-to-Noise Ratio
5kHz Input Signal
100kHz Input Signal
●
90
90
87
90
90
dB
dB
S/(N + D) Signal-to-(Noise + Distortion) Ratio
5kHz Input Signal
100kHz Input Signal (Note 10)
90
89
90
89
dB
dB
●
●
84
THD
Total Harmonic Distortion
Up to 5th Harmonic
5kHz Input Signal
100kHz Input Signal
–100
–94
–100
–94 –88
dB
dB
SFDR
IMD
Spurious Free Dynamic Range
Intermodulation Distortion
100kHz Input Signal
96
–88
5
96
–88
5
dB
dB
f
= 29.37kHz, f = 32.446kHz
IN2
IN1
Full Power Bandwidth
MHz
kHz
Full Linear Bandwidth (S/(N + D) ≥ 84dB
350
350
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I TER AL REFERE CE CHARACTERISTICS
(Note 5)
PARAMETER
CONDITIONS
MIN
TYP
2.500
±15
MAX
UNITS
V
V
V
V
Output Voltage
Output Tempco
Line Regulation
I
I
= 0
= 0
2.475
2.515
REF
REF
REF
OUT
OUT
ppm/°C
4.75 ≤ V ≤ 5.25V
–5.25V ≤ V ≤ –4.75V
0.01
0.01
LSB/V
LSB/V
DD
SS
V
Output Resistance
0 ≤
I
≤ 1mA
OUT
7.5
kΩ
REF
REFCOMP Output Voltage
I
= 0
4.375
V
OUT
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DIGITAL I PUTS A D DIGITAL OUTPUTS
(Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
High Level Input Voltage
Low Level Input Voltage
Digital Input Current
Digital Input Capacitance
High Level Output Voltage
V
V
V
= 5.25V
= 4.75V
= 0V to V
●
●
●
2.4
V
V
IH
IL
DD
DD
IN
0.8
I
±10
µA
pF
IN
DD
C
V
5
IN
V
DD
V
DD
= 4.75V, I
= 4.75V, I
= –10µA
= –400µA
4.5
V
V
OH
OUT
OUT
●
4.0
V
Low Level Output Voltage
V
V
= 4.75V, I
= 4.75V, I
= 160µA
= 1.6mA
0.05
0.10
V
V
OL
DD
DD
OUT
OUT
●
●
●
0.4
±10
15
I
Hi-Z Output Leakage D15 to D0
Hi-Z Output Capacitance D15 to D0
Output Source Current
V
OUT
= 0V to V , CS High
µA
pF
OZ
DD
C
OZ
CS High (Note 11)
I
I
V
OUT
V
OUT
= 0V
–10
10
mA
mA
SOURCE
SINK
Output Sink Current
= V
DD
3
LTC1604
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POWER REQUIRE E TS (Note 5)
SYMBOL
PARAMETER
CONDITIONS
(Notes 12, 13)
(Note 12)
MIN
4.75
TYP
MAX
5.25
UNITS
V
V
Positive Supply Voltage
Negative Supply Voltage
V
V
DD
SS
–4.75
–5.25
I
Positive Supply Current
Nap Mode
CS = RD = 0V
●
●
●
18
1.5
1
30
2.4
100
mA
mA
µA
DD
CS = 0V, SHDN = 0V
CS = 5V, SHDN = 0V
Sleep Mode
I
Negative Supply Current
Nap Mode
CS = RD = 0V
26
1
1
40
100
100
mA
µA
µA
SS
CS = 0V, SHDN = 0V
CS = 5V, SHDN = 0V
Sleep Mode
P
Power Dissipation
Nap Mode
CS = RD = 0V
220
7.5
0.01
350
12
1
mW
mW
mW
D
CS = 0V, SHDN = 0V
CS = 5V, SHDN = 0V
Sleep Mode
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(Note 5)
TI I G CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN
333
1.5
TYP
MAX
UNITS
kHz
µs
f
t
t
t
t
t
t
t
t
t
Maximum Sampling Frequency
Conversion Time
●
●
●
●
●
●
●
SMPL(MAX)
2.45
2.8
480
3
CONV
Acquisition Time
(Note 11)
ns
ACQ
Throughput Time (Acquisition + Conversion)
CS to RD Setup Time
µs
ACQ+CONV
(Notes 11, 12)
(Notes 11, 12)
(Notes 11, 12)
CS = Low (Note 12)
(Note 12)
0
ns
1
2
3
4
5
6
CS↓ to CONVST↓ Setup Time
SHDN↓ to CS↑ Setup Time
SHDN↑ to CONVST↓ Wake-Up Time
CONVST Low Time
10
10
ns
ns
400
ns
●
●
40
ns
CONVST to BUSY Delay
C = 25pF
L
36
60
ns
ns
80
t
Data Ready Before BUSY↑
ns
ns
7
●
●
●
32
200
–5
t
t
t
Delay Between Conversions
Wait Time RD↓ After BUSY↑
Data Access Time After RD↓
(Note 12)
(Note 12)
ns
ns
8
9
C = 25pF
L
40
45
50
50
60
ns
ns
10
●
●
C = 100pF
L
60
75
ns
ns
t
Bus Relinquish Time
60
70
75
ns
ns
ns
11
LTC1604C
LTC1604I
●
●
t
t
t
RD Low Time
(Note 12)
(Note 12)
●
●
t
ns
ns
ns
12
13
14
10
CONVST High Time
40
Aperture Delay of Sample-and-Hold
2
4
LTC1604
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TI I G CHARACTERISTICS
(Note 5)
denotes specifications that apply over the full operating temperature
The
●
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
range.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND, OGND
Note 8: Typical RMS noise at the code transitions. See Figure 17 for
histogram.
and AGND wired together unless otherwise noted.
Note 3: When these pin voltages are taken below V or above V , they
Note 9: Bipolar offset is the offset voltage measured from –0.5LSB when
the output code flickers between 0000 0000 0000 0000 and 1111 1111
1111 1111.
Note 10: Signal-to-Noise Ratio (SNR) is measured at 5kHz and distortion
is measured at 100kHz. These results are used to calculate Signal-to-Nosie
Plus Distortion (SINAD).
SS
DD
will be clamped by internal diodes. This product can handle input currents
greater than 100mA below V or above V without latchup.
SS
DD
Note 4: When these pin voltages are taken below V , they will be clamped
by internal diodes. This product can handle input currents greater than
SS
100mA below V without latchup. These pins are not clamped to V
.
Note 11: Guaranteed by design, not subject to test.
Note 12: Recommended operating conditions.
SS
DD
Note 5: V = 5V, V = –5V, f
= 333kHz, and t = t = 5ns unless
r f
DD
SS
SMPL
otherwise specified.
Note 13: The falling CONVST edge starts a conversion. If CONVST returns
high at a critical point during the conversion it can create small errors. For
best performance ensure that CONVST returns high either within 250ns
after conversion start or after BUSY rises.
Note 6: Linearity, offset and full-scale specification apply for a single-
+
–
ended A input with A grounded.
IN
IN
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TYPICAL PERFORMANCE CHARACTERISTICS
S/(N + D) vs Input Frequency
and Amplitude
Integral Nonlinearity vs
Output Code
Differential Nonlinearity vs
Output Code
2.0
1.5
1.0
0.8
100
90
80
70
60
50
40
30
20
10
0
V
= 0dB
IN
0.6
V
= –20dB
= –40dB
1.0
IN
IN
0.4
0.5
0.2
V
0.0
0.0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.5
–1.0
–1.5
–2.0
–32768
–16384
0
16384
32767
1k
10k
100k
1M
–32768
–16384
0
16384
32767
FREQUENCY (Hz)
CODE
CODE
1604 G01
1604 G11
1604 G10
Spurious-Free Dynamic Range
vs Input Frequency
Signal-to-Noise Ratio vs
Input Frequency
Distortion vs Input Frequency
0
100
90
80
70
60
50
40
30
20
10
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
THD
3RD
2ND
10k
INPUT FREQUENCY (Hz)
1k
100k
1M
10k
INPUT FREQUENCY (Hz)
10k
FREQUENCY (Hz)
1k
100k
1M
1k
100k
1M
1604 G05
1604 G03
1604 G04
5
LTC1604
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TYPICAL PERFORMANCE CHARACTERISTICS
Input Common Mode Rejection
vs Input Frequency
Power Supply Feedthrough vs
Intermodulaton Distortion
Ripple Frequency
0
–20
80
70
60
50
40
30
20
10
0
0
–20
f
= 333kHz
= 10mV
SAMPLE
RIPPLE
f
f
f
= 333kHz
SAMPLE
V
= 29.3kHz
IN1
IN2
= 32.4kHz
–40
–40
–60
–60
–80
–80
A
VDD
–100
–120
–140
–100
–120
V
SS
1k
10k
100k
1M
1k
10k
100k
1M
0
20 40 60
120 140 160
80 100
INPUT FREQUENCY (Hz)
INPUT FREQUENCY (Hz)
FREQUENCY (kHz)
1604 G06
1604 G07
1604G09
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PIN FUNCTIONS
AIN+ (Pin 1): Positive Analog Input. The ADC converts the
OGND (Pin 28): Digital Ground for Output Drivers.
difference voltage between AIN+ and AIN– with a differen-
OVDD (Pin 29): Digital Power Supply for Output Drivers.
Bypass to OGND with 10µF tantalum in parallel with 0.1µF
ceramic.
+
tial range of ±2.5V. AIN has a ±2.5V input range when
–
AIN is grounded.
AIN– (Pin2):NegativeAnalogInput. Canbegrounded, tied
RD (Pin 30): Read Input. A logic low enables the output
drivers when CS is low.
+
to a DC voltage or driven differentially with AIN
.
VREF (Pin3):2.5VReferenceOutput.BypasstoAGNDwith
2.2µF tantalum in parallel with 0.1µF ceramic.
CONVST (Pin 31): Conversion Start Signal. This active
low signal starts a conversion on its falling edge when CS
is low.
REFCOMP (Pin 4): 4.375 Reference Compensation Pin.
Bypass to AGND with 47µF tantalum in parallel with 0.1µF
ceramic.
CS (Pin 32): The Chip Select Input. Must be low for the
ADC to recognize CONVST and RD inputs.
AGND(Pins5to8): AnalogGrounds. Tietoanalogground
plane.
SHDN (Pin 33): Power Shutdown. Drive this pin low with
CS low for nap mode. Drive this pin low with CS high for
sleep mode.
DVDD (Pin 9): 5V Digital Power Supply. Bypass to DGND
with 10µF tantalum in parallel with 0.1µF ceramic.
VSS (Pin 34): –5V Negative Supply. Bypass to AGND with
10µF tantalum in parallel with 0.1µF ceramic.
DGND (Pin 10): Digital Ground for Internal Logic. Tie to
analog ground plane.
AVDD (Pin 35): 5V Analog Power Supply. Bypass to AGND
with 10µF tantalum in parallel with 0.1µF ceramic.
D15 to D0 (Pins 11 to 26): Three-State Data Outputs. D15
is the Most Significant Bit.
AVDD (Pin 36): 5V Analog Power Supply. Bypass to AGND
with 10µF tantalum in parallel with 0.1µF ceramic and
connect this pin to Pin 35 with a 10Ω resistor.
BUSY (Pin 27): The BUSY output shows the converter
status. It is low when a conversion is in progress. Data is
valid on the rising edge of BUSY.
6
LTC1604
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W
FU CTIO AL BLOCK DIAGRA
2.2µF
10µF
5V 10µF
5V 10µF
10Ω
+
+
+
3
10
36
DD
35
9
V
AV
AV
DD
DV
DD
DGND
REF
SHDN
CS
33
32
31
30
27
CONTROL
LOGIC
µP
CONVST
RD
CONTROL
LINES
REFCOMP
7.5k
AND
4
2.5V
REF
1.75X
TIMING
+
4.375V
BUSY
47µF
OV
DD
29
28
5V OR
+
3V
10µF
+
OGND
1
2
A
IN
+
DIFFERENTIAL
ANALOG INPUT
±2.5V
16-BIT
SAMPLING
ADC
OUTPUT
BUFFERS
B15 TO B0
16-BIT
PARALLEL
BUS
–
A
IN
D15 TO D0
–
11 TO 26
AGND AGND AGND AGND
V
SS
1604 TA01
5
6
7
8
34
10µF
+
–5V
TEST CIRCUITS
Load Circuits for Access Timing
Load Circuits for Output Float Delay
5V
5V
1k
1k
DN
DN
DN
DN
1k
C
L
C
1k
C
C
L
L
L
(A) Hi-Z TO V AND V TO V
OH OL
(B) Hi-Z TO V AND V TO V
OL OH
(A) V TO Hi-Z
OH
(B) V TO Hi-Z
OL
OH
OL
1604 TC01
1604 TC02
7
LTC1604
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APPLICATIONS INFORMATION
CONVERSION DETAILS
summing junctions. This input charge is successively
compared with the binary-weighted charges supplied by
the differential capacitive DAC. Bit decisions are made by
the high speed comparator. At the end ofa conversion, the
The LTC1604 uses a successive approximation algorithm
and internal sample-and-hold circuit to convert an analog
signaltoa16-bitparalleloutput. TheADCiscompletewith
a sample-and-hold, a precision reference and an internal
clock. The control logic provides easy interface to micro-
processorsandDSPs. (Please refer to the Digital Interface
section for the data format.)
+
–
differential DAC output balances the AIN and AIN input
charges. The SAR contents (a 16-bit data word) which
+
–
represent the difference of AIN and AIN are loaded into
the 16-bit output latches.
Conversion start is controlled by the CS and CONVST
inputs. At the start of the conversion the successive
approximation register (SAR) resets. Once a conversion
cycle has begun it cannot be restarted.
DIGITAL INTERFACE
The A/D converter is designed to interface with micropro-
cessors as a memory mapped device. The CS and RD
control inputs are common to all peripheral memory
interfacing. A separate CONVST is used to initiate a con-
version.
During the conversion, the internal differential 16-bit
capacitive DAC output is sequenced by the SAR from the
Most Significant Bit (MSB) to the Least Significant Bit
+
–
Internal Clock
(LSB). Referring to Figure 1, the AIN and AIN inputs are
acquired during the acquire phase and the comparator
offset is nulled by the zeroing switches. In this acquire
phase,adurationof480nswillprovideenoughtimeforthe
sample-and-hold capacitors to acquire the analog signal.
Duringtheconvertphasethecomparatorzeroingswitches
open, putting the comparator into compare mode. The
input switches connect the CSMPL capacitors to ground,
transferring the differential analog input charge onto the
The A/D converter has an internal clock that runs the A/D
conversion.Theinternalclockisfactorytrimmedtoachieve
a typical conversion time of 2.45µs and a maximum
conversion time of 2.8µs over the full temperature range.
No external adjustments are required. The guaranteed
maximumacquisitiontimeis480ns.Inaddition,athrough-
put time (acquisition + conversion) of 3µs and a minimum
sampling rate of 333ksps are guaranteed.
3V Input/Output Compatible
C
SMPL
SAMPLE
SAMPLE
+
–
A
The LTC1604 operates on ±5V supplies, which makes the
device easy to interface to 5V digital systems. This device
can also talk to 3V digital systems: the digital input pins
(SHDN, CS, CONVST and RD) of the LTC1604 recognize
3V or 5V inputs. The LTC1604 has a dedicated output
supply pin (OVDD) that controls the output swings of the
digital output pins (D0 to D15, BUSY) and allows the part
to talk to either 3V or 5V digital systems. The output is
two’s complement binary.
IN
IN
HOLD
ZEROING SWITCHES
HOLD
C
SMPL
A
HOLD
HOLD
+C
DAC
DAC
+
–C
COMP
–
+V
DAC
Power Shutdown
–V
DAC
The LTC1604 provides two power shutdown modes, Nap
and Sleep, to save power during inactive periods. The Nap
mode reduces the power by 95% and leaves only the
digital logic and reference powered up. The wake-up time
from Nap to active is 200ns. In Sleep mode all bias
16
D15
D0
•
•
•
OUTPUT
LATCHES
SAR
1604 F01
Figure 1. Simplified Block Diagram
8
LTC1604
U
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APPLICATIONS INFORMATION
currents are shut down and only leakage current remains
(about 1µA). Wake-up time from Sleep mode is much
slower since the reference circuit must power up and
settle. Sleepmodewake-uptimeisdependentonthevalue
of the capacitor connected to the REFCOMP (Pin 4). The
wake-up time is 160ms with the recommended 47µF
capacitor.
SHDN
t
3
CS
1604 F02a
Figure 2a. Nap Mode to Sleep Mode Timing
Shutdown is controlled by Pin 33 (SHDN). The ADC is in
shutdown when SHDN is low. The shutdown mode is
selected with Pin 32 (CS). When SHDN is low, CS low
selects nap and CS high selects sleep.
SHDN
t
4
CONVST
1604 F02b
Timing and Control
Figure 2b. SHDN to CONVST Wake-Up Timing
Conversion start and data read operations are controlled
by three digital inputs: CONVST, CS and RD. A falling edge
applied to the CONVST pin will start a conversion after the
ADC has been selected (i.e., CS is low). Once initiated, it
cannot be restarted until the conversion is complete.
Converter status is indicated by the BUSY output. BUSY is
low during a conversion.
CS
t
2
CONVST
RD
t
1
We recommend using a narrow logic low or narrow logic
high CONVST pulse to start a conversion as shown in
Figures 5 and 6. A narrow low or high CONVST pulse
prevents the rising edge of the CONVST pulse from upset-
ting the critical bit decisions during the conversion time.
Figure 4 shows the change of the differential nonlinearity
error versus the low time of the CONVST pulse. As shown,
if CONVST returns high early in the conversion (e.g.,
CONVST low time <500ns), accuracy is unaffected. Simi-
larly, if CONVST returns high after the conversion is over
(e.g., CONVST low time >tCONV), accuracy is unaffected.
For best results, keep t5 less than 500ns or greater than
1604 F03
Figure 3. CS top CONVST Setup Timing
4
3
2
1
0
t
t
ACQ
CONV
tCONV
.
Figures 5 through 9 show several different modes of
operation. In modes 1a and 1b (Figures 5 and 6), CS and
RDarebothtiedlow.ThefallingedgeofCONVSTstartsthe
conversion. The data outputs are always enabled and data
can be latched with the BUSY rising edge. Mode 1a shows
operationwithanarrowlogiclowCONVSTpulse. Mode1b
shows a narrow logic high CONVST pulse.
1200
1600
0
400
800
2000
2400 2800
CONVST LOW TIME, t (ns)
5
1604 F04
Figure 4. Change in DNL vs CONVST Low Time. Be Sure the
CONVST Pulse Returns High Early in the Conversion or After
the End of Conversion
In mode 2 (Figure 7) CS is tied low. The falling edge of
CONVST signal starts the conversion. Data outputs are in
9
LTC1604
APPLICATIONS INFORMATION
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t
CONV
CS = RD = 0
t
5
CONVST
t
t
8
6
BUSY
DATA
t
7
DATA (N – 1)
D15 TO D0
DATA N
D15 TO D0
DATA (N + 1)
D15 TO D0
1604 F05
Figure 5. Mode 1a. CONVST Starts a Conversion. Data Outputs Always Enabled
(CONVST =
)
t
CS = RD = 0
CONVST
t
8
CONV
t
t
5
13
t
t
6
6
BUSY
DATA
t
7
DATA (N – 1)
D15 TO D0
DATA N
D15 TO D0
DATA (N + 1)
D15 TO D0
1604 F06
Figure 6. Mode 1b. CONVST Starts a Conversion. Data Outputs Always Enabled
(CONVST =
)
t
13
t
t
t
8
CS = 0
CONV
5
CONVST
t
6
BUSY
RD
t
t
11
9
t
12
t
10
DATA N
D15 TO D0
DATA
1604 F07
Figure 7. Mode 2. CONVST Starts a Conversion. Data is Read by RD
10
LTC1604
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APPLICATIONS INFORMATION
t
t
8
CS = 0
CONV
RD = CONVST
t
t
11
6
BUSY
DATA
t
t
7
10
DATA (N – 1)
D5 TO D0
DATA N
D15 TO D0
DATA N
D15 TO D0
DATA (N + 1)
D15 TO D0
1604 F08
Figure 8. Mode 2. Slow Memory Mode Timing
t
t
8
CONV
CS = 0
RD = CONVST
t
t
11
6
BUSY
t
10
DATA (N – 1)
D15 TO D0
DATA N
D15 TO D0
DATA
1604 F09
Figure 9. ROM Mode Timing
three-stateuntilreadbytheMPUwiththeRDsignal. Mode
2 can be used for operation with a shared data bus.
DIFFERENTIAL ANALOG INPUTS
Driving the Analog Inputs
In slow memory and ROM modes (Figures 8 and 9) CS is
tied low and CONVST and RD are tied together. The MPU
starts the conversion and reads the output with the com-
bined CONVST-RD signal. Conversions are started by the
MPU or DSP (no external sample clock is needed).
The differential analog inputs of the LTC1604 are easy to
drive.Theinputsmaybedrivendifferentiallyorasasingle-
endedinput(i.e.,theAIN– inputisgrounded).TheAIN+ and
–
AIN inputs are sampled at the same instant. Any un-
wanted signal that is common mode to both inputs will be
reduced by the common mode rejection of the sample-
and-hold circuit. The inputs draw only one small current
spike while charging the sample-and-hold capacitors at
the end of conversion. During conversion the analog
inputs draw only a small leakage current. If the source
impedance of the driving circuit is low, then the LTC1604
inputs can be driven directly. As source impedance in-
creases so will acquisition time (see Figure 10). For
minimum acquisition time with high source impedance, a
buffer amplifier should be used. The only requirement is
that the amplifier driving the analog input(s) must settle
after the small current spike before the next conversion
In slow memory mode the processor applies a logic low to
RD (= CONVST), starting the conversion. BUSY goes low,
forcing the processor into a wait state. The previous
conversion result appears on the data outputs. When the
conversion is complete, the new conversion results
appear on the data outputs; BUSY goes high, releasing the
processor and the processor takes RD (=CONVST) back
high and reads the new conversion data.
In ROM mode, the processor takes RD (=CONVST) low,
startingaconversionandreadingthepreviousconversion
result. Aftertheconversioniscomplete, theprocessorcan
read the new result and initiate another conversion.
11
LTC1604
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10
LT®1007: Low Noise Precision Amplifier. 2.7mA supply
current, ±5V to ±15V supplies, gain bandwidth product
8MHz, DC applications.
1
0.1
LT1097:LowCost, LowPowerPrecisionAmplifier. 300µA
supply current, ±5V to ±15V supplies, gain bandwidth
product 0.7MHz, DC applications.
LT1227:140MHzVideoCurrentFeedbackAmplifier.10mA
supply current, ±5V to ±15V supplies, low noise and low
distortion.
0.01
1
10
100
1k
10k
SOURCE RESISTANCE (Ω)
LT1360: 37MHz Voltage Feedback Amplifier. 3.8mA sup-
ply current, ±5V to ±15V supplies, good AC/DC specs.
1604 F10
Figure 10. tACQ vs Source Resistance
LT1363: 50MHz Voltage Feedback Amplifier. 6.3mA sup-
ply current, good AC/DC specs.
LT1364/LT1365: Dual and Quad 50MHz Voltage Feedback
Amplifiers. 6.3mA supply current per amplifier, good AC/
DC specs.
starts (settling time must be 200ns for full throughput
rate).
Choosing an Input Amplifier
Input Filtering
Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, to limit the magnitude
of the voltage spike seen by the amplifier from charging
the sampling capacitor, choose an amplifier that has a
lowoutputimpedance (<100Ω) at the closed-loop band-
width frequency. For example, if an amplifier is used in a
gainof+1andhasaunity-gainbandwidthof50MHz,then
the output impedance at 50MHz should be less than
100Ω. The second requirement is that the closed-loop
bandwidth must be greater than 15MHz to ensure
adequate small-signal settling for full throughput rate. If
slower op amps are used, more settling time can be
provided by increasing the time between conversions.
The noise and the distortion of the input amplifier and
other circuitry must be considered since they will add to
the LTC1604 noise and distortion. The small-signal band-
width of the sample-and-hold circuit is 15MHz. Any noise
or distortion products that are present at the analog inputs
will be summed over this entire bandwidth. Noisy input
circuitry should be filtered prior to the analog inputs to
minimize noise. A simple 1-pole RC filter is sufficient for
manyapplications.Forexample,Figure11showsa3000pF
capacitor from AIN+ to ground and a 100Ω source resistor
to limit the input bandwidth to 530kHz. The 3000pF
capacitor also acts as a charge reservoir for the input
sample-and-hold and isolates the ADC input from sam-
pling glitch sensitive circuitry. High quality capacitors and
resistors should be used since these components can add
distortion. NPO and silver mica type dielectric capacitors
haveexcellentlinearity.Carbonsurfacemountresistorscan
also generate distortion from self heating and from damage
that may occur during soldering. Metal film surface mount
resistors are much less susceptible to both problems.
The best choice for an op amp to drive the LTC1604 will
dependontheapplication. Generallyapplicationsfallinto
two categories: AC applications where dynamic specifi-
cations are most critical and time domain applications
where DC accuracy and settling time are most critical.
The following list is a summary of the op amps that are
suitable for driving the LTC1604. More detailed informa-
tion is available in the Linear Technology databooks, the
LinearViewTM CD-ROM and on our web site at:
www.linear-tech. com.
LinearView is a trademark of Linear Technology Corporation.
12
LTC1604
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100Ω
1
2
3
4
5
R1
7.5k
+
ANALOG INPUT
A
A
V
IN
V
3
4
REF
BANDGAP
REFERENCE
2.500V
3000pF
–
IN
LTC1604
REFCOMP
REFERENCE
AMP
REF
4.375V
REFCOMP
AGND
R2
12k
47µF
47µF
R3
16k
AGND
5
1604 F11
LTC1604
1604 F12a
Figure 11. RC Input Filter
Figure 12a. LTC1604 Reference Circuit
Input Range
5V
1
2
3
+
–
A
A
V
The±2.5VinputrangeoftheLTC1604isoptimizedforlow
noise and low distortion. Most op amps also perform well
over this same range, allowing direct coupling to the
analog inputs and eliminating the need for special transla-
tion circuitry.
IN
IN
ANALOG
INPUT
V
IN
LT1019A-2.5
V
OUT
REF
LTC1604
4
REFCOMP
Some applications may require other input ranges. The
LTC1604 differential inputs and reference circuitry can
accommodate other input ranges often with little or no
additional circuitry. The following sections describe the
reference and input circuitry and how they affect the input
range.
+
10µF
0.1µF
5
AGND
1604 F12b
Figure 12b. Using the LT1019-2.5 as an External Reference
Internal Reference
The VREF pin can be driven with a DAC or other means
showninFigure13.Thisisusefulinapplicationswherethe
peak input signal amplitude may vary. The input span of
the ADC can then be adjusted to match the peak input
signal, maximizing the signal-to-noise ratio. The filtering
of the internal LTC1604 reference amplifier will limit
the bandwidth and settling time of this circuit. A settling
time of 20ms should be allowed for after a reference
adjustment.
The LTC1604 has an on-chip, temperature compensated,
curvature corrected, bandgap reference that is factory
trimmedto2.500V.Itisconnectedinternallytoareference
amplifier and is available at VREF (Pin 3) (see Figure 12a).
A 7.5k resistor is in series with the output so that it can be
easily overdriven by an external reference or other
circuitry (see Figure 12b). The reference amplifier gains
the voltage at the VREF pin by 1.75 to create the required
internal reference voltage. This provides buffering
between the VREF pin and the high speed capacitive DAC.
Thereferenceamplifiercompensationpin(REFCOMP, Pin
4) must be bypassed with a capacitor to ground. The
reference amplifier is stable with capacitors of 22µF or
greater. For the best noise performance a 47µF ceramic or
47µF tantalum in parallel with a 0.1µF ceramic is recom-
mended.
Differential Inputs
The LTC1604 has a unique differential sample-and-hold
circuit that allows rail-to-rail inputs. The ADC will always
+
–
convert the difference of AIN – AIN independent of the
common mode voltage (see Figure 15a). The common
mode rejection holds up to extremely high frequencies
(see Figure 14a). The only requirement is that both inputs
13
LTC1604
APPLICATIONS INFORMATION
U
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1
2
3
4
5
+
1
2
+
–
A
A
V
IN
ANALOG INPUT
A
A
IN
IN
ANALOG INPUT
2V TO 2.7V
DIFFERENTIAL
–
0V TO
5V
IN
+
–
±2.5V
3
V
LTC1604
REF
2V TO 2.7V
LTC1604
LTC1450
REF
4
REFCOMP
AGND
REFCOMP
AGND
10µF
47µF
5
1604 F13
1604 F14b
Figure 13. Driving VREF with a DAC
Figure 14b. Selectable 0V to 5V or ±2.5V Input Range
80
Full-Scale and Offset Adjustment
70
60
50
40
30
20
10
0
Figure 15a shows the ideal input/output characteristics
for the LTC1604. The code transitions occur midway
between successive integer LSB values (i.e., –FS +
0.5LSB, –FS + 1.5LSB, –FS + 2.5LSB,... FS – 1.5LSB,
FS –0.5LSB). The output is two’s complement binary with
1LSB = FS – (–FS)/65536 = 5V/65536 = 76.3µV.
In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero. Offset
error must be adjusted before full-scale error. Figure 15b
shows the extra components required for full-scale error
adjustment. Zero offset is achieved by adjusting the offset
1k
10k
100k
1M
INPUT FREQUENCY (Hz)
1604 G14a
Figure 14a. CMRR vs Input Frequency
–
applied to the AIN input. For zero offset error apply
can not exceed the AVDD or VSS power supply voltages.
Integral nonlinearity errors (INL) and differential nonlin-
earity errors (DNL) are independent of the common mode
voltage, however, the bipolar zero error (BZE) will vary.
The change in BZE is typically less than 0.1% of the
common mode voltage. Dynamic performance is also
affected by the common mode voltage. THD will degrade
astheinputsapproacheitherpowersupplyrail,from96dB
with a common mode of 0V to 86dB with a common mode
of 2.5V or –2.5V.
011...111
011...110
000...001
000...000
111...111
111...110
100...001
100...000
Differential inputs allow greater flexibility for accepting
different input ranges. Figure 14b shows a circuit that
converts a 0V to 5V analog input signal with only an
additional buffer that is not in the signal path.
–(FS – 1LSB)
INPUT VOLTAGE (A – A
FS – 1LSB
+
–
)
IN
IN
1604 F15a
Figure 15a. LTC1604 Transfer Characteristics
14
LTC1604
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APPLICATIONS INFORMATION
–5V
ANALOG
INPUT
1
+
analog ground plane. No other digital grounds should be
connected to this analog ground plane. Low impedance
analog and digital power supply common returns are
essential to low noise operation of the ADC and the foil
width for these tracks should be as wide as possible. In
applications where the ADC data outputs and control
signals are connected to a continuously active micropro-
cessor bus, it is possible to get errors in the conversion
results. These errors are due to feedthrough from the
microprocessor to the successive approximation com-
parator. The problem can be eliminated by forcing the
microprocessor into a WAIT state during conversion or by
using three-state buffers to isolate the ADC data bus. The
traces connecting the pins and bypass capacitors must be
kept short and should be made as wide as possible.
A
IN
R3
24k
2
–
R8
A
IN
50k
R4
100Ω
LTC1604
3
R5 R7
47k 50k
V
REF
R6
24k
4
5
REFCOMP
AGND
+
0.1µF
47µF
1604 F15b
Figure 15b. Offset and Full-Scale Adjust Circuit
+
–38µV (i.e., –0.5LSB) at AIN and adjust the offset at the
–
AIN input until the output code flickers between 0000
The LTC1604 has differential inputs to minimize noise
coupling. CommonmodenoiseontheAIN+ andAIN– leads
will be rejected by the input CMRR. The AIN– input can be
0000 0000 0000 and 1111 1111 1111 1111. For full-scale
adjustment,aninputvoltageof2.499886V(FS/2–1.5LSBs)
is applied to AIN+ and R2 is adjusted until the output code
flickers between 0111 1111 1111 1110 and 0111 1111
1111 1111.
+
used as a ground sense for the AIN input; the LTC1604
+
will hold and convert the difference voltage between AIN
and AIN–. The leads to AIN+ (Pin 1) and AIN– (Pin 2) should
be kept as short as possible. In applications where this is
BOARD LAYOUT AND GROUNDING
+
–
not possible, the AIN and AIN traces should be run side
by side to equalize coupling.
Wire wrap boards are not recommended for high resolu-
tion or high speed A/D converters. To obtain the best
performance from the LTC1604, a printed circuit board
with ground plane is required. Layout should ensure that
digital and analog signal lines are separated as much as
possible. Particular care should be taken not to run any
digital track alongside an analog signal track or under-
neath the ADC.The analog input should be screened by
AGND.
SUPPLY BYPASSING
High quality, low series resistance ceramic, 10µF or 47µF
bypasscapacitorsshouldbeusedattheVDD andREFCOMP
pins as shown in Figure 16 and in the Typical Application
on the first page of this data sheet. Surface mount ceramic
capacitors such as Murata GRM235Y5V106Z016 provide
excellent bypassing in a small board space. Alternatively,
10µF tantalum capacitors in parallel with 0.1µF ceramic
capacitors can be used. Bypass capacitors must be lo-
cated as close to the pins as possible. The traces connect-
ing the pins and the bypass capacitors must be kept short
and should be made as wide as possible.
An analog ground plane separate from the logic system
ground should be established under and around the ADC.
Pin 5 to Pin 8 (AGNDs), Pin 10 (ADC’s DGND) and all other
analog grounds should be connected to this single analog
ground point. The REFCOMP bypass capacitor and the
DVDD bypass capacitor should also be connected to this
15
LTC1604
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1
+
DIGITAL
SYSTEM
LTC1604
AV AV
A
IN
–
A
IN
V
V
DV
DGND OV
10
OGND
28
REFCOMP AGND
REF
3
SS
DD
DD
DD
9
DD
29
ANALOG
INPUT
CIRCUITRY
2
4
5 TO 8 34
36
35
+
–
2.2µF
10µF
47µF
10µF 10µF 10µF
10µF
1604 F16
Figure 16. Power Supply Grounding Practice
2500
DC PERFORMANCE
The noise of an ADC can be evaluated in two ways: signal-
to-noise raio (SNR) in frequency domain and histogram in
time domain. The LTC1604 excels in both. Figure 18a
demonstrates that the LTC1604 has an SNR of over 90dB
in frequency domain. The noise in the time domain histo-
gram is the transition noise associated with a high resolu-
tion ADC which can be measured with a fixed DC signal
applied to the input of the ADC. The resulting output codes
are collected over a large number of conversions. The
shape of the distribution of codes will give an indication of
the magnitude of the transition noise. In Figure 17 the
distribution of output codes is shown for a DC input that
hasbeendigitized4096times.ThedistributionisGaussian
and the RMS code transition noise is about 0.66LSB. This
correspondstoanoiselevelof90.9dBrelativetofullscale.
Adding to that the theoretical 98dB of quantization error
for 16-bit ADC, the resultant corresponds to an SNR level
of 90.1dB which correlates very well to the frequency
domain measurements in DYNAMIC PERFORMANCE
section.
2000
1500
1000
500
0
–4
–5
–3 –2 –1
0
1
2
3
4
5
CODE
1604 F17
Figure 17. Histogram for 4096 Conversions
0
f
f
= 333kHz
SAMPLE
IN
SINAD = 90.2dB
THD = –103.2dB
= 4.959kHz
–20
–40
–60
–80
–100
–120
DYNAMIC PERFORMANCE
The LTC1604 has excellent high speed sampling capabil-
ity. Fast fourier transform (FFT) test techniques are used
to test the ADC’s frequency response, distortions and
noise at the rated throughput. By applying a low distortion
sine wave and analyzing the digital output using an FFT
algorithm, theADC’s spectralcontentcanbeexamined for
frequenciesoutsidethefundamental. Figures18aand18b
show typical LTC1604 FFT plots.
–140
0
20 40 60 80 100 120 140 160
FREQUENCY (kHz)
1604 F18a
Figure 18a. This FFT of the LTC1604’s Conversion of a
Full-Scale 5kHz Sine Wave Shows Outstanding Response
with a Very Low Noise Floor When Sampling at 333ksps
16
LTC1604
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Signal-to-Noise Ratio
0
f
f
= 333kHz
SAMPLE
IN
= 97.152kHz
–20
SINAD = 89dB
THD = –96dB
The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratiobetweentheRMSamplitudeofthefundamentalinput
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
tofrequenciesfromaboveDCandbelowhalfthesampling
frequency. Figure 18a shows a typical spectral content
with a 333kHz sampling rate and a 5kHz input. The
dynamicperformanceisexcellentforinputfrequenciesup
to and beyond the Nyquist limit of 167kHz.
–40
–60
–80
–100
–120
–140
0
20 40 60 80 100 120 140 160
FREQUENCY (kHz)
1604 F18b
Effective Number of Bits
Figure 18b. Even with Inputs at 100kHz, the LTC1604’s
Dynamic Linearity Remains Robust
The effective number of bits (ENOBs) is a measurement of
the resolution of an ADC and is directly related to the
S/(N + D) by the equation:
98
92
86
80
74
68
62
56
50
16
15
14
13
12
11
10
9
N = [S/(N + D) – 1.76]/6.02
where N is the effective number of bits of resolution and
S/(N + D) is expressed in dB. At the maximum sampling
rate of 333kHz the LTC1604 maintains above 14 bits up to
theNyquistinputfrequencyof167kHz(refertoFigure19).
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sumofallharmonicsoftheinputsignaltothefundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD is
expressed as:
8
1k
10k
100k
1M
FREQUENCY (Hz)
1604 F19
Figure 19. Effective Bits and Signal/(Noise + Distortion)
vs Input Frequency
2
2
2
2
V2 + V3 + V4 +...Vn
0
–10
–20
–30
–40
–50
–60
–70
THD = 20Log
V1
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through Vn are the amplitudes of the
secondthroughnthharmonics.THDvsInputFrequencyis
shown in Figure 20. The LTC1604 has good distortion
performance up to the Nyquist frequency and beyond.
–80
–90
THD
3RD
–100
–110
2ND
10k
INPUT FREQUENCY (Hz)
1k
100k
1M
1604 G04
Figure 20. Distortion vs Input Frequency
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Intermodulation Distortion
etc. For example, the 2nd order IMD terms include
(fa – fb). If the two input sine waves are equal in magni-
tude, thevalue(indecibels)ofthe2ndorderIMDproducts
can be expressed by the following formula:
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
Amplitude at (fa ± fb)
IMD fa± fb = 20Log
(
)
Amplitude at fa
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer func-
tion can create distortion products at the sum and differ-
ence frequencies of mfa ±nfb, where m and n = 0, 1, 2, 3,
Peak Harmonic or Spurious Noise
The peak harmonic or spurious noise is the largest spec-
tral component excluding the input signal and DC. This
value is expressed in decibels relative to the RMS value of
a full-scale input signal.
0
f
f
f
= 333kHz
SAMPLE
IN1
IN2
= 29.3kHz
–20
–40
Full-Power and Full-Linear Bandwidth
= 32.4kHz
The full-power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is
reduced by 3dB for a full-scale input signal.
–60
–80
The full-linear bandwidth is the input frequency at which
the S/(N + D) has dropped to 84dB (13.66 effective bits).
The LTC1604 has been designed to optimize input band-
width, allowingtheADCtoundersampleinputsignalswith
frequenciesabovetheconverter’sNyquistFrequency. The
noise floor stays very low at high frequencies; S/(N + D)
becomes dominated by distortion at frequencies far
beyond Nyquist.
–100
–120
–140
0
20 40 60
FREQUENCY (kHz)
120 140 160
80 100
1604 G06
Figure 21. Intermodulation Distortion Plot
18
LTC1604
U
PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted.
G Package
36-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
0.499 – 0.509*
(12.67 – 12.93)
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
0.301 – 0.311
(7.65 – 7.90)
5
7
8
1
2
3
4
6
9 10 11 12 13 14 15 16 17 18
0.205 – 0.212**
(5.20 – 5.38)
0.068 – 0.078
(1.73 – 1.99)
0° – 8°
0.0256
(0.65)
BSC
0.005 – 0.009
(0.13 – 0.22)
0.022 – 0.037
(0.55 – 0.95)
0.002 – 0.008
(0.05 – 0.21)
0.010 – 0.015
(0.25 – 0.38)
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
G36 SSOP 1196
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
19
LTC1604
TYPICAL APPLICATION
U
Using the LTC1604 and Two LTC1391s as an 8-Channel Differential 16-Bit ADC System
5V
2.2µF
10µF
5V 10µF
5V 10µF
10Ω
36
+
+
+
+
+
LTC1391
3
35
10
9
1µF
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
+
+
DV
DD
V
REF
AV
AV
DD
DGND
DD
CH0
CH0
V
SHDN 33
CS 32
CH1
CH2
CH3
CH4
CH5
CH6
CH7
D
–
–5V
1µF
CONTROL
LOGIC
AND
TIMING
V
µP
CONTROL
LINES
CONVST 31
RD 30
7.5k
REFCOMP
D
OUT
4
2.5V
REF
1.75X
+
4.375V
D
IN
BUSY 27
47µF
CS
OV
DD
29
5V OR
3V
10µF
LTC1604
CLK
+
+
–
A
1
2
IN
+
–
OGND 28
CH7
CH0
GND
+
–
3000pF
3000pF
16-BIT
SAMPLING
ADC
OUTPUT
BUFFERS
B15 TO B0
16-BIT
PARALLEL
BUS
5V
D15 TO D0
A
IN
LTC1391
1µF
11 TO 26
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
+
AGND AGND AGND AGND V
SS
34
V
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
1604 TA03
5
6
7
8
D
–
–5V
10µF
+
V
+
–5V
D
OUT
D
D
IN
IN
µP
CONTROL
LINES
CS
CS
CLK
CLK
–
GND
CH7
RELATED PARTS
SAMPLING ADCs
PART NUMBER
LTC1410
DESCRIPTION
COMMENTS
12-Bit, 1.25Msps, ±5V ADC
71.5dB SINAD at Nyquist, 150mW Dissipation
55mW Power Dissipation, 72dB SINAD
15mW, Serial/Para llel ±10V
LTC1415
12-Bit, 1.25Msps, Single 5V ADC
14-Bit, 200ksps, Single 5V ADC
Low Power 14-Bit, 800ksps ADC
16-Bit, 100ksps, Single 5V ADC
LTC1418
LTC1419
True 14-Bit Linearity, 81.5dB SINAD, 150mW Dissipation
LTC1605
±10V Inputs, 55mW, Byte or Parallel I/O
DACs
PART NUMBER
LTC1595
LTC1596
LTC1597
LTC1650
DESCRIPTION
COMMENTS
16-Bit Serial Multiplying I
16-Bit Serial Multiplying I
DAC in SO-8
DAC
±1LSB Max INL/DNL, Low Glitch, DAC8043 16-Bit Upgrade
OUT
±1LSB Max INL/DNL, Low Glitch, AD7543/DAC8143 16-Bit Upgrade
±1LSB Max INL/DNL, Low Glitch, 4 Quadrant Resistors
Low Power, Low Gritch, 4-Quadrant Multiplication
OUT
16-Bit Parallel, Multiplying DAC
16-Bit Serial V DAC
OUT
1604fa LT/TP 1098 REV A 2K • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 1998
20 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
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