LTC1604IG#PBF [Linear]
LTC1604 - High Speed, 16-Bit, 333ksps Sampling A/D Converter with Shutdown; Package: SSOP; Pins: 36; Temperature Range: -40°C to 85°C;
| 型号： | LTC1604IG#PBF |
| 厂家： | 
Linear |
| 描述： | LTC1604 - High Speed, 16-Bit, 333ksps Sampling A/D Converter with Shutdown; Package: SSOP; Pins: 36; Temperature Range: -40°C to 85°C 光电二极管 转换器 |
| 文件： | 总20页 (文件大小：579K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1604
High Speed, 16-Bit, 333ksps
Sampling A/D Converter
with Shutdown
FEATURES
DESCRIPTION
The LTC®1604 is a 333ksps, 16-bit sampling A/D con-
verter that draws only 220mW from ±±5 sꢀppliesꢁ This
high performance device inclꢀdes a high dynamic range
sample-and-hold, a precision reference and a high speed
parallel oꢀtpꢀtꢁ Two digitally selectable power shꢀtdown
modes provide power savings for low power systemsꢁ
n
A Complete, 333ksps 16-Bit ADC
n
90dB S/(N+D) and –100dB THD (Typ)
n
Power Dissipation: 220mW (Typ)
n
No Pipeline Delay
n
No Missing Codes over Temperatꢀre
n
Nap (7mW) and Sleep (10μW) Shutdown Modes
n
Operates with Internal 1±ppm/°C Reference
The LTC1604’s fꢀll-scale inpꢀt range is ±2ꢁ±5ꢁ Oꢀtstand-
ing AC performance inclꢀdes 90dB S/(N+D) and –100dB
THD at a sample rate of 333kspsꢁ
or External Reference
n
Trꢀe Differential Inpꢀts Reject Common Mode Noise
n
±MHz Fꢀll Power Bandwidth
n
Theꢀniqꢀedifferentialinpꢀtsample-and-holdcanacqꢀire
single-ended or differential inpꢀt signals ꢀp to its 1±MHz
bandwidthꢁ The 68dB common mode rejection allows
ꢀsers to eliminate groꢀnd loops and common mode noise
by measꢀring signals differentially from the soꢀrceꢁ
±2ꢁ±5 Bipolar Inpꢀt Range
n
36-Pin SSOP Package
APPLICATIONS
n
Telecommꢀnications
n
Digital Signal Processing
The ADC has μP compatible,16-bit parallel oꢀtpꢀt portꢁ
ThereisnopipelinedelayinconversionresꢀltsꢁAseparate
convert start inpꢀt and a data ready signal (BUSY) ease
connections to FlFOs, DSPs and microprocessorsꢁ
n
Mꢀltiplexed Data Acqꢀisition Systems
High Speed Data Acqꢀisition
Spectrꢀm Analysis
Imaging Systems
n
n
n
L, LTC and LT are registered trademarks of Linear Technology Corporationꢁ
TYPICAL APPLICATION
2ꢁ2μF
10μF
±5 10μF
±5 10μF
LTC1604 4096 Point FFT
10Ω
+
+
+
0
3
10
36
3±
9
5
A5
A5
DD
D5
DD
DGND
REF
DD
–20
–40
SHDN
CS
33
32
31
30
27
CONTROL
LOGIC
AND
TIMING
μP
CONTROL
LINES
CONVST
RD
REFCOMP
7ꢁ±k
4
2ꢁ±5
REF
–60
1ꢁ7±X
+
4ꢁ37±5
BUSY
47μF
–80
O5
DD
29
28
±5 OR
+
35
–100
–120
–140
10μF
+
OGND
1
2
A
IN
+
DIFFERENTIAL
ANALOG INPUT
±2ꢁ±5
16-BIT
SAMPLING
ADC
OUTPUT
BUFFERS
B1± TO B0
16-BIT
–
A
IN
PARALLEL
BUS
D1± TO D0
–
0
20 40 60 80 100
120
140 160
11 TO 26
FREQUENCY (kHz)
AGND AGND AGND AGND
5
SS
34
1604 TA01
±
6
7
8
1604 TA02
10μF
+
–±5
1604fa
1
LTC1604
ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDER INFORMATION
AVDD = DVDD = OVDD = VDD (Notes 1, 2)
TOP 5IEW
ORDER
PART NUMBER
+
Sꢀpply 5oltage (5 )ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ65
A
A
1
2
3
4
±
6
7
8
9
36 A5
3± A5
DD
IN
DD
DD
–
IN
Negative Sꢀpply 5oltage (5 )ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ–65
SS
5
34
5
SS
REF
LTC1604CG
LTC1604IG
LTC1604ACG
LTC1604AIG
Total Sꢀpply 5oltage (5 to 5 ) ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ125
DD
SS
REFCOMP
AGND
33 SHDN
32 CS
Analog Inpꢀt 5oltage
(Note 3)ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ(5 – 0ꢁ35) to (5 + 0ꢁ35)
AGND
31 CONV
30 RD
SS
DD
DD
DD
AGND
5
5oltage (Note 4)ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ –0ꢁ35 to (5 + 0ꢁ35)
AGND
29 O5
DD
REF
D5
DD
28 OGND
27 BUSY
26 D0
2± D1
24 D2
23 D3
22 D4
21 D±
20 D6
19 D7
REFCOMP 5oltage (Note 4)ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ –0ꢁ35 to (5 + 0ꢁ35)
DGND 10
D1± (MSB) 11
D14 12
Digital Inpꢀt 5oltage (Note 4)ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ –0ꢁ35 to 105
Digital Oꢀtpꢀt 5oltageꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ –0ꢁ35 to (5 + 0ꢁ35)
DD
D13 13
Power Dissipationꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ ±00mW
D12 14
Operating Temperatꢀre Range
D11 1±
D10 16
LTC1604C ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ 0°C to 70°C
LTC1604Iꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ–40°C to 8±°C
Storage Temperatꢀre Range ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ –6±°C to 1±0°C
Lead Temperatꢀre (Soldering, 10 sec)ꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁꢁ300°C
D9 17
D8 18
G PACKAGE
36-LEAD PLASTIC SSOP
T
JMAX
= 12±°C, θ = 9±°C/W
JA
Consꢀlt factory for Military grade partsꢁ
CONVERTER CHARACTERISTICS With Internal Reference (Notes 5, 6)
LTC1604
LTC1604A
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Bits
l
l
Resolꢀtion (No Missing Codes)
Integral Linearity Error
Transition Noise
1±
16
16
16
(Note 7)
(Note 8)
(Note 9)
(Note 9)
±1
±4
±0ꢁ±
0ꢁ7
±2
LSB
0ꢁ7
LSB
l
Offset Error
±0ꢁ0± ±0ꢁ12±
0ꢁ±
±0ꢁ0± ±0ꢁ12±
0ꢁ±
%
Offset Tempco
ppm/°C
Fꢀll-Scale Error
Internal Reference
External Reference
±0ꢁ12± ±0ꢁ2±
±0ꢁ2±
±0ꢁ12± ±0ꢁ2±
±0ꢁ2±
%
%
Fꢀll-Scale Tempco
I (Reference) = 0, Internal Reference
OUT
±1±
±1±
ppm/°C
ANALOG INPUT
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
5
Analog Inpꢀt Range (Note 2)
4ꢁ7± ≤ 5 ≤ ±ꢁ2±5, –±ꢁ2± ≤ 5 ≤ –4ꢁ7±5,
SS
±2ꢁ±
5
IN
DD
SS
–
+
5
≤ (A , A ) ≤ A5
IN IN DD
l
I
Analog Inpꢀt Leakage Cꢀrrent
Analog Inpꢀt Capacitance
CS = High
±1
μA
IN
C
Between Conversions
Dꢀring Conversions
43
±
pF
pF
IN
t
t
t
Sample-and-Hold Acqꢀisition Time
380
–1ꢁ±
±
ns
ns
ACQ
Sample-and-Hold Acqꢀisition Delay Time
Sample-and-Hold Acqꢀisition Delay Time Jitter
Analog Inpꢀt Common Mode Rejection Ratio
AP
ps
jitter
RMS
–
+
CMRR
–2ꢁ±5 < (A = A ) < 2ꢁ±5
68
dB
IN
IN
1604fa
2
LTC1604
DYNAMIC ACCURACY (Note 5)
LTC1604
TYP
LTC1604A
TYP
SYMBOL PARAMETER
CONDITIONS
MIN
MAX MIN
MAX UNITS
l
S/N
Signal-to-Noise Ratio
±kHz Inpꢀt Signal
100kHz Inpꢀt Signal
90
90
87
90
90
dB
dB
S/(N + D) Signal-to-(Noise + Distortion) Ratio
±kHz Inpꢀt Signal
90
89
90
89
dB
dB
l
l
100kHz Inpꢀt Signal (Note 10)
84
THD
Total Harmonic Distortion
Up to ±th Harmonic
±kHz Inpꢀt Signal
100kHz Inpꢀt Signal
–100
–94
–100
–94
dB
dB
–88
SFDR
IMD
Spꢀrioꢀs Free Dynamic Range
Intermodꢀlation Distortion
100kHz Inpꢀt Signal
96
–88
±
96
–88
±
dB
f
IN1
= 29ꢁ37kHz, f = 32ꢁ446kHz
dB
IN2
Fꢀll Power Bandwidth
MHz
kHz
Fꢀll Linear Bandwidth (S/(N + D) ≥ 84dB
3±0
3±0
INTERNAL REFERENCE CHARACTERISTICS (Note 5)
PARAMETER
CONDITIONS
MIN
TYP
2ꢁ±00
MAX
UNITS
5
5
REF
5
REF
5
REF
Oꢀtpꢀt 5oltage
Oꢀtpꢀt Tempco
Line Regꢀlation
I
I
= 0
= 0
2ꢁ47±
2ꢁ±1±
OUT
OUT
±1±
ppm/°C
4ꢁ7± ≤ 5 ≤ ±ꢁ2±5
–±ꢁ2±5 ≤ 5 ≤ –4ꢁ7±5
0ꢁ01
0ꢁ01
LSB/5
LSB/5
DD
SS
5
Oꢀtpꢀt Resistance
0 ≤ |I | ≤ 1mA
7ꢁ±
kΩ
5
REF
OUT
REFCOMP Oꢀtpꢀt 5oltage
I
= 0
4ꢁ37±
OUT
DIGITAL INPUTS AND DIGITAL OUTPUTS (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
l
5
5
High Level Inpꢀt 5oltage
Low Level Inpꢀt 5oltage
Digital Inpꢀt Cꢀrrent
Digital Inpꢀt Capacitance
High Level Oꢀtpꢀt 5oltage
5
5
5
= ±ꢁ2±5
= 4ꢁ7±5
= 05 to 5
2ꢁ4
5
5
IH
IL
DD
DD
IN
0ꢁ8
I
IN
±10
μA
pF
DD
C
5
±
IN
5
DD
5
DD
= 4ꢁ7±5, I
= 4ꢁ7±5, I
= –10μA
= –400μA
4ꢁ±
5
5
OH
OUT
OUT
l
4ꢁ0
5
Low Level Oꢀtpꢀt 5oltage
5
5
= 4ꢁ7±5, I
= 4ꢁ7±5, I
= 160μA
= 1ꢁ6mA
0ꢁ0±
0ꢁ10
5
5
OL
DD
DD
OUT
OUT
l
l
l
0ꢁ4
±10
1±
I
OZ
Hi-Z Oꢀtpꢀt Leakage D1± to D0
Hi-Z Oꢀtpꢀt Capacitance D1± to D0
Oꢀtpꢀt Soꢀrce Cꢀrrent
5
OUT
= 05 to 5 , CS High
μA
pF
DD
C
OZ
CS High (Note 11)
I
I
5
OUT
5
OUT
= 05
–10
10
mA
mA
SOURCE
SINK
Oꢀtpꢀt Sink Cꢀrrent
= 5
DD
1604fa
3
LTC1604
POWER REQUIREMENTS (Note 5)
SYMBOL
PARAMETER
CONDITIONS
(Notes 12, 13)
(Note 12)
MIN
4ꢁ7±
TYP
MAX
±ꢁ2±
UNITS
5
5
Positive Sꢀpply 5oltage
Negative Sꢀpply 5oltage
5
5
DD
SS
–4ꢁ7±
–±ꢁ2±
l
l
l
I
Positive Sꢀpply Cꢀrrent
Nap Mode
CS = RD = 05
18
1ꢁ±
1
30
2ꢁ4
100
mA
mA
μA
DD
CS = 05, SHDN = 05
CS = ±5, SHDN = 05
Sleep Mode
I
Negative Sꢀpply Cꢀrrent
Nap Mode
CS = RD = 05
26
1
1
40
100
100
mA
μA
μA
SS
CS = 05, SHDN = 05
CS = ±5, SHDN = 05
Sleep Mode
P
Power Dissipation
Nap Mode
CS = RD = 05
220
7ꢁ±
0ꢁ01
3±0
12
1
mW
mW
mW
D
CS = 05, SHDN = 05
CS = ±5, SHDN = 05
Sleep Mode
TIMING CHARACTERISTICS (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
333
1ꢁ±
TYP
MAX
UNITS
kHz
μs
l
l
l
l
l
l
l
f
t
t
t
t
t
t
t
t
t
Maximꢀm Sampling Freqꢀency
Conversion Time
SMPL(MAX)
2ꢁ4±
2ꢁ8
480
3
CON5
Acqꢀisition Time
(Note 11)
ns
ACQ
Throꢀghpꢀt Time (Acqꢀisition + Conversion)
CS to RD Setꢀp Time
μs
ACQ+CON5
(Notes 11, 12)
(Notes 11, 12)
(Notes 11, 12)
CS = Low (Note 12)
(Note 12)
0
ns
1
2
3
4
±
6
CS↓ to CONVST↓ Setꢀp Time
SHDN↓ to CS↑ Setꢀp Time
SHDN↑ to CONVST↓ Wake-Up Time
CONVST Low Time
10
10
ns
ns
400
ns
l
l
40
ns
CONVST to BUSY Delay
C = 2±pF
L
36
60
ns
ns
80
t
7
Data Ready Before BUSY↑
ns
ns
l
l
l
32
200
–±
t
t
t
Delay Between Conversions
Wait Time RD↓ After BUSY↑
Data Access Time After RD↓
(Note 12)
(Note 12)
ns
ns
8
9
C = 2±pF
L
40
4±
±0
±0
60
ns
ns
10
l
l
C = 100pF
L
60
7±
ns
ns
t
11
Bꢀs Relinqꢀish Time
60
70
7±
ns
ns
ns
l
l
LTC1604C
LTC1604I
l
l
t
12
t
13
t
14
RD Low Time
(Note 12)
(Note 12)
t
ns
ns
ns
10
CONVST High Time
40
Apertꢀre Delay of Sample-and-Hold
2
1604fa
4
LTC1604
TIMING CHARACTERISTICS (Note 5)
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing throꢀgh the actꢀal endpoints of the transfer cꢀrveꢁ
The deviation is measꢀred from the center of the qꢀantization bandꢁ
The l denotes specifications that apply over the fꢀll operating temperatꢀre
rangeꢁ
Note 1: Absolꢀte Maximꢀm Ratings are those valꢀes beyond which the life
Note 8: Typical RMS noise at the code transitionsꢁ See Figꢀre 17 for
of a device may be impairedꢁ
histogramꢁ
Note 2: All voltage valꢀes are with respect to groꢀnd with DGND, OGND
Note 9: Bipolar offset is the offset voltage measꢀred from –0ꢁ±LSB when
the oꢀtpꢀt code flickers between 0000 0000 0000 0000 and 1111 1111
1111 1111ꢁ
Note 10: Signal-to-Noise Ratio (SNR) is measꢀred at ±kHz and distortion
is measꢀred at 100kHzꢁ These resꢀlts are ꢀsed to calcꢀlate Signal-to-Nosie
Plꢀs Distortion (SINAD)ꢁ
and AGND wired together ꢀnless otherwise notedꢁ
Note 3: When these pin voltages are taken below 5 or above 5 , they
SS
DD
will be clamped by internal diodesꢁ This prodꢀct can handle inpꢀt cꢀrrents
greater than 100mA below 5 or above 5 withoꢀt latchꢀpꢁ
SS
DD
Note 4: When these pin voltages are taken below 5 , they will be clamped
by internal diodesꢁ This prodꢀct can handle inpꢀt cꢀrrents greater than
SS
Note 11: Gꢀaranteed by design, not sꢀbject to testꢁ
Note 12: Recommended operating conditionsꢁ
100mA below 5 withoꢀt latchꢀpꢁ These pins are not clamped to 5
ꢁ
DD
SS
Note 5: 5 = ±5, 5 = –±5, f
= 333kHz, and t = t = ±ns ꢀnless
DD
SS
SMPL
r f
otherwise specifiedꢁ
Note 13: The falling CONVST edge starts a conversionꢁ If CONVST retꢀrns
high at a critical point dꢀring the conversion it can create small errorsꢁ For
best performance ensꢀre that CONVST retꢀrns high either within 2±0ns
after conversion start or after BUSY risesꢁ
Note 6: Linearity, offset and fꢀll-scale specification apply for a single-
+
–
ended A inpꢀt with A groꢀndedꢁ
IN
IN
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity vs
Output Code
Differential Nonlinearity vs
Output Code
S/(N + D) vs Input Frequency
and Amplitude
2ꢁ0
1ꢁ±
1ꢁ0
0ꢁ8
100
90
80
70
60
±0
40
30
20
10
0
5
= 0dB
IN
0ꢁ6
5
= –20dB
= –40dB
1ꢁ0
IN
IN
0ꢁ4
0ꢁ±
0ꢁ2
5
0ꢁ0
0ꢁ0
–0ꢁ2
–0ꢁ4
–0ꢁ6
–0ꢁ8
–1ꢁ0
–0ꢁ±
–1ꢁ0
–1ꢁ±
–2ꢁ0
1k
10k
100k
1M
–32768
–16384
0
16384
32767
–32768
–16384
0
16384
32767
FREQUENCY (Hz)
CODE
CODE
1604 G01
1604 G11
1604 G10
Signal-to-Noise Ratio vs
Input Frequency
Spurious-Free Dynamic Range
vs Input Frequency
Distortion vs Input Frequency
0
100
90
80
70
60
50
40
30
20
10
0
0
–10
–20
–30
–40
–±0
–60
–70
–80
–90
–100
–110
–10
–20
–30
–40
–±0
–60
–70
–80
–90
–100
–110
THD
3RD
2ND
10k
INPUT FREQUENCY (Hz)
1k
100k
1M
10k
FREQUENCY (Hz)
10k
INPUT FREQUENCY (Hz)
1k
100k
1M
1k
100k
1M
1604 G04
1604 G03
1604 G0±
1604fa
5
LTC1604
TYPICAL PERFORMANCE CHARACTERISTICS
Power Supply Feedthrough vs
Input Common Mode Rejection
vs Input Frequency
Intermodulaton Distortion
Ripple Frequency
0
–20
0
–20
80
70
60
±0
40
30
20
10
0
f
= 333kHz
= 10m5
RIPPLE
f
f
f
= 333kHz
SAMPLE
SAMPLE
5
= 29ꢁ3kHz
IN1
IN2
= 32ꢁ4kHz
–40
–40
–60
–60
–80
–80
A
5DD
–100
–120
–140
–100
–120
5
SS
1k
10k
100k
1M
1k
10k
100k
1M
0
20 40 60
FREQUENCY (kHz)
120 140 160
80 100
INPUT FREQUENCY (Hz)
INPUT FREQUENCY (Hz)
1604 G06
1604 G07
1604G09
PIN FUNCTIONS
+
A
(Pin 1): Positive Analog Inpꢀtꢁ The ADC converts the
OGND (Pin 28): Digital Groꢀnd for Oꢀtpꢀt Driversꢁ
IN
+
–
difference voltage between A and A with a differ-
IN
IN
OV (Pin 29): Digital Power Sꢀpply for Oꢀtpꢀt Driversꢁ
DD
+
ential range of ±2ꢁ± ꢁ A has a ±2ꢁ±5 inpꢀt range when
A
IN
Bypass to OGND with 10μF tantalꢀm in parallel with 0ꢁ1μF
–
is groꢀndedꢁ
IN
ceramicꢁ
–
A
(Pin2):NegativeAnalogInpꢀtꢁCanbegroꢀnded, tied
IN
RD (Pin 30): Read Inpꢀtꢁ A logic low enables the oꢀtpꢀt
drivers when CS is lowꢁ
+
to a DC voltage or driven differentially with A
ꢁ
IN
V
(Pin3):2ꢁ±5ReferenceOꢀtpꢀtꢁBypasstoAGNDwith
REF
CONVST (Pin 31): Conversion Start Signalꢁ This active
low signal starts a conversion on its falling edge when
CS is lowꢁ
2ꢁ2μF tantalꢀm in parallel with 0ꢁ1μF ceramicꢁ
REFCOMP (Pin 4): 4ꢁ37± Reference Compensation Pinꢁ
Bypass to AGND with 47μF tantalꢀm in parallel with 0ꢁ1μF
ceramicꢁ
CS (Pin 32): The Chip Select Inpꢀtꢁ Mꢀst be low for the
ADC to recognize CONVST and RD inpꢀtsꢁ
AGND(Pins5to8):AnalogGroꢀndsꢁTietoanaloggroꢀnd
planeꢁ
SHDN (Pin 33): Power Shꢀtdownꢁ Drive this pin low with
CS low for nap modeꢁ Drive this pin low with CS high for
sleep modeꢁ
DV (Pin 9): ±5 Digital Power Sꢀpplyꢁ Bypass to DGND
DD
with 10μF tantalꢀm in parallel with 0ꢁ1μF ceramicꢁ
V
(Pin 34): –±5 Negative Sꢀpplyꢁ Bypass to AGND with
SS
DGND (Pin 10): Digital Groꢀnd for Internal Logicꢁ Tie to
analog groꢀnd planeꢁ
10μF tantalꢀm in parallel with 0ꢁ1μF ceramicꢁ
AV (Pin 35): ±5 Analog Power Sꢀpplyꢁ Bypass to AGND
DD
D15 to D0 (Pins 11 to 26): Three-State Data Oꢀtpꢀtsꢁ D1±
is the Most Significant Bitꢁ
with 10μF tantalꢀm in parallel with 0ꢁ1μF ceramicꢁ
AV (Pin 36): ±5 Analog Power Sꢀpplyꢁ Bypass to AGND
DD
BUSY (Pin 27): The BUSY oꢀtpꢀt shows the converter
statꢀsꢁ It is low when a conversion is in progressꢁ Data is
valid on the rising edge of BUSYꢁ
with 10μF tantalꢀm in parallel with 0ꢁ1μF ceramic and
connect this pin to Pin 3± with a 10Ω resistorꢁ
1604fa
6
LTC1604
FUNCTIONAL BLOCK DIAGRAM
2ꢁ2μF
10μF
±5 10μF
±5 10μF
10Ω
+
+
+
3
10
36
3±
9
5
A5
A5
DD
D5
DD
DGND
REF
DD
SHDN
CS
33
32
31
30
27
CONTROL
LOGIC
μP
CONVST
RD
CONTROL
LINES
REFCOMP
7ꢁ±k
AND
4
2ꢁ±5
REF
1ꢁ7±X
TIMING
+
4ꢁ37±5
BUSY
47μF
O5
DD
29
28
±5 OR
+
35
10μF
+
OGND
1
2
A
IN
+
DIFFERENTIAL
ANALOG INPUT
±2ꢁ±5
16-BIT
SAMPLING
ADC
OUTPUT
BUFFERS
B1± TO B0
16-BIT
PARALLEL
BUS
–
A
IN
D1± TO D0
–
11 TO 26
AGND AGND AGND AGND
5
SS
1604 TA01
±
6
7
8
34
10μF
+
–±5
TEST CIRCUIT
Load Circuits for Access Timing
Load Circuits for Output Float Delay
±5
±5
1k
1k
DN
DN
DN
DN
1k
1k
C
C
L
C
C
L
L
L
(A) Hi-Z TO 5 AND 5 TO 5
OH OL
(B) Hi-Z TO 5 AND 5 TO 5
OL OH
(A) 5 TO Hi-Z
OH
(B) 5 TO Hi-Z
OL
OH
OL
1604 TC01
1604 TC02
1604fa
7
LTC1604
APPLICATIONS INFORMATION
CONVERSION DETAILS
sꢀmming jꢀnctionsꢁ This inpꢀt charge is sꢀccessively
compared with the binary-weighted charges sꢀpplied by
the differential capacitive DACꢁ Bit decisions are made by
the high speed comparatorꢁ At the end of a conversion, the
The LTC1604 ꢀses a sꢀccessive approximation algorithm
and internal sample-and-hold circꢀit to convert an analog
signaltoa16-bitparalleloꢀtpꢀtꢁTheADCiscompletewith
a sample-and-hold, a precision reference and an internal
clockꢁ The control logic provides easy interface to micro-
processorsandDSPsꢁ(PleaserefertotheDigitalInterface
section for the data formatꢁ)
+
–
differential DAC oꢀtpꢀt balances the A and A inpꢀt
IN
IN
chargesꢁ The SAR contents (a 16-bit data word) which
+
–
represent the difference of A and A are loaded into
IN
IN
the 16-bit oꢀtpꢀt latchesꢁ
Conversion start is controlled by the CS and CONVST
inpꢀtsꢁ At the start of the conversion the sꢀccessive
approximation register (SAR) resetsꢁ Once a conversion
cycle has begꢀn it cannot be restartedꢁ
DIGITAL INTERFACE
The A/D converter is designed to interface with micropro-
cessors as a memory mapped deviceꢁ The CS and RD
control inpꢀts are common to all peripheral memory
interfacingꢁ A separate CONVST is ꢀsed to initiate a con-
versionꢁ
Dꢀring the conversion, the internal differential 16-bit
capacitive DAC oꢀtpꢀt is seqꢀenced by the SAR from the
Most Significant Bit (MSB) to the Least Significant Bit
+
–
Internal Clock
(LSB)ꢁ Referring to Figꢀre 1, the A and A inpꢀts are
IN
IN
acqꢀired dꢀring the acqꢀire phase and the comparator
offset is nꢀlled by the zeroing switchesꢁ In this acqꢀire
phase,adꢀrationof480nswillprovideenoꢀghtimeforthe
sample-and-hold capacitors to acqꢀire the analog signalꢁ
Dꢀringtheconvertphasethecomparatorzeroingswitches
open, pꢀtting the comparator into compare modeꢁ The
The A/D converter has an internal clock that rꢀns the A/D
conversionꢁTheinternalclockisfactorytrimmedtoachieve
a typical conversion time of 2ꢁ4±μs and a maximꢀm
conversion time of 2ꢁ8μs over the fꢀll temperatꢀre rangeꢁ
No external adjꢀstments are reqꢀiredꢁ The gꢀaranteed
maximꢀmacqꢀisitiontimeis480nsꢁInaddition,athroꢀgh-
pꢀt time (acqꢀisition + conversion) of 3μs and a minimꢀm
sampling rate of 333ksps are gꢀaranteedꢁ
inpꢀt switches connect the C
capacitors to groꢀnd,
SMPL
transferring the differential analog inpꢀt charge onto the
3V Input/Output Compatible
C
SMPL
SMPL
SAMPLE
SAMPLE
+
–
A
A
The LTC1604 operates on ±±5 sꢀpplies, which makes the
device easy to interface to ±5 digital systemsꢁ This device
can also talk to 35 digital systems: the digital inpꢀt pins
(SHDN, CS, CONVST and RD) of the LTC1604 recognize
35 or ±5 inpꢀtsꢁ The LTC1604 has a dedicated oꢀtpꢀt
IN
IN
HOLD
ZEROING SWITCHES
HOLD
C
HOLD
HOLD
sꢀpply pin (O5 ) that controls the oꢀtpꢀt swings of the
DD
+C
digital oꢀtpꢀt pins (D0 to D1±, BUSY) and allows the part
to talk to either 35 or ±5 digital systemsꢁ The oꢀtpꢀt is
two’s complement binaryꢁ
DAC
DAC
+
–C
COMP
–
+5
DAC
Power Shutdown
–5
The LTC1604 provides two power shꢀtdown modes, Nap
and Sleep, to save power dꢀring inactive periodsꢁ The
Nap mode redꢀces the power by 9±% and leaves only the
digital logic and reference powered ꢀpꢁ The wake-ꢀp
time from Nap to active is 200nsꢁ In Sleep mode all bias
DAC
16
D1±
D0
t
t
t
OUTPUT
LATCHES
SAR
1604 F01
Figure 1. Simplified Block Diagram
1604fa
8
LTC1604
APPLICATIONS INFORMATION
cꢀrrents are shꢀt down and only leakage cꢀrrent remains
(aboꢀt 1μA)ꢁ Wake-ꢀp time from Sleep mode is mꢀch
slower since the reference circꢀit mꢀst power ꢀp and
settleꢁSleepmodewake-ꢀptimeisdependentonthevalꢀe
of the capacitor connected to the REFCOMP (Pin 4)ꢁ The
wake-ꢀp time is 160ms with the recommended 47μF
capacitorꢁ
SHDN
t
3
CS
1604 F02a
Figure 2a. Nap Mode to Sleep Mode Timing
Shꢀtdown is controlled by Pin 33 (SHDN)ꢁ The ADC is in
shꢀtdown when SHDN is lowꢁ The shꢀtdown mode is
selected with Pin 32 (CS)ꢁ When SHDN is low, CS low
selects nap and CS high selects sleepꢁ
SHDN
t
4
CONVST
1604 F02b
Figure 2b. SHDN to CONVST Wake-Up Timing
Timing and Control
Conversion start and data read operations are controlled
by three digital inpꢀts: CONVST, CS and RDꢁ A falling edge
applied to the CONVST pin will start a conversion after the
ADC has been selected (iꢁeꢁ, CS is low)ꢁ Once initiated,
it cannot be restarted ꢀntil the conversion is completeꢁ
Converter statꢀs is indicated by the BUSY oꢀtpꢀtꢁ BUSY
is low dꢀring a conversionꢁ
CS
t
2
CONVST
RD
t
1
We recommend ꢀsing a narrow logic low or narrow logic
high CONVST pꢀlse to start a conversion as shown in
Figꢀres ± and 6ꢁ A narrow low or high CONVST pꢀlse
prevents the rising edge of the CONVST pꢀlse from ꢀpset-
ting the critical bit decisions dꢀring the conversion timeꢁ
Figꢀre 4 shows the change of the differential nonlinearity
error versꢀs the low time of the CONVST pꢀlseꢁ As shown,
if CONVST retꢀrns high early in the conversion (eꢁgꢁ,
CONVST low time <±00ns), accꢀracy is ꢀnaffectedꢁ
Similarly, if CONVST retꢀrns high after the conversion is
1604 F03
Figure 3. CS top CONVST Setup Timing
4
3
2
1
0
t
t
ACQ
CON5
over(eꢁgꢁ, CONVST low time >t
), accꢀracy is ꢀnaf-
CON5
fectedꢁ For best resꢀlts, keep t less than ±00ns or greater
±
than t
ꢁ
CON5
Figꢀres ± throꢀgh 9 show several different modes of op-
erationꢁ In modes 1a and 1b (Figꢀres ± and 6), CS and RD
are both tied lowꢁ The falling edge of CONVST starts the
conversionꢁ The data oꢀtpꢀts are always enabled and data
can be latched with the BUSY rising edgeꢁ Mode 1a shows
operationwithanarrowlogiclowCONVSTpꢀlseꢁMode1b
shows a narrow logic high CONVST pꢀlseꢁ
1200
1600
0
400
800
2000
2400 2800
CONVST LOW TIME, t (ns)
±
1604 F04
Figure 4. Change in DNL vs CONVST Low Time. Be Sure the
CONVST Pulse Returns High Early in the Conversion or After
the End of Conversion
In mode 2 (Figꢀre 7) CS is tied lowꢁ The falling edge of
CONVST signal starts the conversionꢁ Data oꢀtpꢀts are
1604fa
9
LTC1604
APPLICATIONS INFORMATION
t
CON5
CS = RD = 0
t
±
CONVST
t
t
8
6
BUSY
t
7
DATA (N – 1)
D1± TO D0
DATA N
D1± TO D0
DATA (N + 1)
D1± TO D0
DATA
1604 F0±
Figure 5. Mode 1a. CONVST Starts a Conversion. Data Outputs Always Enabled
(CONVST =
)
t
CS = RD = 0
t
8
CON5
t
t
±
13
CONVST
t
t
6
6
BUSY
t
7
DATA (N – 1)
D1± TO D0
DATA N
D1± TO D0
DATA (N + 1)
D1± TO D0
DATA
1604 F06
Figure 6. Mode 1b. CONVST Starts a Conversion. Data Outputs Always Enabled
(CONVST =
)
t
13
t
t
t
8
CS = 0
CON5
±
CONVST
BUSY
RD
t
6
t
t
11
9
t
12
t
10
DATA N
D1± TO D0
DATA
1604 F07
Figure 7. Mode 2. CONVST Starts a Conversion. Data is Read by RD
1604fa
10
LTC1604
APPLICATIONS INFORMATION
t
t
8
CS = 0
CON5
RD = CONVST
t
t
11
6
BUSY
t
t
7
10
DATA (N – 1)
D± TO D0
DATA N
D1± TO D0
DATA N
D1± TO D0
DATA (N + 1)
D1± TO D0
DATA
1604 F08
Figure 8. Mode 2. Slow Memory Mode Timing
t
t
8
CONV
CS = 0
RD = CONVST
t
t
11
6
BUSY
t
10
DATA (N – 1)
D15 TO D0
DATA N
D15 TO D0
DATA
1604 F09
Figure 9. ROM Mode Timing
in three-state ꢀntil read by the MPU with the RD signalꢁ
DIFFERENTIAL ANALOG INPUTS
Driving the Analog Inputs
Mode 2 can be ꢀsed for operation with a shared data bꢀsꢁ
In slow memory and ROM modes (Figꢀres 8 and 9) CS
is tied low and CONVST and RD are tied togetherꢁ The
MPU starts the conversion and reads the oꢀtpꢀt with the
combined CONVST-RD signalꢁ Conversions are started
by the MPU or DSP (no external sample clock is needed)ꢁ
The differential analog inpꢀts of the LTC1604 are easy
to driveꢁ The inpꢀts may be driven differentially or as a
–
single-ended inpꢀt (iꢁeꢁ, the A inpꢀt is groꢀnded)ꢁ The
IN
+
–
A
and A inpꢀts are sampled at the same instantꢁ
IN
IN
Any ꢀnwanted signal that is common mode to both in-
pꢀts will be redꢀced by the common mode rejection of
the sample-and-hold circꢀitꢁ The inpꢀts draw only one
small cꢀrrent spike while charging the sample-and-hold
capacitors at the end of conversionꢁ Dꢀring conversion
the analog inpꢀts draw only a small leakage cꢀrrentꢁ If the
soꢀrce impedance of the driving circꢀit is low, then the
LTC1604 inpꢀts can be driven directlyꢁ As soꢀrce imped-
anceincreasessowillacqꢀisitiontime(seeFigꢀre10)ꢁFor
minimꢀm acqꢀisition time with high soꢀrce impedance, a
bꢀffer amplifier shoꢀld be ꢀsedꢁ The only reqꢀirement is
that the amplifier driving the analog inpꢀt(s) mꢀst settle
after the small cꢀrrent spike before the next conversion
In slow memory mode the processor applies a logic low
to RD (= CONVST), starting the conversionꢁ BUSY goes
low, forcing the processor into a wait stateꢁ The previoꢀs
conversion resꢀlt appears on the data oꢀtpꢀtsꢁ When the
conversion is complete, the new conversion resꢀlts ap-
pear on the data oꢀtpꢀts; BUSY goes high, releasing the
processor and the processor takes RD (=CONVST) back
high and reads the new conversion dataꢁ
In ROM mode, the processor takes RD (=CONVST) low,
startingaconversionandreadingtheprevioꢀsconversion
resꢀltꢁ After the conversion is complete, the processor
can read the new resꢀlt and initiate another conversionꢁ
1604fa
11
LTC1604
APPLICATIONS INFORMATION
LT®1007: Low Noise Precision Amplifierꢁ 2ꢁ7mA sꢀpply
cꢀrrent, ±±5 to ±1±5 sꢀpplies, gain bandwidth prodꢀct
8MHz, DC applicationsꢁ
10
1
0ꢁ1
LT1097: Low Cost, Low Power Precision Amplifierꢁ 300μA
sꢀpply cꢀrrent, ±±5 to ±1±5 sꢀpplies, gain bandwidth
prodꢀct 0ꢁ7MHz, DC applicationsꢁ
LT1227:140MHz5ideoCꢀrrentFeedbackAmplifierꢁ10mA
sꢀpply cꢀrrent, ±±5 to ±1±5 sꢀpplies, low noise and low
distortionꢁ
0ꢁ01
1
10
100
1k
10k
LT1360:37MHz5oltageFeedbackAmplifierꢁ3ꢁ8mAsꢀpply
cꢀrrent, ±±5 to ±1±5 sꢀpplies, good AC/DC specsꢁ
SOURCE RESISTANCE (Ω)
1604 F10
LT1363: ±0MHz 5oltage Feedback Amplifierꢁ 6ꢁ3mA sꢀp-
ply cꢀrrent, good AC/DC specsꢁ
Figure 10. tACQ vs Source Resistance
LT1364/LT136±: Dꢀal and Qꢀad ±0MHz 5oltage Feedback
Amplifiersꢁ 6ꢁ3mA sꢀpply cꢀrrent per amplifier, good AC/
DC specsꢁ
starts (settling time mꢀst be 200ns for fꢀll throꢀghpꢀt
rate)ꢁ
Choosing an Input Amplifier
Input Filtering
Choosing an inpꢀt amplifier is easy if a few reqꢀirements
are taken into considerationꢁ First, to limit the magnitꢀde
of the voltage spike seen by the amplifier from charging
the sampling capacitor, choose an amplifier that has a low
oꢀtpꢀtimpedance(<100Ω)attheclosed-loopband-width
freqꢀencyꢁ For example, if an amplifier is ꢀsed in a gain
of +1 and has a ꢀnity-gain bandwidth of ±0MHz, then the
oꢀtpꢀt impedance at ±0MHz shoꢀld be less than 100Ωꢁ
Thesecondreqꢀirementisthattheclosed-loopbandwidth
mꢀst be greater than 1±MHz to ensꢀre adeqꢀate small-
signal settling for fꢀll throꢀghpꢀt rateꢁ If slower op amps
areꢀsed, moresettlingtimecanbeprovidedbyincreasing
the time between conversionsꢁ
The noise and the distortion of the inpꢀt amplifier and
other circꢀitry mꢀst be considered since they will add to
the LTC1604 noise and distortionꢁ The small-signal band-
width of the sample-and-hold circꢀit is 1±MHzꢁ Any noise
or distortion prodꢀcts that are present at the analog inpꢀts
will be sꢀmmed over this entire bandwidthꢁ Noisy inpꢀt
circꢀitry shoꢀld be filtered prior to the analog inpꢀts to
minimize noiseꢁ A simple 1-pole RC filter is sꢀfficient for
manyapplicationsꢁForexample,Figꢀre11showsa3000pF
+
capacitorfromA togroꢀndanda100Ωsoꢀrceresistorto
IN
limit the inpꢀt bandwidth to ±30kHzꢁ The 3000pF capacitor
alsoactsasachargereservoirfortheinpꢀtsample-and-hold
and isolates the ADC inpꢀt from sampling glitch sensitive
circꢀitryꢁ High qꢀality capacitors and resistors shoꢀld be
ꢀsed since these components can add distortionꢁ NPO and
silvermicatypedielectriccapacitorshaveexcellentlinearityꢁ
Carbon sꢀrface moꢀnt resistors can also generate distor-
tion from self heating and from damage that may occꢀr
dꢀring solderingꢁ Metal film sꢀrface moꢀnt resistors are
mꢀch less sꢀsceptible to both problemsꢁ
The best choice for an op amp to drive the LTC1604 will
depend on the applicationꢁ Generally applications fall into
two categories: AC applications where dynamic specifica-
tionsaremostcriticalandtimedomainapplicationswhere
DCaccꢀracyandsettlingtimearemostcriticalꢁThefollow-
ing list is a sꢀmmary of the op amps that are sꢀitable for
drivingtheLTC1604ꢁMoredetailedinformationisavailable
in the Linear Technology databooks, the Linear5iew™
CD-ROM and on oꢀr web site at: wwwꢁlinear-techꢁ comꢁ
Linear5iew is a trademark of Linear Technology Corporationꢁ
1604fa
12
LTC1604
APPLICATIONS INFORMATION
100Ω
1
2
3
4
±
R1
7ꢁ±k
+
ANALOG INPUT
A
A
5
IN
5
3
4
REF
BANDGAP
REFERENCE
2ꢁ±005
3000pF
–
IN
LTC1604
REFCOMP
REFERENCE
AMP
REF
4ꢁ37±5
REFCOMP
AGND
R2
12k
47μF
47μF
R3
16k
AGND
±
1604 F11
LTC1604
1604 F12a
Figure 11. RC Input Filter
Figure 12a. LTC1604 Reference Circuit
Input Range
±5
1
2
3
+
–
The ±2ꢁ±5 inpꢀt range of the LTC1604 is optimized for
low noise and low distortionꢁ Most op amps also perform
well over this same range, allowing direct coꢀpling to
the analog inpꢀts and eliminating the need for special
translation circꢀitryꢁ
A
A
5
IN
IN
ANALOG
INPUT
5
IN
LT1019A-2ꢁ±
5
OUT
REF
LTC1604
4
REFCOMP
Some applications may reqꢀire other inpꢀt rangesꢁ The
LTC1604 differential inpꢀts and reference circꢀitry can
accommodate other inpꢀt ranges often with little or no
additional circꢀitryꢁ The following sections describe the
reference and inpꢀt circꢀitry and how they affect the inpꢀt
rangeꢁ
+
10μF
0ꢁ1μF
±
AGND
1604 F12b
Figure 12b. Using the LT1019-2.5 as an External Reference
The 5
pin can be driven with a DAC or other means
REF
Internal Reference
shown in Figꢀre 13ꢁ This is ꢀsefꢀl in applications where
the peak inpꢀt signal amplitꢀde may varyꢁ The inpꢀt span
of the ADC can then be adjꢀsted to match the peak inpꢀt
signal, maximizing the signal-to-noise ratioꢁ The filtering
of the internal LTC1604 reference amplifier will limit the
bandwidth and settling time of this circꢀitꢁ A settling time
of20msshoꢀldbeallowedforafterareferenceadjꢀstmentꢁ
The LTC1604 has an on-chip, temperatꢀre compensated,
cꢀrvatꢀre corrected, bandgap reference that is factory
trimmedto2ꢁ±005ꢁItisconnectedinternallytoareference
amplifier and is available at 5 (Pin 3) (see Figꢀre 12a)ꢁ
REF
A 7ꢁ±k resistor is in series with the oꢀtpꢀt so that it can be
easilyoverdrivenbyanexternalreferenceorothercircꢀitry
(see Figꢀre 12b)ꢁ The reference amplifier gains the volt-
age at the 5 pin by 1ꢁ7± to create the reqꢀired internal
Differential Inputs
REF
reference voltageꢁ This provides bꢀffering between the
The LTC1604 has a ꢀniqꢀe differential sample-and-hold
circꢀit that allows rail-to-rail inpꢀtsꢁ The ADC will always
convert the difference of A – A independent of the
common mode voltage (see Figꢀre 1±a)ꢁ The common
mode rejection holds ꢀp to extremely high freqꢀencies
(see Figꢀre 14a)ꢁ The only reqꢀirement is that both inpꢀts
5
REF
pin and the high speed capacitive DACꢁ The refer-
ence amplifier compensation pin (REFCOMP, Pin 4) mꢀst
be bypassed with a capacitor to groꢀndꢁ The reference
amplifier is stable with capacitors of 22μF or greaterꢁ
For the best noise performance a 47μF ceramic or 47μF
tantalꢀminparallelwitha0ꢁ1μFceramicisrecommendedꢁ
+
–
IN
IN
1604fa
13
LTC1604
APPLICATIONS INFORMATION
1
2
1
+
+
–
ANALOG INPUT
A
A
A
IN
IN
IN
ANALOG INPUT
25 TO 2ꢁ75
DIFFERENTIAL
2
3
4
±
–
05 TO
±5
A
5
+
–
IN
±2ꢁ±5
3
5
REF
LTC1604
25 TO 2ꢁ75
LTC1604
LTC14±0
REF
4
REFCOMP
AGND
REFCOMP
AGND
10μF
47μF
±
1604 F14b
1604 F13
Figure 13. Driving VREF with a DAC
Figure 14b. Selectable 0V to 5V or 2.5V Input Range
80
70
60
±0
40
30
20
10
0
Full-Scale and Offset Adjustment
Figꢀre 1±a shows the ideal inpꢀt/oꢀtpꢀt characteristics
for the LTC1604ꢁ The code transitions occꢀr midway
between sꢀccessive integer LSB valꢀes (iꢁeꢁ, –FS +
0ꢁ±LSB, –FS + 1ꢁ±LSB, –FS + 2ꢁ±LSB,ꢁꢁꢁ FS – 1ꢁ±LSB,
FS – 0ꢁ±LSB)ꢁ The oꢀtpꢀt is two’s complement binary with
1LSB = FS – (–FS)/6±±36 = ±5/6±±36 = 76ꢁ3μ5ꢁ
In applications where absolꢀte accꢀracy is important,
offset and fꢀll-scale errors can be adjꢀsted to zeroꢁ Offset
error mꢀst be adjꢀsted before fꢀll-scale errorꢁ Figꢀre 1±b
shows the extra components reqꢀired for fꢀll-scale er-
1k
10k
100k
1M
INPUT FREQUENCY (Hz)
1604 G14a
ror adjꢀstmentꢁ Zero offset is achieved by adjꢀsting the
–
Figure 14a. CMRR vs Input Frequency
offset applied to the A inpꢀtꢁ For zero offset error apply
IN
can not exceed the A5 or 5 power sꢀpply voltagesꢁ
DD
SS
011ꢁꢁꢁ111
011ꢁꢁꢁ110
Integral nonlinearity errors (INL) and differential nonlin-
earity errors (DNL) are independent of the common
mode voltage, however, the bipolar zero error (BZE) will
varyꢁ The change in BZE is typically less than 0ꢁ1% of the
common mode voltageꢁ Dynamic performance is also
affected by the common mode voltageꢁ THD will degrade
astheinpꢀtsapproacheitherpowersꢀpplyrail,from96dB
with a common mode of 05 to 86dB with a common mode
of 2ꢁ±5 or –2ꢁ± ꢁ
000ꢁꢁꢁ001
000ꢁꢁꢁ000
111ꢁꢁꢁ111
111ꢁꢁꢁ110
100ꢁꢁꢁ001
100ꢁꢁꢁ000
–(FS – 1LSB)
INPUT 5OLTAGE (A – A
FS – 1LSB
Differential inpꢀts allow greater flexibility for accepting
different inpꢀt rangesꢁ Figꢀre 14b shows a circꢀit that
converts a 05 to ±5 analog inpꢀt signal with only an
additional bꢀffer that is not in the signal pathꢁ
+
–
)
IN
IN
1604 F1±a
Figure 15a. LTC1604 Transfer Characteristics
1604fa
14
LTC1604
APPLICATIONS INFORMATION
analog groꢀnd planeꢁ No other digital groꢀnds shoꢀld be
connected to this analog groꢀnd planeꢁ Low impedance
analog and digital power sꢀpply common retꢀrns are
essential to low noise operation of the ADC and the foil
width for these tracks shoꢀld be as wide as possibleꢁ In
applications where the ADC data oꢀtpꢀts and control
signals are connected to a continꢀoꢀsly active micropro-
cessor bꢀs, it is possible to get errors in the conversion
resꢀltsꢁ These errors are dꢀe to feedthroꢀgh from the
microprocessor to the sꢀccessive approximation com-
paratorꢁ The problem can be eliminated by forcing the
microprocessor into a WAIT state dꢀring conversion or by
ꢀsing three-state bꢀffers to isolate the ADC data bꢀsꢁ The
traces connecting the pins and bypass capacitors mꢀst
be kept short and shoꢀld be made as wide as possibleꢁ
–±5
ANALOG
INPUT
1
+
A
IN
R3
24k
2
–
R8
A
IN
±0k
R4
100Ω
LTC1604
3
R± R7
47k ±0k
5
REF
R6
24k
4
±
REFCOMP
AGND
+
0ꢁ1μF
47μF
1604 F1±b
Figure 15b. Offset and Full-Scale Adjust Circuit
+
–38μ5 (iꢁeꢁ, –0ꢁ±LSB) at A and adjꢀst the offset at the
IN
–
A
IN
inpꢀt ꢀntil the oꢀtpꢀt code flickers between 0000
0000 0000 0000 and 1111 1111 1111 1111ꢁ For fꢀll-scale
The LTC1604 has differential inpꢀts to minimize noise
adjꢀstment,aninpꢀtvoltageof2ꢁ4998865(FS/2–1ꢁ±LSBs)
+
–
coꢀplingꢁ Common mode noise on the A and A leads
IN
IN
+
is applied to A and R2 is adjꢀsted ꢀntil the oꢀtpꢀt code
–
IN
will be rejected by the inpꢀt CMRRꢁ The A inpꢀt can be
IN
flickers between 0111 1111 1111 1110 and 0111 1111
+
ꢀsed as a groꢀnd sense for the A inpꢀt; the LTC1604
IN
1111 1111ꢁ
+
will hold and convert the difference voltage between A
IN
–
+
–
and A ꢁ The leads to A (Pin 1) and A (Pin 2) shoꢀld
IN
IN
IN
BOARD LAYOUT AND GROUNDING
be kept as short as possibleꢁ In applications where this is
+
–
not possible, the A and A traces shoꢀld be rꢀn side
IN
IN
Wire wrap boards are not recommended for high resolꢀ-
tion or high speed A/D convertersꢁ To obtain the best
performance from the LTC1604, a printed circꢀit board
with groꢀnd plane is reqꢀiredꢁ Layoꢀt shoꢀld ensꢀre that
digital and analog signal lines are separated as mꢀch as
possibleꢁ Particꢀlar care shoꢀld be taken not to rꢀn any
digitaltrackalongsideananalogsignaltrackorꢀnderneath
the ADCꢁ The analog inpꢀt shoꢀld be screened by AGNDꢁ
by side to eqꢀalize coꢀplingꢁ
SUPPLY BYPASSING
High qꢀality, low series resistance ceramic, 10μF or 47μF
bypasscapacitorsshoꢀldbeꢀsedatthe5 andREFCOMP
DD
pins as shown in Figꢀre 16 and in the Typical Application
on the first page of this data sheetꢁ Sꢀrface moꢀnt ceramic
capacitors sꢀch as Mꢀrata GRM23±Y±5106Z016 provide
excellent bypassing in a small board spaceꢁ Alternatively,
10μF tantalꢀm capacitors in parallel with 0ꢁ1μF ceramic
capacitorscanbeꢀsedꢁBypasscapacitorsmꢀstbelocated
as close to the pins as possibleꢁ The traces connecting the
pins and the bypass capacitors mꢀst be kept short and
shoꢀld be made as wide as possibleꢁ
An analog groꢀnd plane separate from the logic system
groꢀnd shoꢀld be established ꢀnder and aroꢀnd the ADCꢁ
Pin ± to Pin 8 (AGNDs), Pin 10 (ADC’s DGND) and all other
analog groꢀnds shoꢀld be connected to this single analog
groꢀnd pointꢁ The REFCOMP bypass capacitor and the
D5 bypass capacitor shoꢀld also be connected to this
DD
1604fa
15
LTC1604
APPLICATIONS INFORMATION
1
+
DIGITAL
SYSTEM
LTC1604
A5 A5
A
IN
–
A
IN
5
5
D5
DGND O5
10
OGND
28
REFCOMP AGND
REF
SS
DD
DD
DD
9
DD
29
ANALOG
INPUT
CIRCUITRY
2
3
4
± TO 8 34
36
3±
+
–
2ꢁ2μF
10μF
47μF
10μF 10μF 10μF
10μF
1604 F16
Figure 16. Power Supply Grounding Practice
2±00
DC PERFORMANCE
The noise of an ADC can be evalꢀated in two ways: signal-
to-noise raio (SNR) in freqꢀency domain and histogram
in time domainꢁ The LTC1604 excels in bothꢁ Figꢀre 18a
demonstrates that the LTC1604 has an SNR of over 90dB
in freqꢀency domainꢁ The noise in the time domain
histogram is the transition noise associated with a high
resolꢀtion ADC which can be measꢀred with a fixed DC
signal applied to the inpꢀt of the ADCꢁ The resꢀlting oꢀtpꢀt
codes are collected over a large nꢀmber of conversionsꢁ
The shape of the distribꢀtion of codes will give an indica-
tion of the magnitꢀde of the transition noiseꢁ In Figꢀre 17
the distribꢀtion of oꢀtpꢀt codes is shown for a DC inpꢀt
that has been digitized 4096 timesꢁ The distribꢀtion is
Gaꢀssian and the RMS code transition noise is aboꢀt
0ꢁ66LSBꢁ This corresponds to a noise level of 90ꢁ9dB
relative to fꢀll scaleꢁ Adding to that the theoretical 98dB
of qꢀantization error for 16-bit ADC, the resꢀltant corre-
sponds to an SNR level of 90ꢁ1dB which correlates very
well to the freqꢀency domain measꢀrements in DYNAMIC
PERFORMANCE sectionꢁ
2000
1±00
1000
±00
0
–4
–±
–3 –2 –1
0
1
2
3
4
±
CODE
1604 F17
Figure 17. Histogram for 4096 Conversions
0
f
f
= 333kHz
SAMPLE
= 4ꢁ9±9kHz
IN
–20
–40
SINAD = 90ꢁ2dB
THD = –103ꢁ2dB
–60
–80
–100
–120
DYNAMIC PERFORMANCE
TheLTC1604hasexcellenthighspeedsamplingcapabilityꢁ
Fastfoꢀriertransform(FFT)testtechniqꢀesareꢀsedtotest
theADC’sfreqꢀencyresponse,distortionsandnoiseatthe
rated throꢀghpꢀtꢁ By applying a low distortion sine wave
and analyzing the digital oꢀtpꢀt ꢀsing an FFT algorithm,
the ADC’s spectral content can be examined for freqꢀen-
cies oꢀtside the fꢀndamentalꢁ Figꢀres 18a and 18b show
typical LTC1604 FFT plotsꢁ
–140
0
20 40 60 80 100 120 140 160
FREQUENCY (kHz)
1604 F18a
Figure 18a. This FFT of the LTC1604’s Conversion of a
Full-Scale 5kHz Sine Wave Shows Outstanding Response
with a Very Low Noise Floor When Sampling at 333ksps
1604fa
16
LTC1604
APPLICATIONS INFORMATION
Signal-to-Noise Ratio
0
f
f
= 333kHz
SAMPLE
IN
= 97ꢁ1±2kHz
–20
SINAD = 89dB
THD = –96dB
The signal-to-noise plꢀs distortion ratio [S/(N + D)] is the
ratiobetweentheRMSamplitꢀdeofthefꢀndamentalinpꢀt
freqꢀency to the RMS amplitꢀde of all other freqꢀency
components at the A/D oꢀtpꢀtꢁ The oꢀtpꢀt is band limited
tofreqꢀenciesfromaboveDCandbelowhalfthesampling
freqꢀencyꢁFigꢀre18ashowsatypicalspectralcontentwith
a 333kHz sampling rate and a ±kHz inpꢀtꢁ The dynamic
performance is excellent for inpꢀt freqꢀencies ꢀp to and
beyond the Nyqꢀist limit of 167kHzꢁ
–40
–60
–80
–100
–120
–140
0
20 40 60 80 100 120 140 160
FREQUENCY (kHz)
1604 F18b
Effective Number of Bits
Figure 18b. Even with Inputs at 100kHz, the LTC1604’s
Dynamic Linearity Remains Robust
The effective nꢀmber of bits (ENOBs) is a measꢀrement
of the resolꢀtion of an ADC and is directly related to the
S/(N + D) by the eqꢀation:
98
92
86
80
74
68
62
±6
±0
16
1±
14
13
12
11
10
9
N = [S/(N + D) – 1ꢁ76]/6ꢁ02
where N is the effective nꢀmber of bits of resolꢀtion and
S/(N + D) is expressed in dBꢁ At the maximꢀm sampling
rate of 333kHz the LTC1604 maintains above 14 bits ꢀp to
theNyqꢀistinpꢀtfreqꢀencyof167kHz(refertoFigꢀre19)ꢁ
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sꢀmofallharmonicsoftheinpꢀtsignaltothefꢀndamental
itselfꢁ The oꢀt-of-band harmonics alias into the freqꢀency
band between DC and half the sampling freqꢀencyꢁ THD
is expressed as:
8
1k
10k
100k
1M
FREQUENCY (Hz)
1604 F19
Figure 19. Effective Bits and Signal/(Noise + Distortion)
vs Input Frequency
522 + 532 + 542 +ꢁꢁꢁ5n2
THD=20Log
51
0
–10
–20
–30
–40
–±0
–60
–70
where 51 is the RMS amplitꢀde of the fꢀndamental fre-
qꢀency and 52 throꢀgh 5n are the amplitꢀdes of the
second throꢀgh nth harmonicsꢁ THD vs Inpꢀt Freqꢀency
is shown in Figꢀre 20ꢁ The LTC1604 has good distortion
performance ꢀp to the Nyqꢀist freqꢀency and beyondꢁ
–80
–90
THD
3RD
–100
–110
2ND
10k
INPUT FREQUENCY (Hz)
1k
100k
1M
1604 G04
Figure 20. Distortion vs Input Frequency
1604fa
17
LTC1604
APPLICATIONS INFORMATION
Intermodulation Distortion
etcꢁ For example, the 2nd order IMD terms inclꢀde
(fa–fb)ꢁIfthetwoinpꢀtsinewavesareeqꢀalinmagnitꢀde,
the valꢀe (in decibels) of the 2nd order IMD prodꢀcts can
be expressed by the following formꢀla:
If the ADC inpꢀt signal consists of more than one spectral
component, the ADC transfer fꢀnction nonlinearity can
prodꢀce intermodꢀlation distortion (IMD) in addition to
THDꢁ IMD is the change in one sinꢀsoidal inpꢀt caꢀsed
by the presence of another sinꢀsoidal inpꢀt at a different
freqꢀencyꢁ
Amplitꢀde at (fa ± fb)
IMD fa± fb =20Log
(
)
Amplitꢀde at fa
Peak Harmonic or Spurious Noise
If two pꢀre sine waves of freqꢀencies fa and fb are applied
totheADCinpꢀt,nonlinearitiesintheADCtransferfꢀnction
can create distortion prodꢀcts at the sꢀm and difference
freqꢀencies of mfa ±nfb, where m and n = 0, 1, 2, 3,
Thepeakharmonicorspꢀrioꢀsnoiseisthelargestspectral
component exclꢀding the inpꢀt signal and DCꢁ This valꢀe
is expressed in decibels relative to the RMS valꢀe of a
fꢀll-scale inpꢀt signalꢁ
0
Full-Power and Full-Linear Bandwidth
f
f
f
= 333kHz
SAMPLE
IN1
IN2
= 29ꢁ3kHz
–20
–40
= 32ꢁ4kHz
The fꢀll-power bandwidth is that inpꢀt freqꢀency at which
theamplitꢀdeofthereconstrꢀctedfꢀndamentalisredꢀced
by 3dB for a fꢀll-scale inpꢀt signalꢁ
–60
The fꢀll-linear bandwidth is the inpꢀt freqꢀency at which
the S/(N + D) has dropped to 84dB (13ꢁ66 effective bits)ꢁ
The LTC1604 has been designed to optimize inpꢀt band-
width, allowingtheADCtoꢀndersampleinpꢀtsignalswith
freqꢀencies above the converter’s Nyqꢀist Freqꢀencyꢁ The
noise floor stays very low at high freqꢀencies; S/(N + D)
becomes dominated by distortion at freqꢀencies far
beyond Nyqꢀistꢁ
–80
–100
–120
–140
0
20 40 60
FREQUENCY (kHz)
120 140 160
80 100
1604 G06
Figure 21. Intermodulation Distortion Plot
1604fa
18
LTC1604
PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted.
G Package
36-Lead Plastic SSOP (0.209)
(LTC DWG # 0±-08-1640)
0ꢁ499 – 0ꢁ±09*
(12ꢁ67 – 12ꢁ93)
36 3± 34 33 32 31 30 29 28 27 26 2± 24 23 22 21 20 19
0ꢁ301 – 0ꢁ311
(7ꢁ6± – 7ꢁ90)
±
7
8
1
2
3
4
6
9 10 11 12 13 14 1± 16 17 18
0ꢁ20± – 0ꢁ212**
(±ꢁ20 – ±ꢁ38)
0ꢁ068 – 0ꢁ078
(1ꢁ73 – 1ꢁ99)
0° – 8°
0ꢁ02±6
(0ꢁ6±)
BSC
0ꢁ00± – 0ꢁ009
(0ꢁ13 – 0ꢁ22)
0ꢁ022 – 0ꢁ037
(0ꢁ±± – 0ꢁ9±)
0ꢁ002 – 0ꢁ008
(0ꢁ0± – 0ꢁ21)
0ꢁ010 – 0ꢁ01±
(0ꢁ2± – 0ꢁ38)
*DIMENSIONS DO NOT INCLUDE MOLD FLASHꢁ MOLD FLASH
SHALL NOT EXCEED 0ꢁ006" (0ꢁ1±2mm) PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASHꢁ INTERLEAD
FLASH SHALL NOT EXCEED 0ꢁ010" (0ꢁ2±4mm) PER SIDE
G36 SSOP 1196
1604fa
Information fꢀrnished by Linear Technology Corporation is believed to be accꢀrate and reliableꢁ
However, no responsibility is assꢀmed for its ꢀseꢁ Linear Technology Corporation makes no representa-
tion that the interconnection of its circꢀits as described herein will not infringe on existing patent rightsꢁ
19
LTC1604
TYPICAL APPLICATION
Using the LTC1604 and Two LTC1391s as an 8-Channel Differential 16-Bit ADC System
±5
2ꢁ2μF
10μF
±5 10μF
±5 10μF
10Ω
36
+
+
+
+
+
LTC1391
3
3±
10
9
1μF
16
1±
14
13
12
11
10
9
1
2
3
4
±
6
7
8
+
+
D5
DD
5
REF
A5
A5
DD
DGND
DD
CH0
CH0
5
SHDN 33
CS 32
CH1
CH2
CH3
CH4
CH±
CH6
CH7
D
–
–±5
1μF
CONTROL
LOGIC
AND
TIMING
5
μP
CONTROL
LINES
CONVST 31
RD 30
7ꢁ±k
REFCOMP
D
OUT
4
2ꢁ±5
REF
1ꢁ7±X
+
4ꢁ37±5
D
IN
BUSY 27
47μF
CS
O5
29
±5 OR
35
10μF
DD
LTC1604
CLK
+
+
–
A
1
2
IN
+
–
OGND 28
CH7
CH0
GND
+
–
3000pF
3000pF
16-BIT
SAMPLING
ADC
OUTPUT
BUFFERS
B1± TO B0
16-BIT
PARALLEL
BUS
±5
D1± TO D0
A
IN
LTC1391
1μF
11 TO 26
1
2
3
4
±
6
7
8
16
1±
14
13
12
11
10
9
+
AGND AGND AGND AGND 5
SS
34
5
CH0
CH1
CH2
CH3
CH4
CH±
CH6
CH7
1604 TA03
±
6
7
8
D
–
–±5
10μF
+
5
+
–±5
D
OUT
D
D
IN
IN
μP
CONTROL
LINES
CS
CS
CLK
CLK
–
GND
CH7
RELATED PARTS
SAMPLING ADCs
PART NUMBER
LTC1410
DESCRIPTION
COMMENTS
12-Bit, 1ꢁ2±Msps, ±±5 ADC
71ꢁ±dB SINAD at Nyqꢀist, 1±0mW Dissipation
±±mW Power Dissipation, 72dB SINAD
1±mW, Serial/Parallel ±105
LTC141±
12-Bit, 1ꢁ2±Msps, Single ±5 ADC
14-Bit, 200ksps, Single ±5 ADC
Low Power 14-Bit, 800ksps ADC
16-Bit, 100ksps, Single ±5 ADC
LTC1418
LTC1419
Trꢀe 14-Bit Linearity, 81ꢁ±dB SINAD, 1±0mW Dissipation
±105 Inpꢀts, ±±mW, Byte or Parallel I/O
LTC160±
DACs
PART NUMBER
LTC1±9±
LTC1±96
LTC1±97
LTC16±0
DESCRIPTION
COMMENTS
16-Bit Serial Mꢀltiplying I
16-Bit Serial Mꢀltiplying I
DAC in SO-8
DAC
±1LSB Max INL/DNL, Low Glitch, DAC8043 16-Bit Upgrade
OUT
OUT
±1LSB Max INL/DNL, Low Glitch, AD7±43/DAC8143 16-Bit Upgrade
±1LSB Max INL/DNL, Low Glitch, 4 Qꢀadrant Resistors
Low Power, Low Gritch, 4-Qꢀadrant Mꢀltiplication
16-Bit Parallel, Mꢀltiplying DAC
16-Bit Serial 5 DAC
OUT
1604fa
1604a LT/TP 1098 REV A 2K • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvdꢁ, Milpitas, CA 9±03±-7417
20
●
●
© LINEAR TECHNOLOGY CORPORATION 1998
(408) 432-1900 FAX: (408) 434-0±07 wwwꢁlinea ꢁcom
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