LTC1288IS8#PBF [Linear]
LTC1288 - 3V Micropower Sampling 12-Bit A/D Converters in SO-8 Packages; Package: SO; Pins: 8; Temperature Range: -40°C to 85°C;型号: | LTC1288IS8#PBF |
厂家: | Linear |
描述: | LTC1288 - 3V Micropower Sampling 12-Bit A/D Converters in SO-8 Packages; Package: SO; Pins: 8; Temperature Range: -40°C to 85°C 光电二极管 转换器 |
文件: | 总24页 (文件大小:341K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC1285/LTC1288
3V Micropower Sampling
12-Bit A/D Converters in
SO-8 Packages
U
DESCRIPTION
FEATURES
TheLTC®1285/LTC1288are3Vmicropower, 12-bit, suc-
cessive approximation sampling A/D converters. They
typically draw only 160µA of supply current when con-
verting and automatically power down to a typical supply
currentof1nAwhenevertheyarenotperformingconver-
sions. They are packaged in 8-pin SO packages and
operate on 3V to 6V supplies. These 12-bit, switched-
capacitor, successive approximation ADCs include
sample-and-holds. The LTC1285 has a single differential
analog input. The LTC1288 offers a software selectable
2-channel MUX.
■
12-Bit Resolution
■
8-Pin SO Plastic Package
■
Low Cost
■
Low Supply Current: 160µA Typ
■
Auto Shutdown to 1nA Typ
■
Guaranteed ±3/4LSB Max DNL
■
Single Supply 3V to 6V Operation
■
Differential Inputs (LTC1285)
■
2-Channel MUX (LTC1288)
■
On-Chip Sample-and-Hold
■
100µs Conversion Time
■
Sampling Rates:
On-chip serial ports allow efficient data transfer to a wide
rangeofmicroprocessorsandmicrocontrollersoverthree
wires.This,coupledwithmicropowerconsumption,makes
remote location possible and facilitates transmitting data
through isolation barriers.
7.5ksps (LTC1285)
6.6ksps (LTC1288)
■
I/O Compatible withU SPI, Microwire, etc.
APPLICATIONS
These circuits can be used in ratiometric applications or
with an external reference. The high impedance analog
inputs and the ability to operate with reduced spans (to
1.5V full scale) allow direct connection to sensors and
transducersinmanyapplications, eliminatingtheneedfor
gain stages.
■
Pen Screen Digitizing
■
Battery-Operated Systems
■
Remote Data Acquisition
■
Isolated Data Acquisition
Battery Monitoring
■
■
Temperature Measurement
, LTC and LT are registered trademarks of Linear Technology Corporation.
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TYPICAL APPLICATIONS N
12µW, S0-8 Package, 12-Bit ADC
Supply Current vs Sample Rate
Samples at 200Hz and Runs Off a 3V Supply
1000
T
= 25°C
A
V
V
= 2.7V
CC
REF
CLK
1µF
3V
= 2.5V
f
= 120kHz
100
10
1
MPU
(e.g., 8051)
1
2
3
4
8
V
V
P1.4
P1.3
P1.2
REF
CC
7
6
5
+IN
CLK
ANALOG INPUT
0V TO 3V RANGE
LTC1285
–IN
D
OUT
SERIAL DATA LINK
GND
CS/SHDN
LTC1285/88 • TA01
0.1
1
10
100
SAMPLE FREQUENCY (kHz)
LTC1285/88 • TA02
1
LTC1285/LTC1288
W W
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ABSOLUTE MAXIMUM RATINGS
(Notes 1 and 2)
Supply Voltage (VCC) to GND................................... 12V
Voltage
Power Dissipation.............................................. 500mW
Operating Temperature Range .................... 0°C to 70°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec.)................ 300°C
Analog and Reference ................ –0.3V to VCC + 0.3V
Digital Inputs......................................... –0.3V to 12V
Digital Output ............................. –0.3V to VCC + 0.3V
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PACKAGE/ORDER INFORMATION
ORDER PART
TOP VIEW
ORDER PART
NUMBER
TOP VIEW
NUMBER
V
1
2
3
4
8
7
6
5
V
V
1
2
3
4
8
7
6
5
V
CC
REF
CC
REF
+IN
–IN
CLK
D
CLK
D
+IN
–IN
LTC1285CN8
LTC1285CS8
OUT
OUT
CS/SHDN
GND
CS/SHDN
GND
PART MARKING
1285C
S8 PACKAGE
N8 PACKAGE
8-LEAD PDIP
8-LEAD PLASTIC SO
TJMAX = 150°C, θJA = 130°C/W
T
JMAX = 150°C, θJA = 175°C/W
TOP VIEW
TOP VIEW
ORDER PART
NUMBER
ORDER PART
NUMBER
1
2
3
4
V
(V
)
CS/SHDN
CH0
1
2
3
4
8
7
6
5
V
(V )
CS/SHDN
CH0
8
7
6
5
CC REF
CC REF
CLK
D
CLK
D
LTC1288CN8
LTC1288CS8
CH1
CH1
OUT
OUT
D
GND
GND
D
IN
IN
PART MARKING
1288C
N8 PACKAGE
8-LEAD PDIP
S8 PACKAGE
8-LEAD PLASTIC SO
TJMAX = 150°C, θJA = 130°C/W
TJMAX = 150°C, θJA = 175°C/W
Consult factory for Industrial and Military grade parts.
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RECOM ENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Supply Voltage (Note 3)
LTC1285
LTC1288
2.7
2.7
6
6
V
V
CC
f
t
Clock Frequency
Total Cycle Time
V
= 2.7V
CC
(Note 4)
120
kHz
CLK
CYC
LTC1285, f
LTC1288, f
= 120kHz
= 120kHz
125.0
141.5
µs
µs
CLK
CLK
t
t
Hold Time, D After CLK↑
V = 2.7V
CC
450
ns
hDI
IN
Setup Time CS↓ Before First CLK↑ (See Operating Sequence)
LTC1285, V = 2.7V
LTC1288, V = 2.7V
2
2
µs
µs
suCS
CC
CC
t
t
t
t
t
Setup Time, D Stable Before CLK↑
V
V
V
V
= 2.7V
= 2.7V
= 2.7V
= 2.7V
600
3.5
3.5
2
ns
µs
µs
µs
suDI
IN
CC
CC
CC
CC
CLK High Time
WHCLK
WLCLK
WHCS
WLCS
CLK Low Time
CS High Time Between Data Transfer Cycles
CS Low Time During Data Transfer
LTC1285, f
LTC1288, f
= 120kHz
= 120kHz
123.0
139.5
µs
µs
CLK
CLK
2
LTC1285/LTC1288
U
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CONVERTER AND MULTIPLEXER CHARACTERISTICS (Note 5)
LTC1285
TYP
LTC1288
TYP
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
Bits
LSB
LSB
LSB
LSB
V
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Offset Error
●
●
●
●
●
●
12
12
(Note 6)
±3/4
±1/4
±3/4
±2
±2
±3/4
±3
±3/4
±1/4
±3/4
±2
±2
±3/4
±3
Gain Error
±8
±8
–0.05V to V + 0.05V
Analog Input Range
(Note 7 and 8)
CC
REF Input Range (LTC1285)
(Notes 7, 8, and 9)
2.7 ≤ V ≤ 6V
V
V
1.5V to V + 0.05V
CC
CC
Analog Input Leakage Current (Note 10)
●
±1
±1
µA
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DIGITAL AND DC ELECTRICAL CHARACTERISTICS (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
V
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output Voltage
V
V
V
V
= 3.6V
= 2.7V
●
●
●
●
2
IH
IL
CC
CC
IN
0.8
2.5
V
I
I
= V
µA
µA
IH
IL
CC
= 0V
–2.5
IN
V
V
CC
V
CC
= 2.7V, I = 10µA
●
●
2.4
2.1
2.64
2.30
V
V
OH
O
= 2.7V, I = 360µA
O
V
Low Level Output Voltage
Hi-Z Output Leakage
Output Source Current
Output Sink Current
V
= 2.7V, I = 400µA
●
●
0.4
V
µA
OL
CC
O
I
I
I
CS = High
±3
OZ
V
OUT
V
OUT
= 0V
–10
15
mA
mA
SOURCE
SINK
= V
CC
R
Reference Input Resistance
(LTC1285)
CS = V
CS = V
2700
54
MΩ
kΩ
REF
IH
IL
I
I
Reference Current (LTC1285)
CS = V
●
0.001
50
50
2.5
70
µA
µA
µA
REF
CC
t
t
≥ 640µs, f
= 134µs, f
≤ 25kHz
= 120kHz
CYC
CYC
CLK
CLK
●
●
Supply Current
CS = V
0.001 ±3.0
µA
CC
CC
LTC1285, t
LTC1285, t
≥ 640µs, f
= 134µs, f
≤ 25kHz
= 120kHz
150
160
µA
µA
CYC
CYC
CLK
CLK
●
●
320
390
LTC1288, t
LTC1288, t
≥ 720µs, f
= 150µs, f
≤ 25kHz
= 120kHz
200
210
µA
µA
CYC
CYC
CLK
CLK
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DYNAMIC ACCURACY
SYMBOL
S/(N +D)
THD
fSMPL = 7.5kHz (LTC1285), fSMPL = 6.6kHz (LTC1288) (Note 5)
PARAMETER
CONDITIONS
MIN
TYP
67
MAX
UNITS
dB
Signal-to-Noise Plus Distortion Ratio
Total Harmonic Distortion (Up to 5th Harmonic)
Spurious-Free Dynamic Range
Peak Harmonic or Spurious Noise
1kHz Input Signal
1kHz Input Signal
1kHz Input Signal
1kHz Input Signal
–80
88
dB
SFDR
dB
–88
dB
3
LTC1285/LTC1288
(Note 5)
AC CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
t
f
Analog Input Sample Time
Maximum Sampling Frequency
See Operating Sequence
1.5
CLK Cycles
SMPL
LTC1285
LTC1288
●
●
7.5
6.6
kHz
kHz
SMPL(MAX)
t
t
t
t
t
t
t
Conversion Time
See Operating Sequence
See Test Circuits
12
600
220
180
520
60
CLK Cycles
CONV
dDO
dis
en
Delay Time, CLK↓ to D
Data Valid
●
●
●
1500
660
ns
ns
ns
ns
ns
ns
OUT
Delay Time, CS↑ to D
Hi-Z
See Test Circuits
OUT
Delay Time, CLK↓ to D
Enable
See Test Circuits
500
OUT
Time Output Data Remains Valid After CLK↓
C
LOAD
= 100pF
hDO
f
D
D
Fall Time
See Test Circuits
See Test Circuits
●
●
180
180
OUT
OUT
Rise Time
80
r
C
IN
Input Capacitance
Analog Inputs, On Channel
Analog Inputs, Off Channel
Digital Input
20
5
5
pF
pF
pF
Note 7: Two on-chip diodes are tied to each reference and analog input
The
●
denotes specifications which apply over the full operating
which will conduct for reference or analog input voltages one diode drop
temperature range.
below GND or one diode drop above V . This spec allows 50mV forward
CC
Note 1: Absolute maximum ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 3: These devices are specified at 3V. For 5V specified devices, see
LTC1286 and LTC1298.
Note 4: Increased leakage currents at elevated temperatures cause the
sample-and-hold to droop, therefore it is recommended that f
at 70° and f
bias of either diode for 2.7V ≤ V ≤ 6V. This means that as long as the
CC
reference or analog input does not exceed the supply voltage by more than
50mV the output code will be correct. To achieve an absolute 0V to 2.7V
input voltage range will therefore require a minimum supply voltage of
2.650V over initial tolerance, temperature variations and loading. For 2.7V
< V ≤ 6V, reference and analog input range cannot exceed 6.05V. If
CC
≥ 75kHz
CLK
reference and analog input range are greater than 6.05V, the output code
≥ 1kHz at 25°C.
CLK
will not be guaranteed to be correct.
Note 5: V = 2.7V, V = 2.5V and CLK = 120kHz unless otherwise
specified.
CC
REF
Note 8: The supply voltage range for the LTC1285 and the LTC1288 is
from 2.7V to 6V.
Note 6: Linearity error is specified between the actual end points of the
A/D transfer curve.
Note 9: Recommended operating conditions
Note 10: Channel leakage current is measured after the channel selection.
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TYPICAL PERFORMANCE CHARACTERISTICS
Shutdown Supply Current vs Clock
Rate with CS High and CS Low
Supply Current vs Sample Rate
Supply Current vs Temperature
250
200
150
1000
100
10
9
8
LTC1288
SMPL
T
= 25°C
= 2.7V
T
V
V
= 25°C
= 2.7V
REF
A
CC
A
CC
f
= 6.6kHz
V
V
= 2.5V
= 2.5V
REF
CLK
7
6
5
f
= 120kHz
LTC1285
= 7.5kHz
LTC1288
f
SMPL
4
3
CS = 0
(AFTER CONVERSION)
100
50
0
LTC1285
2
1
V
V
= 2.7V
CC
REF
CLK
= 2.5V
0.002
0
CS = V
60
CC
f
= 120kHz
1
–55 –35 –15
5
25 45 65 85 105 125
0.1
1
10
1
20
80
100
120
40
SAMPLE RATE (kHz)
TEMPERATURE (°C)
FREQUENCY (kHz)
LTC1285/88 • TPC01
LTC1285/88 • TPC02
LTC1285/88 • TPC03
4
LTC1285/LTC1288
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TYPICAL PERFORMANCE CHARACTERISTICS
Reference Current vs
Sample Rate (LTC1285)
Change in Offset
vs Reference Voltage
3.0
Reference Current vs Temperature
53
52
51
50
49
48
47
46
45
44
43
50
45
40
35
30
25
20
15
10
5
V
V
f
= 2.7V
= 2.5V
= 120kHz
= 7.5kHz
T
= 25°C
= 2.7V
T
A
= 25°C
= 2.7V
CC
REF
CLK
A
CC
V
V
f
V
f
SMPL
CC
CLK
2.5
= 2.5V
= 120kHz
= 7.5kHz
REF
f
= 120kHz
f
SMPL
CLK
2.0
1.5
1.0
0.5
0
0
0
4
6
7
–55 –35 –15
5
25 45 65 85 105 125
0.5
1.0
1.5
2.0
2.5
3.0
1
2
3
5
8
TEMPERATURE (°C)
REFERENCE VOLTAGE (V)
SAMPLE RATE (kHz)
LTC1285/88 • TPC05
LTC1285/88 • TPC04
LTC1285/88 • TPC06
Change in Gain
vs Reference Voltage
Change in Linearity
vs Reference Voltage
Change in Offset vs Temperature
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
0.20
T
= 25°C
= 2.7V
= 120kHz
= 7.5kHz
T
= 25°C
= 2.7V
CC
V
V
f
= 2.7V
= 2.5V
= 120kHz
= f
A
CC
A
CC
REF
CLK
V
f
V
f
0.15
0.10
= 120kHz
= 7.5kHz
CLK
SMPL
CLK
f
f
SMPL
f
SMPL SMPL(MAX)
0.05
0
–0.05
–0.10
–0.15
–0.20
10
20
40
50
60
70
1.0 1.2 1.4 1.6
2.0
2.4 2.6 2.8
1.0 1.2 1.4 1.6
2.0
2.4 2.6 2.8
2.2
0
30
1.8
2.2
1.8
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
TEMPERATURE (°C)
LTC1285/88 • TPC07
LTC1285/88 • TPC08
LTC1285/88 • TPC09
Effective Bits and S/(N + D)
vs Input Frequency
Differential Nonlinearity vs Code
12
11
10
9
74
68
62
56
50
1
0.5
T
= 25°C
A
V
V
f
= 2.7V
CC
= 2.5V
REF
CLK
= 120kHz
8
7
6
0
5
4
–0.5
3
T
= 25°C
A
2
V
= 2.7V
CC
1
f
= 120kHz
CLK
0
–1
1
10
INPUT FREQUENCY (kHz)
100
0
512 1024 1536 2048 2560 3072 3584 4096
CODE
LTC1285/88 • TPC12
LTC1285/88 • TPC11
5
LTC1285/LTC1288
W
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TYPICAL PERFORMANCE CHARACTERISTICS
Spurious-Free Dynamic Range
vs Input Frequency
S/(N + D) vs Input Level
Attenuation vs Input Frequency
100
90
80
70
60
50
40
30
20
10
0
0
10
20
30
40
50
60
70
80
90
100
80
70
60
50
40
30
20
10
0
T
V
V
= 25°C
A
= 2.7V
CC
REF
= 1kHz
= 2.5V
f
f
IN
SMPL SMPL(MAX)
= f
T
V
V
= 25°C
A
T
V
V
= 25°C
A
= 2.7V
CC
REF
= 2.7V
CC
REF
= 2.5V
= f
= 2.5V
= f
f
SMPL SMPL(MAX)
f
SMPL SMPL(MAX)
1
10
INPUT FREQUENCY (kHz)
100
–25 –20
–15 –10 –5
INPUT LEVEL (dB)
–45 –40 –35 –30
0
1k
10k
100k
1M
10M
INPUT FREQUENCY (Hz)
LTC1285/88 • G13
LTC1285/86 • TPC15
LTC1285/88 • TPC14
Power Supply Feedthrough
vs Ripple Frequency
4096 Point FFT Plot
Intermodulation Distortion
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
0
–20
T
= 25°C
T
= 25°C
A
A
V
V
f
= 2.7V
= 2.5V
V
V
f
= 2.7V (V
= 1mV)
CC
REF
CC
RIPPLE
–20
–40
= 2.5V
REF
= 3.05kHz
= 120kHz
= 7.5kHz
= 120kHZ
IN
CLK
SMPL
CLK
f
f
–40
–60
–60
–80
–80
–100
–120
–100
–120
2.5 3.0
0.5 1.0 1.5 2.0
FREQUENCY (kHz)
0
3.5 4.0
1k
10k
100k
1M
10M
2.5 3.0
0.5 1.0 1.5 2.0
FREQUENCY (kHz)
0
3.5 4.0
RIPPLE FREQUENCY (Hz)
LTC1285/86 • TPC18
LTC1285/88 • TPC16
LTC1285/88 • TPC17
Maximum Clock Frequency
vs Source Resistance
Sample-and-Hold Acquisition
Time vs Source Resistance
Maximum Clock Frequency
vs Supply Voltage
10000
1000
100
300
280
260
240
220
200
180
160
140
120
100
200
180
160
140
120
100
80
T
= 25°C
REF
T
V
V
= 25°C
= 2.7V
REF
T
A
= 25°C
= 2.7V
= 2.5V
A
A
CC
V
= 2.5V
V
CC
V
= 2.5V
REF
V
IN
+INPUT
–INPUT
+
R
60
SOURCE
V
+INPUT
–INPUT
IN
40
–
R
SOURCE
20
0
0.1
1
10
1
10
100
1000
10000
2.5
3.5 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)
3.0
SOURCE RESISTANCE (kΩ)
SOURCE RESISTANCE (Ω)
LTC1285/88 • G19
LTC1285/88 • TPC20
LTC1285/88 • TPC21
6
LTC1285/LTC1288
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TYPICAL PERFORMANCE CHARACTERISTICS
Digital Input Logic Threshold
vs Supply Voltage
Minimum Clock Frequency
for 0.1 LSB Error vs Temperature
Input Channel Leakage Current
vs Temperature
3.0
2.5
2.0
1.5
1000
100
10
120
100
V = 2.7V
CC
V = 2.5V
REF
T
= 25°C
V = 2.7V
CC
V = 2.5V
REF
A
80
60
40
20
1
0.1
1.0
0.5
0
ON CHANNEL
OFF CHANNEL
2
0
0.01
20
30
50
–15
5
65 85
105 125
0
10
40
60
70
4.5
SUPPLY VOLTAGE (V)
5.5
6.0
–55 –35
25 45
2.5 3.0
3.5 4.0
5.0
TEMPERATURE (°C)
TEMPERATURE (°C)
LTC1285/88 • TPC22
LTC1285/88 • TPC24
LTC1285/88 • TPC23
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PIN FUNCTIONS
LTC1285
LTC1288
VREF (Pin 1): Reference Input. The reference input defines
CS/SHDN (Pin 1): Chip Select Input. A logic low on this
input enables the LTC1288. A logic high on this input
disables and powers down the LTC1288.
the span of the A/D converter.
IN+ (Pin 2): Positive Analog Input.
IN– (Pin 3): Negative Analog Input.
CH0 (Pin 2): Analog Input.
CH1 (Pin 3): Analog Input.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
CS/SHDN (Pin 5): Chip Select Input. A logic low on this
input enables the LTC1285. A logic high on this input
disables and powers down the LTC1285.
DIN (Pin 5): Digital Data Input. The multiplexer address is
shifted into this input.
DOUT (Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this output.
DOUT (Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this output.
CLK(Pin7):ShiftClock. Thisclocksynchronizestheserial
data transfer and determines conversion speed.
CLK (Pin 7): Shift Clock. This clock synchronizes the
serial data transfer and determines conversion speed.
VCC (Pin 8): Power Supply Voltage. This pin provides
power to the A/D converter. It must be kept free of noise
and ripple by bypassing directly to the analog ground
plane.
VCC/VREF (Pin 8): Power Supply and Reference Voltage.
This pin provides power and defines the span of the A/D
converter. It must be kept free of noise and ripple by
bypassing directly to the analog ground plane.
7
LTC1285/LTC1288
W
BLOCK DIAGRAM
CS/SHDN
CLK
(D
)
V
(V /V
CC CC REF
)
IN
BIAS AND
SHUTDOWN CIRCUIT
SERIAL PORT
D
OUT
+
IN (CH0)
C
SAMPLE
–
+
SAR
–
IN (CH1)
MICROPOWER
COMPARATOR
CAPACITIVE DAC
LTC1285/88 • BD
V
REF
GND
PIN NAMES IN PARENTHESES REFER TO THE LTC1288
TEST CIRCUITS
Load Circuit for tdDO, tr and tf
Voltage Waveforms for DOUT Rise and Fall Times, tr, tf
1.4V
V
V
OH
OL
D
OUT
3k
D
OUT
TEST POINT
t
t
f
LTC1285/88 • TC02
r
100pF
LTC1285/88 • TC01
Voltage Waveforms for DOUT Delay Times, tdDO
Load Circuit for tdis and ten
TEST POINT
3k
CLK
V
IL
t
V
t
t
WAVEFORM 2, t
CC dis
en
dDO
D
OUT
V
OH
WAVEFORM 1
dis
100pF
D
OUT
V
OL
LTC1285/88 • TC04
LTC1285/88 • TC03
8
LTC1285/LTC1288
TEST CIRCUITS
Voltage Waveforms for tdis
Voltage Waveforms for ten
LTC1285
CS
V
CS
IH
D
OUT
90%
10%
WAVEFORM 1
(SEE NOTE 1)
1
2
CLK
t
dis
D
OUT
WAVEFORM 2
(SEE NOTE 2)
B11
D
OUT
V
OL
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL.
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL.
t
en
LTC1285/88 • TC06
LTC1285/88 • TC05
Voltage Waveforms for ten
LTC1288
CS
START
D
IN
1
2
3
4
CLK
B11
D
OUT
V
OL
t
en
LTC1285/88 • TC07
9
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OVERVIEW
basic design, the LTC1285 and LTC1288 differ in some
respects. The LTC1285 has a differential input and has an
external reference input pin. It can measure signals float-
ing on a DC common-mode voltage and can operate with
reduced spans to 1.5V. Reducing the spans allows it to
achieve 366µV resolution. The LTC1288 has a two-chan-
nel input multiplexer and can convert either channel with
respect to ground or the difference between the two. The
reference input is tied to the supply pin.
The LTC1285 and LTC1288 are 3V micropower, 12-bit,
successive approximation sampling A/D converters. The
LTC1285 typically draws 160µA of supply current when
sampling at 7.5kHz while the LTC1288 nominally con-
sumes 210µA of supply current when sampling at 6.6 kHz.
The extra 50µA of supply current on the LTC1288 comes
from the reference input which is intentionally tied to the
supply. Supply current drops linearly as the sample rate is
reduced (see Supply Current vs Sample Rate). The ADCs
automatically power down when not performing conver-
sions, drawing only leakage current. They are packaged in
8-pin SO and DIP packages. The LTC1285 and LTC1288
operate on a single supply from 2.7V to 6V.
SERIAL INTERFACE
The 2-channel LTC1288 communicates with micropro-
cessors and other external circuitry via a synchronous,
half duplex, 4-wire serial interface. The single channel
LTC1285 uses a 3-wire interface (see Operating Sequence
in Figures 1 and 2).
Both the LTC1285 and the LTC1288 contain a 12-bit,
switched-capacitor ADC, a sample-and-hold, and a serial
port (see Block Diagram). Although they share the same
t
CYC
CS
POWER
DOWN
t
suCS
CLK
OUT
NULL
HI-Z
NULL
HI-Z
D
BIT
B11
B10 B9 B8
BIT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0*
(MSB)
t
SMPL
t
t
DATA
CONV
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW,
THE ADC WILL OUTPUT LSB-FIRST DATA THEN FOLLOWED WITH ZEROS INDEFINITELY.
t
CYC
CS
t
POWER DOWN
suCS
CLK
NULL
BIT
HI-Z
HI-Z
D
OUT
B10
B9
B11*
B8
B3 B2 B1
B2 B3 B4 B5 B6 B7
B11 B10 B9 B8 B7 B6 B5 B4
(MSB)
B0 B1
t
SMPL
t
t
DATA
CONV
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW,
THE ADC WILL OUTPUT ZEROS INDEFINITELY.
t
: DURING THIS TIME, THE BIAS CIRCUIT AND THE COMPARATOR POWER DOWN AND THE REFERENCE INPUT
DATA
LTC1285/88 • F01
BECOMES A HIGH IMPEDANCE NODE, LEAVING THE CLK RUNNING TO CLOCK OUT LSB-FIRST DATA OR ZEROES.
Figure 1. LTC1285 Operating Sequence
10
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MSB-First Data (MSBF = 0)
t
CYC
CS
t
POWER DOWN
suCS
CLK
ODD/
SIGN
START
D
IN
DON’T CARE
MSBF
SGL/
DIFF
NULL
HI-Z
HI-Z
BIT
D
OUT
B10
B2 B3 B4 B5 B6 B7 B8 B9
B11*
B3 B2 B1 B0 B1
B11 B10 B9 B8 B7 B6 B5 B4
(MSB)
t
SMPL
t
t
DATA
CONV
MSB-First Data (MSBF = 1)
t
CYC
CS
POWER
DOWN
t
suCS
CLK
ODD/
SIGN
START
D
IN
DON’T CARE
MSBF
SGL/
DIFF
NULL
HI-Z
HI-Z
D
OUT
BIT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0*
(MSB)
t
t
CONV
SMPL
t
DATA
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW,
THE ADC WILL OUTPUT ZEROS INDEFINITELY.
t
: DURING THIS TIME, THE BIAS CIRCUIT AND THE COMPARATOR POWER DOWN AND THE REFERENCE INPUT
DATA
BECOMES A HIGH IMPEDANCE NODE, LEAVING THE CLK RUNNING TO CLOCK OUT LSB-FIRST DATA OR ZEROES.
LTC1285/88 • F02
Figure 2. LTC1288 Operating Sequence Example: Differential Inputs (CH+, CH–)
11
LTC1285/LTC1288
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Data Transfer
the rising edge of the clock. The input data words are
defined as follows:
The CLK synchronizes the data transfer with each bit
being transmitted on the falling CLK edge and captured
on the rising CLK edge in both transmitting and receiving
systems.
SGL/ ODD/
DIFF
START
MSBF
SIGN
MUX
MSB FIRST/
ADDRESS LSB FIRST
LTC1285/88 • AI02
The LTC1285 does not require a configuration input word
and has no DIN pin. A falling CS initiates data transfer as
shown in the LTC1285 operating sequence. After CS falls
the second CLK pulse enables DOUT. After one null bit the
A/D conversion result is output on the DOUT line. Bringing
CS high resets the LTC1285 for the next data exchange.
Start Bit
The first “logical one” clocked into the DIN input after CS
goes low is the start bit. The start bit initiates the data
transfer. The LTC1288 will ignore all leading zeros which
precede this logical one. After the start bit is received, the
remaining bits of the input word will be clocked in. Further
inputs on the DIN pin are then ignored until the next CS
cycle.
The LTC1288 first receives input data and then transmits
back the A/D conversion result (half duplex). Because of
the half duplex operation, DIN and DOUT may be tied
together allowing transmission over just 3 wires: CS, CLK
and DATA (DIN/DOUT).
Multiplexer (MUX) Address
Datatransferisinitiatedbyafallingchipselect(CS)signal.
After CS falls the LTC1288 looks for a start bit. After the
start bit is received, the 3-bit input word is shifted into the
DIN input which configures the LTC1288 and starts the
conversion. After one null bit, the result of the conversion
is output on the DOUT line. At the end of the data exchange
CS should be brought high. This resets the LTC1288 in
preparation for the next data exchange.
The bits of the input word following the START bit assign
the MUX configuration for the requested conversion. For
a given channel selection, the converter will measure the
voltage between the two channels indicated by the “+”
and “–” signs in the selected row of the following tables.
In single-ended mode, all input channels are measured
with respect to GND.
LTC1288 Channel Selection
CS
MUX ADDRESS
CHANNEL #
D
1
D
2
IN
SGL/DIFF ODD/SIGN
0
1
GND
IN
1
1
0
0
0
1
0
1
+
–
–
SINGLE-ENDED
MUX MODE
D
1
D
2
OUT
OUT
+
–
+
+
–
DIFFERENTIAL
MUX MODE
SHIFT MUX
ADDRESS IN
LTC1285/88 • AI03
1 NULL BIT SHIFT A/D CONVERSION
RESULT OUT
LTC1285/88 • AI01
MSB First/LSB First (MSBF)
Input Data Word
The output data of the LTC1288 is programmed for
MSB first or LSB first sequence using the MSBF bit.
When the MSBF bit is a logical one, data will appear on
The LTC1285 requires no DIN word. It is permanently
configured to have a single differential input. The conver-
sion result appears on the DOUT line. The data format is
MSB first followed by the LSB sequence. This provides
easy interface to MSB or LSB first serial ports. For MSB
first data the CS signal can be taken high after B0 (see
Figure 1). The LTC1288 clocks data into the DIN input on
the D
line in MSB first format. Logical zeros will be
OUT
filled in indefinitely following the last data bit. When the
MSBF bit is a logical zero, LSB first data will follow the
normal MSB first data on the D
Sequence).
line (see Operating
OUT
12
LTC1285/LTC1288
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Transfer Curve
either an input or an output. The LTC1288 will take control
of the data line and drive it low on the 4th falling CLK edge
after the start bit is received (see Figure 3). Therefore the
processor port line must be switched to an input before
this happens to avoid a conflict.
TheLTC1285/LTC1288arepermanentlyconfiguredfor
unipolar only. The input span and code assignment for
this conversion type are shown in the following figures.
Transfer Curve
In the Typical Applications section, there is an example of
interfacingtheLTC1288withDINandDOUT tiedtogetherto
the Intel 8051 MPU.
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 0
•
•
•
ACHIEVING MICROPOWER PERFORMANCE
With typical operating currents of 160µA and automatic
shutdown between conversions, the LTC1285/LTC1288
achieves extremely low power consumption over a wide
range of sample rates (see Figure 4). The auto-shutdown
allows the supply curve to drop with reduced sample rate.
0 0 0 0 0 0 0 0 0 0 0 1
V
IN
0 0 0 0 0 0 0 0 0 0 0 0
V
4096
REF
1LSB =
LTC1285/88 • AI04
Output Code
1000
INPUT VOLTAGE
(V = 5.000V)
T
= 25°C
A
OUTPUT CODE
INPUT VOLTAGE
REF
V
V
= 2.7V
CC
REF
CLK
= 2.5V
= 120kHz
4.99878V
1 1 1 1 1 1 1 1 1 1 1 1 1 1
V
V
– 1LSB
REF
REF
f
4.99756V
1 1 1 1 1 1 1 1 1 1 1 1 1 0
– 2LSB
100
10
1
•
•
•
•
•
•
•
•
•
0.00122V
0V
0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0
1LSB
0V
LTC1285/88 • AI05
Operation with DIN and DOUT Tied Together
The LTC1288 can be operated with DIN and DOUT tied
together. This eliminates one of the lines required to
communicatetothemicroprocessor(MPU).Dataistrans-
mitted in both directions on a single wire. The processor
pin connected to this data line should be configurable as
0.1
1
10
100
SAMPLE FREQUENCY (kHz)
LTC1285/88 • F04
Figure 4. Automatic Power Shutdown Between Conversions
Allows Power Consumption to Drop with Sample Rate
MSBF BIT LATCHED
CS
BY LTC1288
1
2
3
4
CLK
DATA
IN OUT
START
SGL/DIFF
ODD/SIGN
MSBF
B11
B10
• • •
(D /D
)
MPU CONTROLS DATA LINE AND SENDS
MUX ADDRESS TO LTC1288
LTC1288 CONTROLS DATA LINE AND SENDS
A/D RESULT BACK TO MPU
PROCESSOR MUST RELEASE DATA LINE AFTER
4TH RISING CLK AND BEFORE THE 4TH FALLING CLK
LTC1288 TAKES CONTROL OF DATA LINE
ON 4TH FALLING CLK
LTC1285/88 F03
Figure 3. LTC1288 Operation with DIN and DOUT Tied Together
13
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Several things must be taken into account to achieve such
lowest current drain. This minimizes the amount of time
the device draws power. After a conversion the ADC
automatically shuts down even if CS is held low (see
Figures 1 and 2). If the clock is left running to clock out
LSB-data or zero, the logic will draw a small current.
Figure 5 shows that the typical supply current with CS =
ground varies from 1µA at 1kHz to 9µA at 120kHz. When
CS = VCC, the logic is gated off and no supply current is
drawn regardless of the clock frequency.
a low power consumption.
Shutdown
TheLTC1285/LTC1288areequippedwithautomaticshut-
down features. They draw power when the CS pin is low
and shut down completely when that pin is high. The bias
circuit and comparator powers down and the reference
input becomes high impedance at the end of each conver-
sionleavingtheCLKrunningtoclockouttheLSBfirstdata
or zeroes(seeFigures1and2).IftheCSisnotrunningrail-
to-rail,theinputlogicbufferwilldrawcurrent.Thiscurrent
may be large compared to the typical supply current. To
obtain the lowest supply current, bring the CS pin to
groundwhenitislowandtosupplyvoltagewhenitishigh.
DOUT Loading
Capacitive loading on the digital output can increase
power consumption. A 100pF capacitor on the DOUT pin
can add more than 16.2µA to the supply current at a
120kHz clock frequency. An extra 16.2µA or so of current
goesintocharginganddischargingtheloadcapacitor.The
same goes for digital lines driven at a high frequency by
anylogic. The C × V × fcurrentsmustbeevaluatedandthe
troublesome ones minimized.
When the CS pin is high (= supply voltage), the converter
is in shutdown mode and draws only leakage current. The
status of the DIN and CLK input have no effect on supply
current during this time. There is no need to stop DIN and
CLK with CS = high; they can continue to run without
drawing current.
OPERATING ON OTHER THAN 3V SUPPLIES
Both the LTC1285 and the LTC1288 operate from a 2.7V
to 6V supply. To operate the LTC1285/LTC1288 on other
than 3V supplies a few things must be kept in mind.
Minimize CS Low Time
In systems that have significant time between conver-
sions, lowest power drain will occur with the minimum CS
low time. Bringing CS low, transferring data as quickly as
possible, and then bringing it back high will result in the
Input Logic Levels
The input logic levels of CS, CLK and DIN are made to
meetTTLona3Vsupply.Whenthesupplyvoltagevaries,
the input logic levels also change. For the LTC1285/
LTC1288 to sample and convert correctly, the digital
inputs have to be in the proper logical low and high levels
relative to the operating supply voltage (see typical curve
of Digital Input Logic Threshold vs Supply Voltage). If
achieving micropower consumption is desirable, the
digital inputs must go rail-to-rail between supply voltage
and ground (see ACHIEVING MICROPOWER PERFOR-
MANCE section).
9
T
V
V
= 25°C
= 2.7V
REF
A
CC
8
= 2.5V
7
6
5
4
3
CS = 0
(AFTER CONVERSION)
2
1
0.002
0
CS = V
60
CC
1
20
80
100
120
40
Clock Frequency
FREQUENCY (kHz)
LTC1285/88 • TPC03
The maximum recommended clock frequency is 120kHz
for the LTC1285/LTC1288 running off a 3V supply. With
the supply voltage changing, the maximum clock fre-
quency for the devices also changes (see the typical curve
Figure 5. Shutdown Current with CS High is 1nA Typically,
Regardless of the Clock. Shutdown Current with CS = Ground
Varies From 1µA at 1kHz to 9µA at 120kHz
14
LTC1285/LTC1288
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of Maximum Clock Rate vs Supply Voltage). If the maxi-
mum clock frequency is used, care must be taken to
ensure that the device converts correctly.
BOARD LAYOUT CONSIDERATIONS
Grounding and Bypassing
The LTC1285/LTC1288 are easy to use if some care is
taken. They should be used with an analog ground plane
and single point grounding techniques. The GND pin
should be tied directly to the ground plane.
Mixed Supplies
It is possible to have a microprocessor running off a 5V
supply and communicate with the LTC1285/LTC1288
operating on a 3V supply. The inputs of CS, CLK and DIN
of the LTC1285/LTC1288 have no problem to take a
voltage swing from 0V to 5V. With the LTC1285 operating
on a 3V supply, the output of DOUT may only go between
0V and 3V. The 3V output level is higher enough to trip a
TTL input of the MPU. Figure 6 shows a 3V powered
LTC1285 interfacing a 5V system.
The VCC pin should be bypassed to the ground plane with
a 10µF tantalum capacitor with leads as short as possible.
If the power supply is clean, the LTC1285/LTC1288 can
also operate with smaller 1µF or less surface mount or
ceramic bypass capacitors. All analog inputs should be
referenced directly to the single point ground. Digital
inputs and outputs should be shielded from and/or routed
away from the reference and analog circuitry.
4.7µF
3V
MPU
(e.g. 8051)
SAMPLE-AND-HOLD
5V
Both the LTC1285 and the LTC1288 provide a built-in
sample-and-hold (S&H) function to acquire signals. The
S&H of the LTC1285 acquires input signals from “+” input
relative to “–” input during the tSMPL time (see Figure 1).
However, the S&H of the LTC1288 can sample input
signals in the single-ended mode or in the differential
inputs during the tSMPL time (see Figure 7).
3V
V
V
P1.4
REF
CC
DIFFERENTIAL INPUTS
+IN
–IN
GND
CLK
P1.3
P1.2
COMMON-MODE RANGE
0V TO 3V
D
OUT
CS
LTC1285
LTC1285/88 • F06
Figure 6. Interfacing a 3V Powered LTC1285 to a 5V System
SAMPLE
HOLD
"+" INPUT MUST
SETTLE DURING
THIS TIME
CS
t
t
CONV
SMPL
CLK
D
START
SGL/DIFF
MSBF
DON’T CARE
IN
D
OUT
B11
1ST BIT TEST "–" INPUT MUST
SETTLE DURING THIS TIME
"+" INPUT
"–" INPUT
LTC1285/88 • F07
Figure 7. LTC1288 “+” and “–” Input Settling Windows
15
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Single-Ended Inputs
“+” Input Settling
The sample-and-hold of the LTC1288 allows conversion
of rapidly varying signals. The input voltage is sampled
during the tSMPL time as shown in Figure 7. The sampling
interval begins as the bit preceding the MSBF bit is shifted
in and continues until the falling CLK edge after the MSBF
bit is received. On this falling edge, the S&H goes into hold
mode and the conversion begins.
The input capacitor of the LTC1285 is switched onto “+”
input during the tSMPL time (see Figure 1) and samples
the input signal within that time. However, the input
capacitor of the LTC1288 is switched onto “+” input
during the sample phase (tSMPL, see Figure 7). The
sample phase is 1 1/2 CLK cycles before conversion
starts. The voltage on the “+” input must settle com-
pletely within tSMPLE for the LTC1285 and the LTC1288
respectively. Minimizing RSOURCE+ and C1 will improve
the input settling time. If a large “+” input source resis-
tance must be used, the sample time can be increased by
using a slower CLK frequency.
Differential Inputs
With differential inputs, the ADC no longer converts just a
single voltage but rather the difference between two volt-
ages. In this case, the voltage on the selected “+” input is
still sampled and held and therefore may be rapidly time
varying just as in single-ended mode. However, the volt-
ageon theselected“–”inputmustremainconstantandbe
free of noise and ripple throughout the conversion time.
Otherwise, the differencing operation may not be per-
formed accurately. The conversion time is 12 CLK cycles.
Therefore, a change in the “–” input voltage during this
interval can cause conversion errors. For a sinusoidal
voltage on the “–” input this error would be:
“–” Input Settling
At the end of the tSMPL, the input capacitor switches to the
“–” input and conversion starts (see Figures 1 and 7).
During the conversion, the “+” input voltage is effectively
“held” by the sample-and-hold and will not affect the
conversion result. However, it is critical that the “–” input
voltage settles completely during the first CLK cycle of the
–
conversiontimeandbefreeofnoise.MinimizingRSOURCE
and C2 will improve settling time. If a large “–” input
source resistance must be used, the time allowed for
settling can be extended by using a slower CLK frequency.
VERROR (MAX) = VPEAK × 2 × π × f(“–”) × 12/fCLK
Where f(“–”) is the frequency of the “–” input voltage,
VPEAK is its peak amplitude and fCLK is the frequency of the
CLK. In most cases VERROR will not be significant. For a
60Hz signal on the “–” input to generate a 1/4LSB error
(152µV) with the converter running at CLK = 120kHz, its
peak value would have to be 4.03mV.
Input Op Amps
When driving the analog inputs with an op amp it is
important that the op amp settle within the allowed time
(see Figure 7). Again, the“+” and “–” input sampling times
can be extended as described above to accommodate
slower op amps. Most op amps, including the LT1006 and
LT1413 single supply op amps, can be made to settle well
even with the minimum settling windows of 12.5µs (“+”
input) which occur at the maximum clock rate of 120kHz.
ANALOG INPUTS
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1285/
LTC1288 have capacitive switching input current spikes.
These current spikes settle quickly and do not cause a
problem. However, if large source resistances are used or
if slow settling op amps drive the inputs, care must be
taken to insure that the transients caused by the current
spikes settle completely before the conversion begins.
Source Resistance
The analog inputs of the LTC1285/LTC1288 look like a
20pF capacitor (CIN) in series with a 500Ω resistor (RON)
as shown in Figure 8. CIN gets switched between the
16
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selected “+” and “–” inputs once during each conversion
cycle. Large external source resistors and capacitances
will slow the settling of the inputs. It is important that the
overall RC time constants be short enough to allow the
analog inputs to completely settle within the allowed time.
Input Leakage Current
Inputleakagecurrentscanalsocreateerrorsifthesource
resistance gets too large. For instance, the maximum
input leakage specification of 1µA (at 125°C) flowing
through a source resistance of 240Ω will cause a voltage
drop of 240µV or 0.4LSB. This error will be much
reduced at lower temperatures because leakage drops
rapidly (see typical curve of Input Channel Leakage
Current vs Temperature).
“+”
INPUT
+
R
SOURCE
LTC1285
LTC1288
V
IN
+
C1
R
= 500Ω
ON
“–”
INPUT
C
= 20pF
IN
–
R
SOURCE
V
IN
–
REFERENCE INPUTS
C2
The reference input of the LTC1285 is effectively a 50kΩ
resistor from the time CS goes low to the end of the
conversion.Thereferenceinputbecomesahighimpedence
node at any other time (see Figure 10). Since the voltage
on the reference input defines the voltage span of the A/D
converter, the reference input should be driven by a
referencewithlowROUT(ex.LT1004,LT1019andLT1021)
LTC1285/88 • F08
Figure 8. Analog Input Equivalent Circuit
RC Input Filtering
It is possible to filter the inputs with an RC network as
shown in Figure 9. For large values of CF (e.g., 1µF), the
capacitive input switching currents are averaged into a
net DC current. Therefore, a filter should be chosen with
a small resistor and large capacitor to prevent DC drops
across the resistor. The magnitude of the DC current is
approximately IDC = 20pF × VIN/tCYC and is roughly
proportional to VIN. When running at the minimum cycle
time of 133.3µs, the input current equals 0.375µA at VIN
= 2.5V. In this case, a filter resistor of 160Ω will cause
0.1LSB of full-scale error. If a larger filter resistor must
be used, errors can be eliminated by increasing the cycle
time.
or a voltage source with low ROUT
.
+
REF
LTC1285
1
R
OUT
V
REF
GND
4
LTC1285/88 • F10
Figure 10. Reference Input Equivalent Circuit
Reduced Reference Operation
The minimum reference voltage of the LTC1288 is limited
to 2.7V because the VCC supply and reference are inter-
nally tied together. However, the LTC1285 can operate
with reference voltages below 1.5V.
I
DC
R
FILTER
V
“+”
LTC1285
“–”
IN
C
FILTER
The effective resolution of the LTC1285 can be increased
by reducing the input span of the converter. The LTC1285
exhibits good linearity and gain over a wide range of
referencevoltages(seetypicalcurvesofChangeinLinear-
ity vs Reference Voltage and Change in Gain vs Reference
LTC1285/88 • F09
Figure 9. RC Input Filtering
17
LTC1285/LTC1288
U
W
U U
APPLICATION INFORMATION
Voltage). However, care must be taken when operating at
low values of VREF because of the reduced LSB step size
and the resulting higher accuracy requirement placed on
the converter. The following factors must be considered
when operating at low VREF values:
noise becomes equal to 3.3LSBs and a stable code may
be difficult to achieve. In this case averaging multiple
readings may be necessary.
This noise data was taken in a very clean setup. Any setup
induced noise (noise or ripple on VCC, VREF or VIN) will add
to the internal noise. The lower the reference voltage to be
usedthemorecriticalitbecomestohaveaclean, noisefree
setup.
1. Offset
2. Noise
3. Conversion speed (CLK frequency)
Offset with Reduced VREF
Conversion Speed with Reduced VREF
The offset of the LTC1285 has a larger effect on the output
code. When the ADC is operated with reduced reference
voltage. The offset (which is typically a fixed voltage)
becomes a larger fraction of an LSB as the size of the LSB
is reduced. The typical curve of Change in Offset vs
Reference Voltage shows how offset in LSBs is related to
reference voltage for a typical value of VOS. For example,
a VOS of 122µV which is 0.2LSB with a 2.5V reference
becomes 1LSB with a 1V reference and 5LSBs with a 0.2V
reference. Ifthisoffsetisunacceptable, itcanbecorrected
digitally by the receiving system or by offsetting the “–”
input of the LTC1285.
With reduced reference voltages, the LSB step size is
reduced and the LTC1285 internal comparator over-
drive is reduced. Therefore, it may be necessary to
reduce the maximum CLK frequency when low values
of V
are used.
REF
DYNAMIC PERFORMANCE
The LTC1285/LTC1288 have exceptional sampling capa-
bility. Fast Fourier Transform (FFT) test techniques are
used to characterize the ADC’s frequency response, dis-
tortion and noise at the rated throughput. By applying a
low distortion sine wave and analyzing the digital output
using an FFT algorithm, the ADC’s spectral content can be
examined for frequencies outside the fundamental. Figure
11 shows a typical LTC1285 plot.
Noise with Reduced VREF
The total input referred noise of the LTC1285 can be
reduced to approximately 400µV peak-to-peak using a
ground plane, good bypassing, good layout techniques
and minimizing noise on the reference inputs. This noise
is insignificant with a 2.5V reference but will become a
larger fraction of an LSB as the size of the LSB is reduced.
0
T
= 25°C
A
V
V
f
= 2.7V
CC
REF
= 3.05kHz
–20
–40
= 2.5V
IN
CLK
SMPL
f
f
= 120kHz
= 7.5kHz
–60
For operation with a 2.5V reference, the 400µV noise is
only 0.66LSB peak-to-peak. In this case, the LTC1285
noise will contribute a little bit of uncertainty to the
output code. However, for reduced references the noise
may become a significant fraction of an LSB and cause
undesirable jitter in the output code. For example, with
a 1.25V reference this same 400µV noise is 1.32LSB
peak-to-peak. This will reduce the range of input volt-
ages over which a stable output code can be achieved by
1LSB.Ifthereferenceisfurtherreducedto1V,the400µV
–80
–100
–120
2.5 3.0
FREQUENCY (kHz)
0
0.5 1.0 1.5 2.0
3.5 4.0
LTC1285/88 • TPC16
Figure 11. LTC1285 Non-Averaged, 4096 Point FFT Plot
18
LTC1285/LTC1288
U
W
U U
APPLICATION INFORMATION
Signal-to-Noise Ratio
V2 + V32 + V42 +... + VN2
2
THD = 20log
The Signal-to-Noise plus Distortion Ratio (S/N + D) is the
V
1
ratio between the RMS amplitude of the fundamental
input frequency to the RMS amplitude of all other fre-
quency components at the ADC’s output. The output is
band limited to frequencies above DC and below one half
the sampling frequency. Figure 12 shows a typical spec-
tral content with a 7.5kHz sampling rate.
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through VN are the amplitudes of the
secondthroughtheNth harmonics. ThetypicalTHDspeci-
fication in the Dynamic Accuracy table includes the 2nd
through 5th harmonics. With a 1kHz input signal, the
LTC1285/LTC1288 have typical THD of 80dB with
12
11
10
9
74
68
62
56
50
V
CC = 2.7V.
Intermodulation Distortion
8
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition
to THD. IMD is the change in one sinusoidal input
caused by the presence of another sinusoidal input at a
different frequency.
7
6
5
4
3
T
= 25°C
A
2
V
f
= 2.7V
CC
1
= 120kHz
CLK
0
1
10
INPUT FREQUENCY (kHz)
100
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer func-
tion can create distortion products at sum and difference
frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc.
For example, the 2nd order IMD terms include (fa + fb) and
(fa – fb) while 3rd order IMD terms include (2fa + fb),
(2fa – fb), (fa + 2fb), and (fa – 2fb). If the two input sine
wavesareequalinmagnitudes, thevalue(indB)ofthe2nd
order IMD products can be expressed by the following
formula:
LTC1285/88 • TPC12
Figure 12. Effective Bits and S/(N + D) vs Input Frequency
Effective Number of Bits
TheEffectiveNumberofBits(ENOBs)isameasurementof
the resolution of an ADC and is directly related to S/(N+D)
by the equation:
ENOB = [S/(N + D) – 1.76]/6.02
where S/(N + D) is expressed in dB. At the maximum
sampling rate of 7.5kHz with a 2.7V supply, the LTC1285
maintains above 10.7 ENOBs at 10kHz input frequency.
Above 10kHz the ENOBs gradually decline, as shown in
Figure 12, due to increasing second harmonic distortion.
The noise floor remains low.
amplitude f ± f
(
)
b
a
IMD f ± f = 20log
(
)
a
b
amplitude at fa
For input frequencies of 2.05kHz and 3.05kHz, the IMD of
the LTC1285/LTC1288 is 72dB with a 2.7V supply.
Peak Harmonic or Spurious Noise
Total Harmonic Distortion
The peak harmonic or spurious noise is the largest spec-
tral component excluding the input signal and DC. This
valueisexpressedindBsrelativetotheRMSvalueofafull-
scale input signal.
Total Harmonic Distortion (THD) is the ratio of the RMS
sumofallharmonicsoftheinputsignaltothefundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half of the sampling frequency. THD
is defined as:
19
LTC1285/LTC1288
U
TYPICAL APPLICATIONS N
MICROPROCESSOR INTERFACES
Table 1. Microprocessor with Hardware Serial Interfaces
Compatible with the LTC1286/LTC1298
The LTC1285/LTC1288 can interface directly without ex-
ternal hardware to most popular microprocessor (MPU)
synchronous serial formats (see Table 1). If an MPU
without a dedicated serial port is used, then 3 or 4 of the
MPU's parallel port lines can be programmed to form the
serial link to the LTC1285/LTC1288. Included here is one
serial interface example and one example showing a
parallel port programmed to form the serial interface.
PART NUMBER
Motorola
TYPE OF INTERFACE
MC6805S2,S3
MC68HC11
MC68HC05
SPI
SPI
SPI
RCA
CDP68HC05
SPI
Hitachi
HD6305
HD63705
HD6301
HD63701
HD6303
HD64180
SCI Synchronous
SCI Synchronous
SCI Synchronous
SCI Synchronous
SCI Synchronous
CSI/O
Motorola SPI (MC68HC11)
TheMC68HC11hasbeenchosenasanexampleofanMPU
with a dedicated serial port. This MPU transfers data MSB
-firstandin8-bitincrements.TheDIN wordsenttothedata
register starts with the SPI process. With three 8-bit
transfers, the A/D result is read into the MPU. The second
8-bittransferclocksB11throughB8oftheA/Dconversion
result into the processor. The third 8-bit transfer clocks
the remaining bits, B7 through B0, into the MPU. The data
is right justified into two memory locations. ANDing the
second byte with OFHEX clears the four most significant
bits. This operation was not included in the code. It can be
inserted in the data gathering loop or outside the loop
when the data is processed.
National Semiconductor
COP400 Family
COP800 Family
NS8050U
MICROWIRE†
MICROWIRE/PLUS†
MICROWIRE/PLUS†
MICROWIRE/PLUS†
HPC16000 Family
Texas Instruments
TMS7002
TMS7042
TMS70C02
TMS70C42
TMS32011*
TMS32020
Serial Port
Serial Port
Serial Port
Serial Port
Serial Port
Serial Port
Intel
MC68HC11 Code
8051
Bit Manipulation on Parallel Port
* Requires external hardware
MICROWIRE and MICROWIRE/PLUS are trademarks of
National Semiconductor Corp.
In this example the DIN word configures the input MUX for
a single-ended input to be applied to CHO. The conversion
result is output MSB-first.
†
20
LTC1285/LTC1288
U
TYPICAL APPLICATIONS N
Timing Diagram for Interface to the MC68HC11
CS
CLK
SGL/
DIFF
ODD/
SIGN
DON'T CARE
MSBF
D
START
IN
D
OUT
B11 B10
B9
X
B8
X
B7
B6
X
B5
X
B4
X
B3
X
B2
X
B1
X
B0
X
MPU
TRANSMIT
WORD
ODD/
SIGN
SGL/
0
?
0
?
0
?
0
0
?
0
?
0
?
1
?
MSBF
?
X
X
X
X
DIFF
BYTE 2
BYTE 1
BYTE 3 (DUMMY)
MPU
RECEIVED
WORD
?
?
?
0
B11 B10
B9
B8
B7
B6
B5
B3
BYTE 3
B2
B1
B4
B0
BYTE 2
BYTE 1
LTC1285/88 • TA03
Hardware and Software Interface to the MC68HC11
D
FROM LTC1298 STORED IN MC68HC11 RAM
OUT
MSB
CH0
D0
CS
CLK
0
0
B11
B3
B9
B1
B8
B0
BYTE 1
BYTE 2
0
0
B10
B2
#62
#63
SCK
ANALOG
INPUTS
LTC1288
MC68HC11
LSB
B4
D
OUT
MISO
B7
B6
B5
D
MOSI
CH1
IN
LTC1285/88 • TA04
LABEL MNEMONIC OPERAND
COMMENTS
LABEL MNEMONIC OPERAND
COMMENTS
LDAA
STAA
LDAA
STAA
LDAA
STAA
LDAA
STAA
LDAA
#$50
$1028
#$1B
$1009
#$01
$50
#$A0
$51
#$00
CONFIGURATION DATA FOR SPCR
LOAD DATA INTO SPCR ($1028)
CONFIG. DATA FOR PORT D DDR
LOAD DATA INTO PORT D DDR
LOAD DIN WORD INTO ACC A
LOAD DIN DATA INTO $50
LOAD DIN WORD INTO ACC A
LOAD DIN DATA INTO $51
LOAD DUMMY DIN WORD INTO
ACC A
WAIT1 BPL
LDAA
STAA
WAIT2 LDAA
BPL
WAIT1
$51
CHECK IF TRANSFER IS DONE
LOAD DIN INTO ACC A FROM $51
LOAD DIN INTO SPI, START SCK
CHECK SPI STATUS REG
CHECK IF TRANSFER IS DONE
LOAD LTC1288 MSBs INTO ACC A
STORE MSBs IN $62
LOAD DUMMY INTO ACC A
FROM $52
LOAD DUMMY DIN INTO SPI,
START SCK
$102A
$1029
WAIT2
$102A
$62
LDAA
STAA
LDAA
$52
STAA
$102A
STAA
LDX
$52
#$1000
LOAD DUMMY DIN DATA INTO $52
LOAD INDEX REGISTER X WITH
$1000
WAIT3 LDAA
BPL
$1029
WAIT3
CHECK SPI STATUS REG
CHECK IF TRANSFER IS DONE
LOOP BCLR
LDAA
$08,X,#$01 D0 GOES LOW (CS GOES LOW)
BSET
LDAA
STAA
JMP
$08,X#$01 DO GOES HIGH (CS GOES HIGH)
$50
LOAD DIN INTO ACC A FROM $50
LOAD DIN INTO SPI, START SCK
CHECK SPI STATUS REG
$102A
$63
LOAD LTC1288 LSBs IN ACC
STORE LSBs IN $63
STAA
LDAA
$102A
$1029
LOOP
START NEXT CONVERSION
21
LTC1285/LTC1288
U
TYPICAL APPLICATIONS N
Interfacing to the Parallel Port of the INTEL 8051
Family
LABEL
MNEMONIC
OPERAND
COMMENTS
MOV
SETB
CLR
MOV
RLC
CLR
MOV
SETB
DJNZ
MOV
CLR
MOV
MOV
RLC
SETB
CLR
DJNZ
MOV
CLR
MOV
MOV
RLC
SETB
CLR
DJNZ
MOV
RRC
DJNZ
MOV
SETB
A, #FFH
P1.4
D word for LTC1288
IN
Make sure CS is high
CS goes low
The Intel 8051 has been chosen to demonstrate the
interface between the LTC1288 and parallel port micro-
processors. Normally the CS, CLK and DIN signals would
be generated on 3 port lines and the DOUT signal read on
a 4th port line. This works very well. However, we will
demonstratehereaninterfacewiththeDIN andDOUT ofthe
LTC1288 tiedtogetherasdescribedintheSERIALINTER-
FACE section. This saves one wire.
P1.4
R4, #04
A
Load counter
LOOP 1
Rotate D bit into Carry
IN
P1.3
P1.2, C
P1.3
SCLK goes low
Output D bit to LTC1288
IN
SCLK goes high
R4, LOOP 1 Next bit
P1, #04
P1.3
R4, #09
C, P1.2
A
P1.3
P1.3
Bit 2 becomes an input
SCLK goes low
Load counter
LOOP 2
Read data bit into Carry
Rotate data bit into Acc.
SCLK goes high
The 8051 first sends the start bit and MUX address to the
LTC1288 over the data line connected to P1.2. Then P1.2
is reconfigured as an input (by writing to it a one) and the
8051 reads back the 12-bit A/D result over the same data
line.
SCLK goes low
R4, LOOP 2 Next bit
R2, A
A
Store MSBs in R2
Clear Acc.
R4, #04
C, P1.2
A
P1.3
P1.3
Load counter
LOOP 3
LOOP 4
Read data bit into Carry
Rotate data bit into Acc.
SCLK goes high
SCLK goes low
CS
CLK
P1.4
P1.3
P1.2
ANALOG
INPUTS
LTC1288
8051
R4, LOOP 3 Next bit
D
OUT
R4, #04
A
Load counter
Rotate right into Acc.
D
IN
MUX ADDRESS
A/D RESULT
LTC1285/88 • TA01
R4, LOOP 4 Next Rotate
R3, A
P1.4
Store LSBs in R3
CS goes high
DOUT FROM 1288 STORED IN 8501 RAM
MSB
R2 B11 B10 B9 B8 B7 B6 B5 B4
LSB
R3 B3 B2 B1 B0 0
0
0
0
MSBF BIT LATCHED
INTO LTC1288
CS
CLK
DATA
IN OUT
SGL/
START DIFF
(
D
/D
)
MSBF
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
ODD/
SIGN
8051 P1.2 OUTPUTS DATA
TO LTC1288
LTC1288 SENDS A/D RESULT
BACK TO 8051 P1.2
8051 P1.2 RECONFIGURED
AS IN INPUT AFTER THE 4TH RISING CLK
AND BEFORE THE 4TH FALLING CLK
LTC1288 TAKES CONTROL OF DATA
LINE ON 4TH FALLING CLK
LTC1285/88 • TA07
22
LTC1285/LTC1288
U
TYPICAL APPLICATIONS N
A “Quick Look” Circuit for the LTC1285
Micropower Battery Voltage Monitor
Users can get a quick look at the function and timing of the
LT1285 by using the following simple circuit (Figure 13).
A common problem in battery systems is battery voltage
monitoring.Thiscircuitmonitorsthe10cellstackofNiCad
orNiMHbatteriesfoundinlaptopcomputers.Itdrawsonly
40µA from the 2.7V supply at fSMPL = 0.1kHz and 30µA to
62µA from the battery. The 12-bits of resolution of the
LTC1285 are positioned over the desired range of 8V to
16V. This is easily accomplished by using the ADC’s
differential inputs. Tying the –input to the reference gives
an ADC input span of VREF to 2VREF (1.2V to 2.4V). The
resistordividerthenscalestheinputvoltagefor8Vto16V.
VREF is tied to VCC. VIN is applied to the +IN input and the
–IN input is tied to the ground. CS is driven at 1/16 the
clock rate by the 74C161 and DOUT outputs the data. The
output data from the DOUT pin can be viewed on an
oscilloscope that is set up to trigger on the falling edge of
CS (Figure 14). Note the LSB data is partially clocked out
before CS goes high.
2.7V
4.7µF
BATTERY MONITOR
INPUT 8V TO 16V
2.7V
CLR
CLK
A
B
C
D
P
GND
V
CC
RC
0.1µF
V
V
REF
CC
220k
39k
QA
QB
QC
QD
T
V
CC
V
+IN
–IN
GND
CLK
IN
+IN
–IN
CS
CLK
D
74HC161
LTC1285
LTC1285
D
OUT
CS
OUT
V
LOAD
REF
GND
1µF
3Ω
39k
LT1004-1.2
LTC1285/88 • F13
CLOCK IN 120kHz
LTC1285/88 • F15
TO OSCILLOSCOPE
Figure 15. Micropower Battery Voltage Monitor
Figure 13. “Quick Look” Circuit for the LTC1285
NULL
BIT
LSB
(B0)
MSB
(B11)
VERTICAL: 2V/DIV
HORIZONTAL: 20µs/DIV
Figure 14. Scope Trace the LTC1285 “Quick Look” Circuit
Showing A/D Output 101010101010 (AAAHEX
)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
23
LTC1285/LTC1288
U
PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
N8 Package
8-Lead Plastic DIP
0.400*
(10.160)
MAX
0.130 ± 0.005
(3.302 ± 0.127)
0.300 – 0.325
(7.620 – 8.255)
0.045 – 0.065
(1.143 – 1.651)
8
1
7
6
5
4
0.065
(1.651)
TYP
0.255 ± 0.015*
(6.477 ± 0.381)
0.009 – 0.015
(0.229 – 0.381)
0.125
0.005
0.015
(0.380)
MIN
(3.175)
MIN
(0.127)
MIN
+0.025
–0.015
2
3
0.325
N8 0695
+0.635
8.255
(
)
–0.381
0.100 ± 0.010
(2.540 ± 0.254)
0.018 ± 0.003
(0.457 ± 0.076)
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
S8 Package
8-Lead Plastic SOIC
0.189 – 0.197*
(4.801 – 5.004)
0.010 – 0.020
(0.254 – 0.508)
7
5
8
6
× 45°
0.053 – 0.069
(1.346 – 1.752)
0.004 – 0.010
(0.101 – 0.254)
0.008 – 0.010
(0.203 – 0.254)
0°– 8° TYP
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
0.016 – 0.050
0.406 – 1.270
0.050
(1.270)
BSC
0.014 – 0.019
(0.355 – 0.483)
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
1
3
4
2
SO8 0695
RELATED PARTS
PART NUMBER
LTC1096/LTC1098
LTC1196/LTC1198
LTC1282
DESCRIPTION
COMMENTS
8-Pin SOIC, Micropower 8-Bit ADC
8-Pin SOIC, 1Msps 8-bit ADC
3V High Speed Parallel 12-Bit ADC
Multiplexed 3V, 1A 12-Bit ADC
16-Pin SOIC, 3V Micropower 12-Bit ADC
Low Power, Small Size, Low Cost
Low Power, Small Size, Low Cost
Complete, V , CLK, Sample-and-Hold, 140ksps
REF
LTC1289
8-Channel, 12-Bit Serial I/O
4-Channel, 12-Bit Serial I/O
LTC1522
LT/GP 0894 10K • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7487
24
●
●
LINEAR TECHNOLOGY CORPORATION 1994
(408) 432-1900 FAX: (408) 434-0507 TELEX: 499-3977
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