LTC1289BCJ#TR [Linear]
IC 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP20, 0.300 INCH, CERDIP-20, Analog to Digital Converter;型号: | LTC1289BCJ#TR |
厂家: | Linear |
描述: | IC 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP20, 0.300 INCH, CERDIP-20, Analog to Digital Converter CD 转换器 |
文件: | 总28页 (文件大小:663K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC1289
3 Volt Single Chip 12-Bit
Data Acquisition System
U
FEATURES
DESCRIPTIO
The LTC®1289 is a 3V data acquisition component which
contains a serial I/O successive approximation A/D con-
verter. The device specifications are guaranteed at a
supply voltage of 2.7V. It uses LTCMOSTM switched ca-
pacitor technology to perform a 12-bit unipolar, or 11-bit
plus sign bipolar A/D conversion. The 8 channel input
multiplexer can be configured for either single-ended or
differential inputs (or combinations thereof). An on-chip
sample and hold is included for all single-ended input
channels. When the LTC1289 is idle it can be powered
down in applications where low power consumption is
desired.
■
Single Supply 3.3V or ±3.3V Operation
■
Software Programmable Features
Unipolar/Bipolar Conversions
4 Differential/8 Single-Ended Inputs
Variable Data Word Length
Power Shutdown
■
Built-In Sample-and-Hold
Direct 4-Wire Interface to Most MPU Serial Ports
and All MPU Parallel Ports
25kHz Maximum Throughput Rate
Available in 20-Lead PDIP and 20-Lead SW Packages
■
■
■
U
The serial I/O is designed to be compatible with industry
standardfullduplexserialinterfaces. ItallowseitherMSB-
or LSB- first data and automatically provides 2’s comple-
ment output coding in the bipolar mode. The output data
word can be programmed for a length of 8, 12 or 16 bits.
This allows easy interface to shift registers and a variety of
processors.
APPLICATIO S
■
Minimum Guaranteed Supply Voltage: 2.7V
Resolution: 12 Bits
Fast Conversion Time: 26µs Max Over Temp
Low Supply Currents: 1.0mA
■
■
■
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
LTCMOS is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
U
TYPICAL APPLICATIO
Single Cell 3V 12-Bit Data Acquisition System
+3V
CH0
V
CC
3V
+
1N4148
22µF
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
DGND
ACLK
SCLK
LITHIUM
10k
TANTALUM
–
+
BOOST
V
10Ω
TO AND
FROM
MPU
1/4 LTC1079
D
+
IN
CAP
OSC
LV
LTC1044
+
D
+
OUT
LTC1289
GND
1N4148
1N5817
10µF
10µF
CS
–
CAP
V
OUT
–3V
+
REF
–3V
+
LT1004-1.2
–
22µF
22µF
+
REF
FOR OVERVOLTAGE PROTECTION ON
ONLY ONE CHANNEL LIMIT THE INPUT
CURRENT TO 15mA. FOR MORE THAN
ONE CHANNEL LIMIT THE INPUT
CURRENT TO 7mA PER CHANNEL AND
28mA FOR ALL CHANNELS.
CONVERSION RESULTS ARE NOT VALID
–
V
AGND
0.1µF
WHEN THE SELECTED OR ANY OTHER
LTC1289 TA01
–
CHANNEL IS OVERVOLTAGED (V < V
IN
or V > V ).
IN
CC
1289fb
1
LTC1289
W W W
U
ABSOLUTE AXI U RATI GS (Notes 1 and 2)
Supply Voltage VCC to GND or V–........................... 12V
Negative Supply Voltage (V–) .................... –6V to GND
Voltage
Power Dissipation............................................. 500mW
Operating Temperature Range
LTC1289BC, LTC1289CC......................... 0°C to 70°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec.)................ 300°C
Analog and Reference Inputs... (V–) – 0.3V to VCC + 0.3V
Digital Inputs ........................................ –0.3V to 12V
Digital Outputs ........................... –0.3V to VCC + 0.3V
W U
/O
PACKAGE RDER I FOR ATIO
TOP VIEW
1
2
V
CC
20
19
18
17
16
15
14
13
12
11
CH0
CH1
TOP VIEW
ACLK
SCLK
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
1
2
3
4
5
6
7
8
9
20
V
CC
3
CH2
19 ACLK
18 SCLK
17 DIN
4
D
CH3
IN
5
D
CH4
OUT
6
CS
CH5
16
D
OUT
+
7
REF
CH6
15 CS
–
8
REF
CH7
+
–
14 REF
–
9
V
COM
DGND
13 REF
–
10
AGND
12
V
N PACKAGE, 20-LEAD PLASTIC DIP
= 110°C, θ = 100°C/W (N)
DGND 10
11 AGND
T
JMAX
JA
SW PACKAGE
20-LEAD PLASTIC SO WIDE
= 110°C, θ = 150°C/W (SW)
J PACKAGE, 20-LEAD CERAMIC DIP
= 150°C, θ = 80°C/W (J)
T
JMAX
JA
T
JMAX
JA
OBSOLETE PACKAGE
Consider the N Package for Alternate Source
ORDER PART NUMBER
ORDER PART NUMBER
LTC1289BCN
LTC1289CCN
LTC1289BIJ
LTC1289CIJ
LTC1289BCJ
LTC1289CCJ
LTC1289BCSW
LTC1289CCSW
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
U
U W
The
●
denotes the specifications
CO VERTER A D ULTIPLEXER CHARACTERISTICS
which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 3)
A
LTC1289B
TYP
LTC1289C
TYP
PARAMETER
CONDITIONS
= 2.7V
MIN
MAX
MIN
MAX
UNITS
Offset Error
V
●
●
●
±1.5
±1.5
LSB
CC
(Note 4)
Linearity Error (INL)
Gain Error
V
= 2.7V
±0.5
±0.5
±0.5
±1.0
LSB
CC
(Notes 4 and 5)
V
= 2.7V
LSB
CC
(Note 4)
1289fb
2
LTC1289
U
U W
The
●
denotes the specifications
CO VERTER A D ULTIPLEXER CHARACTERISTICS
which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 3)
A
LTC1289B
TYP
LTC1289C
TYP
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
Minimum Resolution for
Which No Missing Codes are
Guaranteed
●
12
12
BITS
–
–
Analog and REF Input Range
(Note 7)
(V ) – 0.05V to V + 0.05V
(V ) – 0.05V to V + 0.05V
V
CC
CC
On Channel Leakage Current
(Note 8)
On Channel = 3V
Off Channel = 0V
On Channel = 0V
Off Channel = 3V
●
●
±1
±1
µA
±1
±1
µA
Off Channel Leakage Current
(Note 8)
On Channel = 3V
Off Channel = 0V
On Channel = 0V
Off Channel = 3V
●
●
±1
±1
±1
±1
µA
µA
AC CHARACTERISTICS
The
●
denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T = 25°C. (Note 3)
A
LTC1289B
LTC1289C
TYP
SYMBOL
PARAMETER
CONDITIONS
(Note 6)
MIN
MAX
1.0
UNITS
MHz
f
f
t
Shift Clock Frequency
A/D Clock Frequency
Delay time from CS↓ to D
0
SCLK
ACLK
ACC
(Note 6)
(Note 10)
2.0
MHz
Data Valid
(Note 9)
2
7
ACLK
Cycles
OUT
t
t
t
Analog Input Sample Time
Conversion Time
See Operating Sequence
SCLK
Cycles
SMPL
CONV
CYC
See Operating Sequence
52
ACLK
Cycles
Total Cycle Time
See Operating Sequence (Note 6)
12 SCLK +
56 ACLK
Cycles
t
t
t
t
t
t
t
t
t
t
Delay Time, SCLK↓ to D
Data Valid
See Test Circuits
See Test Circuits
See Test Circuits
(Note 6)
●
●
●
200
70
350
150
250
ns
ns
ns
ns
ns
ns
ns
ns
ns
dDO
dis
OUT
Delay Time, CS↑ to D
Hi-Z
OUT
Delay Time, 2nd ACLK↓ to D
Enabled
OUT
130
en
Hold Time, CS After Last SCLK↓
Hold Time, D After SCLK↑
0
hCS
hDI
hDO
f
(Note 6)
50
IN
Time Output Data Remains Valid After SCLK↓
50
40
40
D
D
Fall Time
See Test Circuits
See Test Circuits
(Note 6 and 9)
(Note 6 and 9)
●
●
100
100
OUT
Rise Time
r
OUT
Setup Time, D Stable Before SCLK↑
50
suDI
suCS
IN
Setup Time, CS↓ Before Clocking in
First Address Bit
2 ACLK Cycles
+ 180ns
t
CS High Time During Conversion
Input Capacitance
(Note 6)
52
ACLK
Cycles
WHCS
C
Analog Inputs On Channel
Analog Inputs Off Channel
Digital Inputs
100
5
5
pF
pF
pF
IN
1289fb
3
LTC1289
U
The
●
denotes the specifications which
D
A
ELECTRICAL CHARACTERISTICS
A
DC
DIGITAL
apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 3)
LTC1289B
LTC1289C
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output Voltage
V
V
V
V
V
= 3.6V
= 3.0V
●
●
●
●
2.1
V
V
IH
IL
CC
CC
IN
0.45
2.5
I
I
= V
µA
µA
V
IH
IL
CC
= 0V
–2.5
IN
V
= 3.0V
OH
CC
I = 20µA
O
●
●
2.90
2.85
O
I = 400µA
2.7
V
Low Level Output Voltage
High Z Output Leakage
V
= 3.0V
V
OL
CC
I = 20µA
0.05
0.10
O
I = 400µA
0.3
O
I
V
V
= V , CS High
= 0V, CS High
●
●
3
–3
µA
µA
OZ
OUT
OUT
CC
I
I
I
Output Source Current
Output Sink Current
V
V
= 0V
–10
9
mA
mA
SOURCE
SINK
CC
OUT
OUT
= V
CC
Positive Supply Current
CS High
CS High, Power Shutdown, ACLK Off
= 2.5V
●
●
1.5
1.0
5
10
mA
µA
I
I
Reference Current
V
●
●
10
1
50
50
µA
µA
REF
–
REF
Negative Supply Current
CS High
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 7: Two on-chip diodes are tied to each analog input which will
conduct for analog voltages one diode drop below GND or one diode drop
above V . Be careful during testing at low V levels, as high level analog
inputs can cause this input diode to conduct, especially at elevated
temperature, and cause errors for inputs near full scale. This spec allows
50mV forward bias of either diode. This means that as long as the analog
input does not exceed the supply voltage by more than 50mV, the output
code will be correct.
CC
CC
Note 2: All voltage values are with respect to ground with DGND, AGND
–
and REF wired together (unless otherwise noted).
–
Note 3: V = 3V, V + = 2.5V, V – = 0V, V = 0V for unipolar mode
CC
REF
REF
and –3V for bipolar mode, ACLK = 2.0MHz unless otherwise specified.
Note 4: These specs apply for both unipolar and bipolar modes. In bipolar
Note 8: Channel leakage current is measured after the channel selection.
Note 9: To minimize errors caused by noise at the chip select input, the
internal circuitry waits for two ACLK falling edges after a chip select falling
edge is detected before responding to control input signals. Therefore, no
attempt should be made to clock an address in or data out until the
minimum chip select set-up time has elasped. See Typical Peformance
mode, one LSB is equal to the bipolar input span (2V ) divided by 4096.
REF
For example, when V = 2.5V, 1LSB(bipolar) = 2(2.5)/4096 = 1.22mV.
REF
–
V
= –2.7V for bipolar mode.
Note 5: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Characteristics curves for additional information (t
vs V ).
suCS
CC
Note 10: Increased leakage currents at elevated temperatures cause the
Note 6: Recommended operating conditions.
S/H to droop, therefore it's recommended that f
≥ 125kHz at 85°C and
ACLK
f
≥ 15kHz at 25°C.
ACLK
1289fb
4
LTC1289
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Unadjusted Offset Voltage vs
Reference Voltage
Supply Current vs Supply Voltage
Supply Current vs Temperature
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
1.9
1.8
1.7
1.6
1.5
1.4
1.3
V
= 3V
ACLK = 2MHz
CC
ACLK = 2MHz
A
CC
V
= 3V
T
= 25°C
V
V
= 0.250mV
= 0.125mV
OS
OS
0
50
TEMPERATURE (°C)
–40 –25 –10
5
20 35
65 80 95
0
2.0
REFERENCE VOLTAGE (V)
2.5
3.0
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
SUPPLY VOLTAGE (V)
0.5
1.0
1.5
LTC 1289 TPC02
LTC1289 TPC03
LTC1289 TPC01
Change in Linearity vs Reference
Voltage
Change in Gain vs Reference
Voltage
Change in Offset vs Temperature
0.5
0.4
0.3
0.2
0.25
0.20
0.15
0.10
0.05
0
0.5
V
= 3V
V
= 3V
V
V
= 3V
CC
CC
CC
= 2.5V
REF
ACLK = 2MHz
0.4
0.3
–0.05
–0.10
–0.15
–0.20
0.2
0.1
0
0.1
0
–0.25
0
1.0
1.5
2.0
2.5
3.0
0.5
20
AMBIENT TEMPERATURE (°C)
0
0.5
1.0
1.5
2.0
2.5
3.0
–60 –40 –20
0
40 60 80 100
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
LTC1289 TPC04
LTC1289 TPC05
LTC1289 TPC06
Change in Linearity vs
Temperature
Maximum ACLK Frequency vs
Source Resistance
Change in Gain vs Temperature
0.5
0.5
3
2
1
0
V
V
= 3V
V
V
= 3V
V
V
T
= 3V
REF
= 25°C
A
CC
CC
CC
= 2.5V
= 2.5V
= 2.5V
REF
REF
ACLK = 2MHz
ACLK = 2MHz
0.4
0.3
0.4
0.3
V
R
+ INPUT
IN
SOURCE
–
INPUT
–
0.2
0.1
0
0.2
0.1
0
20
20
AMBIENT TEMPERATURE (°C)
–60 –40 –20
0
40 60 80 100
–60 –40 –20
0
40 60 80 100
100
1k
10 k
100k
AMBIENT TEMPERATURE (°C)
R
(Ω)
SOURCE
LTC1289 TPC07
LTC1289 TPC08
LTC1289 TPC09
* MAXIMUM ACLK FREQUENCY REPRESENTS THE ACLK FREQUENCY AT WHICH A 0.1LSB SHIFT
IN THE ERROR AT ANY CODE TRANSITION FROM ITS 2MHZ VALUE IS FIRST DETECTED.
1289fb
5
LTC1289
TYPICAL PERFOR A CE CHARACTERISTICS
U W
Supply Current (Power Shutdown)
vs Temperature
Maximum Filter Resistor vs
Cycle Time
Sample and Hold Acquisition
Time vs Source Resistance
100
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
10k
1k
V
V
A
= 2.5V
CC
= 25°C
ACLK OFF DURING
POWER SHUTDOWN
REF
= 3V
T
0V TO 2.5V INPUT STEP
R
+
SOURCE
V
+
–
IN
10
100
10
1
R
FILTER
V
+
–
IN
C
≥ 1µF
FILTER
1
1k
10k
–60
20
60 80
–40 –20
0
40
100
10
100
1000
10000
100
R + (Ω)
SOURCE
AMBIENT TEMPERATURE (°C)
CYCLE TIME (µs)
LTC1289 TPC11
LTC1289 TPC12
LTC1289 TPC10
Supply Current (Power Shutdown)
vs ACLK
Input Channel Leakage Current
vs Temperature
Noise Error vs Reference Voltage
1000
900
800
700
600
500
400
300
200
100
0
18
16
1.0
0.8
0.6
0.4
0.2
0
V
= 3V
CC
LTC1289 NOISE = 200µV
p-p
GUARANTEED
CMOS LOGIC SWINGS
14
12
10
8
ON CHANNEL
OFF CHANNEL
6
4
400
600
1000
200
800
–50 –30 –10 10 30 50 70 90 110 130
0
0.5
1.0
1.5
2.0
2.5
3.0
AMBIENT TEMPERATURE (°C)
ACLK FREQUENCY (kHZ)
REFERENCE VOLTAGE (V)
LTC1298 TPC13
LTC1289 TPC14
LTC1289 TPC15
Power Consumption with Power
t
vs Supply Voltage
Shutdown vs f
suCS
SAMPLE
10000
1000
100
300
250
V
V
= 3V
CC
T
= 25°C
A
= 2.5V
REF
ACLK = 2MHz
CMOS LOGIC SWINGS
THREE CONVERSIONS/CYCLE
200
150
100
50
0
10
1
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
SUPPLY VOLTAGE (V)
1
10
100
1000
10000
** MAXIMUM RFILTER REPRESENTS THE FILTER
RESISTOR VALUE AT WHICH A 0.1LSB CHANGE
IN FULL SCALE ERROR FROM ITS VALUE AT RFILTER
= 0 IS FIRST DETECTED.
f
(Hz)
SAMPLE
LTC1289 TPC16
LTC1289 TPC17
1289fb
6
LTC1289
U
U
U
PI FU CTIO S
CH0 – CH7 (Pins 1 – 8): Analog Inputs. The analog in-
puts must be free of noise with respect to AGND.
CS (Pin 15): Chip Select Input. A logic low on this input
enables data transfer.
COM (Pin 9): Common. Thecommonpindefinesthezero
reference point for all single-ended inputs. It must be free
of noise and is usually tied to the analog ground plane.
D
OUT (Pin 16): Digital Data Output. The A/D conversion
result is shifted out of this output.
DIN (Pin 17): Digital Input. The A/D configuration word is
shifted into this input.
DGND (Pin 10):Digital Ground. This is the ground for the
internal logic. Tie to the ground plane.
SCLK (Pin 18): Shift Clock. This clock synchronizes the
serial data transfer.
AGND (Pin 11):Analog Ground. AGND should be tied di-
rectly to the analog ground plane.
ACLK (Pin 19): A/D Conversion Clock. This clock con-
trols the A/D conversion process.
V– (Pin 12): Negative Supply. Tie V– to the most negative
potential in the circuit. (Ground in single supply applica-
tions.)
VCC (Pin 20): Positive Supply. This supply must be kept
free of noise and ripple by bypassing directly to the analog
ground plane.
REF–, REF+ (Pins 13,14) Reference Inputs. The reference
inputs must be kept free of noise with respect to AGND.
BLOCK DIAGRAM
18
SCLK
20
V
CC
INPUT
SHIFT
REGISTER
OUTPUT
16
17
D
D
SHIFT
OUT
IN
REGISTER
1
2
3
4
5
6
7
8
9
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
SAMPLE
AND
HOLD
COMP
ANALOG
INPUT MUX
12-BIT
SAR
12-BIT
CAPACITIVE
DAC
COM
19
15
ACLK
CS
CONTROL
AND
TIMING
10
11
AGND
12
–
14
+
13
–
V
REF
REF
DGND
LTC1289 BD
1289fb
7
LTC1289
TEST CIRCUITS
On and Off Channel Leakage Current
Voltage Waveforms for D
Delay Time, t
OUT dDO
3V
I
ON
A
SCLK
0.45V
ON CHANNEL
t
dDO
I
OFF
A
2.1V
D
OUT
0.6V
OFF
CHANNELS
LTC1289 TC03
POLARITY
LTC1283 TC01
Load Circuit for t , t and t
Voltage Waveforms for D
Rise and Fall Times, t ,t
OUT r f
dDO
r
f
2.1V
D
OUT
1.5V
0.6V
3k
t
t
r
f
D
TEST POINT
OUT
LTC1289 TC04
100pF
LTC1289 TC02
Load Circuit for t and t
dis
en
TEST POINT
3V t WAVEFORM 2, t
dis en
3k
D
OUT
t
WAVEFORM 1
dis
100pF
LTC1289 TC05
Voltage Waveforms for t and t
en
dis
1
2
ACLK
CS
2.1V
D
OUT
2.1V
0.6V
90%
10%
WAVEFORM 1
(SEE NOTE 1)
t
t
dis
en
D
OUT
WAVEFORM 2
(SEE NOTE 2)
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH CONDITIONS SUCH THAT THE OUTPUT IS HIGH
UNLESS DISABLED BY THE OUTPUT CONTROL.
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT
IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL.
LTC1289 TC06
1289fb
8
LTC1289
O U
W
U
PPLICATI
A
S I FOR ATIO
The LTC1289 is a data acquisition component which
contains the following functional blocks:
previous conversion is output on the DOUT line. At the end
of the data exchange the requested conversion begins and
CS should be brought high. After tCONV, the conversion is
complete and the results will be available on the next data
transfer cycle. As shown below, the result of a conversion
is delayed by one CS cycle from the input word requesting
it.
1. 12-bit successive approximation capacitive A/D
converter
2. Analog multiplexer (MUX)
3. Sample-and-hold (S/H)
4. Synchronous, full duplex serial interface
5. Control and timing logic
D
D
WORD 1
D
WORD 2
D
WORD 3
IN
IN
IN
IN
D
D
WORD 0
D
WORD 1
D
WORD 2
OUT
OUT
OUT
OUT
t
t
CONV
A/D
CONV
A/D
DIGITAL CONSIDERATIONS
Serial Interface
DATA
TRANSFER
DATA
TRANSFER
CONVERSION
CONVERSION
LTC1289 AI01
The LTC1289 communicates with microprocessors and
otherexternalcircuitryviaasynchronous, fullduplex, four
wire serial interface (see Operating Sequence). The shift
clock (SCLK) synchronizes the data transfer with each bit
being transmitted on the falling SCLK edge and captured
ontherisingSCLKedgeinbothtransmittingandreceiving
systems. The data is transmitted and received simulta-
neously (full duplex).
Input Data Word
The LTC1289 8-bit data word is clocked into the DIN input
on the first eight rising SCLK edges after chip select is
recognized. Further inputs on the DIN pin are then ignored
until the next CS cycle. The eight bits of the input word are
defined as follows:
UNIPOLAR/
BIPOLAR
WORD
LENGTH
Datatransferisinitiatedbyafallingchipselect(CS)signal.
After the falling CS is recognized, an 8-bit input word is
shifted into the DIN input which configures the LTC1289
for the next conversion. Simultaneously, the result of the
SGL/
DIFF
ODD/
SIGN
SELECT SELECT
UNI
MSBF
WL1
WL0
1
0
MSB-FIRST/
LSB-FIRST
MUX ADDRESS
LTC1289 AI02
Operating Sequence
(Example: Differential Inputs (CH3-CH2), Bipolar, MSB-First and 12-Bit Word Length)
t
CYC
1
2
3
4
5
6
7
8
9
10 11 12
SCLK
CS
DON'T CARE
t
t
CONV
SMPL
D
IN
DON'T CARE
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
D
OUT
(SB)
SHIFT CONFIGURATION
WORD IN
SHIFT A/D RESULT OUT AND
NEW CONFIGURATION WORD IN
LTC1289 AI03
1289fb
9
LTC1289
PPLICATI
O U
W
U
A
S I FOR ATIO
MUX Address
The first four bits of the input word assign the MUX
configuration for the requested conversion. For a given
channel selection, the converter will measure the voltage
between the two channels indicated by the + and – signs
in the selected row of Table 1. Note that in differential
mode (SGL/DIFF = 0) measurements are limited to four
adjacent input pairs with either polarity. In single-ended
mode, all input channels are measured with respect to
COM.
Table 1. Multiplexer Channel Selection
DIFFERENTIAL CHANNEL SELECTION
SINGLE-ENDED CHANNEL SELECTION
MUX ADDRESS
MUX ADDRESS
SGL/ ODD SELECT
SGL/ ODD SELECT
1
0
1
2
3
4
5
6
7
COM
0
2
3
4
5
6
7
SIGN
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
DIFF
DIFF SIGN
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
+
–
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
+
–
–
–
–
–
–
–
–
+
–
+
+
–
+
+
–
–
+
+
–
+
+
–
+
+
–
+
+
+
4 Differential
8 Single-Ended
Combinations of Differential and Single-Ended
CHANNEL
CHANNEL
CHANNEL
+
–
+
–
(
(
)
)
0
1
2
3
4
5
6
7
+
+
+
+
+
+
+
+
+
–
+
0,1
0,1
{
{
–
–
(
(
)
)
–
+
2,3
2,3
{
{
+
4
5
6
7
+
+
–
+
–
(
(
)
)
–
+
4,5
{
+
+
(
(
)
)
+
–
+
6,7
{
COM (
)
COM (
)
–
–
Changing the MUX Assignment “On the Fly”
+
–
+
–
–
4,5
6,7
5,4
{
{
{
{
+
6
7
+
+
COM (UNUSED)
COM ( )
–
1ST CONVERSION
2ND CONVERSION
LTC1289 AIF01
Figure 1. Examples of Multiplexer Options on the LTC1289
1289fb
10
LTC1289
O U
W
U
PPLICATI
A
S I FOR ATIO
Unipolar/Bipolar (UNI)
The fifth input bit (UNI) determines whether the conver-
sion will be unipolar or bipolar. When UNI is a logical one,
a unipolar conversion will be performed on the selected
input voltage. When UNI is a logical zero, a bipolar conver-
sion will result. The input span and code assignment for
each conversion type are shown in the figures below.
Unipolar Transfer Curve (UNI = 1)
Unipolar Output Code (UNI = 1)
INPUT VOLTAGE
1 1 1 1 1 1 1 1 1 1 1 1
(V
= 2.5V)
OUTPUT CODE
INPUT VOLTAGE
REF
1 1 1 1 1 1 1 1 1 1 1 0
2.4994V
1 1 1 1 1 1 1 1 1 1 1 1
V
V
– 1LSB
REF
REF
2.4988V
1 1 1 1 1 1 1 1 1 1 1 0
– 2LSB
•
•
•
•
•
•
•
•
•
•
•
•
0.0006V
0V
0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0
1LSB
0V
0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0
V
IN
LTC1289 AI04a
LTC1289 AI04b
Bipolar Output Code (UNI = 0)
INPUT VOLTAGE
INPUT VOLTAGE
(V = 2.5V)
(V
= 2.5V)
OUTPUT CODE
INPUT VOLTAGE
OUTPUT CODE
INPUT VOLTAGE
REF
REF
2.4988V
–0.0012V
0 1 1 1 1 1 1 1 1 1 1 1
V
REF
V
REF
– 1LSB
1 1 1 1 1 1 1 1 1 1 1 1
–1LSB
2.4976V
–0.0024V
0 1 1 1 1 1 1 1 1 1 1 0
– 2LSB
1 1 1 1 1 1 1 1 1 1 1 0
–2LSB
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0.0012V
0V
–2.4988V
–2.5000V
0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0
1LSB
0V
1 0 0 0 0 0 0 0 0 0 0 1 –(V ) + 1LSB
1 0 0 0 0 0 0 0 0 0 0 0
REF
– (V
)
REF
LTC1289 AI05a
Bipolar Transfer Curve (UNI = 0)
0 1 1 1 1 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1 1 1 1 0
•
•
•
0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0
V
IN
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 0
•
•
•
1 0 0 0 0 0 0 0 0 0 0 1
1 0 0 0 0 0 0 0 0 0 0 0
LTC1289 AI05b
1289fb
11
LTC1289
PPLICATI
O U
W
U
A
S I FOR ATIO
Example 2 (Diff.): IN–
Example 3 (Diff.): IN– – 2V
≤
IN+
≤
IN– + 2V
IN+ IN– + 2V.
The following discussion will demonstrate how the two
reference pins are to be used in conjunction with the
analog input multiplexer. In unipolar mode the input span
oftheA/DissetbythedifferenceinvoltageontheREF+ pin
and the REF– pin. In the bipolar mode the input span is
twice the difference in voltage on the REF+ pin and the
REF– pin. In the unipolar mode the lower value of the input
span is set by the voltage on the COM pin for single-ended
inputs and by the voltage on the minus input pin for
differential inputs. For the bipolar mode of operation the
voltage on the COM pin or the minus input pin sets the
center of the input span.
≤
≤
MSB-First/LSB-First Format (MSBF)
The output data of the LTC1289 is programmed for MSB-
first or LSB-first sequence using the MSBF bit. For MSB-
first output data, the input word clocked to the LTC1289
should always contain a logical one in the sixth bit location
(MSBF bit). Likewise for LSB-first output data the input
wordclockedtotheLTC1289shouldalwayscontainazero
in the MSBF bit location. The MSBF bit affects only the
order of the output data word. The order of the input word
is unaffected by this bit.
The upper and lower value of the input span can now be
summarized in the following table:
MSBF
0
1
OUTPUT FORMAT
LSB-First
INPUT
CONFIGURATION
UNIPOLAR MODE
BIPOLAR MODE
+
–
MSB-First
Single-Ended Lower Value COM
–(REF – REF ) + COM
+
–
+
–
LTC1289 AI06
Upper Value (REF – REF ) + COM (REF – REF ) + COM
–
+
–
–
Differential
Lower Value IN
Upper Value (REF – REF ) + IN
–(REF – REF ) + IN
Word Length (WL1, WL0) and Power Shutdown
+
–
–
+
–
–
(REF – REF ) + IN
The last two bits of the input word (WL1 and WL0)
program the output data word length and the power
shutdown feature of the LTC1289. Word lengths of 8, 12
or 16 bits can be selected according to the following table.
The refere–nce voltages REF+ and REF– can fall between
VCC and V , but the difference (REF+– REF–) must be less
than or equal to VCC. The input voltages must be less than
or equal to VCC and greater than or equal to V–.
The following examples are for a single-ended input con-
figuration.
Example 1: Let VCC = 3.3V, V– = 0V, REF+ = 3V, REF– = 1V
and COM = 0V. Unipolar mode of operation. The resulting
input span is 0V ≤ IN+ ≤ 2V.
WL1
WL0
OUTPUT WORD LENGTH
8 Bits
0
0
1
1
0
1
0
1
Power Shutdown
12 Bits
16 Bits
LTC1289 AI07
The WL1 and WL0 bits in a given DIN word control the
length of the present, not the next, DOUT word. WL1 and
WL0 are never “don’t cares” and must be set for the
correct DOUT word length even when a “dummy” DIN word
is sent. On any transfer cycle, the word length should be
made equal to the number of SCLK cycles sent by the
MPU. Power down will occur when WL1 = 0 and WL0 = 1
is selected. The previous result will be clocked out as a 10
bit word so a “dummy”conversion is required before
powering down the LTC1289. Conversions are resumed
once CS goes low or an SCLK is applied, if CS is already
low.
Example 2: The same conditions as Example 1 except
COM = 1V. The resulting input span is 1V ≤ IN+ ≤ 3V. Note
ifIN+ ≥3VtheresultingDOUTwordisall1’s.IfIN+ ≤1Vthen
the resulting DOUT word is all 0’s.
Example 3: Let VCC = 3.3V, V– = –3.3V, REF+ = 3V, REF–
= 1V and COM = 1V. Bipolar mode of operation. The
resulting input span is –1V ≤ IN+ ≤ 3V.
For differential input configurations with the same condi-
tions as in the above three examples the resulting input
spans are as follows:
Example 1 (Diff.): IN–
≤ ≤
IN+ IN– + 2V
1289fb
12
LTC1289
O U
W
U
PPLICATI
A
S I FOR ATIO
8-Bit Word Length
t
t
CONV
SMPL
CS
SCLK
1
D
THE LAST FOUR BITS
ARE TRUNCATED
OUT
B11 B10
(SB)
B9
B2
B8
B3
B7
B4
B6
B5
B5
B6
B4
B7
MSB-FIRST
D
OUT
LSB-FIRST
B0
B1
12-Bit Word Length
t
t
CONV
SMPL
CS
1
10
12
SCLK
(SB)
B11 B10 B9
D
OUT
MSB-FIRST
B8
B3
B7
B4
B6
B5
B5
B6
B4
B7
B3
B8
B2
B1
B0
(SB)
B9 B10 B11
D
OUT
LSB-FIRST
B0
B1
B2
16-Bit Word Length
t
t
CONV
SMPL
CS
SCLK
1
12
16
(SB)
B11 B10 B9
FILL
ZEROS
D
OUT
MSB-FIRST
B8
B3
B7
B4
B6
B5
B5
B6
B4
B7
B3
B8
B2
B1
B0
(SB)
B9 B10 B11
D
OUT
LSB-FIRST
B0
B1
B2
*
*
*
* IN UNIPOLAR MODE, THESE BITS ARE FILLED WITH ZEROS.
IN BIPOLAR MODE, THE SIGN BIT IS EXTENDED INTO THESE LOCATIONS.
LTC1289 AIF02
Figure 2. Data Output (D ) Timing with Different Word Lengths
OUT
1289fb
13
LTC1289
PPLICATI
O U
W
U
A
S I FOR ATIO
Deglitcher
CS Low During Conversion
In the normal mode of operation, CS is brought high
during the conversion time. The serial port ignores any
SCLK activity while CS is high. The LTC1289 will also
operate with CS low during the conversion. In this mode,
SCLK must remain low during the conversion as shown in
the following figure. After the conversion is complete, the
A deglitching circuit has been added to the Chip Select
input of the LTC1289 to minimize the effects of errors
causedbynoiseonthatinput.Thiscircuitignoreschanges
in state on the CS input that are shorter in duration than
oneACLKcycle.AfterachangeofstateontheCSinput,the
LTC1289 waits for two falling edge of the ACLK before
recognizing a valid chip select. One indication of CS
recognition is the DOUT line becoming active (leaving the
Hi-Z state). Note that the deglitching applies to both the
rising and falling CS edges.
D
OUT line will become active with the first output bit. Then
the data transfer can begin as normal.
Low CS Recognized Internally
High CS Recognized Internally
ACLK
ACLK
CS
CS
Hi-Z
Hi-Z
D
OUT
VALID OUTPUT
D
OUT
VALID OUTPUT
LTC1289 AI08
LTC1289 AI08a
SHIFT
MUX ADDRESS
IN
t
SMPL
SAMPLE ANALOG
INPUT
48 TO 52
ACLK CYC
SHIFT RESULT OUT
AND NEW ADDRESS IN
CS
SCLK
D
DON'T CARE
IN
D
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
OUT
LTC1289 AIF03
Figure 3. CS High During Conversion
SHIFT
MUX ADDRESS
IN
t
SMPL
SAMPLE ANALOG
INPUT
48 TO 52
ACLK CYC
SHIFT RESULT OUT
AND NEW ADDRESS IN
CS
SCLK MUST
REMAIN LOW
SCLK
D
DON'T CARE
IN
D
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
OUT
LTC1289 AIF04
Figure 4. CS Low During Conversion
1289fb
14
LTC1289
O U
W
U
PPLICATI
A
S I FOR ATIO
range. The code for these processors remains the same
and can be found in the LTC1290 datasheet or application
notes AN36A and AN36B.
Logic Levels
The logic level standards for this supply range have not
been well defined. What standards that do exist are not
universally accepted. The trip point on the logic inputs of
the LTC1289 is 0.28 × VCC. This makes the logic inputs
compatible with HC type logic levels and processors that
are specified at 3.3V. The output DOUT is also compatible
withtheabovestandards. Thefollowingsummarizessuch
levels.
Sharing the Serial Interface
The LTC1289 can share 3-wire serial interface with other
peripheral components or other LTC1289s (See Figure 5).
Inthiscase, theCSsignalsdecidewhichLTC1289isbeing
addressed by the MPU.
VOH (no load)
VCC - 0.1V
0.1V
0.9 × VCC
0.1 × VCC
0.7 × VCC
0.2 × VCC
ANALOG CONSIDERATIONS
1. Grounding
VOL (no load)
VOH
VOL
VIH
VIL
The LTC1289 should be used with an analog ground plane
and single point grounding techniques.
Pin11(AGND)shouldbetieddirectlytothisgroundplane.
The LTC1289 can be driven with 5V logic even when VCC
is at 3.3V. This is due to a unique input protection device
that is found on the LTC1289.
Pin 10 (DGND) can also be tied directly to this ground
plane because minimal digital noise is generated within
the chip itself.
Microprocessor Interfaces
Pin 20(V ) should be bypassed to the ground plane with a
CC
TheLTC1289caninterfacedirectly(withoutexternalhard-
ware) to most popular microprocessor (MPU) synchro-
nous serial formats. If an MPU without a serial interface is
used, then four of the MPU’s parallel port lines can be
programmed to form the serial link to the LTC1289. Many
of the popular MPU's can operate with 3V supplies. For
example the MC68HC11 is an MPU with a serial format
(SPI). Likewise parallel MPU’s that have the 8051 type
architecture are also capable of operating at this voltage
–
22µF tantalum with leads as short as possible. Pin 12 (V )
should be bypassed with a 0.1µF ceramic disk. For single
supply applications, V– can be tied to the ground plane.
Itisalsorecommendedthatpin13(REF–)andpin9(COM)
be tied directly to the ground plane. All analog inputs
should be referenced directly to the single point ground.
Digital inputs and outputs should be shielded from and/or
routed away from the reference and analog circuitry.
2
1
0
OUTPUT PORT
SERIAL DATA
3-WIRE SERIAL
3
INTERFACE TO OTHER
3
3
3
PERIPHERALS OR LTC1289s
MPU
CS
LTC1289
CS
LTC1289
CS
LTC1289
8 CHANNELS
8 CHANNELS
8 CHANNELS
LTC1289 AIF05
Figure 5. Several LTC1289s Sharing One 3-Wire Serial Interface
1289fb
15
LTC1289
PPLICATI
O U
W
U
A
S I FOR ATIO
Figure6showsanexampleofanidealgroundplanedesign
for a two-sided board. Of course, this much ground plane
will not always be possible, but users should strive to get
as close to this ideal as possible.
capacitor. The noise and ripple is approximately 0.5mV.
Figure 8b shows the response of a lithium battery with a 10µF
bypass capacitor. The noise and ripple is kept below 0.5mV.
2. Bypassing
For good performance, VCC must be free of noise and
ripple. Any changes in the VCC voltage with respect to
analog ground during a conversion cycle can induce
errorsornoiseintheoutputcode. VCC noiseandripplecan
be kept below 0.5mV by bypassing the VCC pin directly to
the analog ground plane with a 22µF tantalum capacitor
and leads as short as possible. The lead from the device to
the VCC supply should also be kept to a minimum and the
VCC supply should have a low output impedance such as
that obtained from a voltage regulator (e.g., LT1117).
Using a battery to power the LTC1289 will help reduce the
amount of bypass capacitance required on the VCC pin. A
battery placed close to the device will only require 10µF to
adequately bypass the supply pin. Figure 7 shows the
effect of poor VCC bypassing. Figure 8a shows the settling
of a LT1117 low dropout regulator with a 22µF bypass
HORIZONTAL: 10µs/DIV
Figure 7. Poor V Bypassing.
CC
Noise and Ripple Can Cause A/D Errors.
5V/DIV
CS
VCC
V
CC
0.5mV/DIV
0.1µF
22µF
TANTALUM
HORIZONTAL: 20µs/DIV
Figure 8a. LT1117 Regulator with 22µF Bypassing on V
CC
1
20
19
18
17
16
15
14
13
12
11
2
3
4
5
5V/DIV
CS
6
7
8
9
–
10
V
0.5mV/DIV
VCC
ANALOG
GROUND
PLANE
0.1µF
CERAMIC
DISK
LTC1289 AIF06
HORIZONTAL: 20µs/DIV
Figure 8b. Lithium Battery with 10µF Bypassing on V
Figure 6. Example Ground Plane for the LTC1289
CC
1289fb
16
LTC1289
O U
W
U
PPLICATI
A
S I FOR ATIO
the inputs. It is important that the overall RC time con-
stants be short enough to allow the analog inputs to
completely settle within the allotted time.
3. Analog Inputs
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1289 have
capacitive switching input current spikes. These current
spikes settle quickly and do not cause a problem. How-
ever, iflargesourceresistancesareusedorifslowsettling
opampsdrivetheinputs, caremustbetakentoinsurethat
the transients caused by the current spikes settle com-
pletely before the conversion begins.
“+” Input Settling
This input capacitor is switched onto the “+” input during
the sample phase (tSMPL, see Figure 10). The sample
phasestartsatthe4thSCLKcycleandlastsuntilthefalling
edge of the last SCLK (the 8th, 12th or 16th SCLK cycle
depending on the selected word length). The voltage on
the “+” input must settle completely within this sample
time. Minimizing RSOURCE+ and C1 will improve the input
settling time. If large “+” input source resistance must be
used, the sample time can be increased by using a slower
SCLK frequency or selecting a longer word length. With
the minimum possible sample time of 4µs, RSOURCE+ < 2k
and C1 < 20pF will provide adequate settling.
Source Resistance
The analog inputs of the LTC1289 look like a 100pF
capacitor (CIN) is series with a 1500Ω resistor (RON) as
shown in Figure 9. This value for RON is for VCC = 2.7V.
With larger supply voltages RON will be reduced. For
example with VCC = 2.7V and V–= –2.7V RON becomes
500Ω. C gets switched between the selected “+” and “–”
IN
inputs once during each conversion cycle. Large external
“–” Input Settling
source resistors and capacitances will slow the settling of
Attheendofthesamplephasetheinputcapacitorswitches
to the “–” input and the conversion starts (see Figure 10).
During the conversion, the “+” input voltage is effectively
“held” by the sample and hold and will not affect the
conversion result. However, it is critical that the “–” input
voltage be free of noise and settle completely during the
first four ACLK cycles of the conversion time. Minimizing
RSOURCE– and C2 will improve settling time. If large “–”
inputsourceresistancemustbeused, thetimeallowedfor
“+”
INPUT
R
+
–
SOURCE
LTC1289
V
+
–
IN
4TH SCLK
= 1.5k
C1
R
ON
“–”
INPUT
C
=
IN
100pF
LAST SCLK
R
SOURCE
V
IN
C2
LTC1289 AIF09
Figure 9. Analog Input Equivalent Circuit
“+” INPUT
SAMPLE
MUST SETTLE
HOLD
DURING THIS TIME
MUX ADDRESS
SHIFTED IN
t
SMPL
CS
• • •
• • •
• • •
LAST SCLK (8TH, 12TH OR 16TH DEPENDING ON WORK LENGTH)
SCLK
ACLK
1
2
3
4
1
2
3
4
• • •
1ST BIT TEST
“–” INPUT MUST SETTLE
DURING THIS TIME
“+” INPUT
“–” INPUT
1289 AIF10
Figure 10. “+” and “–” Input Settling Windows
1289fb
17
LTC1289
PPLICATI
O U
W
U
A
S I FOR ATIO
settling can be extended by using a slower ACLK fre-
rapidly (see typical curve of Input Channel Leakage Cur-
rent vs Temperature).
–
quency. At the maximum ACLK rate of 2MHz, RSOURCE
<
200
Ω and C2 < 20pF will provide adequate settling.
Noise Coupling Into Inputs
Input Op Amps
High source resistance input signals (>500Ω) are more
sensitive to coupling from external sources. It is prefer-
able to use channels near the center of the package (i.e.,
CH2-CH7) for signals which have the highest output
resistance because they are essentially shielded by the
When driving the analog inputs with an op amp it is
important that the op amp settle within the allowed time
(see Figure 10). Again, the “+” and “–” input sampling
times can be extended as described above to accommo-
date slower op amps. For single supply low voltage
applications the LT1006, LT1013 and LT1014 can be
made to settle well even with the minimum settling win-
dows of 4µs (“+” input) and 2µs (“–” input) which occur
at the maximum clock rates (ACLK = 2MHz and SCLK =
1MHz). Figures11and12showexamplesofadequateand
poor op amp settling. The LT1077, LT1078 or LT1079 can
beusedheretoreducepowerconsumption. PlacinganRC
network at the output of the op amps will improve the
settling response and also reduce the broadband noise.
RC Input Filtering
HORIZONTAL: 500ns/DIV
Figure 11. Adequate Settling of Op Amps Driving Analog Input
It is possible to filter the inputs with an RC network as
shown in Figure 13. For large values of CF (e.g., 1µF), the
capacitive input switching currents are averaged into a net
DC current. Therefore, a filter should be chosen with a
small resistor and large capacitor to prevent DC drops
across the resistor. The magnitude of the DC current is
approximately IDC = 100pF × VIN/tCYC and is roughly
proportional to VIN. When running at the minimum cycle
time of 40µs, the input current equals 6.3µA at VIN = 2.5V.
In this case, a filter resistor of 10Ω will cause 0.1LSB of
full-scale error. If a larger filter resistor must be used,
errors can be eliminated by increasing the cycle time as
shown in the typical curve of Maximum Filter Resistor vs
Cycle Time.
HORIZONTAL: 20µs/DIV
Figure 12. Poor Op Amp Settling Can Cause A/D Errors
Input Leakage Current
I
IDC
R
FILTER
“+”
LTC1289
“–”
V
IN
Input leakage currents can also create errors if the source
resistancegetstoolarge.Forinstance,themaximuminput
leakage specification of 1µA (at 85°C) flowing through a
source resistance of 1kΩ will cause a voltage drop of 1mV
or 1.6LSB with VREF = 2.5V. This error will be much
reduced at lower temperatures because leakage drops
C
FILTER
LTC1289 AIF13
Figure 13. RC Input Filtering
1289fb
18
LTC1289
O U
W
U
PPLICATI
A
S I FOR ATIO
pins on the package ends (DGND and CH0). Grounding
any unused inputs (especially the end pin, CH0) will also
reduce outside coupling into high source resistances.
a 60Hz signal on the “–” input to generate a 1/4LSB error
(150µV) with the converter running at ACLK = 2MHz, its
peak value would have to be 15mV.
4. Sample and Hold
Single-Ended Inputs
5. Reference Inputs
The voltage between the reference inputs of the LTC1289
defines the voltage span of the A/D converter. The refer-
ence inputs will have transient capacitive switching cur-
rents due to the switched capacitor conversion technique
(see Figure 14). During each bit test of the conversion
(every 4 ACLK cycles), a capacitive current spike will be
generated on the reference pins by the A/D. These current
spikes settle quickly and do not cause a problem. How-
ever, if slow settling circuitry is used to drive the reference
inputs, caremustbetakentoinsurethattransientscaused
by these current spikes settle completely during each bit
test of the conversion.
The LTC1289 provides a built-in sample and hold (S&H)
function for all signals acquired in the single-ended mode
(COM pin grounded). This sample and hold allows the
LTC1289 to convert rapidly varying signals (see typical
curveofS&HAcquisitionTimevsSourceResistance).The
input voltage is sampled during the tSMPL time as shown
in Figure 10. The sampling interval begins after the fourth
MUX address bit is shifted in and continues during the
remainder of the data transfer. On the falling edge of the
final SCLK, the S&H goes into hold mode and the conver-
sionbegins. Thevoltagewillbeheldoneitherthe8th, 12th
or 16th falling edge of the SCLK depending on the word
length selected.
When driving the reference inputs, two things should be
kept in mind:
1. Transients on the reference inputs caused by the
capacitive switching currents must settle completely
during each bit test (each 4 ACLK cycles). Figures 15
and 16 show examples of both adequate and poor
settling. Using a slower ACLK will allow more time for
the reference to settle. However, even at the maximum
ACLK rate of 2MHz most references and op amps can
be made to settle within the 2µs bit time. For example
an LT1019 used in the shunt mode with a 10µF bypass
capacitor will settle adequately. To minimize power an
LT1004-2.5 can be used with a 10µF bypass capacitor.
For lower value references the LT1004-1.2 with a 1µF
bypass capacitor can be used.
Differential Inputs
With differential inputs or when the COM pin is not tied to
ground, the A/D no longer converts just a single voltage
but rather the difference between two voltages. In these
cases, thevoltageontheselected“+”inputisstillsampled
and held and therefore may be rapidly time varing just as
in single ended mode. However, the voltage on the se-
lected “–” input must remain constant and be free of noise
and ripple throughout the conversion time. Otherwise, the
differencing operation may not be performed accurately.
The conversion time is 52 ACLK cycles. Therefore, a
change in the “–” input voltage during this interval can
cause conversion errors. For a sinusoidal voltage on the
“–” input this error would be:
+
REF
LTC1289
14
52
fACLK
EVERY 4 ACLK CYCLES
VERROR (MAX) = VPEAK × 2 × π × f(“–”) ×
R
OUT
R
ON
V
REF
8pF – 40pF
–
REF
13
Where f(“–”) is the frequency of the “–” input voltage,
VPEAK is its peak amplitude and fACLK is the frequency of
theACLK. InmostcasesVERROR willnotbesignificant. For
LTC1289 AIF14
Figure 14. Reference Input Equivalent Circuit
1289fb
19
LTC1289
PPLICATI
O U
W
U
A
S I FOR ATIO
Offset with Reduced VREF
The offset of the LTC1289 has a larger effect on the output
code when the A/D is operated with reduced reference
voltage. The offset (which is typically a fixed voltage)
becomes a larger fraction of an LSB as the size of the LSB
is reduced. The typical curve of Unadjusted Offset Error vs
Reference Voltage shows how offset in LSBs is related to
reference voltage for a typical value of VOS. For example,
a VOS of 0.1mV which is 0.2LSB with a 2.5V reference
becomes 0.4LSB with a 1.25V reference. If this offset is
unacceptable, it can be corrected digitally by the receiving
system or by offsetting the “–” input to the LTC1289.
HORIZONTAL: 1µs/DIV
Figure 15. Adequate Reference Settling
Noise with Reduced VREF
The total input referred noise of the LTC1289 can be
reduced to approximately 200µV peak-to-peak using a
ground plane, good bypassing, good layout techniques
and minimizing noise on the reference inputs. This noise
is insignificant with a 2.5V reference but will become a
larger fraction of an LSB as the size of the LSB is reduced.
The typical curve of Noise Error vs Reference Voltage
shows the LSB contribution of this 200µV of noise.
HORIZONTAL: 1µs/DIV
For operation with a 2.5 reference, the 200µV noise is only
0.32LSB peak-to-peak. In this case, the LTC1289 noise
will contribute virtually no uncertainty to the output code.
However, for reduced references, the noise may become
asignificantfractionofanLSBandcauseundesirablejitter
in the output code. For example, with a 1.25V reference,
this same 200µV noise is 0.64LSB peak-to-peak. This will
reduce the range of input voltages over which a stable
output code can be achieved by 0.64LSB. In this case
averaging readings may be necessary.
Figure 16. Poor Reference Settling Can Cause A/D Errors
2. It is recommended that REF– input be tied directly to
the analog ground plane. If REF– is biased at a voltage
otherthanground, thevoltagemustnotchangeduring
a conversion cycle. This voltage must also be free of
noise and ripple with respect to analog ground.
6. Reduced Reference Operation
The effective resolution of the LTC1289 can be increased
by reducing the input span of the converter. The LTC1289
exhibits good linearity and gain over a wide range of
referencevoltages(seetypicalcurvesofLinearityandGain
Error vs Reference Voltage). However, care must be taken
when operating at low values of VREF because of the
reduced LSB step size and the resulting higher accuracy
requirementplacedontheconverter. Thefollowingfactors
must be considered when operating at low VREF values:
This noise data was taken in a very clean setup. Any setup
induced noise (noise or ripple on VCC, VREF, VIN or V–) will
add to the internal noise. The lower the reference voltage
to be used, the more critical it becomes to have a clean,
noise-free setup.
1. Offset
2. Noise
1289fb
20
LTC1289
O U
W
U
PPLICATI
A
S I FOR ATIO
7. LTC1289 AC Characteristics
output spectrum of the LTC1289 is shown in Figures 17a
and 17b. The input (fIN) frequencies are 1kHz and 12kHz
with the sampling frequency (fS) at 25kHz. The SNR
obtained from the plot are 72.92dB and 72.23dB.
Two commonly used figures of merit for specifying the
dynamic performance of the A/D’s in digital signal pro-
cessing applications are the Signal-to-Noise Ratio (SNR)
and the “effective number of bits (ENOB).” SNR is defined
as the ratio of the RMS magnitude of the fundamental to
the RMS magnitude of all the nonfundamental signals up
to the Nyquist frequency (half the sampling frequency).
The theoretical maximum SNR for a sine wave input is
given by:
Rewriting the SNR expression it is possible to obtain the
equivalent resolution based on the SNR measurement.
SNR – 1.76dB
N =
6.02
This is the so-called effective number of bits (ENOB). For
the example shown in Figures 17a and 17b, N = 11.8 bits
and11.7bits,respectively.Figure18showsaplotofENOB
as a function of input frequency. The curve shows the
A/D’s ENOB remain in the range of 11.8 to 11.7 for input
frequencies up to fS/2
SNR = (6.02N + 1.76dB)
where N is the number of bits. Thus the SNR is a function
oftheresolutionoftheA/D.Foranideal12-bitA/DtheSNR
is equal to 74dB. A Fast Fourier Transform(FFT) plot of the
0
12
f
= 25kHz
S
–20
11
–40
–60
10
9
–80
8
7
6
–100
–120
–140
8
12
14
0
2
4
6
10
0
10
20
30
40
50
FREQUENCY (kHz)
FREQUENCY (kHz)
LTC1289 F17a
LTC1289 • AIF18
Figure 18. LTC1289 ENOB vs Input Frequency
Figure 17a. f = 1kHz, f = 25kHz, SNR = 72.92dB
IN
S
0
0
–20
–20
–40
–60
–40
–60
–80
–80
–100
–120
–100
–120
–140
–140
8
12
14
0
2
4
6
10
8
12
14
0
2
4
6
10
FREQUENCY (kHz)
FREQUENCY (kHz)
LTC1289 F19
LTC1289 F17b
Figure 19. f 1 = 2.6kHz, f 2 = 3.1kHz, f = 25kHz
Figure 17b. f = 12kHz, f = 25kHz, SNR = 72.23dB
IN
IN
S
IN
S
1289fb
21
LTC1289
PPLICATI
O U
W
U
A
S I FOR ATIO
isappliedtotheanalogMUXbeforepowerisappliedtothe
device. Power supply reversal occurs, for example, if the
input is pulled below V– then VCC will pull a diode drop
below ground which could cause the device not to power
up properly. Likewise, if the input is pulled above VCC then
V– will be pulled a diode drop above ground. If no inputs
are present on the MUX, the Schottky diodes are not
required if V– is applied first, then VCC.
Figure19showsanFFTplotoftheoutputspectrumfortwo
tones applied to the input of the A/D. Nonlinearities in the
A/D will cause distortion products at the sum and differ-
ence frequencies of the fundamentals and products of the
fundamentals. This is classically referred to as
intermodulation distortion (IMD).
8. Overvoltage Protection
Applying signals to the analog MUX that exceed the
positive or negative supply of the device will degrade the
accuracy of the A/D and possibly damage the device. For
example this condition would occur if a signal is applied to
the analog MUX before power is applied to the LTC1289.
Another example is the input source is operating from
different supplies of larger value than the LTC1289. These
conditions should be prevented either with proper supply
sequencing or by use of external circuitry to clamp or
current limit the input source. As shown in Figure 20, a
1kΩ resistor is enough to stand off ±15V (15mA for one
only channel). If more than one channel exceeds the
supplies than the following guidelines can be used. Limit
the current to 7mA per channel and 28mA for all channels.
Thismeansfourchannelscanhandle7mAofinputcurrent
each. Reducing the ACLK and SCLK frequencies from the
maximum of 2MHz and 1MHz, respectively (see Typical
Peformance Characteristics curves Maximum ACLK Fre-
quencyvsSourceResistanceandSampleandHoldAcqui-
sition Time vs Source Resistance) allows the use of larger
current limiting resistors. Use 1N4148 diode clamps from
the MUX inputs to VCC and V– if the value of the series
resistor will not allow the maximum clock speeds to be
usedorifanunknownsourceisusedtodrivetheLTC1289
MUX inputs.
Because a unique input protection structure is used on the
digital input pins, the signal levels on these pins can
exceed the device VCC without damaging the device.
1k
V
V
CC
3.3V
CH0
IN
22µF
LTC1289
–
V
–3.3V
0.1µF
DGND
AGND
LTC1289 AIF20
Figure 20. Overvoltage Protection for MUX
20
V
3.3V
CC
22µF
LTC1289
1N4148
14
+
REF
V
REF
LTC1289 AIF21
Figure 21.
How the various power supplies to the LTC1289 are
applied can also lead to overvoltage conditions. For single
supply operation (i.e., unipolar mode), if VCC and REF+ are
not tied together, then VCC should be turned on first, then
REF+. If this sequence cannot be met, connecting a diode
from REF+ to VCC is recommended (see Figure 21).
V
3.3V
22µF
CC
1N5817
LTC1289
–
V
–3.3V
1N5817
0.1µF
DGND
AGND
LTC1289 AIF22
For dual supplies (bipolar mode) placing two Schottky
diodes from VCC and V– to ground (Figure 22) will prevent
powersupplyreversalfromoccuringwhenaninputsource
Figure 22. Power Supply Reversal
1289fb
22
LTC1289
U
O
TYPICAL APPLICATI S
SNEAK-A-BITTM
A “Quick Look” Circuit for the LTC1289
The LTC1289’s unique ability to software select the polar-
ity of the differential inputs and the output word length is
used to achieve one more bit of resolution. Using the
circuit below with two conversions and some software, a
2’s complement 12-bit + sign word is returned to memory
inside the MPU. The MC68HC05C4 was chosen as an
example, however, any processor that operates at 3.3V
could be used.
Users can get a quick look at the function and timing of the
LTC1289 by using the following simple circuit. REF+ and
DIN are tied to VCC selecting a 3V input span, CH7 as a
single-ended input, unipolar mode, MSB-first format and
16-bitwordlength.ACLKisdrivenbyanexternalclockand
SCLK is driven by one half the clock rate. CS is driven at
1/128 the clock rate by the 74HC393 and DOUT outputs the
data. All other pins are tied to a ground plane. The output
data from the DOUT pin can be viewed on an oscilloscope
which is set up to trigger on the falling edge of CS.
Two 12-bit unipolar conversions are performed: the first
over a 0V to 2.5V span and the second over a 0V to –2.5V
span (by reversing the polarity of the inputs). The sign of
the input is determined by which of the two spans con-
tained it. Then the resulting number (ranging from –4095
to +4095 decimal) is converted to 2’s complement nota-
tion and stored in RAM.
A “Quick Look” Circuit for the LTC1289
3.0V
22µF
f
A1
V
CC
0.1µF
CLR1
1QA
A2
V
CHO
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
DGND
CC
CLR2
ACLK
SCLK
1QB 74HC393 2QA
f/2
1QC
1QD
GND
2QB
2QC
2QD
SNEAK-A-BIT Circuit
D
IN
D
OUT
22µF
+3.3V
LTC1289
2MHz
ACLK
CS
+
REF
f/128
–
V
REF
IN
LTC1289 TA02
V
CHO
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
DGND
1k
CC
–
V
CLOCK IN
2MHz MAX
ACLK
SCLK
MC68HC05C4
SCLK
AGND
OTHER CHANNELS
OR SNEAK-A-BIT
INPUTS
MOSI
MISO
CO
D
IN
TO
OSCILLOSCOPE
D
OUT
LTC1289
CS
V
IN
–2.5V TO +2.5V
+
REF
10µF
–
LTC1289 TA03
REF
–
V
LT1019
–2.5
Scope Trace of LTC1289 “Quick Look” Circuit
AGND
Showing A/D Output of 010101010101 (555
)
HEX
0.1µF
–3.3V
ACLK
SCLK
SNEAK-A-BIT
V
IN
2.5V
0V
2.5V
(+) CH6
(–) CH7
V
IN
CS
1ST CONVERSION
4096 STEPS
DOUT
SOFTWARE
1ST CONVERSION
0V
0V
8191 STEPS
(–) CH6
(+) CH7
2ND CONVERSION
4096 STEPS
DEGLITCHER
TIME
LSB
(B0)
FILLS
ZEROES
MSB
(B11)
–2.5V
–2.5V
2ND CONVERSION
VERTICAL: 5V/DIV
LTC1289 TA04
HORIZONTAL: 2µs/DIV
SNEAK-A-BIT is a trademark of Linear Technology Corp.
1289fb
23
LTC1289
U
O
TYPICAL APPLICATI S
SNEAK-A-BIT Code
SNEAK-A-BIT Code for the LTC1289 Using the MC68HC05C4
D
from LTC1289 in MC68HC05C4 RAM
MNEMONIC
DESCRIPTION
OUT
READ +/–: LDA #$7F
Load D word for LTC1289 into ACC
IN
Sign
JSR TRANSFER Read LTC1289 routine
LDA $60
STA $73
LDA $61
STA $74
RTS
Load MSBs from LTC1289 into ACC
Store MSBs in $73
Load LSBs from LTC1289 into ACC
Store LSBs in $74
Return
Location $77
Location $87
B12 B11 B10 B9 B8 B7 B6 B5
LSB
B4 B3 B2 B1 B0 filled with 0s
TRANSFER: BCLR 0, $02
CS goes low
STA $0C
Load D into SPI. Start transfer
Test status of SPIF
Loop to previous instruction if not done
Load contents of SPI data reg into ACC
Start next cycle
Store MSBs in $60
Test status of SPIF
Loop to previous instruction if not done
CS goes high
Load contents of SPI data reg into ACC
Store LSBs in $61
IN
D words for LTC1289
IN
LOOP 1:
LOOP 2:
TST $0B
BPL LOOP 1
LDA $0C
STA $0C
STA $60
TST $0B
BPL LOOP 2
BSET 0, $02
LDA $0C
STA $61
RTS
MUX Addr.
MSBF
UNI
Word
Length
(ODD/SIGN)
D 1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IN
Return
D 2
IN
1
0
CHK SIGN: LDA $73
ORA $74
BEQ MINUS
CLC
Load MSBs of +/– read into ACC
Or ACC (MSBs) with LSBs of +/– read
If result is 0 goto minus
Clear carry
D 3
IN
1
LTC1289 TA05
ROR $73
ROR $74
LDA $73
STA $77
LDA $74
STA $87
BRA END
Rotate right $73 through carry
Rotate right $74 through carry
Load MSBs of +/– read into ACC
Store MSBs in RAM locations $77
Load LSBs of +/– read into ACC
Store LSBs in RAM location $87
Goto end of routine
SNEAK-A-BIT Code for the LTC1289 Using the MC68HC05C4
MNEMONIC
DESCRIPTION
LDA #$50
STA $0A
LDA #$FF
STA $06
BSET 0, $02
JSR READ –/+
Configuration data for SPCR
Load configuration data into $0A
Configuration data for port C DDR
Load configuration data into port C DDR
Make sure CS is high
MINUS:
CLC
Clear carry
ROR $71
ROR $72
COM $71
COM $72
LDA $72
ADD #$01
STA $72
CLRA
Shift MSBs of –/+ read right
Shift LSBs of –/+ read right
1's complement of MSBs
1's complement of LSBs
Load LSBs into ACC
Add 1 to LSBs
Store ACC in $72
Clear ACC
Dummy read configures LTC1289 for
next read
Read CH6 with respect to CH7
Read CH7 with respect to CH6
JSR READ +/–
JSR READ –/+
JSR CHK SIGN Determines which reading has valid
data, converts to 2's complement and
stores in RAM
ADC $71
STA $71
STA $77
LDA $72
STA $87
RTS
Add with carry to MSBs. Result in ACC
Store ACC in $71
Store MSBs in RAM locations $77
Load LSBs in ACC
Store LSBs in RAM location $87
Return
READ –/+: LDA #$3F
Load D word for LTC1289 into ACC
IN
JSR TRANSFER Read LTC1289 routine
LDA $60
STA $71
LDA $61
STA $72
RTS
Load MSBs from LTC1289 in ACC
Store MSBs in $71
Load LSBs from LTC1289 in ACC
Store LSBs in $72
Return
END:
1289fb
24
LTC1289
U
O
TYPICAL APPLICATI S
Power Shutdown
To place the device in power shutdown the word length
bits are set to WL1 = 0 and WL0 = 1. The LTC1289 is
powered up on the next request for conversion and it's
ready to digitize an input signal immediately.
For battery-powered applications it is desirable to keep
power dissipation at a minimum. The LTC1289 can be
powered down when not in use reducing the supply
current from a nominal value of 1mA to typically 1µA (with
ACLKturnedoff).SeetheCurveforSupplyCurrent(Power
Shutdown)vsACLKifACLKcannotbeturnedoffwhenthe
LTC1289 is powered down. In this case the supply current
is proportional to the ACLK frequency and is independent
oftemperatureuntilitreachesthemagnitudeofthesupply
current attained with ACLK turned off.
Power Shutdown Timing Considerations
After power shutdown has been requested, the LTC1289
is powered up on the next request for a conversion. This
request can be initiated either by bringing CS low or by
starting the next cycle of SCLKs if CS is kept low (see
Figures 3 and 4). When the SCLK frequency is much
slower than the ACLK frequency a situation can arise
where the LTC1289 could power down and then prema-
turely power back up. Power shutdown begins at the
negative going edge of the 10th SCLK once it has been
requested. A dummy conversion is executed and the
LTC1289 waits for the next request for conversion. If the
SCLKshavenotfinishedoncetheLTC1289hasfinishedits
dummy conversion, it will recognize the next remaining
SCLKs as a request to start a conversion and power up the
LTC1289 (see Figure 23). To prevent this, bring either CS
high at the 19th SCLK (Figure 24) or clock out only 10
SCLKs (Figure 25) when power shutdown is requested.
As an example of how to use this feature let’s add this to
the previous application, SNEAK-A-BIT. After the CHK
SIGN subroutine call insert the following:
•
•
JSR CHK SIGN
Determines which reading has valid
data, converts to 2’s complement
and stores in RAM
JSR SHUTDOWN
LTC1289 power shutdown routine
The actual subroutine is:
SHUTDOWN: LDA #$3D
Load DIN word for
LTC1289 into ACC
JSR TRANSFER Read LTC1289 routine
RTS Return
CS
1
10
SCLK
POWER SHUTDOWN STARTS
DUMMY CONVERSION FINISHES AFTER 52 ACLK PERIODS
POWER UP LTC1289 TAF23
Figure 23. Power Shutdown Timing Problem
CS
POWER UP
1
10
SCLK
POWER SHUTDOWN STARTS
DUMMY CONVERSION FINISHES AFTER 52 ACLK PERIODS
LTC1289 TAF24
Figure 24. Power Shutdown Timing
1289fb
25
LTC1289
U
O
TYPICAL APPLICATI S
CS
POWER UP
1
10
SCLK
POWER SHUTDOWN STARTS
DUMMY CONVERSION FINISHES AFTER 52 ACLK PERIODS
LTC1289 TAF2
Figure 25. Power Shutdown Timing
U
PACKAGE DESCRIPTIO
J Package
20-Lead CERDIP (Narrow .300 Inch, Hermetic)
(Reference LTC DWG # 05-08-1110)
1.060
(26.924)
MAX
CORNER LEADS OPTION
(4 PLCS)
20
19
18
17
16
15
14
13
12
11
10
0.023 – 0.045
(0.584 – 1.143)
HALF LEAD
OPTION
0.025
(0.635)
RAD TYP
0.220 – 0.310
(5.588 – 7.874)
0.045 – 0.068
(1.143 – 1.727)
FULL LEAD
OPTION
1
2
3
4
5
6
7
8
9
0.005
(0.127)
MIN
0.200
(5.080)
MAX
0.300 BSC
(0.762 BSC)
0.015 – 0.060
(0.381 – 1.524)
0.008 – 0.018
(0.203 – 0.457)
0° – 15°
0.125
(3.175)
MIN
0.045 – 0.065
(1.143 – 1.651)
0.100
(2.54)
BSC
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE
OR TIN PLATE LEADS
0.014 – 0.026
J20 1298
(0.356 – 0.660)
OBSOLETE PACKAGE
1289fb
26
LTC1289
U
PACKAGE DESCRIPTIO
N Package
20-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
1.060*
(26.924)
MAX
20
19
18
17
16
15
14
13
12
11
10
.255 .015*
(6.477 0.381)
3
4
5
6
7
8
9
1
2
.300 – .325
(7.620 – 8.255)
.045 – .065
(1.143 – 1.651)
.125 – .145
(3.175 – 3.683)
.020
(0.508)
MIN
.065
(1.651)
TYP
.008 – .015
(0.203 – 0.381)
+.035
.325
.005
(0.127)
MIN
–.015
.120
(3.048)
MIN
.018 .003
(0.457 0.076)
.100
(2.54)
BSC
+0.889
8.255
(
)
–0.381
NOTE:
INCHES
MILLIMETERS
N20 0405
1. DIMENSIONS ARE
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
1289fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However,
no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the
interconnection of circuits as described herein will not infringe on existing patent rights.
27
LTC1289
U
PACKAGE DESCRIPTIO
SW Package
20-Lead Plastic Small Outline (Wide .300 Inch)
(Reference LTC DWG # 05-08-1620)
.050 BSC .045 ±.005
.030 ±.005
TYP
.496 – .512
(12.598 – 13.005)
NOTE 4
N
19 18
16
14 13 12 11
20
N
17
15
.325 ±.005
.420
MIN
.394 – .419
(10.007 – 10.643)
NOTE 3
1
2
3
N/2
N/2
RECOMMENDED SOLDER PAD LAYOUT
.291 – .299
(7.391 – 7.595)
NOTE 4
2
3
5
7
8
9
10
1
4
6
.037 – .045
.093 – .104
(2.362 – 2.642)
.010 – .029
(0.940 – 1.143)
× 45°
(0.254 – 0.737)
.005
(0.127)
RAD MIN
0° – 8° TYP
.050
(1.270)
BSC
.004 – .012
.009 – .013
(0.102 – 0.305)
NOTE 3
(0.229 – 0.330)
.014 – .019
.016 – .050
(0.406 – 1.270)
INCHES
(MILLIMETERS)
S20 (WIDE) 0502
(0.356 – 0.482)
TYP
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
4. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
RELATED PARTS
PART NUMBER
LTC1285/LTC1288
LTC1290
DESCRIPTION
COMMENTS
1-/2-Channel, 3V, Micropower 12-Bit ADC
8-Channel Configurable, 5V, 12-Bit ADC
Serial-Controlled 8-to-1 Analog Multiplexer
3V, 12-Bit, 200ksps Serial ADC
Autoshutdown, SO-8 Package
Pin-Compatible with LTC1289
LTC1391
Low R , Low Power, 16-Pin SO and SSOP Package
ON
LTC1401
15mW, Internal Reference, SO-8 Package
LTC1448
Dual 12-Bit V
Dual 12-Bit V
DACs in SO-8 Package
DACs in SO-16 Package
DACs
0.5LBS DNL, 3V to 5V Supply, Swings 0V to V
REF
OUT
OUT
LTC1454/LTC1454L
LTC1458/LTC1458L
LTC1594/LTC1598L
LTC1852/LTC1853
LTC2404/LTC2408
LTC2424/LTC2428
5V/3V, Buffered Rail-to-Rail Output, 0.5LSB DNL
5V/3V, Buffered Rail-to-Rail Output, 0.5LSB DNL
Low Power, Small Size
Quad 12-Bit V
OUT
4-/8-Channel, 3V Micropower 12-Bit ADC
10-Bit/12-Bit, 8-Channel, 400ksps ADCs
24-Bit, 4-/8-Channel, No Latency ∆Σ ADC
20-Bit, 4-/8-Channel, No Latency ∆Σ ADC
3V or 5V, Programmable MUX and Sequencer
4ppm INL, 10ppm Total Unadjusted Error, 200µA
1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2404/LTC2408
1289fb
LT 0506 REV B • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
●
●
© LINEAR TECHNOLOGY CORPORATION 1992
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
相关型号:
LTC1289BCJ#TRPBF
IC 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP20, 0.300 INCH, LEAD FREE, CERDIP-20, Analog to Digital Converter
Linear
LTC1289BCN#PBF
LTC1289 - 3 Volt Single Chip 12-Bit Data Acquisition System; Package: PDIP; Pins: 20; Temperature Range: 0°C to 70°C
Linear
LTC1289BCN#TR
IC 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP20, 0.300 INCH, PLASTIC, DIP-20, Analog to Digital Converter
Linear
LTC1289BCN#TRPBF
IC 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP20, 0.300 INCH, LEAD FREE, PLASTIC, DIP-20, Analog to Digital Converter
Linear
LTC1289BCSW#PBF
LTC1289 - 3 Volt Single Chip 12-Bit Data Acquisition System; Package: SO; Pins: 20; Temperature Range: 0°C to 70°C
Linear
LTC1289BCSW#TR
LTC1289 - 3 Volt Single Chip 12-Bit Data Acquisition System; Package: SO; Pins: 20; Temperature Range: 0°C to 70°C
Linear
LTC1289BCSW#TRPBF
LTC1289 - 3 Volt Single Chip 12-Bit Data Acquisition System; Package: SO; Pins: 20; Temperature Range: 0°C to 70°C
Linear
©2020 ICPDF网 联系我们和版权申明