LTC1266IS-5 [Linear]
Synchronous Regulator Controller for N- or P-Channel MOSFETs; 同步稳压器控制器为N或P沟道MOSFET
| 型号： | LTC1266IS-5 |
| 厂家： | 
Linear |
| 描述： | Synchronous Regulator Controller for N- or P-Channel MOSFETs |
| 文件： | 总20页 (文件大小：246K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1266
LTC1266-3.3/LTC1266-5
Synchronous Regulator
Controller for
N- or P-Channel MOSFETs
U
FEATURES
DESCRIPTIO
TheLTC®1266seriesisafamilyofsynchronousswitching
regulator controllers featuring automatic Burst ModeTM
operation to maintain high efficiencies at low output
currents. These devices drive external power MOSFETs at
switching frequencies up to 400kHz using a constant off-
time current mode architecture providing constant ripple
current in the inductor. They can drive either an N-channel
or a P-channel topside MOSFET.
■
Ultrahigh Efficiency: Over 95% Possible
■
Drives N-Channel MOSFET for High Current or
P-Channel MOSFET for Low Dropout
■
Pin Selectable Burst Mode Operation
■
1% Output Accuracy (LTC1266A)
■
Pin Selectable Phase of Topside Driver for Boost
or Step-Down Operation
■
Wide VIN Range: 3.5V to 20V
■
On-Chip Low-Battery Detector
The operating current level is user-programmable via an
external current sense resistor. Wide input supply range
allows operation from 3.5V to 18V (20V maximum).
Constantoff-timearchitectureprovideslowdropoutregu-
lation limited only by the RDS(ON) of the topside MOSFET
(when using the P-channel) and the resistance of the
inductor and current sense resistor.
■
High Efficiency Maintained Over Large Current Range
■
Low 170µA Standby Current at Light Loads
■
Current Mode Operation for Excellent Line and Load
Transient Response
■
Logic Controlled Micropower Shutdown: IQ < 40µA
■
Short-Circuit Protection
■
Synchronous Switching with Nonoverlaping Gate Drives
The LTC1266 series combines synchronous switching for
maximum efficiency at high currents with an automatic
low current operating mode, called Burst Modeoperation,
which reduces switching losses. Standby power is re-
duced to only 1mW at VIN = 5V (at IOUT = 0). Load currents
in Burst Mode operation are typically 0mA to 500mA.
■
Available in 16-Pin Narrow SO Package
U
APPLICATIO S
■
Notebook and Palmtop Computers
■
Portable Instruments
■
Cellular Telephones
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode is a trademark of Linear Technology Corporation.
■
DC Power Distribution Systems
■
GPS Systems
U
TYPICAL APPLICATIO
D2
MBR0530T1
LTC1266-3.3 Efficiency
V
IN
4V TO 9V
100
+
C
IN
LOW BAT OUT
V
= 5V
IN
100µF
×2
C
B
V
PWR V
IN
IN
0.1µF
100k
95
90
85
LOW BAT IN
LB
LB
OUT
IN
PINV
LTC1266-3.3
N-CHANNEL
Si9410
L*
R
SENSE
TDRIVE
5µH
0.02Ω
V
OUT
3.3V
5A
0V = NORMAL
+
–
SHDN
SENSE
>1.5V = SHUTDOWN
1000pF
I
TH
SENSE
R
C
C
T
+
C
OUT
470Ω
N-CHANNEL
Si9410
D1
C
T
BINH
SGND
BDRIVE
PGND
330µF
× 2
MBRS130LT3
180pF
C
C
3300pF
1266 TA01
80
*TOKO 919AS-4R7M
0.01
0.1
1
5
LOAD CURRENT (A)
1266 TA02
Figure 1. High Efficiency Step-Down Converter
1
LTC1266
LTC1266-3.3/LTC1266-5
W W
U W
U W
U
ABSOLUTE AXI U RATI GS
(Note 1)
PACKAGE/ORDER I FOR ATIO
TOP VIEW
ORDER PART
NUMBER
Input Supply Voltage (Pins 2, 5)............... 20V to –0.3V
Continuous Output Current (Pins 1, 16) .............. 50mA
Sense Voltages (Pins 8, 9) ....................... 13V to –0.3V
SHDN Voltage (Pin 11) ............................. 12V to –0.3V
PINV, BINH, LBIN (Pins 3, 4, 13)................20V to –0.3V
LBOUT Output Current ........................................... 12mA
Operating Ambient Temperature Range...... 0°C to 70°C
Industrial Temperature Range ................ –40°C to 85°C
Extended Commercial
Temperature Range ........................... –40°C to 85°C
Junction Temperature (Note 2)............................ 125°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
TDRIVE
BDRIVE
PGND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PWR V
IN
LTC1266CS
PINV
BINH
LB
OUT
LTC1266CS-3.3
LTC1266CS-5
LTC1266ACS
LTC1266IS
LB
IN
V
SGND
SHDN
IN
C
T
I
V
FB
(NC*)
TH
–
+
LTC1266IS-3.3
LTC1266IS-5
LTC1266AIS
SENSE
SENSE
S PACKAGE
16-LEAD PLASTIC SO
*FIXED OUTPUT VERSIONS
TJMAX = 125°C, θJA = 110°C/ W
Consult factory for Industrial and Military grade parts.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 10V, VSHDN = VBINH = 0V unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
= 9V, I
MIN
TYP
MAX
UNITS
V
Feedback Voltage
V
= 700mA, V
= V
= 14V,
FB
IN
LOAD
PINV
PWR
Topside Switch = N-Ch
LTC1266ACS
LTC1266CS
●
●
1.252 1.265 1.278
1.210 1.265 1.290
V
V
I
Feedback Current (LTC1266 Only)
Regulated Output Voltage
●
0.2
1
µA
FB
V
V
= 9V, I
= 700mA, V
= V
= 14V,
OUT
IN
LOAD
PINV
PWR
Topside Switch = N-Ch
LTC1266CS-3.3
LTC1266CS-5
●
●
3.23
4.90
3.33
5.05
3.43
5.20
V
V
Output Ripple (Burst Mode Operation)
Output Voltage Line Regulation
I
I
= 150mA
= 50mA
50
mV
P-P
LOAD
LOAD
V
V
∆V
OUT
= 0V, Topside Switch = P-Ch, V = 7V to 12V
– 40
– 40
0
0
40
40
mV
mV
PINV
PINV
IN
= V
, Topside Switch = N-Ch, V = 7V to 12V
PWR
IN
Output Voltage Load Regulation
LTC1266-3.3
5mA < I
< 2A, R
= 0.05Ω
SENSE
LOAD
Burst Mode Operation Enabled, V
= 0V
●
●
●
●
40
15
60
25
65
25
100
40
mV
mV
mV
mV
BINH
LTC1266-3.3
Burst Mode Operation Inhibited, V
= 2V
BINH
LTC1266-5
LTC1266-5
Burst Mode Operation Enabled, V
= 0V
BINH
Burst Mode Operation Inhibited, V
= 2V
BINH
I
I
V Pin DC Supply Current (Note 3)
IN
Q1
Q2
Normal Mode
Sleep Mode
Shutdown
3.5V < V < 18V
2.1
170
25
3.0
250
50
mA
µA
µA
IN
3.5V < V < 18V
IN
V
= 2.1V, 3.5V < V < 18V
IN
SHDN
PWR V DC Supply Current (Note 3)
IN
Normal Mode
Sleep Mode
Shutdown
3.5V < PWR V < 18V
20
1
1
40
5
5
µA
µA
µA
IN
3.5V < PWR V < 18V
IN
V
= 2.1V, 3.5V < PWR V < 18V
SHDN
IN
2
LTC1266
LTC1266-3.3/LTC1266-5
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 10V, VSHDN = VBINH = 0V unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Current Sense Threshold
(Burst Mode Operation Enabled)
LTC1266
V
= 0V
BINH
SENSE 1
–
V
V
V
V
V
V
= 3.3V, V = V /2.64 + 25mV (Forced)
25
155
25
mV
mV
mV
mV
mV
mV
SENSE
FB
FB
OUT
OUT
–
–
–
–
–
= 3.3V, V = V /2.64 – 25mV (Forced)
●
●
●
135
135
135
175
175
175
SENSE
SENSE
SENSE
SENSE
SENSE
LTC1266-3.3
LTC1266-5
= V
= V
= V
= V
+ 100mV (Forced)
– 100mV (Forced)
+ 100mV (Forced)
– 100mV (Forced)
OUT
OUT
OUT
OUT
155
25
155
V
Current Sense Threshold
(Burst Mode Operation Disabled)
LTC1266
V
= 2.1V
SENSE 2
BINH
–
V
V
V
V
V
V
= 3.3V, V = V /2.64 + 25mV (Forced)
–20
155
–20
155
–20
155
mV
mV
mV
mV
mV
mV
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
FB
FB
OUT
OUT
–
–
–
–
–
= 3.3V, V = V /2.64 – 25mV (Forced)
●
●
●
135
135
175
175
LTC1266-3.3
LTC1266-5
= V
= V
= V
= V
+ 100mV (Forced)
– 100mV (Forced)
+ 100mV (Forced)
– 100mV (Forced)
OUT
OUT
OUT
OUT
135
0.6
175
2
V
Shutdown Pin Threshold
0.8
1.2
0.2
1.2
V
µA
µA
V
SHDN
SHDN
PINV
I
I
Shutdown Pin Input Current
Phase Invert Pin Input Current
0V < V
0V < V
< 8V, V = 16V
5
SHDN
IN
< 18V, V = 18V
1
PINV
IN
V
Burst Mode Operation
Inhibit Pin Threshold
V
= 7V
IN
0.8
2
BINH
BINH
CT
I
I
Burst Mode Operation
Inhibit Pin Input Current
0V < V
< 18V, V = 18V
0.2
1
µA
BINH
IN
+
–
C Pin Discharge Current
T
V
V
= V
– 100mV, V
= V – 300mV
OUT
50
4
70
2
90
10
µA
µA
SENSE
OUT
SENSE
= 0V
OUT
t
t
Off-Time (Note 4)
Max On-Time
C = 390pF, I = 700mA
LOAD
5
6
µs
µs
ns
OFF
T
V
= 0V, V = 18V
60
MAX
OUT
IN
t , t
r
Driver Output Transition Times (Note 7) C = 3000pF (Pins 1, 16), V = 6V
100
200
f
L
IN
V
Output Voltage Clamp in
Burst Mode Operation Inhibit
LTC1266
V
= 2.1V
BINH
CLAMP
Measured at V
Measured at V
Measured at V
1.30
3.43
5.20
V
V
V
FB
SENSE
SENSE
–
–
LTC1266-3.3
LTC1266-5
V
Low-Battery Trip Point
V
V
= 5V
= 12V
1.14
1.17
1.25
1.30
1.35
1.42
V
V
LBTRIP
IN
IN
I
I
I
Max Leakage Current Into Pin 14
Max Sink Current Into Pin 14
Max Leakage Current Into Pin 13
V
V
V
= 18V, V = 2V
LBIN
25
8
200
nA
mA
µA
LBLEAK
LBSINK
LBIN
LBOUT
LBOUT
= 1V, V
= 0V, 2.5V < V < 18V
1
LBIN
IN
= 18V
0.2
1
LBIN
–40°C < TA < 85°C (Note 5), VIN = 10V, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS
= 9V, I
MIN
TYP
MAX
UNITS
V
Feedback Voltage
V
= 700mA, V
= V
= V
= 14V,
FB
IN
LOAD
PINV
PINV
PWR
Topside Switch = N-Ch
LTC1266AIS
LTC1266CS, LTC1266IS
1.246 1.265 1.290
1.210 1.265 1.290
V
V
V
Regulated Output Voltage
V
= 9V, I = 700mA, V
LOAD
= 14,
OUT
IN
PWR
Topside Switch = N-Ch
LTC1266CS-3.3, LTC1266IS-3.3
LTC1266CS-5, LTC1266IS-5
3.23
4.90
3.33
5.05
3.43
5.20
V
V
3
LTC1266
LTC1266-3.3/LTC1266-5
ELECTRICAL CHARACTERISTICS
–40°C < TA < 85°C (Note 5), VIN = 10V, unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I
V Pin DC Supply Current (Note 3)
IN
Q1
Normal Mode
Sleep Mode
Shutdown
3.5V < V < 18V
2.1
170
25
3.3
260
60
mA
µA
µA
IN
3.5V < V < 18V
IN
V
= 2.1V, 3.5V < V < 18V
IN
SHUTDOWN
I
PWR V DC Supply Current (Note 3)
Q2
IN
Normal Mode
Sleep Mode
Shutdown
3.5V < PWR V < 18V
20
1
1
50
7
7
µA
µA
µA
IN
3.5V < PWR V < 18V
IN
V
= 2.1V, 3.5V < PWR V < 18V
SHUTDOWN
IN
V
V
V
Current Sense Threshold
(Burst Mode Operation Enabled)
LTC1266CS, LTC1266IS
LTC1266CS
V
= 0V
SENSE1
BINH
–
V
SENSE
V
SENSE
V
SENSE
V
SENSE
V
SENSE
V
SENSE
= 3.3V, V = V /2.64 + 25mV (Forced)
25
mV
mV
mV
mV
mV
mV
FB
FB
OUT
OUT
–
–
–
–
–
= 3.3V, V = V /2.64 – 25mV (Forced)
135
135
155
155
25
180
190
LTC1266IS
= 3.3V, V = V /2.64 – 25mV (Forced)
FB OUT
LTC1266-3.3, LTC1266-5 (I and C)
LTC1266CS-3.3, LTC1266CS-5
LTC1266IS-3.3, LTC1266IS-5
= V
= V
= V
+ 100mV (Forced)
– 100mV (Forced)
– 100mV (Forced)
OUT
OUT
OUT
135
135
155
155
180
190
Current Sense Threshold
(Burst Mode Operation Disabled)
LTC1266CS, LTC1266IS
LTC1266CS
V
BINH
= 2.1V
SENSE2
–
V
SENSE
V
SENSE
V
SENSE
V
SENSE
V
SENSE
V
SENSE
3.3V, V = V /2.64 + 25mV (Forced)
–20
155
155
–20
155
155
mV
mV
mV
mV
mV
mV
FB
FB
OUT
OUT
–
–
–
–
–
3.3V, V = V /2.64 – 25mV (Forced)
130
130
185
195
LTC1266IS
3.3V, V = V /2.64 – 25mV (Forced)
FB OUT
LTC1266-3.3, LTC1266-5 (I and C)
LTC1266CS-3.3, LTC1266CS-5
LTC1266IS-3.3, LTC1266IS-5
= V
= V
= V
+ 100mV (Forced)
– 100mV (Forced)
– 100mV (Forced)
OUT
OUT
OUT
130
130
185
195
Shutdown Pin Threshold
C Grade
I Grade
0.55
0.50
0.8
0.8
2
2
V
V
SHDN
OFF
t
Off-Time (Note 4)
C = 390pF, I
= 700mA, C Grade
= 700mA, I Grade
3.8
3.8
5
5
6.5
7.0
µs
µs
T
LOAD
LOAD
C = 390pF, I
T
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 5: The LTC1266CS, LTC1266CS-3.3, LTC1266-5 and LTC1266ACS
are not tested and not quality assurance sampled at –40°C and 85°C.
These specifications are guaranteed by design and/or correlation. The
LTC1266IS, LTC1266IS-3.3, LTC1266IS-5 and LTC1266AIS are
guaranteed and tested over the –40°C to 85°C operating temperature
range.
Note 2: T is calculated from the ambient temperature T and power
J
A
dissipation P according to the following formula:
D
T = T + (P × 110°C/W)
J
A
D
Note 3: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.
Note 6: Unless otherwise noted the specifications for the LTC1266A are
the same as those for the LTC1266.
Note 4: In applications where R
is placed at ground potential, the off-
SENSE
Note 7: t and t are measured at 10% and 90% levels.
r
f
time increases approximately 40%.
4
LTC1266
LTC1266-3.3/LTC1266-5
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency vs Input Voltage
Line Regulation
Load Regulation
20
100
95
90
85
80
75
70
40
30
FIGURE 1 CIRCUIT
FIGURE 1 CIRCUIT
FIGURE 1 CIRCUIT
I
= 1A
LOAD
10
V
= 9V (Burst Mode
IN
OPERATION ENABLED)
I
= 2.5A
20
LOAD
0
–10
–20
–30
–40
–50
10
I
= 5A
LOAD
V
= 5V
IN
0
I
= 100mA
LOAD
–10
–20
–30
–40
V
= 5V (Burst Mode
IN
OPERATION INHIBITED)
3
5
6
7
8
9
0
1
2
3
4
5
4
3
4
5
6
7
8
9
INPUT VOLTAGE (V)
LOAD CURRENT (A)
INPUT VOLTAGE (V)
1266 G03
1266 G01
1266 G02
Efficiency vs Input Voltage
Line Regulation
Load Regulation
30
20
100
95
90
85
80
75
70
40
30
FIGURE 11 CIRCUIT
FIGURE 11 CIRCUIT
FIGURE 11 CIRCUIT
LOAD
I
= 1A
I
= 1A
LOAD
20
I
= 2.5A
10
LOAD
10
0
V
= 12V (Burst Mode
IN
OPERATION ENABLED)
I
= 100mA
0
LOAD
–10
–20
–30
–40
–10
–20
–30
–40
V
= 5V
IN
V
= 5V (Burst Mode
IN
OPERATION INHIBITED)
0
0.5
1.0
1.5
2.0
2.5
3.0
8
12
0
4
16
0
4
8
12
16
20
LOAD CURRENT (A)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
1266 G06
1266 G05
1266 G04
VIN DC Supply Current
Power VIN DC Supply Current
Supply Current in Shutdown
3.0
2.5
2.0
1.5
1.0
0.5
0
25
20
15
10
5
50
40
30
20
10
0
ACTIVE MODE
V
ACTIVE MODE
IN
SLEEP MODE
12
PWR V
IN
SLEEP MODE
0
0
4
8
16
20
0
4
8
12
16
20
0
5
10
INPUT VOLTAGE (V)
15
20
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
1266 G07
1266 G08
1266 G09
5
LTC1266
LTC1266-3.3/LTC1266-5
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Operating Frequency
vs (VIN – VOUT) Voltage
Current Sense Threshold Voltage
Off-Time vs Output Voltage
100
3.0
2.5
2.0
1.5
1.0
0.5
0
200
150
100
50
V
– = V
OUT
V
= 3.3V
SENSE
OUT
MAX THRESHOLD
0°C
80
60
40
70°C
25°C
MIN THRESHOLD (Burst Mode
OPERATION ENABLED)
MIN THRESHOLD (Burst Mode
OPERATION INHIBIT)
20
0
0
LTC1266-5
LTC1266-3.3
–50
3
4
2
6
20
60
TEMPERATURE (°C)
0
1
2
5
0
4
8
10 12 14 16
0
40
80
100
OUTPUT VOLTAGE (V)
(V – V ) VOLTAGE (V)
IN
OUT
1266 G10
1266 G11
1266 G12
U
U
U
PI FU CTIO S
TDRIVE (Pin 1): High Current Drive for Topside MOSFET.
This MOSFET can be either P-channel or N-channel, user
selectable by Pin 3. Voltage swing at this pin is from PWR
VIN to ground.
SENSE+ (Pin 9): The (+) Input to the Current Comparator.
A built-in offset between Pins 8 and 9 in conjunction with
RSENSE sets the current trip threshold.
VFB (Pin 10): For the LTC1266 adjustable version, Pin 10
serves as the feedback pin from an external resistive
divider used to set the output voltage. On LTC1266-3.3
and LTC1266-5 versions this pin is not used.
PWR VIN (Pin 2): Power Suppy for Drive Signals. Must be
closely decoupled to power ground (Pin 15).
PINV (Pin 3): Phase Invert. Sets the phase of the topside
drivertodriveeitheraP-channeloranN-channelMOSFET
as follows:
SHDN (Pin 11): When grounded, the LTC1266 series
operates normally. Pulling Pin 11 high holds both
MOSFETs off and puts the LTC1266 in micropower shut-
down mode. Requires CMOS logic signal with tr, tf < 1µs.
Should not be left floating.
P-channel: Pin 3 = 0V
N-channel: Pin 3 = PWR VIN
BINH (Pin 4): Burst Mode Operation Inhibit. A CMOS logic
high on this pin will disable the Burst Mode operation
feature forcing continuous operation down to zero load.
SGND (Pin 12): Small-Signal Ground. Must be routed
separately from other grounds to the (–) terminal of COUT
.
LBIN (Pin 13): Input to the Low-Battery Comparator. This
input is compared to an internal 1.25V reference.
VIN (Pin 5): Main Supply Pin.
CT (Pin6):ExternalCapacitor.CT fromPin4togroundsets
the operating frequency. The actual frequency is also
dependent on the input voltage.
LBOUT (Pin 14): Open Drain Output of the Low-Battery
Comparator. This pin will sink current when Pin 13 is
below 1.25V.
ITH (Pin 7): Gain Amplifier Decoupling Point. The current
comparator threshold increases with the Pin 7 voltage.
SENSE– (Pin 8): Connects to internal resistive divider
which sets the output voltage in LTC1266-3.3 and
LTC1266-5 versions. Pin 8 is also the (–) input for the
current comparator.
PGND (Pin 15): Driver Power Ground. Connects to source
of N-channel MOSFET and the (–) terminal of CIN.
BDRIVE (Pin 16): High Current Drive for Bottom
N-Channel MOSFET. Voltage swing at Pin 16 is from
ground to PWR VIN.
6
LTC1266
LTC1266-3.3/LTC1266-5
U
U
W
FU CTIO AL DIAGRA
Pin 10 Connection Shown for LTC1266-3.3 and LTC1266-5; Changes Create LTC1266
14 LB
–
OUT
LB
13
IN
LB
+
1.25V
REFERENCE
V
IN
PWR V
2
PINV
1
3
IN
TDRIVE
+
–
SIGNAL
GROUND
SENSE
9
SENSE
8
12
ADJUSTABLE
VERSION
V
FB
10
16 BDRIVE BINH
PGND
4
–
+
15
V
SLEEP
–
+
C
R
S
+
V
Q
TRIP
+
–
S
5pF
V
OS
–
+
–
–
V
TH2
V
TH1
13k
I
TH
7
G
T
100k
+
MAX
1.265V
ON-TIME
CONTROL
V
IN
OFF-TIME
CONTROL
–
ENABLE
PINV
SENSE
REFERENCE
6
SHDN 11
5 V
IN
V
FB
C
T
1266 FD
U
OPERATIO
The LTC1266 series uses a current mode, constant off-
time architecture to synchronously switch an external pair
of power MOSFETs. Operating frequency is set by an
external capacitor at the timing capacitor Pin 6.
During the switch ON cycle in continuous mode, current
comparator C monitors the voltage between Pins 8 and 9
connected across an external shunt in series with the
inductor. When the voltage across the shunt reaches its
threshold value, the topside driver output is switched to
turn off the topside MOFSET (Power VIN for P-channel or
ground for N-channel). The timing capacitor connected to
Pin 6 is now allowed to discharge at a rate determined by
the off-time controller. The discharge current is made
proportional to the output voltage (measured by Pin 8) to
model the inductor current, which decays at a rate which
is also proportional to the output voltage. While the timing
capacitor is discharging, the bottom-side drive output is
switched to power VIN to turn on the bottom-side
N-channel MOSFET.
The output voltage is sensed by an internal voltage divider
connectedtoSENSE–,Pin8,(LTC1266-3.3andLTC1266-
5) or external divider returned to VFB, Pin 10, (LTC1266).
A voltage comparator V, and a gain block G, compare the
divided output voltage with a reference voltage of 1.265V.
Tooptimizeefficiency,theLTC1266 automaticallyswitches
between two modes of operation, burst and continuous.
The voltage comparator is the primary control element
when the device is in Burst Modeoperation, while the gain
block controls the output voltage in continuous mode.
7
LTC1266
LTC1266-3.3/LTC1266-5
U
OPERATIO
When the voltage on the timing capacitor has discharged
To prevent both the external MOSFETs from ever being
past VTH1, comparator T trips, setting the flip-flop. This turned on at the same time, feedback is incorporated to
causes the bottom-side output to switch off and the sense the state of the driver output pins. Before the
topside output to switch on (ground for P-channel and bottom-side drive output can turn on, the topside output
Power V for N-channel). The cycle then repeats.
must be off. Likewise, the topside output is prevented
from turning on while the bottom-side drive output is
still on.
IN
Astheloadcurrentincreases,theoutputvoltagedecreases
slightly. This causes the output of the gain stage (Pin 7) to
increase the current comparator threshold, thus tracking
the load current.
The LTC1266 has two select pins which provide the user
with choice of topside switch and with the option of
inhibiting Burst Mode operation. The phase select pin
allows the user to choose whether the topside MOSFET
isaP-channeloranN-channel. Thephaseselectpindoes
two things: sets the proper phase of the drive signal (ON
= Power VIN for N-channel and ON = 0V for P-channel)
and also sets an upper limit for the on-time (60µs) when
set to the N-channel. The on-time limit ensures proper
start-up when used in a single supply bootstrap circuit
configuration(seeApplicationsInformation).InP-channel
mode there is no on-time limit and thus, in dropout, the
P-channel MOSFET is turned on continuously (100%
duty cycle).
The sequence of events for Burst Modeoperation is very
similartocontinuousoperationwiththecycleinterrupted
by the voltage comparator. When the output voltage is at
orabovethedesiredregulatedvalue,thetopsideMOSFET
is held off by comparator V and the timing capacitor
continues to discharge below VTH1. When the timing
capacitor discharges past VTH2, voltage comparator S
trips, causing the internal sleep line to go low and the
bottom-side MOSFET to turn off.
The circuit now enters sleep mode with both power
MOSFETs turned off. In sleep mode, a majority of the
circuitry is turned off, dropping the quiescent current
from 2.1mA to 170µA. The load current is now being
supplied from the output capacitor. When the output
voltage has dropped by the amount of hysteresis in
comparator V, the topside MOSFET is again turned on
and this process repeats.
The Burst Mode operation inhibit (BINH, Pin 4) allows the
Burst Mode operation to be disabled by applying a CMOS
logic high to this pin. With Burst Mode operation disabled,
theLTC1266willremainincontinuousmodedowntozero
load. Burst Mode operation is disabled by allowing the
lower current threshold limit to go below zero so that the
voltagecomparatorwillnevertrip.Thevoltagecomparator
trip point is also raised up so that it will not be tripped by
transients. It is still active to provide a voltage clamp to
prevent the output from overshooting.
To avoid the operation of the current loop interfering with
Burst Modeoperation, a built-in offset VOS is incorporated
in the gain stage. This prevents the current comparator
threshold from increasing until the output voltage has
dropped below a minimum threshold.
W U U
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APPLICATIO S I FOR ATIO
One of the three basic LTC1266 application circuits is step is the selection of R
. Once R
is known,
SENSE
SENSE
shown in Figure 1. This circuit uses an N-channel C and L can be chosen. Next, the power MOSFETs and
T
topside driver and a single supply. The other two circuit D1 are selected. Finally, C and C
are selected and
IN
OUT
configurations (see Typical Applications) use an the loop is compensated. Using an N-channel topside
N-channel topside driver and dual supply, and a switch, input voltages are limited to a maximum of
P-channel topside driver. Selections of other external about 15V. With a P-channel, the input voltage may be
componentsaredrivenbytheloadrequirementandare as high as 20V.
the same for all three circuit configurations. The first
8
LTC1266
LTC1266-3.3/LTC1266-5
W U U
APPLICATIO S I FOR ATIO
U
RSENSE Selection for Output Current
15mV
SENSE
I
≈
BURST
R
RSENSE is chosen based on the required output current.
The LTC1266 series current comparator has a threshold
range which extends from a minimum of 25mV/RSENSE
(when Burst Mode operation is enabled) to a maximum of
155mV/RSENSE. The current comparator threshold sets
the peak of the inductor ripple current, yielding a maxi-
mum output current IMAX equal to the peak value less half
the peak-to-peak ripple current. For proper Burst Mode
operation, IRIPPLE(P-P) must be less than or equal to the
minimum current comparator threshold.
155mV
I
=
SC(PK)
R
SENSE
The LTC1266 series automatically extends tOFF during a
short circuit to allow sufficient time for the inductor
current to decay between switch cycles. The resulting
ripple current causes the average short-circuit current
I
SC(AVG) to be reduced to approximately IMAX.
L and CT Selection for Operating Frequency
Since efficiency generally increases with ripple current,
the maximum allowable ripple current is assumed, i.e.,
IRIPPLE(P-P) = 25mV/RSENSE (see CT and L Selection for
Operating Frequency). Solving for RSENSE and allowing
a margin for variations in the LTC1266 series and
external component values yields:
The LTC1266 series uses a constant off-time architecture
with tOFF determined by an external timing capacitor CT.
Each time the topside MOSFET switch turns on, the
voltage on CT is reset to approximately 3.3V. During the
off-time, CT is discharged by a current which is propor-
tional to VOUT. The voltage on CT is analogous to the
current in inductor L, which likewise decays at a rate
proportional to VOUT. Thus the inductor value must track
the timing capacitor value.
100mV
MAX
R
=
SENSE
I
A graph for selecting R
vs maximum output
SENSE
current is given in Figure 2.
The value of CT is calculated from the desired continuous
mode operating frequency, f:
100
1
C =
T
4
75
50
25
0
2.6 • 10 • f
assumes VIN = 2VOUT, (Figure 1 circuit).
A graph for selecting CT vs frequency including the effects
of input voltage is given in Figure 3.
800
V
= 3.3V
OUT
0
2
4
6
8
10
600
400
200
0
MAXIMUM OUTPUT CURRENT (A)
1266 F02
Figure 2. Selecting RSENSE
V
= 12V
IN
The load current, below which Burst Mode operation
commences, (I ), and the peak short-circuit cur-
V
= 5V
100
IN
BURST
rent, (I
), both track I
. Once R
has been
SC(PK)
MAX
SENSE
chosen, I
and I
can be predicted from the
BURST
SC(PK)
0
400
500
200
300
FREQUENCY (kHz)
following:
1266 F03
Figure 3. Timing Capacitor Value
9
LTC1266
LTC1266-3.3/LTC1266-5
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APPLICATIO S I FOR ATIO
As the operating frequency is increased the gate charge
losses will be higher, reducing efficiency (see Efficiency
Considerations). The complete expression for operating
frequency of the circuit in Figure 1 is given by:
current is exceeded. This results in an abrupt increase in
inductor ripple current and consequent output voltage
ripple which can cause Burst Modeoperation to be falsely
triggered. Do not allow the core to saturate!
Kool Mµis a very good, low loss core material for toroids,
with a “soft” saturation characteristic. Molypermalloy is
slightly more efficient at high (>200kHz) switching fre-
quency. Toroids are very space efficient, especially when
you can use several layers of wire. Because they generally
lack a bobbin, mounting is more difficult. However, new
designs for surface mount are available from Coiltronics
and Beckman Industrial Corp. which do not increase the
height significantly.
V
V
1
OFF
OUT
f =
1 –
)
)
t
IN
where:
V
V
REG
OUT
4
t
= 1.3 • 10 • C •
T
OFF
)
)
VREG is the desired output voltage (i.e., 5V, 3.3V). VOUT is the
measured output voltage. Thus VREG/VOUT = 1 in regulation.
Once the frequency has been set by C , the inductor L
T
Power MOSFET and D1 Selection
must be chosen to provide no more than 25mV/R
SENSE
of peak-to-peak inductor ripple current. This results in
a minimum required inductor value of:
Two external power MOSFETs must be selected for use
withtheLTC1266series:eitheraP-channelMOSFEToran
N-channel MOSFET for the main switch and an N-channel
MOSFET for the synchronous switch. The main selection
criteria for the power MOSFETs are the type of MOSFET,
5
L
= 5.1 • 10 • R
• C • V
SENSE T REG
MIN
As the inductor value is increased from the minimum
value, the ESR requirements for the output capacitor
are eased at the expense of efficiency. If too small an
inductorisused,theinductorcurrentwilldecreasepast
zero and change polarity. A consequence of this is that
the LTC1266 series may not enter Burst Modeoperation
and efficiency will be slightly degraded at low currents.
threshold voltage VGS(TH) and on-resistance RDS(ON)
.
The cost and maximum output current determine the type
of MOSFET for the topside switch. N-channel MOSFETs
have the advantage of lower cost and lower RDS(ON) at the
expense of slightly increased circuit complexity. For lower
current applications where the losses due to RDS(ON) are
small, a P-channel MOSFET is recommended due to the
lower circuit complexity. However, at load currents in
excess of 3A where the RDS(ON) becomes a significant
portion of the total power loss, an N-channel is strongly
recommended to maximize efficiency.
Inductor Core Selection
Once the minimum value for L is known, the type of
inductor must be selected. The highest efficiency will be
obtained using ferrite, Kool Mµ® on molypermalloy (MPP)
cores. Lower cost powdered iron cores provide suitable
performance but cut efficiency by 3% to 7%. Actual core
loss is independent of core size for a fixed inductor value,
but it is very dependent on inductance selected. As induc-
tance increases, core losses go down. Unfortunately,
increased inductance requires more turns of wire and
therefore copper losses increase.
ThemaximumoutputcurrentIMAX determinestheRDS(ON)
requirement for the two MOSFETs. When the LTC1266
series is operating in continuous mode, the simplifying
assumption can be made that one of the two MOSFETs is
always conducting the average load current. The duty
cycles for the two MOSFETs are given by:
Ferrite designs have very low core loss, so design goals
can concentrate on copper loss and preventing satura-
tion. Ferrite core material saturates “hard,” which means
that inductance collapses abruptly when the peak design
V
V
OUT
Topside Duty Cycle =
IN
V – V
IN
OUT
Bottom-Side Duty Cycle =
V
IN
Kool Mµ is a registered trademark of Magnetics, Inc.
10
LTC1266
LTC1266-3.3/LTC1266-5
W U U
APPLICATIO S I FOR ATIO
U
From the duty cycles, the required RDS(ON) for each
MOSFET can be derived:
This formula has a maximum at VIN = 2VOUT, where
RMS = IOUT/2. This simple worst-case condition is com-
I
monly used for design because even significant devia-
tions do not offer much relief. Note that capacitor
manufacturer’s ripple current ratings are often based on
only 2000 hours of life. This makes it advisable to further
derate the capacitor, or to choose a capacitor rated at a
higher temperature than required. Always consult the
manufacturer if there is any question. An additional 0.1µF
to 1µF ceramic capacitor is also required on Power VIN
(Pin 2) for high frequency decoupling.
V • P
IN
T
TS R
BS R
=
=
DS(ON)
2
V
• I
• (1 + δ )
OUT MAX
T
V • P
IN
B
DS(ON)
2
(V – V ) • I
• (1 + δ )
B
IN
OUT
MAX
where PT and PB are the allowable power dissipations and
δT andδB arethetemperaturedependenciesofRDS(ON).PT
and PB will be determined by efficiency and/or thermal
requirements(seeEfficiencyConsiderations).ForaMOSFET,
(1 + δ) is generally given in the form of a normalized
RDS(ON) vs temperature curve, but δPCH = 0.007/°C and
δNCH = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
The selection of COUT is driven by the required ESR. The
ESR of COUT must be less than twice the value of RSENSE
for proper operation of the LTC1266 series:
COUT Required ESR < 2RSENSE
Optimum efficiency is obtained by making the ESR equal
to RSENSE. As the ESR is increased up to 2RSENSE, the
efficiency degrades by less than 1%. If the ESR is greater
than 2RSENSE, the voltage ripple on the output capacitor
willprematurelytriggerBurstModeoperation, resultingin
disruption of continuous mode and an efficiency hit which
can be several percent. If Burst Mode operation is dis-
abled, the ESR requirement can be relaxed and is limited
only by the allowable output voltage ripple.
The minimum input voltage determines whether standard
thresholdorlogic-levelthresholdMOSFETsmustbeused.
For VIN > 8V, standard threshold MOSFETs (VGS(TH) < 4V)
may be used. If VIN is expected to drop below 8V, logic-
level threshold MOSFETs (VGS(TH) < 2.5V) are strongly
recommended. The LTC1266 series Power VIN must al-
ways be less than the absolute maximum VGS ratings for
the MOSFETs.
The Schottky diode D1 shown in Figure 1 only conducts
during the deadtime between the conduction of the two
powerMOSFETs. D1’ssolepurposeinlifeistopreventthe
body diode of the bottom-side MOSFET from turning on
and storing charge during the deadtime, which could cost
as much as 1% in efficiency (although there are no other
harmful effects if D1 is omitted). Therefore, D1 should be
selected for a forward voltage of less than 0.7V when
Manufacturers such as Nichicon and United Chemicon
should be considered for high performance capacitors.
The OS-CON semiconductor dielectric capacitor available
fromSanyohasthelowestESR/sizeratioofanyaluminum
electrolytic at a somewhat higher price. Once the ESR
requirement for COUT has been met, the RMS current
rating generally far exceeds the IRIPPLE(P-P) requirement.
In surface mount applications multiple capacitors may
havetobeparalleledtomeetthecapacitance,ESRorRMS
current handling requirements of the application. An
excellent choice is the AVX TPS series of surface mount
tantalums.
conducting IMAX
.
CIN and COUT Selection
In continuous mode, the current through the topside
MOSFET is a square wave of duty cycle VOUT/VIN. To
prevent large voltage transients, a low ESR (Effective
Series Resistance) input capacitor sized for the maximum
RMS current must be used. The maximum RMS capacitor
current is given by:
Atlowsupplyvoltages, aminimumcapacitanceatC
OUT
is needed to prevent an abnormal low frequency oper-
ating mode (see Figure 4). When C is made too
OUT
small, the output ripple at low frequencies will be large
enough to trip the voltage comparator. This causes
BurstModeoperationtobeactivatedwhentheLTC1266
1/2
[V (V – V )]
OUT IN
OUT
C Required I
≈ I
MAX
IN
RMS
V
IN
11
LTC1266
LTC1266-3.3/LTC1266-5
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APPLICATIO S I FOR ATIO
1000
Driving N-Channel Topside MOSFETs
L = 50µH
SENSE
R
= 0.02Ω
DrivinganN-channeltopsideMOSFET(PINV,Pin3,tiedto
PWR VIN) is a little trickier than driving a P-channel since
the gate voltage must be positive with respect to the
source to turn it on, which means that the gate voltage
must be higher than VIN. This requires either a second
supplyatleastVGS(ON) aboveVIN orabootstrappingcircuit
to boost the VIN to the proper level. The easiest method is
using a higher supply (see Figure 14) but if one is not
available, the bootstrap method can be used at the ex-
pense of an additional diode (see Figure 1). The bootstrap
works by charging the bootstrap capacitor to VIN during
the off-time. During the on-time, the bottom plate of the
capacitor is pulled up to VIN so that the voltage at Pin 2 is
now twice VIN (plus any ringing on the switch node).
800
600
L = 25µH
SENSE
R
= 0.02Ω
400
200
0
L = 50µH
SENSE
R
= 0.05Ω
0
1
2
3
4
5
(V – V ) VOLTAGE (V)
IN
OUT
1266 F04
Figure 4. Minimum Value of COUT
series would normally be in continuous operation. The
outputremainsinregulationatalltimes. Thisminimum
capacitance requirement may be relaxed if Burst Mode
operation is disabled.
Since the maximum allowable voltage at Pin 2 is 20V, the
Figure 1 bootstrap circuit limits VIN to less than 10V. A
higher VIN can be achieved if the bootstrap capacitor is
charged to a voltage less than VIN, in which case
N-Channel vs P-Channel MOSFETs
VIN(MAX) = 20 – VCAP
.
The LTC1266 has the capability to drive either an
N-channel or a P-channel topside switch to give the user
more flexibility. N-channel MOSFETs are superior in per-
formance to P-channel due to their lower RDS(ON) and
lower gate capacitance and are typically less expensive;
however, they do have a slightly more complicated gate
drive requirement and a more limited input voltage range
(see following sections).
N-channel mode, internal circuitry limits the maximum
on-time to 60µs to guarantee start-up of the bootstrap
circuit. This maximum on-time reduces the maximum
duty cycle to:
60µs
60µs + t
Max Duty Cycle =
OFF
which slightly increases the minimum input voltage at
which dropout occurs. However, because of the superior
on-conductance of the N-channel, the dropout perfor-
mance of an all N-channel regulator is still better (see
Figure5)evenwiththedutycyclelimitation, exceptatlight
loads.
Driving P-Channel Topside MOSFETs
The P-channel topside switch circuit configuration is the
most straightforward due to the requirement of only one
supply voltage level. This is due to the negative gate
threshold of the P-channel MOSFET which allows the
MOSFET to be switched on and off by swinging the gate
between VIN and ground. The phase invert (Pin 3) is tied
to ground to choose this operating mode. Normally, the
converter input (VIN) is connected to the LTC1266 supply
Pins 2 and 5 and can go as high as 20V. Pin 2 supplies the
high frequency current pulses to switch the MOSFETs and
should be decoupled with a 0.1µF to 1µF ceramic capaci-
tor. Pin 5 supplies most of the quiescent power to the rest
of the chip.
Low-Battery Comparator
The LTC1266 has an on-chip low-battery comparator
which can be used to sense a low-battery condition when
implemented as shown in Figure 6. The resistor divider
R1, R2 sets the comparator trip point as follows:
R2
R1
V
TRIP
= 1.25 1 +
)
)
12
LTC1266
LTC1266-3.3/LTC1266-5
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W
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APPLICATIO S I FOR ATIO
100
90
600
V
OUT
= 3.3V
Burst Mode OPERATION
ENABLED
TOPSIDE
N-CHANNEL WITH
CHARGE PUMP
500
400
300
200
100
0
TOPSIDE
P-CHANNEL
80
Burst Mode OPERATION
INHIBITED
70
TOPSIDE N-CHANNEL
WITH POWER V = 12V
IN
60
0.01
0.1
1
5
0
1
2
3
4
5
LOAD CURRENT (A)
LOAD CURRENT
1266 F07
1266 F05
Figure 5. Comparison of Dropout Performance
Figure 7. Effect of Disabling Burst Mode Operation on Efficiency
V
IN
2. If the load is never expected to drop low enough to
benefit from the efficiency advantages of Burst Mode
operation, theoutputcapacitorESRandminimumcapaci-
tancerequirements(whichmayfalselytriggerBurstMode
operation if not met) can be relaxed if Burst Mode opera-
tion is disabled.
R2
LTC1266
–
LB
OUT
R1
+
1.25V
REFERENCE
3. If an auxiliary winding is used. Disabling Burst Mode
operation guarantees switching independent of the load
on the primary. This allows power to be taken from the
auxiliary winding independently.
1266 F06
Figure 6. Low-Battery Comparator
Thedivideddownvoltageatthe“–”inputtothecomparator
is compared to an internal 1.25V reference. This reference
is separate from the 1.265V reference used by the voltage
comparator and current comparator for regulation and is
notdisabledbytheshutdownpin,thereforethelow-battery
detection is operational even when the rest of the chip is
shut down. The comparator is functional down to an input
voltage of 2.5V. Thus, the output will provide a valid state
even when the rest of the chip does not have sufficient
voltage to operate. For best performance, the value of the
pull-up resistor should be high enough that the output is
pulled down to ground when sinking 200µA or less.
4. Tighter load regulation (< 1%).
Burst Mode operation is disabled by applying a CMOS
logichighvoltage(>2.1V)toPin4.Whenitisdisabled, the
voltagecomparatorlimitisraisedhighenoughsothatitno
longer is involved in regulation; however it is still active
and is useful as a voltage clamp to keep the output from
overshooting.
Note that since the inductor current must reverse to
regulate the output at zero load when Burst Mode opera-
tion is disabled, the minimum inductance (LMIN) specified
during Inductor Core Selection is no longer applicable.
Suppressing Burst Mode Operation
Checking Transient Response
Normally, enablingBurstModeoperationisdesireddueto
its superior efficiency at low load currents (see Figure 7).
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in DC (resistive) load
current. When a load step occurs, VOUT shifts by an
amount equal to ∆ILOAD (ESR), where ESR is the effective
series resistance of COUT. ∆ILOAD also begins to charge or
However, in certain applications it may be desirable to
inhibit this feature. Some reasons for doing so are:
1. To eliminate audible noise from certain types of induc-
tors at light loads.
13
LTC1266
LTC1266-3.3/LTC1266-5
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APPLICATIO S I FOR ATIO
discharge COUT until the regulator loop adapts to the
current change and returns VOUT to its steady-state value.
During this recovery time VOUT can be monitored for
overshoot or ringing which would indicate a stability
problem. The Pin 7 external components shown in the
Figure 1 circuit will prove adequate compensation for
most applications.
15nC. This results in IGATECHG = 6mA in 200kHz continu-
ousoperationfora2%to3%typicalmid-currentlosswith
VIN = 5V.
Note that the gate charge loss increases directly with
both input voltage and operating frequency. This is the
principal reason why the highest efficiency circuits oper-
ateatmoderatefrequencies.Furthermore,itarguesagainst
using larger MOSFETs than necessary to control I2R
losses, since overkill can cost efficiency as well as money!
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:
3. I2R losses are easily predicted from the DC resistances
of the MOSFET, inductor and current shunt. In continuous
mode the average output current flows through L and
RSENSE, but is “chopped” between the topside and bot-
tom-side MOSFETs. If the two MOSFETs have approxi-
mately the same RDS(ON), then the resistance of one
MOSFET can simply be summed with the resistances of L
and RSENSE to obtain I2R losses. For example, if each
RDS(ON) = 0.05Ω, RL = 0.05Ω and RSENSE = 0.02Ω, then
thetotalresistanceis0.12Ω.Thisresultsinlossesranging
from3.5%to15%astheoutputcurrentincreasesfrom1A
to 5A. I2R losses cause the efficiency to roll off at high
output currents.
% Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc., are the individual losses as a percent-
ageofinputpower. (Forhighefficiencycircuits, onlysmall
errors are incurred by expressing losses as a percentage
of output power).
Although all dissipative elements in the circuit produce
losses, threemainsourcesusuallyaccountformostofthe
losses in LTC1266 series circuits: 1) LTC1266 DC bias
current, 2)MOSFETgatechargecurrentand3)I2Rlosses.
Figure 8 shows how the efficiency losses in a typical
LTC1266 series regulator end up being apportioned. The
gate charge loss is responsible for the majority of the
efficiency lost in the mid-current region. If Burst Mode
operation was not employed at low currents, the gate
charge loss alone would cause efficiency to drop to
unacceptable levels (see Figure 7). With Burst Mode
1. The DC supply current is the current which flows into
VIN (Pin 2). For VIN = 10V the LTC1266 DC supply current
is 170µA for no load, and increases proportionally with
load up to a constant 2.1mA after the LTC1266 series has
entered continuous mode. Because the DC bias current is
drawn from VIN, the resulting loss increases with input
voltage. For VIN = 5V the DC bias losses are generally less
than 1% for load currents over 30mA. However, at very
low load currents the DC bias current accounts for nearly
all of the loss.
100
2
I R
GATE CHARGE
95
LTC1266 I
Q
90
85
80
2. MOSFETgatechargecurrentresultsfromswitchingthe
gate capacitance of the power MOSFETs. Each time a
MOSFET gate is switched from low to high to low again, a
packetofchargedQmovesfromPowerVIN toground. The
resulting dQ/dt is a current flowing into Power VIN (Pin 5)
which is typically much larger than the DC supply current.
In continuous mode, IGATECHG = f (QN + QP). The typical
gate charge for a 0.05Ω N-channel power MOSFET is
0.01
0.03
0.1
I
0.3
(A)
1
5
OUT
1266 F08
Figure 8. Efficiency Loss
14
LTC1266
LTC1266-3.3/LTC1266-5
W U U
APPLICATIO S I FOR ATIO
U
operation, the DC supply current represents the lone (and
unavoidable) loss component which continues to become
a higher percentage as output current is reduced. As
expected the I2R losses dominate at high load currents.
CIN will require an RMS current rating of at least 2.5A at
temperature and COUT will require an ESR of 0.02Ω for
optimum efficiency.
NowallowVIN todroptoitsminimumvalue.Theminimum
VIN can be calculated from the maximum duty cycle and
voltage drop across the topside FET,
Other losses including CIN and COUT ESR dissipative
losses, MOSFET switching losses, Schottky conduction
losses during deadtime and inductor core losses, gener-
ally account for less than 2% total additional loss.
VOUT + ILOAD • (RDS(ON) + RL + RSENSE
)
VMIN
=
= 4.0V
DMAX
Design Example
At this lower input voltage, the operating frequency de-
creasesandthetopsideFETwillbeconductingmostofthe
time, causing the power dissipation to increase.
At dropout,
As a design example, assume VIN = 5V (nominal),
VOUT = 3.3V, IMAX = 5A and f = 200kHz; RSENSE, CT and L
can immediately be calculated:
RSENSE = 100mV/5 = 0.02Ω
1
fMIN
=
= 16kHz
tON (MAX) + tOFF
tOFF = (1/200kHz) • [1 – (3.3/5)] = 1.7µs
CT = 1.7µs/(1.3 • 104) = 130pF
LMIN = 5.1 • 105 • 0.02Ω • 130pF • 3.3V = 5µH
PT = I2LOAD • RDS(ON) • (1 + δT) • DMAX
This last step is necessary to assure that the power
dissipation and junction temperature of the topside FET
are not exceeded.
Assume that the MOSFET dissipations are to be limited to
PT = PB = 2W.
If TA = 40°C and the thermal resistance of each MOSFET
is 50°C/W, then the junction temperatures will be 140°C
and δT = δB = 0.60. The required RDS(ON) for each MOSFET
can now be calculated:
These last calculations assume that Power VIN is high
enough to keep the topside FET fully turned on at dropout,
as would be the case with the Figure 11circuit. If this isn’t
true (as with the Figure 1 circuit) the RDS(ON) will increase
which in turn increases VMIN and PT.
5(2)
3.3(5) (1.60)
TS R
=
=
= 0.076Ω
= 0.147Ω
DS(ON)
DS(ON)
2
Adjustable Applications
When an output voltage other than 3.3V or 5V is required,
the LTC1266 adjustable version is used with an external
resistive divider from VOUT to VFB, Pin 10. The regulated
voltage is determined by:
5(2)
BS R
2
1.7(5) (1.60)
The topside FET requirement can be met by an N-channel
Si9410DY which has an RDS(ON) of about 0.04Ω at
VGS = 5V. The bottom-side FET requirement is exceeded
byanSi9410DY. Notethatthemoststringentrequirement
for the bottom-side MOSFET is with VOUT = 0 (i.e., short
circuit). During a continuous short circuit, the worst-case
dissipation rises to:
R2
V
OUT
= 1.265 1 +
)
)
R1
To prevent stray pickup a 100pF capacitor is suggested
across R1 located close to the LTC1266.
For Figure 1 applications with VOUT below 2V, or when
RSENSE is moved to ground, the current sense comparator
inputsoperatenearground. Whenthecurrentcomparator
is operated at less than 2V common mode, the off-time
increases approximately 40%, requiring the use of a
smaller timing capacitor CT.
PB = ISC(AVG)2 • RDS(ON) • (1 + δB)
With the 0.02Ω sense resistor, ISC(AVG) ≈ 6A will result,
increasingthe0.04Ωbottom-sideFETdissipationto2.3W.
15
LTC1266
LTC1266-3.3/LTC1266-5
W U U
U
APPLICATIO S I FOR ATIO
Troubleshooting Hints
If Pin 6 is observed falling to ground at high output
currents,itindicatespoordecouplingorimproperground-
ing. Refer to the Board Layout Checklist.
Since efficiency is critical to LTC1266 series applications,
it is very important to verify that the circuit is functioning
correctly in both continuous and Burst Mode operation.
The waveform to monitor is the voltage on the timing
capacitor, Pin 6.
Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1266 series. These items are also illustrated graphi-
cally in the layout diagram of Figure 10. Check the follow-
ing in your layout:
In continuous mode (ILOAD > IBURST) the voltage on the CT
pin should be a sawtooth with a 0.9VP-P swing. This
voltage should never dip below 2V as shown in Figure 9a.
When load currents are low (ILOAD < IBURST) Burst Mode
operation should occur with the CT pin waveform periodi-
cally falling to ground for periods of time as shown in
Figure 9b.
1. Are the signal and power grounds segregated? The
LTC1266 signal ground (Pin 12) must return to the (–)
plate of C . The power ground returns to the source
OUT
of the bottom-side MOSFET, anode of the Schottky
3.3V
diode and (–) plate of C , which should have as short
IN
lead lengths as possible.
0V
2. Does the LTC1266 SENSE– (Pin 8) connect to a point
close to RSENSE and the (+) plate of COUT? In adjustable
applications, the resistive divider R1 and R2 must be
connected between the (+) plate of COUT and signal
ground.
(a) Continuous Mode Operation
3.3V
0V
1266 F09
(b) Burst Mode Operation
Figure 9. CT Waveforms
+
BOLD LINES INDICATE
HIGH CURRENT PATHS
V
IN
C
IN
C
B
+
L
–
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
BDRIVE
PGND
TDRIVE
PWR V
PINV
IN
LB
OUT
LTC1266
LB
BINH
IN
SGND
SHDN
V
IN
–
SHUTDOWN
C
T
R1
R2
C
OUT
V
OUT
+
V
I
FB
TH
C
3300pF
470Ω
T
R
SENSE
+
–
SENSE
SENSE
+
OUTPUT DIVIDER REQUIRED WITH
ADJUSTABLE VERSION ONLY
1000pF
1266 F10
Figure 10. LTC1266 Layout Diagram (See Layout Checklist)
16
LTC1266
LTC1266-3.3/LTC1266-5
W U U
U
APPLICATIO S I FOR ATIO
3. Are the SENSE– and SENSE+ leads routed together with
minimum PC trace spacing? The 1000pF capacitor be-
tween Pins 8 and 9 should be as close as possible to the
LTC1266.
helpful in eliminating instabilities at high input voltage and
high output loads.
6. Is the shutdown (Pin 11) actively pulled to ground
during normal operation? The shutdown pin is high im-
pedance and must not be allowed to float. The select (Pins
3 and 4) are also high impedance and must be tied high or
low depending on the application.
4. Does the (+) plate of CIN connect to the source of the
topside MOSFET as closely as possible? This capacitor
provides the AC current to the topside MOSFET.
5. A 0.1µF to 1µF decoupling capacitor connected be-
tweenVIN (Pin5)andgroundisoptional, butissometimes
U
TYPICAL APPLICATIO S
(Layout Assist Schematics)
V
IN
≈3.9V TO 18V
(V
IN(MIN)
= 3.5V IF I
< 0.8A)
LOAD
Si9430DY
Si9410DY
+
C
IN
100µF
25V
1
16
15
14
13
12
11
10
9
D1
MBRS140T3
TDRIVE
BDRIVE
PGND
1µF
+
2
3
4
5
6
7
8
PWR V
PINV
IN
LB
OUT
BINH
BINH
LB
IN
LTC1266-3.3
V
IN
C
T
SGND
SHDN
NC
SHUTDOWN
L*
10µH
C
OUT
220µF
10V
I
TH
C
T
220pF
C
C
+
3300pF
–
+
SENSE
SENSE
2 ×
R
C
1000pF
R
SENSE
1k
0.033Ω
V
OUT
3.3V
3A
*DALE LPT4545-A001
COILTRONICS CTX10-4
1266 F11
Figure 11. Low Dropout, 3.3V/3A High Efficiency Regulator
17
LTC1266
LTC1266-3.3/LTC1266-5
U
TYPICAL APPLICATIO S
(Layout Assist Schematics)
V
IN
4.3V TO 10V
= 3.5V IF I
D1
L*
20µH
(V
< 100mA
LOAD
IN (MIN)
MBRS130LT3
0.068Ω
V
OUT
12V/500mA
+
C
IN
0.1µF
127k
1%
100µF
+
20V
C
0UT
Si9410DY
100µF
1M
1M
20V
1
2
3
4
5
6
7
8
16
15k
1%
TDRIVE
BDRIVE
PGND
100pF
15
14
13
12
11
10
9
PWR V
PINV
IN
LB
Q1**
OUT
LB
IN
BINH
BINH
LTC1266
SGND
SHDN
V
C
I
IN
T
V
FB
TH
C
C
T
C
+
200pF
3300pF
–
SENSE
SENSE
R
C
180k
100k
1N4148
1000pF
1k
SHUTDOWN
*DALE LPT4545-A002
COILTRONICS CTX20-4
**MMBT2222ALT1
1266 F12
Figure 12. 5V to 12V/500mA High Efficiency Boost Regulator
V
IN
4V TO PWR V – 4.5V
IN(MIN)
IN
(V
= 3.5V IF I
< 2.5A)
LOAD
Si9410DY
Si9410DY
C
IN
+
100µF
20V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
D1
MBRS140T3
2 ×
TDRIVE
BDRIVE
PGND
1µF
+
PWR V
IN
PWR V
PINV
IN
V
+ 4.5V TO 18V
IN
LB
OUT
BINH
BINH
LB
IN
LTC1266-3.3
V
C
SGND
SHDN
NC
IN
T
SHUTDOWN
L*
C
OUT
220µF
10V
I
TH
5µH
C
T
180pF
C
C
+
3300pF
–
+
SENSE
SENSE
2 ×
R
C
1000pF
R
470Ω
SENSE
0.02Ω
V
3.3V
5A
OUT
1266 F13
*TOKO 919AS-4R7M
Figure 13. All N-Channel 5V to 3.3V/5A Converter with Drivers Powered from External PWR VIN Supply
18
LTC1266
LTC1266-3.3/LTC1266-5
U
TYPICAL APPLICATIO S
(Layout Assist Schematics)
V
IN
4V TO 9V
0.1µF
MBR0530T1
Si4410DY
Si4410DY
47µF
+
10V
OS-CON
3 ×
1
2
3
4
5
6
7
8
16
D1
MBRS340T3
TDRIVE
BDRIVE
PGND
15
14
13
12
11
10
9
PWR V
PINV
IN
LB
OUT
BINH
BINH
LB
IN
LTC1266-3.3
V
C
SGND
SHDN
NC
IN
T
SHUTDOWN
L*
5µH
C
OUT
I
TH
330µF
10V
C
C
T
C
+
220pF
3300pF
–
+
SENSE
SENSE
3 ×
R
C
1000pF
R
470Ω
SENSE
0.01Ω
V
3.3V
10A
OUT
1266 F14
*MAGNETICS Kool Mµ 77120-A7
Figure 14. All N-Channel 5V to 3.3V/10A High Efficiency Regulator
V
IN
4V TO 9V
= 3.5V IF I
(V
IN(MIN)
< 1A)
LOAD
0.1µF
MBR0530T1
Si9410DY
Si9410DY
100µF
10V
OS-CON
2 ×
+
1
2
3
4
5
6
7
8
16
15
14
13
12
11
D1
MBRS130T3
TDRIVE
BDRIVE
PGND
PWR V
PINV
IN
LB
OUT
BINH
BINH
LB
IN
LTC1266
V
C
SGND
SHDN
IN
T
L*
100k
1%
100pF
SHUTDOWN
5µH
10
9
C
OUT
I
V
TH
FB
+
330µF
10V
2 ×
C
C
T
C
+
180pF
3300pF
–
SENSE
SENSE
97.6k
1%
R
C
1000pF
R
SENSE
470Ω
0.02Ω
V
2.5V
5A
OUT
1266 F15
*TOKO 919AS-4R7M
Figure 15. All N-Channel 5V to 2.5V/5A High Efficiency Regulator
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
19
LTC1266
LTC1266-3.3/LTC1266-5
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
S Package
16-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.386 – 0.394*
(9.804 – 10.008)
16
15
14
13
12
11
10
9
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
5
7
8
1
2
3
4
6
0.010 – 0.020
(0.254 – 0.508)
× 45°
0.053 – 0.069
(1.346 – 1.752)
0.004 – 0.010
(0.101 – 0.254)
0.008 – 0.010
(0.203 – 0.254)
0° – 8° TYP
0.050
(1.270)
BSC
0.014 – 0.019
(0.355 – 0.483)
TYP
0.016 – 0.050
(0.406 – 1.270)
S16 1098
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
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No R
and OPTI-LOOP are trademarks of Linear Technology Corporation.
SENSE
1266fa LT/TP 1000 2K REV A • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 1995
20 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
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