LTC1267-ADJ [Linear]

Dual High Efficiency Synchronous Step-Down Switching Regulators; 双通道高效率同步降压型开关稳压器
LTC1267-ADJ
型号: LTC1267-ADJ
厂家: Linear    Linear
描述:

Dual High Efficiency Synchronous Step-Down Switching Regulators
双通道高效率同步降压型开关稳压器

稳压器 开关
文件: 总16页 (文件大小:341K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
LTC1267  
LTC1267-ADJ/LTC1267-ADJ5  
Dual High Efficiency  
Synchronous Step-Down  
Switching Regulators  
U
DESCRIPTIO  
EATURE  
Dual Outputs: 3.3V and 5V, Two Adjustables or  
Adjustable and 5V  
S
F
The LTC®1267 series are dual synchronous step-down  
switching regulator controllers featuring automatic Burst  
ModeTM operation to maintain high efficiencies at low  
output currents. The LTC1267 is composed of two sepa-  
rateregulatorblocks,eachdrivingapairofexternalcomple-  
mentary power MOSFETs at switching frequencies up to  
400kHz. The LTC1267 uses a constant off-time current-  
mode architecture to provide constant ripple current in the  
inductor and provide excellent line and load transient  
response.  
Wide VIN Range: 4V to 40V  
Ultra-High Efficiency: Up to 95%  
Low Supply Current in Shutdown: 20µA  
Current Mode Operation for Excellent Line and Load  
Transient Response  
High Efficiency Maintained Over a Wide Output  
Current Range  
Independent Micropower Shutdown  
Very Low Dropout Operation: 100% Duty Cycle  
Synchronous FET Switching for High Efficiency  
Available in Standard 28-Pin SSOP  
A separate pin and on-board switch allow the MOSFET  
driver power to be derived from the regulated output  
voltage,providingsignificantefficiencyimprovementwhen  
operating at high input voltage. The output current level is  
user-programmable via an external current sense resistor.  
O U  
PPLICATI  
A
S
The LTC1267 series is ideal for applications requiring dual  
output voltages with high conversion efficiencies over a  
wide load current range in a small amount of board space.  
, LTC and LT are registered trademarks of Linear Technology Corporation.  
Burst Modeis a trademark of Linear Technology Corporation.  
Notebook and Palmtop Computers  
Battery-Operated Digital Devices  
Portable Instruments  
DC Power Distribution Systems  
U
O
TYPICAL APPLICATI  
V
IN  
5.4V to 25V  
+
C
IN5  
+
C
IN3  
100µF  
+
0.15µF  
0.15µF  
27  
100µF  
50V  
+
3.3µF  
1N4148  
1N4148  
50V  
3.3µF  
3
1
8
2
26  
28  
21  
P-CH  
P-CH  
Si9435DY  
Si9435DY  
L3  
20µH  
V
CAP3  
V
V
MSHDN CAP5 EXT V  
V
CC5  
CC3  
CC  
IN  
CC  
PGATE 5  
4
5
25  
24  
18  
L5  
33µH  
R
R
SENSE5  
SENSE3  
0.05Ω  
0.1µF  
PGATE 3  
0.1µF  
V
0.05Ω  
V
5V  
2A  
OUT3  
3.3V  
2A  
OUT5  
PDRIVE 3  
+
PDRIVE 5  
+
14  
SENSE  
3
SENSE  
SENSE  
5
5
1000pF  
1000pF  
LTC1267  
17  
19  
13  
12  
SENSE  
3
SHDN5  
SHDN3  
D3  
MBRS140T3  
D5  
6
23  
NGATE 3  
PGND3 SGND3  
11  
NGATE 5  
MBRS140T3  
C
T5  
16  
C
I
I
SGND5  
20  
PGND5  
22  
T3  
9
TH3  
10  
TH5  
15  
N-CH  
Si9410DY  
C
OUT5  
220µF  
10V  
× 2  
N-CH  
Si9410DY  
C
OUT3  
+
+
7
220µF  
10V  
× 2  
C
C
C5  
C
C
C3  
3300pF 3300pF  
T3  
T5  
270pF  
270pF  
R
C5  
1k  
R
C3  
1k  
R
: KRL SL-1R050J  
R
: KRL SL-1R050J  
SENSE3  
L3: COILTRONICS CTX20-4  
SENSE5  
L5: COILTRONICS CTX33-4  
LTC1267 • F01  
SHDN3, SHDN5, MSHDN  
0V = NORMAL, >2V = SHDN  
Figure 1. High Efficiency Dual 3.3V, 5V  
1
LTC1267  
LTC1267-ADJ/LTC1267-ADJ5  
W W W  
U
W
U
ABSOLUTE AXI U RATI GS  
/O  
PACKAGE RDER I FOR ATIO  
Input Supply Voltage (Pin 2)..................... 0.3V to 40V  
VCC Output Current (Pin 1) .................................. 50mA  
EXT VCC Input Voltage (Pin 28) .............................. 10V  
Continuous Output Current (Pins 5, 6, 23, 24) .... 50mA  
Sense Voltages  
LTC1267 (Pins 13, 14, 17, 18) ............. VCC to 0.3V  
LTC1267-ADJ (Pins 12, 13, 17, 18) ..... VCC to 0.3V  
LTC1267-ADJ5 (Pins 12, 13, 17, 18) ... VCC to 0.3V  
Shutdown Voltages  
ORDER PART  
NUMBER  
TOP VIEW  
V
1
2
28 EXT V  
CC  
CC  
V
27 MSHDN  
26 CAP5  
IN  
LTC1267CG  
CAP3  
PGATE 3  
PDRIVE 3  
NGATE 3  
PGND3  
3
4
25 PGATE 5  
24 PDRIVE 5  
23 NGATE 5  
22 PGND5  
5
6
7
V
8
21  
V
CC5  
CC3  
LTC1267 (Pins 12, 19, 27) ................................... 7V  
LTC1267-ADJ (Pins 11, 27) ................................. 7V  
LTC1267-ADJ5 (Pins 11, 19, 27) ......................... 7V  
Operating Ambient Temperature Range ...... 0°C to 70°C  
Extended Commercial  
C
9
20 SGND5  
T3  
I
10  
19 SHDN5  
TH3  
+
SGND3 11  
18 SENSE 5  
SHDN3 12  
17 SENSE  
5
SENSE  
3
13  
16  
15  
C
T5  
+
SENSE 3 14  
I
TH5  
Temperature Range ........................... 40°C to 85°C  
Junction Temperature (Note 1)............................ 125°C  
Storage Temperature Range ................ – 65°C to 150°C  
Lead Temperature (Soldering, 10 sec)................. 300°C  
G PACKAGE  
28-LEAD PLASTIC SSOP  
T
= 125°C, θ = 95°C/W  
JMAX  
JA  
TOP VIEW  
TOP VIEW  
ORDER PART  
NUMBER  
ORDER PART  
V
1
2
3
4
5
6
7
8
9
28 EXT V  
CC  
V
1
2
3
4
5
6
7
8
9
28 EXT V  
CC  
CC  
CC  
NUMBER  
V
27 MSHDN  
26 CAP5  
V
27 MSHDN  
26 CAP2  
IN  
IN  
CAP1  
PGATE 1  
PDRIVE 1  
NGATE 1  
CAP1  
PGATE 1  
PDRIVE 1  
NGATE 1  
LTC1267CG-ADJ5  
LTC1267CG-ADJ  
25 PGATE 5  
24 PDRIVE 5  
23 NGATE 5  
22 PGND  
25 PGATE 2  
24 PDRIVE 2  
23 NGATE 2  
22 PGND  
V
V
CC1  
CC1  
C
21  
V
CC5  
C
21  
20 SGND2  
19  
V
T1  
T1  
CC2  
I
20 SGND5  
I
TH1  
TH1  
SGND1 10  
19 SHDN5  
SGND1 10  
V
FB2  
+
+
SHDN1 11  
18 SENSE 5  
SHDN1 11  
18 SENSE 2  
SENSE  
1
12  
17 SENSE  
5
SENSE  
1
12  
17 SENSE  
2
+
+
SENSE 1 13  
16  
15  
C
I
SENSE 1 13  
16  
15  
C
I
T5  
T2  
V
14  
V
14  
FB1  
TH5  
FB1  
TH2  
G PACKAGE  
28-LEAD PLASTIC SSOP  
G PACKAGE  
28-LEAD PLASTIC SSOP  
T
= 125°C, θ = 95°C/W  
T
= 125°C, θ = 95°C/W  
JMAX  
JA  
JMAX  
JA  
Consult factory for Industrial and Military grade parts.  
The LTC1267 demo circuit board is now available. Consult factory.  
2
LTC1267  
LTC1267-ADJ/LTC1267-ADJ5  
ELECTRICAL CHARACTERISTICS  
TA = 25°C, VIN = 12V, VMSHDN, VSHDN1,3,5 = 0V (Note 2), unless otherwise noted.  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN  
TYP  
1.25  
0.2  
MAX  
1.29  
1
UNITS  
V
V
FB1  
,
Feedback Voltage  
Feedback Current  
LTC1267-ADJ, LTC1267-ADJ5: V = 9V  
1.21  
2
IN  
I
,
LTC1267-ADJ, LTC1267-ADJ5  
µA  
FB1 2  
V
OUT  
Regulated Output Voltage  
3.3V Output  
LTC1267: V = 9V, I  
= 700mA  
IN  
3.23  
4.90  
3.33  
5.05  
3.43  
5.20  
V
V
IN  
LOAD  
5V Output  
LTC1267, LTC1267-ADJ5: V = 9V, I  
= 700mA  
LOAD  
V  
Output Voltage Line Regulation  
V
IN  
= 9V to 40V  
40  
0
40  
mV  
OUT  
Output Voltage Load Regulation  
3.3V Output  
Figure 1 Circuit  
5mA < I  
5mA < I  
< 2.0A  
< 2.0A  
40  
60  
65  
100  
mV  
mV  
LOAD  
LOAD  
5V Output  
Burst Mode Output Ripple  
Internal Regulator Voltage  
I
= 0A  
50  
4.5  
mV  
P-P  
LOAD  
V
V
V
V
= 12V to 40V, EXT V = 0V, I = 10mA  
4.25  
4.75  
300  
V
CC  
IN  
CC  
CC  
– V  
V
Dropout Voltage  
= 4V, EXT V = Open, I = 10mA  
200  
360  
mV  
IN  
CC  
CC  
IN  
CC  
CC  
I
I
EXT V Pin Current (Note 3)  
EXT V = 5V, Sleep Mode  
µA  
EXTVCC  
IN  
CC  
CC  
V
Pin Current (Note 3)  
Normal  
IN  
V
V
V
V
= 12V, EXT V = 5V  
= 40V, EXT V = 5V  
= 12V, V  
= 40V, V  
320  
550  
15  
µA  
µA  
µA  
µA  
IN  
IN  
IN  
IN  
CC  
CC  
MSHDN  
MSHDN  
Shutdown  
= 2V  
= 2V  
25  
V
V
EXT V Switch Drop  
V
IN  
= 12V, EXT V = 5V, I  
= 10mA  
200  
300  
mV  
EXTVCC  
CC  
CC  
CC  
SWITCH  
V
V
PGate to Source Voltage (Off)  
V
V
= 12V  
= 40V  
0.2  
0.2  
0
0
V
V
PGATE  
IN  
IN  
IN  
+
V
V
Current Sense Threshold Voltage LTC1267-ADJ, LTC1267-ADJ5  
SENSE 1, 2  
V
V
= 5.1V, V  
= 4.9V, V  
= V /4 + 25mV (Forced)  
25  
160  
mV  
mV  
SENSE 1, 2  
SENSE 1, 2  
SENSE 1, 2  
FB1, 2  
FB1, 2  
OUT  
= V /4 – 25mV (Forced)  
135  
135  
180  
180  
OUT  
+
V
V
– Current Sense Threshold Voltage LTC1267  
SENSE 3, 5  
V
V
= V  
= V  
+ 100mV (Forced)  
– 100mV (Forced)  
25  
160  
mV  
mV  
SENSE 3, 5  
SHDN  
SENSE 3, 5  
SENSE 3, 5  
OUT  
OUT  
V
Shutdown Threshold  
MSHDN  
0.8  
0.6  
1.4  
0.8  
2.0  
2.0  
V
V
SHDN1, 3, 5  
I
I
MSHDN Input Current  
V
= 5V  
12  
20  
µA  
MSHDN  
CT  
MSHDN  
C Pin Discharge Current  
T
V
OUT  
V
OUT  
in Regulation  
= 0V  
50  
4
70  
2
90  
10  
µA  
µA  
t
Off-Time (Note 4)  
C = 390pF, I  
T
= 700mA, V = 10V  
5
6
µs  
OFF  
LOAD  
IN  
t , t  
r
Driver Output Transition Times  
C = 3000pF (PDrive and NGate Pins), V = 6V  
100  
200  
ns  
f
L
IN  
3
LTC1267  
LTC1267-ADJ/LTC1267-ADJ5  
ELECTRICAL CHARACTERISTICS  
40°C TA 85°C, VIN = 12V, VMSHDN, VSHDN1,3,5 = 0V (Notes 2, 5), unless otherwise noted.  
SYMBOL  
PARAMETER  
CONDITIONS  
LTC1267-ADJ, LTC1267-ADJ5: V = 9V  
MIN  
TYP  
MAX  
UNITS  
V
V
,
Feedback Voltage  
1.2  
1.25  
1.3  
V
FB1  
2
IN  
Regulated Output Voltage  
3.3V Output  
V
IN  
= 9V  
I
OUT  
= 700mA  
= 700mA  
3.17  
4.85  
3.30  
5.05  
3.48  
5.25  
V
V
LOAD  
LOAD  
5V Output  
I
I
V
Pin Current (Note 3)  
Normal  
IN  
IN  
V
IN  
V
IN  
V
IN  
V
IN  
= 12V, EXT V = 5V  
320  
550  
15  
µA  
µA  
µA  
µA  
CC  
= 40V, EXT V = 5V  
CC  
Shutdown  
= 12V, V  
= 40V, V  
= 2V  
= 2V  
MSHDN  
MSHDN  
25  
I
EXT V Pin Current (Note 3)  
EXT V = 5V, Sleep Mode  
360  
4.5  
µA  
EXTVCC  
CC  
CC  
V
Internal Regulator Voltage  
V
IN  
= 12V to 40V, EXT V = 0V, I = 20mA  
V
CC  
CC  
CC  
+
V
V
Current Sense Threshold Voltage Low Threshold (Forced)  
High Threshold (Forced)  
25  
mV  
mV  
SENSE  
SENSE  
130  
0.8  
3
160  
185  
2.0  
7
V
Shutdown Threshold MSHDN  
Off-Time (Note 4)  
1.4  
5
V
MSHDN  
OFF  
t
C = 390pF, I  
= 700mA, V = 10V  
µs  
T
LOAD  
IN  
The  
temperature range.  
Note 1: T is calculated from the ambient temperature T and power  
denotes specifications which apply over the full operating  
Note 4: In applications where R  
off-time increases approximately 40%.  
Note 5: The LTC1267/LTC1267-ADJ/LTC1267-ADJ5 are not tested and  
quality-assurance sampled at 40°C to 85°C. These specifications are  
guaranteed by design and/or correlation.  
is placed at ground potential, the  
SENSE  
J
A
dissipation P according to the following formula:  
D
LTC1267/LTC1267-ADJ/LTC1267ADJ5: T = T + (P × 95°C/W)  
J
A
D
Note 2: On LTC1267 versions which have MSHDN and SHDN1, 3, 5 pins,  
they must be at ground potential for testing.  
Note 6: The logic level power MOSFETs shown in Figure 1 are rated for  
V = 30V. For operation at V > 30V, use standard threshold  
DS(MAX) IN  
MOSFETs with EXT V powered from a 9V supply. See applications  
information.  
CC  
Note 3: The LTC1267 V and EXT V current measurements exclude  
IN  
CC  
MOSFET driver currents. When V power is derived from the output via  
CC  
EXT V , the input current increases by (I  
× Duty Cycle)/Efficiency.  
Note 7: LTC1267-ADJ and LTC1267-ADJ5 are tested at an output of 3.3V  
CC  
GATECHG  
See Typical Performance Characteristics and Applications Information.  
W
U
TYPICAL PERFORMANCE CHARACTERISTICS  
5V Output Efficiency  
vs Load Current  
3.3V Output Efficiency  
vs Load Current  
Load Regulation  
100  
95  
90  
85  
80  
75  
70  
65  
60  
100  
95  
90  
85  
80  
75  
70  
65  
60  
30  
20  
V
= 10V  
V
= 10V  
IN  
IN  
10  
V
V
= 20V  
IN  
OUT  
= 3.3V  
0
V
V
= 10V  
IN  
OUT  
V
= 20V  
V
= 20V  
IN  
IN  
–10  
–20  
–30  
–40  
–50  
= 3.3V  
V
OUT  
= 10V  
IN  
V
= 5V  
V
OUT  
= 20V  
IN  
V
= 5V  
–60  
0.01  
0.1  
1
10  
0.01  
0.1  
1
10  
0
2.0  
2.5  
0.5  
1.0  
1.5  
LOAD CURRENT (A)  
LOAD CURRENT (A)  
LOAD CURRENT  
LTC1267 • G01  
LTC1267 • G02  
LTC1267 • G03  
4
LTC1267  
LTC1267-ADJ/LTC1267-ADJ5  
W
U
TYPICAL PERFORMANCE CHARACTERISTICS  
5V Output Efficiency  
vs Line Voltage  
3.3V Output Efficiency  
vs Line Voltage  
Line Regulation  
100  
95  
90  
85  
80  
75  
70  
65  
60  
100  
95  
90  
85  
80  
75  
70  
65  
60  
60  
LOGIC THRESHOLD  
LOGIC THRESHOLD  
GATE, 1A  
GATE, 1A  
40  
NOTE 6  
NOTE 6  
NOTE 6  
20  
LOGIC  
THRESHOLD  
GATE, 0.1A  
LOGIC  
THRESHOLD  
GATE, 0.1A  
STANDARD  
THRESHOLD GATE, 1A  
0
STANDARD  
THRESHOLD GATE, 1A  
–20  
V
= 9V  
EXTVCC  
V
= 9V  
EXTVCC  
STANDARD  
STANDARD  
–40  
–60  
THRESHOLD GATE, 0.1A  
THRESHOLD GATE, 0.1A  
V
= 9V  
EXTVCC  
V
= 9V  
EXTVCC  
25 30  
10 15 20  
INPUT VOLTAGE (V)  
20 25  
20 25  
0
5
35 40  
0
5
10 15  
30 35 40  
0
5
10 15  
30 35 40  
INPUT VOLTAGE (V)  
INPUT VOLTAGE (V)  
LTC1267 • G04  
LTC1267 • G05  
LT1267 • G06  
Operating Frequency  
Off-Time vs Output Voltage  
vs (VIN – VOUT  
)
Current Sense Threshold Voltage  
160  
140  
120  
100  
80  
2.0  
1.5  
1.0  
0.5  
0
180  
160  
140  
120  
100  
80  
V
LOAD  
= 5V  
0°C  
OUT  
I
= 700mA  
25°C  
70°C  
MAXIMUM THRESHOLD  
60  
60  
3.3V OUTPUT REGULATOR  
5V OUTPUT REGULATOR  
40  
40  
MINIMUM THRESHOLD  
20  
20  
0
0
0
5
10  
15  
20  
25  
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0  
OUTPUT VOLTAGE (V)  
0
10 20 30 40 50 60 70 80 90 100  
(V – V ) VOLTAGE (V)  
TEMPERATURE (°C)  
IN  
OUT  
LTC1267 • G07  
LTC1267 • F08  
LTC1267 • G09  
U
U
U
(Applies to both regulator sections)  
PI FU CTIO S  
VIN: Main Supply Input Pin.  
SGND: Small-Signal Ground. Must be routed separately  
from other grounds to the (–) terminal of COUT  
.
EXT VCC: External VCC Supply for the Regulators. See EXT  
VCC Pin Connection.  
PGATE: Level Shifted Gate Drive for the Top P-channel  
MOSFET. The voltage swing at the PGate pin is from VIN to  
(VIN – VCC).  
VCC: Output of the Internal 4.5V Linear Regulator, EXT VCC  
Switch, and Supply Inputs for Driver and Control Circuits.  
The driver and control circuits are powered from the  
higher of the 4.5V regulator or EXT VCC voltage. Must be  
closely decoupled to the power ground.  
PDRIVE: High Current Gate Drive for the Top P-channel  
MOSFET. The PDrive pin swings from VCC to GND.  
NGATE: High Current Drive for the Bottom N-channel  
PGND:PowerGround.ConnecttothesourceofN-channel  
MOSFET and the (–) terminal of CIN.  
MOSFET. The NGate pin swings from GND to VCC.  
5
LTC1267  
LTC1267-ADJ/LTC1267-ADJ5  
U
U
U
PI FU CTIO S  
SENSE+: The (+) Input for the Current Comparator. A  
built-in offset between the Sense+ and Sensepins, in  
conjunction with RSENSE, sets the current trip threshold.  
CAP: Charge Compensation Pin. A capacitor to VCC pro-  
vides charge required by the PGate level shift capacitor  
during supply transitions. The charge compensation ca-  
pacitor must be larger than the gate drive capacitor.  
VFB1, 2: These pins receive the feedback voltage from an  
external resistive divider used to set the output voltage of  
the adjustable section.  
CT: External Capacitor. From this pin to ground sets the  
operating frequency. (The frequency is also dependent  
upon the ratio VOUT/VIN).  
MSHDN: Master Shutdown Pin. Taking MSHDN high  
shuts down VCC and all control circuitry.  
ITH : Gain Amplifier Decoupling Point. The regulator cur-  
rent comparator threshold increases with the ITH pin  
voltage.  
SENSE: Connects to internal resistive divider which sets  
the output voltage. The Sensepin is also the (–) input of  
the current comparator.  
SHDN1, 3, 5: These pins shut down the individual regula-  
tor control circuitry (VCC is not affected). Taking SHDN1,  
3, 5 pins high turns off the control circuitry of adjustable  
1, 3.3V, 5V sections andholds bothMOSFETs off. Must be  
at ground potential for normal operation.  
U
U
W
FU CTIO AL DIAGRA  
(Internal divider broken at VFB1,2 for adjustable versions. Only one regulator block shown.)  
V
IN  
LOW  
CAP  
MSHDN  
DROPOUT  
PGATE  
4.5V REGULATOR  
V
CC  
550k  
550k  
LOW DROPOUT  
SWITCH  
V
CC  
EXT V  
CC  
PDRIVE  
SLEEP  
+
SENSE  
SENSE  
NGATE  
+
PGND  
V
R
S
C
Q
+
25mV TO 150mV  
+
S
V
OS  
+
V
TH2  
V
TH1  
13k  
I
G
T
TH  
100k  
+
V
FB1, 2  
1.25V  
OFF-TIME  
CONTROL  
SENSE  
REFERENCE  
SHDN1, 3, 5  
SGND  
C
T
LTC1267 • FD  
6
LTC1267  
LTC1267-ADJ/LTC1267-ADJ5  
U
OPERATIO  
(Refer to Functional Diagram)  
proportional to the output voltage. While the timing ca-  
pacitor is discharging, the NGate output is high, turning  
on the N-channel MOSFET.  
The LTC1267 series consists of two individual regulator  
blocks, each using current mode, constant off-time archi-  
tectures to synchronously switch an external pair of  
complementary power MOSFETs. The two regulators are  
internally set to provide output voltages of 3.3V and 5V for  
the LTC1267. The LTC1267-ADJ is configured to provide  
two adjustable output voltages, each set by their indi-  
vidual external resistor dividers. The LTC1267-ADJ5 has  
adjustable and 5V output voltages. Operating frequency is  
individually set on each section by the external capacitors  
attached to the CT pin.  
When the voltage on the timing capacitor has discharged  
past VTH1, comparator T trips, setting the flip-flop. This  
causes the NGate output to go low (turning off the  
N-channel MOSFET) and the PGate output to also go low  
(turning the P-channel MOSFET back on). The cycle then  
repeats. As the load current increases, the output voltage  
decreases slightly. This causes the output of the gain  
stage to increase the current comparator threshold, thus  
tracking the load current.  
The output voltage is sensed by an internal voltage divider  
connected to the Sensepin or external divider returned  
to the VFB pin (LTC1267-ADJ, LTC1267-ADJ5). A voltage  
comparator V and a gain block G compare the divided  
output voltage with a reference voltage of 1.25V. To  
optimize efficiency, the LTC1267 series automatically  
switches between two modes of operation, Burst Mode  
and continuous mode. The voltage comparator is the  
primary control element when the device is in Burst Mode  
operation, while the gain block controls the output voltage  
in continuous mode.  
The sequence of events for Burst Mode operation is very  
similar to continuous operation with the cycle interrupted  
by the voltage comparator. When the output voltage is at  
or above the desired regulated value, the P-channel  
MOSFET is held off by comparator V and the timing  
capacitor continues to discharge below VTH1. When the  
timing capacitor discharges past VTH2, voltage compara-  
tor S trips, causing the internal SLEEP line to go low and  
the N-channel MOSFET to turn off.  
The circuit now enters sleep mode with both power  
MOSFETs turned off. In sleep mode a majority of the  
circuitry is turned off, dropping the quiescent current  
from several mA (with the MOSFETs switching) to 360µA.  
The load current is now being supplied by the output  
capacitor. When the output voltage has dropped by the  
amount of hysteresis in comparator V, the P-channel  
MOSFET is again turned on and this process repeats.  
A low dropout 4.5V regulator provides the operating  
voltage VCC for the MOSFET drivers and control circuitry  
during start-up. During normal operation, the LTC1267  
family powers the drivers and control from the output via  
the EXT VCC pin to improve efficency. The NGate pin is  
referenced to ground and drives the N-channel MOSFET  
gatedirectly. TheP-channelgatedrive mustbereferenced  
to the main supply input VIN, which is accomplished by  
level-shifting the PDrive signal via an internal 550k resis-  
tor and an external capacitor.  
To avoid the operation of the current loop interfering with  
Burst Modeoperation, a built-in offset VOS is incorporated  
in the gain stage. This prevents the current comparator  
threshold from increasing until the output voltage has  
dropped below a minimum threshold.  
During the switch “ON” cycle in continuous mode, current  
comparator C monitors the voltage between Sense+ and  
Sensepins connected across an external shunt in series  
with the inductor. When the voltage across the shunt  
reaches its threshold value, the PGate output is switched  
to VIN, turning off the P-channel MOSFET. The timing  
capacitor CT is now allowed to discharge at a rate deter-  
mined by the off-time controller. The discharge current is  
made proportional to the output voltage to model the  
inductor current, which decays at a rate that is also  
To prevent both the external MOSFETs from ever being  
turned on at the same time, feedback is incorporated to  
sense the state of the driver output pins. Before the  
NGate output can go high, the PDrive output must also be  
high. Likewise, the PDrive output is prevented from going  
low while the NGate output is high.  
7
LTC1267  
LTC1267-ADJ/LTC1267-ADJ5  
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APPLICATIO S I FOR ATIO  
The LTC1267 works well with values of RSENSE from  
0.02to 0.2. Figure 2 shows the selection of RSENSE vs  
maximum output current.  
The LTC1267 Compared to the LTC1159, LTC1149 and  
LTC1142 Family  
The LTC1267 family is a dual LTC1159. Identical to the  
LTC1159, the LTC1267 can reduce the quiescent and  
shutdown currents by making use of an internal switch  
which allows the driver and control sections to be  
poweredfromanexternalsourcetoimproveefficiency.  
0.20  
0.15  
0.10  
0.05  
0
The basic LTC1267 application circuit shown in Figure  
1 is limited to a maximum input voltage of 30V due to  
external MOSFET breakdown. If the application does  
not require greater than 18V operation the LTC1142HV  
should be used.  
0
1
2
3
4
5
MAXIMUM OUTPUT CURRENT (A)  
LTC1267 • F02  
Component Selection  
Figure 2. Selecting RSENSE  
T
he basic LTC1267 application circuit is shown in Figure  
1. External component selection is driven by the load  
requirement and begins with the selection of RSENSE  
The load current below which Burst Modeoperation com-  
mences, IBURST and the peak short-circuit current ISC(PK)  
bothtrackIMAX.OnceRSENSE hasbeenchosen,IBURST and  
ISC(PK) can be predicted from the following:  
.
Once RSENSE is known, CT and L can be chosen. Next, the  
power MOSFETs and diode are selected. Finally, CIN and  
COUT are selected and the loop is compensated. Since the  
adjustable, 3.3V and 5V sections in the LTC1267 are  
identical, the process of component selection is the same  
for both sections.  
15mV  
SENSE  
I
BURST  
R
150mV  
SENSE  
I
=
RSENSE Selection for Output Current  
SC(PK)  
R
RSENSE is chosen based on the required output current.  
The LTC1267 current comparators have a threshold range  
which extends from a minimum of 25mV/RSENSE to a  
maximum of 150mV/RSENSE. The current comparator  
threshold sets the peak of the inductor ripple current,  
yielding a maximum output current IMAX equal to the peak  
value less half the peak-to-peak ripple current. For proper  
Burst Mode operation, IRIPPLE(P-P) must be less than or  
equal to the minimum current comparator threshold.  
The LTC1267 automatically extends tOFF during a short  
circuit to allow sufficient time for the inductor current to  
decay between switch cycles. The resulting ripple current  
causes the average short-circuit current ISC(AVG) to be  
reduced to approximately IMAX  
.
CT and L Selection for Operating Frequency  
EachregulatorsectionoftheLTC1267usesaconstantoff-  
time architecture with tOFF determined by an external  
timing capacitor CT. The value of CT is calculated from the  
desired continuous mode operating frequency (fO):  
Since efficiency generally increases with ripple current,  
the maximum allowable ripple current is assumed, i.e.,  
IRIPPLE(P-P) = 25mV/RSENSE (see CT and L Selection for  
Operating Frequency). Solving for RSENSE and allowing a  
margin for variations in the LTC1267 andexternal compo-  
nent values yields:  
–5  
V
V
7.8 × 10  
OUT  
C =  
1 –  
T
)
)
f
IN  
O
A graph for selecting CT vs frequency including the effects  
of input voltage is given in Figure 3.  
100mV  
MAX  
R
=
SENSE  
I
8
LTC1267  
LTC1267-ADJ/LTC1267-ADJ5  
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APPLICATIO S I FOR ATIO  
1400  
value, but it is very dependent on inductance selected. As  
inductanceincreases, corelossesgodownbutcopperI2R  
losses increase. For additional information regarding in-  
ductor selection, please refer to the LTC1159 data sheet.  
V
OUT  
= 5V  
1200  
1000  
800  
600  
400  
200  
0
V
= 24V  
IN  
Power MOSFET and Diode Selection  
V
IN  
= 12V  
Two external power MOSFETs must be selected for use  
with each section of the LTC1267: a P-channel MOSFET  
for the main switch, and an N-channel MOSFET for the  
synchronous switch.  
50  
100  
FREQUENCY (kHz)  
250  
0
150  
200  
The peak-to-peak gate drive levels are set by the VCC  
voltage on the LTC1267. This voltage is typically 4.5V  
duringstart-upand5Vto7Vduringnormaloperation(see  
EXTVCCPinConnection).Consequently,logic-levelthresh-  
old MOSFETs must be used in most LTC1267 family  
applications. The only exceptions are applications in  
whichEXTVCC ispoweredfromanexternalsupplygreater  
than 8V, in which standard threshold MOSFETs (VGS(TH)  
> 4V) may be used. Pay close attention to the BVDSS  
specification for the MOSFETs as well; many of the logic-  
level MOSFETs are limited to 30V.  
LTC1267 • F03  
Figure 3. Timing Capacitor Value  
As the operating frequency is increased the gate charge  
losses will be higher, reducing efficiency (see Efficiency  
Considerations). The complete expression for operating  
frequency is given by:  
V
V
1
OFF  
OUT  
f =  
1 –  
O
)
)
t
IN  
where:  
Selection criteria for the power MOSFETs include the on-  
tOFF = 1.3 × 104 × CT  
resistance RDS(ON), reverse transfer capacitance CRSS  
,
input voltage, and maximum output current. When the  
LTC1267 isoperating in continuous mode, the duty cycles  
for the two MOSFETs are given by:  
OncethefrequencyhasbeensetbyCT,theinductorLmust  
be chosen to provide no more than 0.025V/RSENSE of  
peak-to-peak inductor ripple current. This results in a  
minimum required inductor value of:  
V
V
OUT  
Duty Cycle =  
LMIN = 5.1 × 105 × RSENSE × CT × VOUT  
IN  
V – V  
As the inductor value is increased from the minimum  
value, the ESR requirements for the output capacitor are  
eased at the expense of efficiency. If too small an inductor  
is used, the LTC1267 may not enter Burst Modeoperation  
and efficiency will be severely degraded at low currents.  
IN  
OUT  
N-Channel Duty Cycle =  
V
IN  
The MOSFET dissipations at maximum output current are  
given by:  
Inductor Core Selection  
V
V
OUT  
2
P-Ch P =  
(I  
) (1 + δ ) R  
MAX P DS(ON)  
D
Once the minimum value for L is known, the type of  
inductor must be selected. High efficiency converters  
generally cannot afford the core loss found in low cost  
powdered iron cores, forcing the use of more expensive  
ferrite, molypermalloy (MPP), or Kool Mµ® cores. Actual  
core loss is independent of core size for a fixed inductor  
IN  
2
+ k (V ) (I  
) (C ) f  
O
IN  
MAX  
RSS  
V – V  
IN  
OUT  
2
N-Ch P =  
(I  
) (1 + δ ) R  
D
MAX  
N
DS(ON)  
V
IN  
Kool Mµ is a registered trademark of Magnetics, Inc.  
9
LTC1267  
LTC1267-ADJ/LTC1267-ADJ5  
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APPLICATIO S I FOR ATIO  
Where δ is the temperature dependency of RDS(ON) and k  
of life. This makes it advisable to further derate the  
capacitor or to choose a capacitor rated at a higher  
temperaturethanrequired.Severalcapacitorsmayalsobe  
paralleled to meet size or height requirements in the  
design. Always consult the manufacturer if there is any  
question. An additional 0.1µF ceramic capacitor is also  
required on VIN for high frequency decoupling.  
is a constant inversely related to the gate drive current.  
Both MOSFETs have I2R losses, while the P-channel  
equation includes an additional term for transition losses,  
which are highest at high input voltages. For VIN < 20V, the  
high current efficiency generally improves with larger  
MOSFETs,whileforVIN >20V,thetransitionlossesrapidly  
increasetothepointthattheuseofahigherRDS(ON) device  
with lower CRSS actually provides higher efficiency. The  
N-channel MOSFET losses are the greatest at high input  
voltage or during a short circuit when the N-channel duty  
cycle is nearly 100%.  
The selection of COUT is driven by the required Effective  
Series Resistance (ESR). The ESR of COUT must be less  
than twice the value of RSENSE for proper operation of the  
LTC1267:  
COUT Required ESR < 2RSENSE  
The term (1 + δ) is generally given for a MOSFET in the  
form of a normalized RDS(ON) vs temperature curve, but δ  
= 0.007/°C can be used as an approximation for low  
voltageMOSFETs.CRSS isusuallyspecifiedinthe MOSFET  
electrical characteristics. The constant k = 5 can be used  
for the LTC1267 to estimate the relative contributions of  
the two terms in the P-channel dissipation equation.  
Optimum efficiency is obtained by making the ESR equal  
to RSENSE. As the ESR is increased up to 2RSENSE, the  
efficiency degrades by less than 1%. If the ESR is greater  
than 2RSENSE, the voltage ripple on the output capacitor  
willprematurelytriggerBurstModeoperation, resultingin  
disruption of continuous mode and an efficiency hit which  
can be several percent.  
The Schottky diodes D3 and D5 shown in Figure 1 only  
conduct during the dead-time between the conduction of  
the respective power MOSFETs. The sole purpose of D3  
and D5 is to prevent the body diode of the N-channel  
MOSFET from turning on and storing charge during the  
dead-time, which could cost as much as 1% in efficiency  
(although there are no other harmful effects if D3 and D5  
are omitted). Therefore, D3 and D5 should be selected for  
Manufacturers such as Nichicon, United Chemicon, and  
Sprague should be considered for high performance ca-  
pacitors. In surface mount applications multiple capaci-  
tors may have to be paralleled to meet the capacitance,  
ESR, or RMS current handling requirements of the appli-  
cation. For additional information regarding capacitor  
selection, please refer to the LTC1159 data sheet.  
At low supply voltages, a minimum capacitance at COUT is  
needed to prevent an abnormal low frequency operating  
mode (see Figure 4). When COUT is made too small, the  
outputrippleatlowfrequencieswillbelargeenoughtotrip  
a forward voltage of less than 0.6V when conducting IMAX  
.
CIN and COUT Selection  
In continuous mode, the source current of the P-channel  
MOSFET is a square wave of duty cycle VOUT/VIN. To  
prevent large voltage transients, a low ESR input capaci-  
torsizedforthemaximumRMScurrentmustbeused.The  
maximum RMS capacitor current is given by:  
1000  
L = 50µH  
SENSE  
R
= 0.02Ω  
800  
600  
400  
200  
0
L = 25µH  
= 0.02Ω  
R
SENSE  
1/2  
[V (V – V )]  
OUT IN  
OUT  
C Required I  
I  
MAX  
IN  
RMS  
V
L = 50µH  
= 0.05Ω  
IN  
R
SENSE  
This formula has a maximum at VIN = 2VOUT where IRMS  
=
IOUT/2. This simple worst-case condition is commonly  
usedfordesignbecauseevensignificantdeviationsdonot  
offer much relief. Note that capacitor manufacturer’s  
ripple current ratings are often based on only 2000 hours  
0
1
2
3
4
5
(V – V ) VOLTAGE (V)  
IN  
OUT  
LTC1267 • F04  
Figure 4. Minimum Suggested COUT  
10  
LTC1267  
LTC1267-ADJ/LTC1267-ADJ5  
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APPLICATIO S I FOR ATIO  
the voltage comparator. This causes Burst Mode opera-  
tion to be activated when the LTC1267 would normally be  
in continuous operation. The effect is most pronounced  
with low values of RSENSE and can be improved by oper-  
ating at higher frequencies with lower values of L. The  
output remains in regulation at all times.  
V
IN  
+
1N4148  
C
IN  
+
EXT V  
V
IN  
CC  
L
1:1  
1µF  
P-CH  
PGATE 3  
R
SENSE  
V
3.3V  
PDRIVE 3  
OUT  
LTC1267  
NGATE 3  
N-CH  
+
C
OUT  
EXT VCC Pin Connection  
PGND3  
LTC1267 • F05A  
The LTC1267 contains an internal PNP switch connected  
between the EXT VCC and VCC pins. The switch closes and  
suppliestheVCC powerwhenevertheEXTVCC pinishigher  
in voltage than the 4.5V internal regulator. This allows the  
MOSFET driver and control power to be derived from the  
output during normal operation and from the internal  
regulator when the output is out of regulation (start-up,  
short circuit).  
Figure 5a. Inductive Boost Circuit for EXT VCC  
+
V
IN  
BAT 85  
1µF  
+
0.22µF  
BAT 85  
C
IN  
EXT V  
V
IN  
CC  
P-CH  
PGATE 3  
VN2222LL  
BAT 85  
PDRIVE 3  
L
R
SENSE  
V
OUT  
LTC1267  
3.3V  
NGATE 3  
N-CH  
+
SignificantefficiencygaincanberealizedbypoweringVCC  
from the output, since the VIN current resulting from the  
driver and control currents will be scaled by a factor of  
Duty Cycle/Efficiency. For LTC1267, LTC1267-ADJ or  
LTC1267-ADJ5 this simply means connecting the EXT  
VCC pin directly to VOUT of the 5V regulator.  
C
OUT  
PGND3  
LTC1267 • F05B  
Figure 5b. Capacitive Charge Pump for EXT VCC  
4. EXT VCC connected to an external supply. If an external  
supply is available in the 5V to 10V range it may be used  
to power EXT VCC providing it is compatible with the  
MOSFET gate drive requirements. When driving stan-  
dard threshold MOSFETs, the external supply must  
always be present during operation to prevent MOSFET  
failure due to insufficient gate drive.  
The following list summarizes the four possible connec-  
tions for EXT VCC:  
1. EXT VCC left open. This will cause VCC to be powered  
only from the internal 4.5V regulator, resulting in re-  
duced MOSFET gate drive levels and an efficiency  
penalty of up to 10% at high input voltages.  
Under the condition that EXT VCC is connected to VOUT1  
which is greater than 5.5V, to power down the whole  
regulator, both the pins MSHDN and SHDN1 have to be  
pulled high. If SHDN1 is left floating or grounded the  
EXT VCC may self-power from VOUT1, preventing com-  
plete shutdown.  
2. EXT VCC connected directly to highest VOUT of the two  
regulators. This is the normal connection for LTC1267/  
LTC1267-ADJ/LTC1267-ADJ5 and provides the high-  
est efficiency.  
3. EXT VCC connected to an output-derived boost net-  
work. For 3.3V and other low voltage regulators, effi-  
ciency gains can still be realized by connecting EXT VCC  
toanoutput-derivedvoltagewhichhasbeenboostedto  
greater than 4.5V. This can be done either with the  
inductive boost winding shown in Figure 5a or the  
capacitivechargepumpshowninFigure5b.Thecharge  
pump has the advantage of simple magnetics and  
generally provides the highest efficiency at the expense  
of a slightly higher parts count.  
LTC1267 Adjustable Applications  
When an output voltage other than 3.3V or 5V is required,  
the LTC1267-ADJ and LTC1267-ADJ5 adjustable ver-  
sions are used with an external resistive divider from VOUT  
to the VFB1, 2 pins. This is shown in Figure 6. The regulated  
voltage is determined by:  
R2  
R1  
V
= 1 +  
1.25V  
OUT  
)
)
11  
LTC1267  
LTC1267-ADJ/LTC1267-ADJ5  
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1. LTC1267 VIN current is the DC supply current given in  
the electrical characteristics which excludes MOSFET  
driver and control currents. VIN currents results in a  
small (<1%) loss which increases with VIN.  
The VFB1, 2 pin is extremely sensitive to pickup from the  
inductor switching node. Care should be taken to isolate  
the feedback network from the inductor and a 100pF  
capacitor should be connected between the VFB1, 2 and  
SGND pins next to the package.  
2. LTC1267 VCC current is the sum of the MOSFET driver  
and control circuits currents. The MOSFET driver cur-  
rent results from switching the gate capacitance of the  
power MOSFETs. Each time a MOSFET gate is switched  
from low to high to low again, a packet of charge dQ  
moves from VCC to ground. The resulting dQ/dt is a  
current out of VCC which is typically much larger than  
thecontrolcircuitcurrent.IncontinuousmodeIGATECHG  
fO(QP +QN), where QP and QN are the gate charges of  
the two MOSFETs.  
The circuit in Figure 6 cannot be used to regulate a VOUT  
which is greater than the maximum voltage allowed on the  
LTC1267 EXT VCC pin (10V). In applications with  
VOUT > 10V, RSENSE must be moved to the ground side of  
the output capacitor and load. This operates the current  
sense comparator at 0V common mode, increasing the  
off-time approximately 40% and requiring the use of a  
smaller timing capacitor CT.  
R
SENSE  
By powering EXT VCC from an output-derived source,  
the additional VIN current resulting from the driver and  
control currents will be scaled by a factor of Duty Cycle/  
Efficiency. For example, in a 20V to 5V application,  
10mA of VCC current results in approximately 3mA of  
VIN current. This reduces the mid-current loss from  
10% or more (if the driver was powered directly from  
VIN) to only a few percent.  
R2  
V
V
FB1, 2  
OUT  
+
R1  
100pF  
C
OUT  
SGND  
LTC1267 • F06  
Figure 6. LTC1267-ADJ/LTC1267-ADJ5  
External Feedback Network  
3. I2R losses are easily predicted from the DC resistances  
of the MOSFET, inductor, and current shunt. In continu-  
ous mode all the output current flows through L and  
RSENSE, but is “chopped” between the P-channel and N-  
channel MOSFETs. If the two MOSFETs have approxi-  
mately the same RDS(ON), then the resistance of one  
MOSFET can simply be summed with the resistances of  
L and RSENSE to obtain I2R losses. For example, if each  
RDS(ON) = 0.1, RL = 0.15, and RSENSE = 0.05, then  
the total resistance is 0.3. This results in losses  
rangingfrom3%to12%astheoutputcurrentincreases  
from 0.5A to 2A. I2R losses cause the efficiency to roll  
off at high output currents.  
Efficiency Considerations  
The percent efficiency of a switching regulator is equal to  
the output power divided by the input power times 100%.  
It is often useful to analyze individual losses to determine  
what is limiting the efficiency and which change would  
produce the most improvement. Percent efficiency can be  
expressed as:  
% Efficiency = 100% – (L1 + L2 + L3 + ...)  
where L1, L2, etc., are the individual losses as a percent-  
ageofinputpower. (Forhighefficiencycircuits, onlysmall  
errors are incurred by expressing losses as a percentage  
of output power.)  
Although all dissipative elements in the circuit produce  
losses, four main sources usually account for most of the  
losses in LTC1267 circuits:  
4. Transition losses apply only to the P-channel MOSFET  
andonlywhenoperatingathighinputvoltages(typically  
20V or greater). Transition losses can be estimated  
from:  
1. LTC1267 VIN current  
2. LTC1267 VCC current  
3. I2R losses  
Transition Loss 5 × VIN2 × IMAX × CRSS × fO  
Other losses including CIN and COUT ESR dissipative  
losses, Schottky conduction losses during dead-time,  
4. P-channel transition losses  
12  
LTC1267  
LTC1267-ADJ/LTC1267-ADJ5  
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APPLICATIO S I FOR ATIO  
and inductor core losses, generally account for less  
than 2% total additional loss.  
75  
MAX  
R
mΩ  
SENSE  
I
To prevent noise spikes from erroneously tripping the  
current comparator, a 1000pF capacitor is needed across  
Sense+ and Sensepins.  
Auxiliary Windings––Suppressing Burst Mode  
Operation  
The LTC1267 synchronous switch removes the normal  
limitation that power must be drawn from the inductor  
primary winding in order to extract power from auxiliary  
windings. With synchronous switching, auxiliary outputs  
may be loaded without regard to the primary output load,  
providing that the loop remains in continuous mode  
operation.  
Board Layout Checklist  
When laying out the printed circuit board, the following  
checklist should be used to ensure proper operation of the  
LTC1267. These items are also illustrated graphically in  
the layout diagram of Figure 8. In general each block  
should be self-contained with little cross coupling for best  
performance. Check the following in your layout:  
Burst Mode operation can be suppressed at low output  
currents with a simple external network which cancels the  
25mV minimum current comparator threshold. This tech-  
nique is also useful for eliminating audible noise from  
certain types of inductors in high current (IOUT > 5A)  
applications when they are lightly loaded.  
An external offset is put in series with the Sensepin to  
subtract from the built-in 25mV offset. An example of this  
technique is shown in Figure 7. Two 100resistors are  
inserted in series with the sense leads from the sense  
resistor.  
1. Are the signal and power grounds segregated? The  
LTC1267 signal ground must return tothe (–) plate of  
C
. The power ground returns to the source of the  
OUT  
N-channel MOSFET, anode of the Schottky diode,  
and (–) plate of C , which should have as short lead  
IN  
lengths as possible.  
2. DoestheLTC1267Sensepinconnecttoapointclose  
to RSENSE and the (+) plate of COUT? In adjustable  
applications the resistive divider R1 and R2 must be  
connected between the (+) plate of COUT and signal  
ground.  
3. Are the Senseand Sense+ leads routed together with  
minimum PC trace spacing? The 1000pF capacitor  
between the two Sense pins should be as close as  
possible to the LTC1267. Up to 100may be placed in  
series with each Sense lead to help decouple the Sense  
pins. However, when these resistors are used the  
capacitor should be no larger than 1000pF.  
R
SENSE  
L
+
R2  
C
OUT  
100Ω  
+
SENSE  
LTC1267  
SENSE  
R1  
100Ω  
1000pF  
R3  
LTC1267 • F07  
Figure 7. Suppressing Burst Mode Operation  
With the addition of R3 a current is generated through R1  
causing an offset of:  
4. Does the (+) plate of CIN connect to the source of the  
P-channel MOSFET as closely as possible? An addi-  
tional 0.1µF ceramic capacitor between VIN and power  
ground may be required in some applications.  
R1  
V
= V  
OUT  
OFFSET  
)
)
R1 + R3  
5. Is the VCC decoupling capacitor connected closely  
between the VCC pins of the LTC1267 and power  
ground? This capacitor carries the MOSFET driver peak  
currents.  
If VOFFSET > 25mV, the built-in offset will be cancelled and  
Burst Modeoperation is prevented from occurring. Since  
VOFFSET is constant, the maximum load current is also  
decreased by the same offset. Thus, to get back to the  
same IMAX, the value of the sense resistor must be  
reduced:  
13  
LTC1267  
LTC1267-ADJ/LTC1267-ADJ5  
U U  
W
U
APPLICATIO S I FOR ATIO  
V
IN  
1
2
3
4
5
6
7
8
9
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
V
1N4148  
CC  
EXT V  
CC  
1N4148  
N-CH  
MSHDN  
0.15µF  
V
MSHDN  
CAP5  
IN  
0.15µF  
0.1µF  
CAP3  
P-CH  
P-CH  
PGATE 3  
PDRIVE 3  
NGATE 3  
PGND3  
PGATE 5  
PDRIVE 5  
NGATE 5  
PGND5  
0.1µF  
N-CH  
D5  
D3  
L5  
C
C
C
IN5  
IN3  
L3  
1µF  
1µF  
+
V
V
CC5  
CC3  
+
LTC1267  
C
I
SGND5  
T3  
3300pF  
1k  
10  
11  
12  
13  
14  
SHDN5  
+
SHDN5  
C
THR3  
T3  
T5  
C
C
OUT3  
OUT5  
R
SENSE3  
R
SENSE5  
+
SGND3  
SENSE 5  
1000pF  
SHDN3  
SHDN3  
SENSE  
5
V
OUT5  
SENSE  
3
C
BOLD LINES INDICATE HIGH CURRENT PATHS  
T5  
3300pF  
1000pF  
1k  
+
LTC1267 • F08  
SENSE 3  
I
THR5  
V
OUT3  
Figure 8. LTC1267 Layout Diagram  
6. In adjustable versions, the feedback pin is very sensi-  
tive to pickup from the switch node. Care must be taken  
to isolate VFB1, 2 from possible capacitive coupling of  
the inductor switch signal.  
If the CT is observed falling to ground at high output  
currents,itindicatespoordecouplingorimproperground-  
ing. Refer to the Board Layout Checklist.  
Inductor current should also be monitored. Look to verify  
that the peak-to-peak ripple current in continuous mode  
operation is approximately the same as in Burst Mode  
operation.  
7. Are MSHDN and SHDN1, 3, 5 actively pulled to ground  
during normal operation? These shutdown pins are  
high impedance and must not be allowed to float.  
3.3V  
Troubleshooting Hints  
Since efficiency is critical to LTC1267 applications, it is  
very important to verify that the circuit is functioning  
correctly in both continuous and Burst Mode operation.  
The waveform to monitor is the voltage on the CT pin.  
0V  
(a) CONTINUOUS MODE OPERATION  
3.3V  
In continuous mode (ILOAD > IBURST) the voltage on the CT  
pin should be a sawtooth with a 0.9VP-P swing. This  
voltage should never dip below 2V as shown in Figure 9a.  
0V  
LTC1267 • F09  
(b) Burst Mode OPERATION  
Figure 9. CT Waveforms  
When load currents are low (ILOAD < IBURST) Burst Mode  
operation occurs. The voltage on the CT pin now falls to  
ground for periods of time as shown in Figure 9b.  
14  
LTC1267  
LTC1267-ADJ/LTC1267-ADJ5  
U
TYPICAL APPLICATIONS N  
LTC1267-ADJ Dual Regulator with 3.6V/2.5A and 5V/2A Outputs  
V
IN  
5.4V to 25V  
+
C
IN2  
+
C
IN1  
100µF  
100µF  
50V  
50V  
+
0.15µF  
0.15µF  
+
3.3µF  
1N4148  
1N4148  
3.3µF  
3
1
7
2
27  
26  
28  
21  
P-CH  
P-CH  
Si9435DY  
Si9435DY  
L1  
20µH  
V
CAP1  
V
V
MSHDN CAP2 EXT V  
V
CC CC2  
CC1  
CC  
IN  
4
5
25  
24  
18  
L2  
33µH  
R
R
SENSE2  
0.05Ω  
SENSE1  
0.04Ω  
0.1µF  
PGATE 1  
PGATE 2  
0.1µF  
V
V
OUT2  
OUT1  
3.6V  
2.5A  
PDRIVE 1  
+
PDRIVE 2  
+
5V  
2A  
13  
SENSE  
1
1
SENSE  
2
1000pF  
1000pF  
LTC1267-ADJ  
17  
23  
22  
12  
11  
6
SENSE  
2
SENSE  
NGATE 2  
PGND2  
SHDN1  
D1  
D2  
NGATE 1  
MBRS140T3  
MBRS140T3  
N-CH  
Si9410DY  
C
V
SGND1  
10  
C
I
I
SGND2  
20  
V
T2  
FB1  
T1  
8
TH1  
9
TH2  
FB2  
N-CH  
C
OUT2  
220µF  
10V  
× 2  
C
OUT1  
+
+
Si9410DY  
220µF  
10V  
14  
15  
16  
19  
R2  
100k  
1%  
R2  
150k  
1%  
100pF  
100pF  
× 2  
C
C
C2  
C
C
T2  
270pF  
C1  
T1  
3300pF 3300pF  
270pF  
R1  
52.3k  
1%  
R1  
49.9k  
1%  
R
R
C2  
C1  
1k  
1k  
LTC1267 • F010  
R
: KRL SL-1R040J  
MSHDN, SHDN1  
0V = NORMAL, >2V = SHDN  
R
: KRL SL-1R050J  
SENSE1  
SENSE2  
L1: COILTRONICS CTX20-4  
L2: COILTRONICS CTX33-4  
LTC1267-ADJ5 Dual Regulator with 3.45V/2.5A and 5V/2A Outputs  
V
IN  
5.4V to 25V  
+
C
IN2  
+
C
IN1  
100µF  
100µF  
50V  
50V  
+
0.15µF  
0.15µF  
+
3.3µF  
1N4148  
1N4148  
3.3µF  
3
1
7
2
27  
26  
28  
21  
P-CH  
P-CH  
Si9435DY  
Si9435DY  
V
CAP1  
V
V
MSHDN CAP5 EXT V  
V
CC CC5  
CC1  
CC  
IN  
4
5
25  
24  
18  
L2  
33µH  
L1  
R
R
SENSE2  
0.05Ω  
SENSE1  
0.04Ω  
0.1µF  
PGATE 1  
PGATE 5  
0.1µF  
20µH  
V
V
5V  
2A  
OUT1  
OUT2  
PDRIVE 1  
+
PDRIVE 5  
+
3.45V  
2.5A  
13  
SENSE  
1
1
SENSE  
5
1000pF  
1000pF  
LTC1267-ADJ5  
17  
19  
23  
12  
11  
6
SENSE  
5
SENSE  
SHDN5  
NGATE 5  
SHDN1  
D1  
MBRS140T3  
D2  
NGATE 1  
MBRS140T3  
N-CH  
Si9410DY  
N-CH  
Si9410DY  
C
V
SGND1  
10  
C
I
I
TH5  
SGND5 PGND  
T5  
FB1  
T1  
8
TH1  
9
C
C
OUT2  
OUT1  
+
+
220µF  
220µF  
10V  
14  
15  
16  
20  
22  
R2  
100k  
1%  
10V  
× 2  
100pF  
× 2  
C
C
C5  
C
C
T5  
270pF  
C1  
T1  
3300pF 3300pF  
270pF  
R1  
56.2k  
1%  
R
R
C5  
C1  
1k  
1k  
LTC1267 • F011  
R
: KRL SL-1R040J  
MSHDN, SHDN1, SHDN5  
0V = NORMAL, >2V = SHDN  
R
: KRL SL-1R050J  
SENSE1  
SENSE2  
L1: COILTRONICS CTX20-4  
L2: COILTRONICS CTX33-4  
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.  
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-  
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.  
15  
LTC1267  
LTC1267-ADJ/LTC1267-ADJ5  
U
Dimensions in inches (millimeters) unless otherwise noted.  
PACKAGE DESCRIPTIO  
G Package  
28-Lead Plastic SSOP  
0.397 – 0.407*  
(10.07 – 10.33)  
0.205 – 0.212*  
(5.20 – 5.38)  
0.068 – 0.078  
(1.73 – 1.99)  
28 27 26 25 24 23 22 21 20 19 18  
16 15  
17  
0° – 8°  
0.301 – 0.311  
(7.65 – 7.90)  
0.0256  
(0.65)  
BSC  
0.005 – 0.009  
(0.13 – 0.22)  
0.022 – 0.037  
(0.55 – 0.95)  
0.010 – 0.015  
(0.25 – 0.38)  
0.002 – 0.008  
(0.05 – 0.21)  
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.  
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006 INCH (0.15mm).  
5
7
8
1
2
3
4
6
9 10 11 12 13 14  
28SSOP 0694  
RELATED PARTS  
PART NUMBER DESCRIPTION  
COMMENTS  
LTC1142  
LTC1143  
LTC1147  
LTC1148  
LTC1149  
LTC1159  
LTC1174  
LTC1265  
LTC1266  
LTC1574  
Dual Step-Down Switching Regulator Controller  
Dual Step-Down Switching Regulator Controller  
Step-Down Switching Regulator Controller  
Dual Version of LTC1148  
Dual Version of LTC1147  
Nonsynchronous, 8-Pin, V 16V  
IN  
Step-Down Switching Regulator Controller  
Synchronous, V 20V  
IN  
Step-Down Switching Regulator Controller  
Synchronous, V 48V, for Standard Threshold FETs  
IN  
Step-Down Switching Regulator Controller  
Synchronous, V 40V, for Logic Level FETs  
IN  
Step-Down Switching Regulator with Internal 0.5A Switch  
Step-Down Switching Regulator with Internal 1A Switch  
Step-Up/Down Switching Regulator Controller  
V
V
18.5V, Comparator/Low Battery Detector  
13V, Comparator/Low Battery Detector  
IN  
IN  
Synchronous N- or P-Channel FETs, Comparator/Low Battery Detector  
18.5V, Comparator  
Step-Down Switching Regulator with Internal 0.5A Switch  
and Schottky Diode  
V
IN  
LT/GP 0695 10K • PRINTED IN USA  
Linear Technology Corporation  
1630 McCarthy Blvd., Milpitas, CA 95035-7487  
16  
LINEAR TECHNOLOGY CORPORATION 1995  
(408) 432-1900 FAX: (408) 434-0507 TELEX: 499-3977  

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