LTC1264 [Linear]
High Speed, Quad Universal Filter Building Block; 高速，四路通用滤波器积木
| 型号： | LTC1264 |
| 厂家： | 
Linear |
| 描述： | High Speed, Quad Universal Filter Building Block |
| 文件： | 总16页 (文件大小：346K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1264
High Speed, Quad Universal
Filter Building Block
U
DESCRIPTIO
EATURE
S
F
The LTC®1264 consists of four identical, high speed 2nd
order switched-capacitor filter building blocks designed
for center frequencies up to 250kHz. Each building block,
together with three to five resistors, can provide 2nd order
functions like lowpass, highpass, bandpass and notch.
Thecenterfrequencyofeach2ndordersectionistunedvia
an external clock. The clock-to-center frequency ratio is
internally set to 20:1, but it can be modified via external
resistors.
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■
■
■
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High Speed, Up to 250kHz Center Frequency
Four Identical Filters in a 0.3" Wide Package
Clock-to-Center Frequency Ratio of 20:1
Double-Sampling, Improved Aliasing
Operates from ±2.37V to ±8V Power Supplies
Customized Version with Internal Resistors Available
Low Noise
Low Harmonic Distortion
O U
The aliasing performance of the LTC1264 is improved by
double-sampling each 2nd order section. Input signal
frequencies can reach up to twice the clock frequency
before any alias products will be detectable.
PPLICATI
S
A
■
■
■
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Digital Communications
Spread Spectrum Communications
Spectral Analysis
Loran Receivers
Instrumentation
For Q ≤ 5 and for TA < 85°C, the maximum center
frequency is 160kHz. For Q ≤ 2, the maximum center
frequency is 250kHz. Up to 8th order filters can be realized
by cascading all four 2nd order sections.
A customized monolithic version of the LTC1264 includ-
ing internal thin film resistors can be obtained.
, LTC and LT are registered trademarks of Linear Technology Corporation.
U
O
TYPICAL APPLICATI
Clock-Tunable 8th Order Bandpass Filter, fCENTER = fCLK/20
50k
Gain vs Frequency
50k
100kHz Bandpass, f–3dB Bandwidth = fCENTER/10
IN
INV B
HPB/NB
BPB
INV C
HPC/NC
BPC
10k
50k
10k
50k
10
0
MAXIMUM POWER
CENTER
LPB
LPC
–10
–20
–30
–40
–50
f
SUPPLY
SB
SC
160kHz
120kHz
60kHz
±7.5V
±5V
Single 5V
LTC1264
–
AGND
V
0.1µF
+
f
V
CLK
SD
CLK
0.1µF
SA
LPA
LPD
–60
OUT
50k
10k
BPA
BPD
–70
50k
10k
HPA/NA
INV A
HPD/ND
INV D
–80
10k
100k
1M
FREQUENCY (Hz)
1264 TA02
50k
50k
1264 TA01
1
LTC1264
W W W
U
/O
ABSOLUTE AXI U RATI GS
PACKAGE RDER I FOR ATIO
Total Supply Voltage (V+ to V–) .............................. 16V
Input Voltage (Note 2) ........... (V+ + 0.3V) to (V– – 0.3V)
Output Short-Circuit Duration.......................... Indefinite
Power Dissipation............................................. 400mW
Burn-In Voltage ...................................................... 16V
Operating Temperature Range ............... –40°C to 85°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
TOP VIEW
ORDER PART
NUMBER
INV B
HPB/NB
BPB
1
2
INV C
HPC/NC
BPC
24
23
22
21
20
19
18
17
16
15
14
13
3
LTC1264CN
LTC1264CS
LPB
4
LPC
SB
5
SC
–
AGND
6
V
+
V
7
CLK
SA
LPA
8
SD
9
LPD
BPA
10
11
12
BPD
HPA/NA
INV A
HPD/ND
INV D
N PACKAGE
S PACKAGE
24-LEAD PLASTIC DIP 24-LEAD PLASTIC SOL
TJMAX = 110°C, θJA = 65°C/W (N)
T
JMAX = 110°C, θJA = 85°C/W (S)
Consult factory for Industrial and Military grade parts.
ELECTRICAL CHARACTERISTICS
(Internal Op Amps) TA = 25°C, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Operating Supply Range
Voltage Swings
±2.375
±8
V
V
V
V
V = ±2.375V, R = 5k
±1.5
±3.7
S
L
V = ±5V, R = 5k
±3.2
±3.1
S
L
●
V = ±7.5, R = 5k
±6
3
V
mA
S
L
Output Short-Circuit Current (Source/Sink)
DC Open-Loop Gain
GBW Product
80
7
10
dB
MHz
V/µs
Slew Rate
(Complete Filter) VS = ±5V, fCLK = 1MHz, all sides mode 1, fO = 50kHz, Q = 5, TA = 25°C, unless otherwise noted.
PARAMETER
Center Frequency Range, f (Note 1)
CONDITIONS
V = ±7.5V, T < 85°C, Q < 2
MIN
TYP
MAX
UNITS
0.1 - 250
0.1 - 200
0.1 - 100
kHz
kHz
kHz
O
S
A
V = ±5V, T < 85°C, Q < 2
S
A
V = ±2.5V, T < 85°C, Q < 2
S
A
Clock-to-Center Frequency Ratio, f /f
20:1
CLK
O
Center Frequency Error (Note 3)
V = ±7.5V
±0.1
± 0.7
±0.8
±0.8
±1.0
%
%
%
%
S
●
●
V = ±5V
S
±0.2
V = ±2.375V
V ≥ ±5V
S
–1.6
0.4
%
%
%
%
%
S
Clock-to-Center Frequency Ratio,
Side-to-Side Matching
Q Accuracy
0.8
1.0
●
●
V = ±5V
S
–2.7
7.0
f Temperature Coefficient
Q Temperature Coefficient
f
f
< 2MHz
< 2MHz
±1
5
ppm/°C
ppm/°C
O
CLK
CLK
2
LTC1264
ELECTRICAL CHARACTERISTICS
(Complete Filter) VS = ±5V, fCLK = 1MHz, all sides mode 1, fO = 50kHz, Q = 5, TA = 25°C, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DC Offset Voltage (Note 2)
V
V
V
(DC Offset of Input Inverter)
(DC Offset of First Integrator)
(DC Offset of Second Integrator)
●
●
●
±20
±45
±45
mV
mV
mV
OS1
OS2
OS3
Clock Feedthrough
V = ±7.5V (f
is a Square Wave)
is a Square Wave)
160
120
90
µV
µV
µV
S
CLK
RMS
RMS
RMS
V = ±5V (f
S
CLK
V = ±2.375V (f
S
is a Square Wave)
CLK
Maximum Clock Frequency
Power Supply Current
V = ±7.5V, T = 25°C
V = ±5V
S
6
14
MHz
mA
mA
S
A
9
23
26
●
The
● denotes specifications which apply over the full operating
Note 3: The center frequency f , error is calculated as:
O
temperature range.
Note 1: Please refer to Typical Maximum Q vs Clock Frequency graphs.
Note 2: Calculations of output DC offsets of one 2nd order section. Also
f (measured) – f (ideal)
O
O
• 100
f (ideal)
O
see Block Diagram.
V
V
V
OSLP
PINS 4, 9, 16, 21
OSN
OSBP
MODE
PINS 2, 11, 14, 23
PINS 3, 10, 15, 22
1
1b
2
V
V
[(1Q) + 1 ||H ||] – V /Q
V
V
V
V
– V
OSN OS2
OS1
OS1
OLP
OS3
OS3
OS3
OS3
[(1/Q) + 1 + R2/R1] – V /Q
≈(V
– V )(1 + R5/R6)
OSN OS2
OS3
[V (1 + R2/R1 + R2/R3 + R2/R4) – V (R2/R3)]
• [R4/(R2 + R4)] + V [R2/(R2 + R4)]
V
– V
OSN OS2
OS1
OS3
OS2
3
V
V
V
[1 + R4/R1 + R4/R2 + R4/R3] – V (R4/R2)
OS1 OS2
OS3
OS2
OS3
– V (R4/R3)
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Typical Maximum Q
vs Clock Frequency
Typical Maximum Q
vs Clock Frequency
Typical Maximum Q
vs Clock Frequency
26
24
22
20
18
16
14
12
10
8
26
24
22
20
18
16
14
12
10
8
20
18
16
14
12
10
8
A
A
A
V
T
= ±7.5V
V
T
= ±5V
S
A
V
T
= SINGLE 5V
≤ 85°C
S
A
S
A
≤ 85°C
≤ 85°C
A. MODES 1, 1b
B. MODES 3, 3a
A. MODES 1, 1b
B. MODES 3, 3a
A. MODES 1, 1b
B. MODES 3, 3a
B
B
B
6
6
4
2
6
4
2
4
2
0
0
0
1.5
2.5 3.0 3.5
4.0 4.5 5.0
1.0
2.0
2.5
3.0
3.5
4.0
2.0
1.5
1.0
1.2
1.4
1.6
1.8
2.0
CLOCK FREQUENCY (MHz)
CLOCK FREQUENCY (MHz)
CLOCK FREQUENCY (MHz)
1264 G01
1264 G02
1264 G03
3
LTC1264
TYPICAL PERFOR A CE CHARACTERISTICS
U W
Typical Bandpass Gain Error
vs Clock Frequency
Typical Bandpass Gain Error
vs Clock Frequency
Typical Bandpass Gain Error
vs Clock Frequency
5
4
3
2
1
0
5
4
3
2
1
0
5
4
3
2
1
0
MODE 1
Q = 4
MODE 1
MODE 1
Q = 2
V
= SINGLE 5V
S
T
= 25°C
TA = 25°C
T
= 25°C
A
A
V
= ±5V
S
V
= ±5V
Q = 4
Q = 2
S
V
= ±7.5V
S
V
= ±7.5V
S
2.0
2.4
2.8
3.2
3.6
4.0
2.0
2.4
2.8
3.2
3.6
4.0
1.3 1.4 1,5 1.6
1.7 1.8
1.9 2.0
CLOCK FREQUENCY (MHz)
CLOCK FREQUENCY (MHz)
CLOCK FREQUENCY (MHz)
1264 G05
1264 G04
1264 G06
Typical Bandpass Gain Error
vs Clock Frequency
Ratio (fCLK/fO) vs
Clock Frequency
5
4
3
2
1
0
20.5
20.4
20.3
20.2
20.1
20.0
19.9
19.8
19.7
19.6
BANDPASS OUT
MODE 1
V = ±7.5V
S
MODE 3
Q = 4
A
V = ±5V
S
T
= 25°C
V
S
= SINGLE 5V
Q = 10
Q = 4
V
= ±7.5V
S
Q = 2
19.5
1
2
3
1
4
2
3
4
CLOCK FREQUENCY (MHz)
CLOCK FREQUENCY (MHz)
1264 G15
1264 G11
Power Supply Current
vs Supply Voltage
Noise vs R2/R4 Ratio
48
44
40
36
32
28
24
20
16
12
8
600
500
400
300
200
100
0
MODE 3
= ±7.5V
V
S
Q = 2
f
R2
CLK
f
=
O
20 R4
√
–55°C
25°C
125°C
4
0
0
2
4
6 8 10 12 14 16 18 20 22 24
0
0.2
0.4
0.6
0.8
1.0
+
–
POWER SUPPLY VOLTAGE (V – V )
RESISTOR RATIO (R2/R4)
1264 G12
1264 G14
4
LTC1264
U
U
U
PI FU CTIO S
V +,V–(Pins7,19):PowerSupplyPins.TheV+ (Pin7)and
the V– (Pin 19) should each be bypassed with a 0.1µF
capacitor to an adequateanalogground. The filter’s power
supplies should be isolated from other digital or high
voltage analog supplies. A low noise linear supply is
recommended. Using a switching power supply will lower
the signal-to-noise ratio of the filter. The supply during
power-up should have a slew rate less than 1V/µs. When
V+ is applied before V– and V– is allowed to go above
ground, a diode should clamp V– to prevent latch-up.
Figures 1 and 2 show typical connections for dual and
single supply operation.
AGND (Pin 6): Analog Ground Pin. The filter performance
depends on the quality of the analog signal ground. For
either dual or single supply operation, an analog ground
plane surrounding the package is recommended. The
analog ground plane should be connected to any digital
ground at a single point. For dual supply operation, Pin 6
should be connected to the analog ground plane. For
single supply operation, Pin 6 should be biased at 1/2
supplyandshouldbebypassedtotheanaloggroundplane
with at least a 1µF capacitor (Figure 2). For single 5V
operation and fCLK greater than 1MHz, pin 6 should be
biased at 2V. This minimizes passband gain and phase
variations.
1
2
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
17
16
15
14
13
ANALOG
GROUND
PLANE
ANALOG
GROUND
PLANE
3
–7.5V
4
*
5k
+
5
*
*
*
*
V
0.1µF
+
6
V /2
+
LTC1264
7
LTC1264
+
5k
V
7.5V
1µF
8
0.1µF
9
10
11
12
10
11
12
DIGITAL
GROUND
PLANE
DIGITAL
GROUND
PLANE
STAR
SYSTEM
GROUND
STAR
SYSTEM
GROUND
200Ω
200Ω
CLOCK
SOURCE
CLOCK
SOURCE
1264 F01
*
OPTIONAL, 1N4148, 1N5819
1264 F02
*
FOR MODE 3, THE S NODE PINS 5, 8,
17, 20 SHOULD BE TIED TO PIN 6
Figure 1. Dual Supply Ground Plane Connections
Figure 2. Single Supply Ground Plane Connections
5
LTC1264
U
U
U
PI FU CTIO S
CLK (Pin 18): Clock Input Pin. Any TTL or CMOS clock
source with a square wave output and 50% duty cycle
(±10%) is an adequate clock source for the device. The
powersupplyfortheclocksourceshouldnotbethefilter’s
power supply. The analog ground for the filter should be
connected to clock’s ground at a single point only. Table
1showstheclock’slowandhighlevelthresholdvaluesfor
a dual or single supply operation.
HPB/NB, BPB, LPB, LPA, BPA, HPA, HPD, BPD, LPD,
LPC, BPC, HPC/NC (Pins 2, 3, 4, 9, 10, 11, 14, 15, 16,
21, 22, 23): Output Pins. Each 2nd order section of the
LTC1264 has three outputs which typically source 3mA
andsink1mA.Drivingcoaxialcablesorresistiveloadsless
than 20k will degrade the total harmonic distortion perfor-
mance of any filter design. When evaluating the distortion
or noise performance of a particular filter design imple-
mented with an LTC1264, the final output of the filter
should be buffered with a wideband noninverting high
slew rate amplifier (Figure 3).
Table 1. Clock Source High and Low Threshold Levels
POWER SUPPLY
HIGH LEVEL
LOW LEVEL
Dual Supply = ±7.5V
Dual Supply = ±5V
Dual Supply = ±2.5V
Single Supply = 12V
Single Supply = 5V
≥ 2.18V
≥ 1.45V
≥ 0.73V
≥ 7.80V
≥ 1.45V
≤ 0.5V
≤ 0.5V
≤ –2.0V
≤ 6.5V
≤ 0.5V
–
LT1224
5k
+
A pulse generator can be used as a clock source provided
thehighlevelon-timeisgreaterthan0.2µs.Sinewavesare
not recommended for clock input frequencies less than
100kHz, since excessively slow clock rise or fall times
generate internal clock jitter (maximum clock rise or fall
time ≤1µs). The clock signal should be routed from the
rightsideoftheICpackageandperpendiculartoittoavoid
couplingtoanyinputoroutputanalogsignalpath. A200Ω
resistor between clock source and Pin 11 will slow down
the rise and fall times of the clock to further reduce charge
coupling (Figures 1 and 2).
1264 F03
Figure 3. Wideband Buffer
INV B, INV A, INV D, INV C (Pins 1, 12, 13, 24): Inverting
Input Pins. These pins are the high impedance inverting
inputsofinternalopampsandtheyaresusceptibletostray
capacitive connections to low impedance signal outputs
and power supply lines.
SB, SA, SD, SC (Pins 5, 8, 17, 20): Summing Input Pins.
The summing pins connections determine the circuit
topology (mode) of each 2nd order section. Please refer to
Modes of Operation.
W
U
ODES OF OPERATIO
For the definition of filter functions please refer to the
LTC1060 data sheet.
Please refer to the Maximum Frequency of Operation
paragraph under Applications Information for a guide to
the use of capacitor CC.
Mode 1
Mode 1b
In Mode 1, the ratio of the external clock frequency to the
center frequency of each 2nd order section is internally
fixed at 20:1. Figure 4 illustrates Mode 1 providing 2nd
order notch, lowpass, and bandpass outputs. Mode 1 can
be used to make high order Butterworth lowpass filters; it
can also be used to make low Q notches and for cascading
2nd order bandpass functions tuned at the same center
frequency. Mode 1 is faster than Mode 3.
Mode1bisderivedfromMode1.InMode1b(Figure5)two
additional resistors R5 and R6 are added to alternate the
amount of voltage fed back from the lowpass output into
the input of the SA (SB, SC or SD) switched-capacitor
summer. This allows the filter’s clock-to-center frequency
ratio to be adjusted beyond 20:1. Mode 1b maintains the
speed advantages of Mode 1 and should be considered an
6
LTC1264
W
U
ODES OF OPERATIO
optimum mode for high Q designs with fCLK to fCUTOFF (or
fCENTER) ratios greater than 20:1.
Mode 3
In Mode 3, the ratio of the external clock frequency to the
center frequency of each 2nd order section can be
adjusted above or below 20:1. Figure 6 illustrates Mode 3,
the classical state variable configuration, providing high-
pass, bandpass, and lowpass 2nd order filter functions.
Mode 3 is slower than Mode 1. Mode 3 can be used to
make high order all-pole bandpass, lowpass, and high-
pass filters.
Please refer to the Maximum Frequency of Operation
paragraph under Applications Information for a guide to
the use of capacitor CC.
C
C
R3
R2
Please refer to the Maximum Frequency of Operation
paragraph under Applications Information for a guide to
the use of capacitor CC.
N
S
LP
BP
R1
V
–
IN
–
+
Σ
∫
∫
Mode 2
1264 F04
+
1/4 LTC1264
Mode 2 is a combination of Mode 1 and Mode 3, shown in
Figure7.WithMode2,theclock-to-centerfrequencyratio,
fCLK/fO, is always less than 20:1. The advantage of Mode
2 is that it provides less sensitivity to resistor tolerances
than does Mode 3. As in Mode 1, Mode 2 has a notch
output which depends on the clock frequency, and the
notch frequency is therefore less than the center fre-
quency, fO.
f
AGND
CLK
20
f =
i
; f = f ; f = f
O
i
n
O
R2
R3
R1
R3
R2
Q =
; H = – ; H
= –
OBP
ON
R1
H
= H
ON
OLP
Figure 4. Mode 1, 2nd Order Filter Providing Notch,
Bandpass and Lowpass Outputs
Please refer to the Maximum Frequency of Operation
paragraph under Applications Information for a guide to
the use of capacitor CC.
C
C
R6
N
R5
C
C
R3
R2
R4
R3
R2
S
LP
BP
R1
V
–
IN
–
+
HP
S
Σ
LP
BP
∫
∫
1264 F05
+
1/4 LTC1264
R1
V
–
+
IN
–
NOTE: R5 ≤ 5k
+
AGND
Σ
∫
∫
f
CLK
20
R6
(R6 + R5)
f =
i
; f = f
O
; f = f
n O
i
1264 F06
√
1/4 LTC1264
R2
R3
R1
R3
R6
Q =
; H = –
ON
; H
= –
OBP
R1
R2 (R6 + R5)
√
f
1
CLK
20
R2
R4
R2
R3
AGND
f =
i
; f = f
O
; Q = 1.005
i
R2 R6 + R5
R1
(
)
R4
R2
√
R3
√
H
= –
OLP
1 –
(
)
R6
(
)
6.42•R4
R3
R1
R2
1
R3
R4
= –
H
= –
; H
OBP
= –
;
H
OLP
OHP
R1
R1
1 –
(
)
Figure 5. Mode 1b, 2nd Order Filter Providing Notch,
Bandpass and Lowpass Outputs
6.42•R4
Figure 6. Mode 3, 2nd Order Section Providing
Highpass, Bandpass and Lowpass Outputs
7
LTC1264
W
U
ODES OF OPERATIO
C
C
tors RH and RL to create a notch. This is shown in Figure
8. Mode 3a is more versatile than Mode 2 because the
notch frequency can be higher or lower than the center
frequency of the 2nd order section. The external op amp
of Figure 8 is not always required. When cascading the
sections of the LTC1264, the highpass and lowpass
outputs can be summed directly into the inverting input of
the next section.
R4
R3
R2
N
S
LP
BP
R1
V
–
+
IN
–
+
Σ
∫
∫
1264 F07
Please refer to the Maximum Frequency of Operation
paragraph under Applications Information for a guide to
the use of capacitor CC.
1/4 LTC1264
AGND
f
CLK
20
R2
R4
f =
; f = f
O
; f = f
1 +
i
i
n
O
√
Mode 2n
R3
R2
R2
1
Q = 1.005
1 +
(
)
√
R4
R3
6.42•R4
1 –
(
)
R2
R1
This mode extends the circuit topology of Mode 3a to
Mode 2 (Figure 9) where the highpass notch and lowpass
outputs are summed through two external resistors RH
and RL to create a lowpass output with a notch higher in
frequency than the notch in Mode 2. This mode, shown in
Figure 8, is most useful in lowpass elliptic designs. When
cascading the sections of the LTC1264, the highpass
notch and lowpass outputs can be summed directly into
the inverting input of the next section.
R2
R1
1
H
= –
= –
(AC GAIN, f > f ); H
= –
OHPn
(DC GAIN, f < f )
OHP
n
n
R2
1 +
(
)
R4
R3
R1
1
R3
H
; H = H
OLP OHPn
OBP
1 –
(
)
6.42•R4
Figure 7. Mode 2, 2nd Order Filter Providing
Highpass Notch, Bandpass and Lowpass Outputs
Mode 3a
Please refer to the Maximum Frequency of Operation
paragraph under Applications Information for a guide to
the use of capacitor CC.
This is an extension of Mode 3 where the highpass and
lowpass output are summed through two external resis-
C
C
f
R2
R4
R4
R3
CLK
20
R
H
f =
; f = f
n
f = f
; O i
i
i
√
1
√
R
L
R2
R4
R3
Q = 1.005
(
)
R2
√
R3
6.42•R4
R2
1 –
(
)
HP
S
LP
R
BP
R
R
R
G
R2
R1
R4
R1
G
H
R1
H
(f = ∞) =
; H
(f = 0) =
OLPn
OHPn
(
)
(
)
(
)
(
)
V
IN
R
–
L
–
R
G
+
Σ
∫
∫
L
+
–
+
HIGHPASS
OR LOWPASS
NOTCH OUTPUT
1/4 LTC1264
R
H
AGND
EXTERNAL OP AMP OR
INPUT OP AMP OF THE
LTC1264, SIDES A, B, C, D
1264 G08
Figure 8. Mode 3a, 2nd Order Filter Providing a Highpass Notch or Lowpass Notch Output
8
LTC1264
W
U
ODES OF OPERATIO
C
C
f
CLK
20
R
H
f =
; f = f
n i
1 +
i
R4
R3
√
R
L
R2
R4
f
O
= f
i
1 +
√
R
R
R
R
1
R2
R1
G
G
H
(f = 0)=
+
OLPn
R2
(
)
(
)
R2
R4
H
L
HP
S
1 +
LP
R
BP
(
)
R1
R3
R2
R2
R4
1
R3
6.42•R4
Q = 1.005
1 +
V
IN
(
)
–
–
√
R
G
+
1 –
(
)
Σ
∫
∫
L
+
–
+
LOWPASS
NOTCH
OUTPUT
R
H
AGND
1/4 LTC1264
EXTERNAL OP AMP OR
INPUT OP AMP OF THE
LTC1264, SIDES A, B, C, D
1264 G09
Figure 9. Mode 2n, 2nd Order Filter Providing a Lowpass Notch Output
W
BLOCK DIAGRA
HPA/NA
11
BPA
10
LPA
9
+
7
V
INV A
12
6
–
+
18 CLK
–
+
+
+
+
+
+
+
+
+
+
+
+
Σ
–
∫
∫
∫
∫
∫
∫
∫
∫
19
V
AGND
INV B
8
SA
HPB/NB
2
LPB
4
BPB
3
1
–
Σ
–
5
SB
+
LPC
21
HPC/NC
23
BPC
22
INV C
24
13
–
+
Σ
–
20
SC
LPD
16
BPD
15
HPD/ND
14
INV D
–
+
Σ
–
17
1264 BD
SD
9
LTC1264
PPLICATI
O U
W
U
A
S I FOR ATIO
Operating Limits
feedthroughspecifications. Switchingtransientshavefre-
quency contents much higher than the applied clock; their
amplitude strongly depends on scope probing techniques
as well as grounding and power supply bypassing. The
clock feedthrough, if bothersome, can be greatly reduced
by adding a simple RC lowpass network at the final filter
output. This RC will completely eliminate any switching
transients.
The Typical Maximum Q vs Clock Frequency and Band-
pass Gain Error graphs, under Typical Performance Char-
acteristics, define an upper limit of operating Q for each
LTC1264 2nd order section. These graphs indicate the
power supply, fCLK and Q value conditions under which a
filter implemented with an LTC1264 will remain stable
when operated at temperatures of 85°C or less. For a 2nd
order section, a bandpass gain error of 3dB or less is
arbitrarily defined as a condition for stability.
Wideband Noise
The wideband noise of the filter is the total RMS value of
the device’s noise spectral density and it is used to
determine the operating signal-to-noise ratio. Most of its
frequency contents lie within the filter passband and it
cannot be reduced with post filtering.
When the passband gain error begins to exceed 1dB, the
use of capacitor CC will reduce the gain error (capacitor CC
is connected from the lowpass node to the inverting node
of a 2nd order section). Please refer to Figures 4 through
9. The value of CC can be best determined experimentally,
and as a guide it should be about 5pF for each 1dB of gain
error and not to exceed 15pF. When operating LTC1264
very near the limits defined by the Typical Performance
Characteristics graphs, passband gain variations of 2dB
or more should be expected.
Thetotalwidebandnoise(µVRMS)isnearlyindependentof
the value of the clock. The clock feedthrough specifica-
tions are not part of the wideband noise.
For a specific filter design, the total noise depends on the
Q of each section and the cascade sequence. Table 3
shows typical 2nd order section noise (gain = 1) for Q
values and supplies operating at 25°C. Noise increases by
20% at the highest operating temperatures.
Speed Limitations
To avoid op amp slew rate limiting, the signal amplitude
should be kept below a specified level as shown in Table 2.
Table 3. 2nd Order Section Noise (µVRMS) for Modes 1, 1b,
2 or 3 (R2 = R4)
Table 2. Maximum VIN vs VS and Clock
Q
V = ±2.5V
V = ±5V
V = ±7.5V
S
S
S
V
MAXIMUM CLOCK
MAXIMUM V
IN
S
1
2
3
4
5
40µV
50µV
60µV
75µV
90µV
50
60
75
90
110
60
75
95
115
135
RMS
RMS
RMS
RMS
RMS
±7.5V
±5V
Single 5V
4MHz to 5MHz
3MHz to 4MHz
1MHz to 2MHz
0.5V
0.5V
f
≥ 400kHz
≥ 250kHz
f ≥ 160kHz
RMS IN
f
RMS IN
0.35V
RMS IN
Clock Feedthrough
Aliasing
ClockfeedthroughisdefinedastheRMSvalueoftheclock
frequency and its harmonics that are present at the filter’s
output pins. The clock feedthrough is tested with the
filter’s input grounded and it depends on PC board layout
and on the value of the power supplies. With proper layout
techniques, the typical values of clock feedthrough are
listed under Electrical Characteristics.
Aliasingisaninherentphenomenonofswitched-capacitor
filters and it occurs when the frequency of input signals
approaches the sampling frequency. The input signals
that produce the strongest aliased components have a
frequency, fIN, such as (fSAMPLING – fIN) falls into the
filter’s passband. For the LTC1264 the sampling fre-
quency is twice fCLK. If the input signal spectrum is not
band-limited, aliasing may occur.
Any parasitic switching transients during the rise and fall
edges of the incoming clock are not part of the clock
10
LTC1264
O U
W
U
PPLICATI
S I FOR ATIO
A
Table 4. Bandpass Design Specifications (fCENTER is center
For example, for an LTC1264 bandpass filter with fCENTER
= 100kHz and fCLK = 2MHz, a 3.9MHz, 10mV input will
produce a 100kHz, 10mV output. A 1st or 2nd order
prefilter will reduce aliasing to acceptable levels in most
cases.
frequency of passband.)
PASSBAND
RIPPLE
(dB)
PASSBAND
WIDTH
(Hz)
STOPBAND
WIDTH
(Hz)
ATTENU-
ATION
(dB)
≤ 3dB for Butterworth
≤0.1 for Chebyshev
≥ f
≥ f
/20
/20
≥ 5 × Passband –40 to –60
≥ 5 × Passband –40 to –60
CENTER
CENTER
Note: Reducing passband ripple or attenuation will decrease Q values. The
filter order may also increase.
A GUIDE TO BANDPASS DESIGN
Filter design tools like FCAD require design specification
inputs such as passband ripple, attenuation, passband
width and stopband width in order to calculate filter
parameters fO, Q, fn or poles and zeroes. The results of
these filter approximations most often require Q values
which make excessive demands on the gain-bandwidth
products of active filter realizations. The active filter de-
signer should define a gain response so that the filter’s
mathematical approximation has practical requirements.
Table 4 is a guide to practical design specifications for
realizing bandpass filters with LTC1264 (please also refer
to the Typical Maximum Q vs Clock Frequency and Band-
pass Gain Error graphs under Typical Performance Char-
acteristics).
Table 5. Calculated Filter Parameters
STAGE
f
Q
O
1
2
3
4
38.1201kHz
41.9726kHz
35.6418kHz
44.8911kHz
4.3346
4.3346
10.5221
10.5221
Table 6. Calculated Mode 1b Resistors to Nearest 1% Value
Using Table 5 Filter Parameters and Figure 10 Equations
STAGE
R1
R2
R3
R5
R6
1
2
3
4
52.3k
47.5k
56.2k
44.2k
10k
10k
10k
10k
56.2k
51.1k
147k
118k
5k
5k
5k
5k
6.98k
11.8k
5.11k
20.5k
A Bandpass Design Example
R2 = 10k
R5 = 5k
Filter Type:
Bandpass
Butterworth
3dB
Filter Response:
Passband Ripple:
Attenuation:
f
CLK
20
f =
i
R3
OBP
R1 =
R6 =
(FOR BANDPASS)
60dB
H
2
Center Frequency:
Passband Width:
Stopband Width:
40kHz (fCENTER
10kHz
60kHz
)
R5•f
O
f 2 – f
2
O
(
)
i
2
f
f
CENTER
Q2
O
H
=
+ 1
–
OBP
(
)
(
)
f
f
CENTER
O
√
Implementing the Bandpass Design
R2•Q
R3 =
R6
WiththeLTC1264inMode1b,ButterworthandChebyshev
bandpass designs with fCLK to fCENTER ratios greater than
20:1 are possible.
R6 + 5
(
)
√
1264 F10
Figure 10. Equations for Resistors in Mode 1b Operation
First choose the clock frequency which in Mode 1b must
be greater than 20 times the bandpass center frequency of
40kHz. For this example, let’s choose fCLK to be 1MHz.
Table 6 lists the resistors for for the bandpass design
example and Figure 11 shows the complete circuit.
11
LTC1264
O U
S
W
U
PPLICATI
A
I FOR ATIO
R1
first stage and decreasing the R1 resistor of the last stage
by the same amount (multiplying the R1 resistor of the
first stage and dividing the R1 resistor of the last stage by
2 for narrowband filter, and by 5 for wideband filter is a
good rule of thumb). This adjustment may, however,
increase the filter’s passband noise.
R1
R2
R3
IN
INV B
HPB/NB
BPB
INV C
R2
HPC/NC
R3
STAGE 1
STAGE 2
BPC
LPB
LPC
R5
R5
SB
SC
LTC1264
–
AGND
V
R6
R6
R6
R6
1.0
+
f
V
CLK
SD
CLK
MODE 1b
0.5
V
= ±7.5V
S
CLK
CLK CENTER
SA
f
f
= 1MHz
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
R5
R5
/f
= 25:1
LPA
LPD
STAGE 4
BPA
BPD
STAGE 3
R3
R2
R3
R2
HPA/NA
INV A
HPD/ND
INV D
OUT
R1
R1
1264 F11
Figure 11. Mode 1b Bandpass Filter
30 32 34 36 38 40 42
46 48 50
44
FREQUENCY (kHz)
1264 F12
Figures 12 and 13 show the gain response graphs of the
40kHzButterworthbandpassdesigndescribedabove.The
passband gain response graph (Figure 12) shows a 40kHz
gainof–0.4dBandatiltedpassbandfrom37kHzto43kHz.
Theseerrorsareduetothe1%resistorsusedandtheside-
to-side matching of the LTC1264 fCLK-to-fCENTER ratio
which typically is 0.4%. To adjust for 0dB gain at 40kHz,
reduce the value of R1 in the first stage by 5%. To adjust
foraflatpassband, adjustby±1%thevalueofR6instages
3 and 4. Adjusting R6 compensates for the side-to-side
matching errors. Please refer to Figure 5 equations defin-
ing fO and Q as a function of R6.
Figure 12. Passband Gain vs Frequency
40kHz Butterworth Bandpass
10
MODE 1b
0
V
= ±7.5V
S
CLK
CLK CENTER
f
f
= 1MHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
/f
= 25:1
The sequence of 2nd order stages and the bandpass gain
HOBP of each stage will determine the gain peaks at the
filter’s intermediate outputs. A given internal output can
have several dB more gain than the final filter output. Gain
peaks occur around the corners of the passband. The gain
peaks can be reduced by increasing the R1 resistor of the
10 18 26 34 42 50 58
74 82 90
66
FREQUENCY (kHz)
1264 F13
Figure 13. Gain vs Frequency
40kHz Butterworth Bandpass
12
LTC1264
U
O
TYPICAL APPLICATI S
Linear Phase Clock-Tunable to 400kHz, Dual 4th Order Lowpass Filter
Gain vs Frequency
R1
0
–10
–20
–30
–40
–50
–60
–70
–80
R1
OUT 1
IN 1
INV B
HPB/NB
BPB
INV C
HPC/NC
BPC
R2
R3
R4
R2
R3
R4
LPB
LPC
C
C
SB
SC
LTC1264
0.1µF
–
AGND
–8V
V
0.1µF
+
f
8V
V
CLK
SD
CLK
C
C
SA
R4
R3
R2
LPA
LPD
10k
100k
FREQUENCY (Hz)
1M
R4
R3
BPA
BPD
1264 TA04b
HPA/NA
INV A
HPD/ND
INV D
R1
R2
IN 2
OUT 2
R1
B
2
C
2
A
2
17.8k
D
2
20k
LTC1264 SIDE
f
f
(V = ±8V)
–3dB S
CLK
MODE
R1
R2
R3
R4
2MHz
3MHz
4MHz
5MHz
125kHz
200kHz
275kHz
400kHz
17.8k 20k
27.4k 27.4k 27.4k 27.4k
19.6k 21k
51.1k 75k
5pF
19.6k
51.1k
5pF
21k
75k
5pF
T
≤ 50°C
A
1264 TA04a
5pF
C
Clock-Tunable, fCENTER = fCLK/20, 100kHz, 4th Order Bandpass and Notch Filters
Gain vs Frequency
R1
10
0
R1
BANDPASS IN
INV B
HPB/NB
BPB
INV C
HPC/NC
BPC
R2
R3
R2
R3
–10
–20
–30
–40
–50
–60
–70
–80
BANDPASS OUT
–7.5V
LPB
LPC
SB
SC
0.1µF
LTC1264
–
AGND
V
0.1µF
f
+
CLK
7.5V
V
CLK
SD
2MHz
V
CLK
= ±7.5V
S
SA
f
= 2MHz
LPA
NOTCH OUT
LPD
10k
100k
FREQUENCY (Hz)
1M
R3
R2
R3
R2
BPA
BPD
1264 TA05b
HPA/NA
INV A
HPD/ND
INV D
R1
C
C
NOTCH IN
R1
B
C
A
D
LTC1264 SIDE
1
1
1
1
MODE
R1
R2
20k
10k
20k
20k
10k
20k
10k
10k
20k
10k
10k
20k
R3
10pF 10pF
C
1264 TA05a
13
LTC1264
TYPICAL APPLICATI S
U
O
100kHz, 8th Order Notch Filter, fCLK/fCENTER = 20:1
Gain vs Frequency
R1
10
0
C
R1
IN
INV B
HPB/NB
BPB
INV C
HPC/NC
BPC
–10
–20
–30
–40
–50
–60
–70
–80
R2
R3
R2
R3
LPB
LPC
SB
SC
0.1µF
LTC1264
–
AGND
–7.5V
V
0.1µF
f
+
CLK
V
CLK
= ±7.5V
7.5V
V
S
CLK
SD
2MHz
f
= 2MHz
SA
10k
100k
FREQUENCY (Hz)
1M
LPA
BPA
OUT
LPD
R3
R2
R3
R2
1264 TA06b
BPD
HPA/NA
INV A
LTC1264 SIDE
B
1
C
1
A
1
D
1
HPD/ND
INV D
C
MODE
R1
36.5k 3.92k 7.5k 9.09k
R2
R3
C
10k
50k 27.4k
30pF
10k
10k
50k
10k
50k
30pF
R1
R1
1264 TA06a
Clock-Tunable, 8th Order Elliptic Lowpass Filter, fCLK/fCUTOFF = 20:1
Gain vs Frequency
R
L
0
R
V
CLK
= ±7.5V
H
S
–10
f
= 2MHz
R1
IN
INV B
HPB/NB
BPB
INV C
HPC/NC
BPC
–20
–30
–40
–50
–60
–70
–80
R2
R3
R4
R2
R3
R4
LPB
LPC
C
SB
SC
0.1µF
LTC1264
–
–7.5V
AGND
V
+
7.5V
V
CLK
SD
0.1µF
R
L
R
H
C
SA
f
CLK
2MHz
10k
100k
FREQUENCY (Hz)
1M
R4
LPA
BPA
LPD
R4
R3
R2
R3
R2
1264 TA03b
BPD
HPA/NA
INV A
HPD/ND
INV D
OUT
B
3a
27.4k
C
2n
A
2n
D
3
LTC1264 SIDE
R
R
H
MODE
R1
L
23.7k 20k
20k
29.4k
R2
20k 37.4k 37.4k 19.1k
28k 100k 100k 48.7k
137k 100k 130k
R3
R4
1264 TA03a
POWER SUPPLY
MAXIMUM f
CLK
R
±7.5V
±5V
SINGLE 5V
3.6MHz (C = 10pF)
2.0MHz (C = 10pF)
1.6MHz (C = 10pF)
H
27.4k 31.6k 24.3k
R
L
3pF
3pF
C
14
LTC1264
U
Dimensions in inches (millimeters) unless otherwise noted.
PACKAGE DESCRIPTIO
N Package
24-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
1.265*
(32.131)
24
23
22
21
20
19
18
17
16
15
10
14
11
13
12
0.255 ± 0.015*
(6.477 ± 0.381)
3
4
5
6
7
8
9
1
2
0.300 – 0.325
(7.620 – 8.255)
0.045 – 0.065
(1.143 – 1.651)
0.130 ± 0.005
(3.302 ± 0.127)
0.015
(0.381)
MIN
0.065
(1.651)
TYP
0.009 – 0.015
(0.229 – 0.381)
+0.025
0.125
(3.175)
MIN
0.005
(0.127)
MIN
0.100 ± 0.010
(2.540 ± 0.254)
0.018 ± 0.003
(0.457 ± 0.076)
0.325
–0.015
+0.635
8.255
N24 0695
(
)
–0.381
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
SW Package
24-Lead Plastic Small Outline (Wide 0.300)
(LTC DWG # 05-08-1620)
0.598 – 0.614*
(15.190 – 15.600)
24 23 22 21 20 19 18
16 15 14 13
17
0.394 – 0.419
(10.007 – 10.643)
NOTE 1
0.291 – 0.299**
(7.391 – 7.595)
2
3
5
7
8
9
10
1
4
6
11 12
0.037 – 0.045
(0.940 – 1.143)
0.093 – 0.104
(2.362 – 2.642)
0.010 – 0.029
(0.254 – 0.737)
× 45°
0° – 8° TYP
0.050
(1.270)
TYP
0.004 – 0.012
(0.102 – 0.305)
0.009 – 0.013
NOTE 1
(0.229 – 0.330)
0.014 – 0.019
0.016 – 0.050
(0.356 – 0.482)
(0.406 – 1.270)
NOTE:
1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
S24 (WIDE) 0396
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
15
LTC1264
U
O
TYPICAL APPLICATI
8th Order Bandpass Filter, Linear Phase
R
H
R
L
R1
LTC1264 SIDE
B
3a
97.6k
C
3
A
3a
32.4k
D
3
V
INV B
HPB/NB
BPB
INV C
HPC/NC
BPC
IN
R2
R3
R4
R2
R3
R4
MODE
R1
R2
R3
R4
10.7k 12.4k 10.7k 10.0k
39.2k 39.2k 12.4k 29.4k
13.3k 10.7k 11.5k 10.0k
LPB
LPC
C
R
53.6
15.0k
27.4k
100.0k
H
SB
SC
0.1µF
R
L
LTC1264
–
–7.5V
0.1µF
AGND
V
+
7.5V
1MHz
V
f
C
CLK
SD
CLK
1MHz
1.5MHz
2.0MHz
0pF
5pF
10pF
SA
R4
R3
R2
R4
R3
R2
LPA
BPA
LPD
1264 TA07a
BPD
HPA/NA
INV A
HPD/ND
INV D
V
OUT
R
H
R1
R
L
50kHz Bandpass Filter, Linear Phase
Gain vs Frequency
Passband Gain and Group Delay
10
3
0
124
114
104
94
V
CLK
= ±7.5V
S
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
f
= 1MHz
GAIN
–3
–6
–9
84
DELAY
–12
–15
–18
–21
–24
–27
74
64
54
44
34
24
10k
100k
FREQUENCY (Hz)
1M
40 42 44 46 48 50 52
56 58 60
54
FREQUENCY (kHz)
1264 TA07b
1264 TA07c
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1068
Very Low Noise, High Accuracy, Quad Universal Filter Four 2nd Order Filter Sections in 28-Pin SSOP, 56kHz Max Center
Building Block
Frequency, ≤40µV
Noise per 2nd Order Section, Operation 3.3V to ±5V
RMS
LTC1068-25
LTC1068-50
LTC1562
High Speed, High Accuracy, Quad Universal
Filter Building Block
Four 2nd Order Filter Sections in 28-Pin SSOP, 200kHz Max Center
Frequency, Operation 3.3V to ±5V
Low Power, High Accuracy, Quad Universal
Filter Building Block
Four 2nd Order Filter Sections in 28-Pin SSOP, 40kHz Max Center
Frequency, 3.5mA at Single 5V, Operation 3.3V to ±5V
Very Low Noise, Low Distortion, Active RC Quad
Universal Filter
Four 2nd Order Filter Sections, No Clock Required, 150kHz Max Center
Frequency, SSOP
1264fa LT/TP 0198 4K REV A • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 1993
Linear Technology Corporation
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1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900
16
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FAX: (408) 434-0507 TELEX: 499-3977 www.linear-tech.com
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